A perpendicular magnetization ferrimagnetic tunnel junction device and its fabrication method and application

Abstract

The application provides a perpendicular magnetization ferrimagnetic tunnel junction device and a preparation method and application thereof, and comprises a first electrode layer, an insulating barrier layer, a second electrode layer, an insulating protective layer, a top electrode and a bottom electrode formed on a substrate, the insulating barrier layer is arranged between the first electrode layer and the second electrode layer, and the material of the second electrode layer is a rare earth-transition metal alloy. The ferrimagnetic tunnel junction device of the application can change the resistance state only by temperature cycle (across the magnetic compensation temperature), the resistance state is still maintained even if the temperature returns to the initial value after writing, the temperature change itself is a writing means, the resistance state is nonvolatile after writing, and it is not necessary to continuously supply power or apply a magnetic field / voltage to maintain, so that the static power consumption is significantly reduced. In addition, the application can also realize multi-level storage based on the perpendicular magnetization ferrimagnetic-based multi-ferroelectric tunnel junction.

Description

Technical Field

[0001] This invention belongs to the field of magnetic electronic devices, and in particular relates to a vertically magnetized subferromagnetic tunnel junction device, its preparation method, and its application. Background Technology

[0002] Magnetic tunnel junctions (MTJs) are the core units of magnetic random access memory (MRAM), spin logic devices, and neuromorphic computing. Traditional MTJs use ferromagnetic electrodes, which suffer from problems such as large stray magnetic fields, difficulties in miniaturization, and slow spin dynamics. In recent years, subferromagnetic materials (such as rare-earth-transition metal alloys and ferromagnetic oxides) have become ideal candidates for constructing high-density, high-speed memories due to their combination of the controllability of ferromagnetism and the fast dynamics and low stray fields of antiferromagnetism.

[0003] In existing technologies, researchers have used ferrimagnetic CoGd and ferromagnetic CoFe to construct MTJs and observed a sign reversal phenomenon in the TMR (Tunnel Magnetoresistance) as a function of temperature (Kaiser et al., Phys. Rev. Lett. 2005). However, this device employs in-plane magnetic anisotropy and has a small TMR, limiting the realization of perpendicularly magnetized, all-ferrimagnetic devices. Existing ferrimagnetic related patents, such as CN1556998A (Magnetic Memory Using Amorphous Ferrimagnetic Alloy) and US20130083593A1 (Crocus Technology's Self-Reference MRAM), both involve ferrimagnetic layers and temperature compensation, but their operating methods and state definitions are completely different.

[0004] Currently, existing technologies suffer from the following technical problems: Traditional heat-assisted magnetic recording (HAMR) or phase-change memory (PCM) requires laser or Joule heating for writing, resulting in high power consumption, and the writing speed is limited by the thermal diffusion process. Existing STT-MRAMs primarily use heating to reduce coercivity to assist writing (heating during writing and cooling during reading). While existing ferrimagnetic tunnel junctions (MTJs) can achieve TMR sign inversion, their applications are mainly limited to traditional magnetoresistive sensors or spin-torque devices, and their temperature-dependent sign inversion characteristics are not directly used for non-volatile thermal storage. Existing MTJs using ferrimagnetic / ferromagnetic heterojunctions cannot completely eliminate stray fields due to the presence of the ferromagnetic layer, limiting further increases in device density; and in-plane magnetic anisotropy is not conducive to achieving high-density perpendicular magnetization storage cells. There are no reports of utilizing the phenomenon of TMR sign inversion as temperature crosses the compensation point in pure ferrimagnetic perpendicular tunnel junctions to achieve non-volatile rewriting of the resistance state through temperature cycling alone. In other words, no existing technology discloses a non-volatile thermal memory based on TMR sign inversion as a direct storage mechanism. In summary, no studies have yet utilized the sign inversion property of TMR in subferromagnetic tunnel junctions to directly construct non-volatile thermal memories. Summary of the Invention

[0005] In view of this, the present invention aims to overcome the defects in the prior art and proposes a vertically magnetized subferromagnetic tunnel junction device, its fabrication method and application, to solve the problems of high power consumption and limited speed of existing thermal memory writes, as well as the failure of existing subferromagnetic tunnel junction devices to directly utilize TMR sign inversion to achieve non-volatile thermal storage.

[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows: In a first aspect, the present invention provides a vertically magnetized ferrimagnetic tunnel junction device, comprising a first electrode layer, an insulating barrier layer, a second electrode layer, an insulating protective layer, a top electrode, and a bottom electrode formed on a substrate. The insulating barrier layer is disposed between the first electrode layer and the second electrode layer. The first electrode layer is made of a ferromagnetic metal, a ferrimagnetic metal, a ferromagnetic oxide, or a ferrimagnetic oxide. The second electrode layer is made of a rare earth-transition metal alloy. The insulating barrier layer is made of an oxide insulating material, a ferroelectric material, or a multiferroic material. The two ends of the top electrode are respectively connected to the second electrode layer and an external circuit. The two ends of the bottom electrode are respectively connected to the first electrode layer and an external circuit. The insulating protective layer partially covers the surface of the first electrode layer to prevent the first electrode layer from contacting the second electrode layer and to prevent the top electrode from contacting the first electrode.

[0007] Preferably, the material of the second electrode layer is Co. 100-X Gd X and / or Co 100-X Tb X , where x ranges from 10 to 35.

[0008] The second electrode layer has perpendicular magnetic anisotropy; in this embodiment of the invention, Co is used. 100-X Gd X (where x is between 10 and 35) Taking this as an example, the Co and Gd sublattices in this alloy are antiferromagnetically coupled and have a magnetic compensation temperature T. M (This can be adjusted by taking the value of component x).

[0009] Preferably, the material of the first electrode layer is Co, CoFe, CoFeB, Ni, Py, or Co. 100-X Gd X Co 100-X Tb X NiCo2O4 (NCO), La 0.7 Sr 0.3 Mn 0.8 Ru 0.2 One or more of O3 and SrRuO3, wherein Co 100-X Gd XCo 100-X Tb X The value of x in the equation ranges from 10 to 35.

[0010] The first electrode layer has perpendicular magnetic anisotropy, and its net magnetization direction can be modulated by an external magnetic field. In this embodiment of the invention, the ferrimagnetic oxide NCO is used as an example. Its magnetization is dominated by Co sites (Td sites), while spin transport is dominated by Ni sites (Oh sites), exhibiting a nearly half-metallic band structure (spin polarization close to -100%).

[0011] Preferably, the thickness of the first electrode layer is 10~100 nm.

[0012] Preferably, the thickness of the second electrode layer is 3~10 nm.

[0013] Preferably, the thickness of the insulating barrier layer is 1~5 nm.

[0014] Preferably, the thickness of both the top electrode and the bottom electrode is 100~1000 nm.

[0015] Preferably, the insulating barrier layer is made of MgAl2O4 (MAO), MgO, Al2O3, or Pb(Zr) 0.2 Ti 0.8 One or more of O3, BaTiO3, BiFeO3, and BiLaFeO3.

[0016] Preferably, the top electrode and the bottom electrode are made of one or more of Pt, Au, Ta, Ti, and Cu.

[0017] Working principle of the invention: Below the second electrode layer (with Co) 100-X Gd X (For example) Magnetic compensation temperature T M At that time, Co 100-X Gd X The net magnetization is dominated by the Gd sublattice; higher than T M At that time, net magnetization is dominated by the Co sublattice. Meanwhile, Co... 100-X Gd X Spin transport is consistently dominated by the Co sublattice (verified by DFT calculations). The magnetic dominance and spin dominance remain unchanged in the first electrode layer (taking NCO as an example). Therefore, when the temperature drops below... T M Change to above T M At that time, Co 100-X Gd XThe magnetization direction of NCO will reverse relative to the fixed external auxiliary magnetic field (because the dominant magnetization sublattice changes from Gd to Co, and the magnetic moments of the two are opposite), but its transport-dominated spin direction (Co spin) remains unchanged. Meanwhile, the magnetization direction of NCO is always determined by the external auxiliary magnetic field (Co... Td (Along the direction of the magnetic field). This results in a reversal of the relative magnetization parallel / antiparallel states of the two electrodes in the tunnel junction, thus reversing the TMR sign. Specifically: When the temperature < T M At that time, TMR is a positive value (e.g., +20% to +30%). When temperature > T M When TMR is negative (e.g., -10% to -20%), TMR is negative.

[0018] Furthermore, the vertically magnetized subferromagnetic tunnel junction device also includes an external auxiliary magnetic field and an external electrode. The external auxiliary magnetic field is a bias magnetic field with a fixed magnitude and a direction perpendicular to the plane where the subferromagnetic tunnel junction is located. The external electrode is used to connect an external source meter.

[0019] Preferably, the strength of the external auxiliary magnetic field is 0.1~0.5 T.

[0020] Secondly, the present invention also provides a method for fabricating the above-mentioned vertically magnetized subferromagnetic tunnel junction device, the method comprising the following steps: A first electrode layer and an insulating barrier layer are deposited on a substrate using pulsed laser deposition or magnetron sputtering. The first electrode layer and the insulating barrier layer are then photolithographically etched to define the bottom electrode pattern, and an insulating protective layer is deposited in a specific region thereon. A specific region in the insulating protective layer is etched down to the insulating barrier layer to form a tunnel junction region. A top electrode lift-off mask pattern is defined above the tunnel junction region using photolithography. Subsequently, a second electrode layer and a top electrode are deposited sequentially using magnetron sputtering, and a bottom electrode is deposited. Finally, the photoresist is removed using a lift-off process to obtain the vertically magnetized subferromagnetic tunnel junction device.

[0021] Thirdly, the present invention also provides the application of the above-mentioned vertically magnetized subferromagnetic tunnel junction device in non-volatile thermal storage devices.

[0022] Fourthly, the present invention also provides a non-volatile hot-writing method, comprising the following steps: S1. When it is necessary to switch the resistive state of the memory device from a low-resistance state to a high-resistance state, under the action of an external auxiliary magnetic field (with a magnitude of 100 Oe to 500 Oe) perpendicular to the film surface, the memory device is heated from a first temperature T1 to a second temperature T2, wherein T1 <T M T2>T M TM is the magnetic compensation temperature. Due to the sign reversal of TMR, the resistance state of the memory device switches from a low resistance state (corresponding to positive TMR) to a high resistance state (corresponding to negative TMR), and the resistance state is maintained after the magnetic field is removed (that is, non-volatile); even if the temperature is lowered to the first temperature T1, the high resistance state is still maintained.

[0023] S2. When it is necessary to write the resistance state of the memory device back from the high resistance state to the low resistance state, the memory device needs to be cooled from T1 to a third temperature T3 with a lower temperature, where T3<T1, meanwhile, the direction of the external auxiliary magnetic field remains unchanged, and the resistance state automatically switches back to the low resistance state.

[0024] The method achieves non-volatile rewriting of the resistance state by controlling a temperature cycle (crossing the magnetic compensation temperature T M ) without changing the magnetic field direction or applying voltage write pulses.

[0025] In addition, by precisely controlling the temperature at the magnetic compensation temperature T M to different nearby values, intermediate resistance states can be obtained (because the absolute value of TMR changes continuously with temperature), thereby realizing multi-level storage.

[0026] Compared with the prior art, the present invention has the following advantages: (1) Non-volatile thermal writing: The present invention changes the resistance state only through a temperature cycle (crossing the magnetic compensation temperature). After writing, even if the temperature returns to the initial value, the resistance state is still maintained, that is, the temperature change itself is the writing means, and the resistance state is non-volatile after writing, which is essentially different from the prior art. No continuous power supply or external magnetic field / voltage is required for maintenance, which significantly reduces static power consumption.

[0027] (2) Fast writing speed: The spin dynamics speed of the ferrimagnetic material of the present invention can reach the order of picoseconds to femtoseconds, which is much faster than the thermal diffusion process (nanosecond to microsecond level) of traditional phase change memories. The actual writing speed is only limited by the rate of temperature change (temperature can be rapidly raised and lowered by a micro-heater), and nanosecond-level thermal writing can be theoretically achieved.

[0028] (3) Adjustable operating temperature: The present invention adjusts the value of x in Co 100-X Gd X (the value range is 10 to 35). The magnetic compensation temperature can be T M continuously regulated within the range from 10 K to 350 K, so as to adapt to different application scenarios (low-temperature quantum computing, room-temperature consumer electronics, etc.).

[0029] (4) Multi-level storage capability: Since the absolute value of TMR changes continuously with temperature, multiple distinguishable resistance states can be obtained through fine temperature control, enabling a single storage cell to store multiple bits of information (e.g., 4 levels corresponding to 2 bits), thereby improving storage density.

[0030] (5) Fully vertical magnetization and no stray field: Both electrodes of the present invention are vertical magnetic anisotropic subferromagnetic materials and do not contain ferromagnetic layers, which greatly reduces crosstalk between units and is beneficial to high-density three-dimensional integration.

[0031] (6) Compatible with CMOS process: The materials of the first electrode layer used in this invention (such as NiCo2O4, MgAl2O4, CoGd) can be prepared in conventional magnetron sputtering or PLD equipment. The device is processed using standard photolithography and etching processes, which are easy to integrate with the back-end CMOS circuit.

[0032] (7) By replacing the insulating barrier layer in this invention with an insulating barrier ferroelectric layer, multi-level storage based on a vertically magnetized subferromagnetic base multiferroic tunnel junction can be realized. Attached Figure Description

[0033] Figure 1 This is a schematic cross-sectional view of the vertically magnetized subferromagnetic tunnel junction device of the present invention. Figure 2 The resistance-magnetic field of the subferromagnetic tunnel junction device described in Embodiment 1 of the present invention at different temperatures. RH TMR hysteresis loop and zero-field resistance curves at different temperatures (TMR hysteresis loop under small magnetic field: a, 20 K and 40 K (left); b, 10 K and 20 K (left); TMR thermal modulation between a, 20 K and 40 K (right) and b, 10 K and 20 K (right) under +0.3 T magnetic field assistance; c, TMR thermal modulation between 10 K, 20 K and 40 K under magnetic field assistance. In the figure, "0" and "1" correspond to the low resistance state and high resistance state at the corresponding temperatures, respectively; Figure 3 The multi-level storage resistance values ​​of the ferrimagnetic-based multiferroic tunnel junction device described in Embodiment 3 of the present invention under the action of opposite pulse polarization voltage and different external auxiliary magnetic fields.

[0034] Explanation of reference numerals in the attached figures: 1. First electrode layer; 2. Insulating barrier layer; 3. Second electrode layer; 4. External auxiliary magnetic field; 5. Insulating protective layer; 6. Top electrode; 7. Bottom electrode; 8. Substrate. Detailed Implementation

[0035] The embodiments of the present invention are described in detail below. The embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0036] In this document, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0037] In this document, when values ​​are described as ranges, it should be understood that such disclosure includes disclosure of all possible subranges within that range, as well as the specific numerical values ​​that fall within that range, regardless of whether the specific numerical value or specific subrange is explicitly specified.

[0038] In this article, the terms "multiple" or "more than" are used unless otherwise specified, referring to a quantity greater than or equal to 2. For example, "one or more" means one or more types.

[0039] In this document, the terms "preferred" and "more preferred" are used only to describe implementation methods or embodiments with better effects, and should be understood as not constituting a limitation on the scope of protection of this invention.

[0040] In this document, terms such as "further" are used for descriptive purposes to indicate differences in content, but should not be construed as limiting the scope of protection of this invention.

[0041] In this article, the term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0042] In this document, the term "about" means a specified value of + / - 10%, preferably + / - 5%, and more preferably + / - 1%.

[0043] In this article, the terms “include,” “including,” “have,” “contain,” etc., are all open-ended terms, meaning that they include but are not limited to.

[0044] Unless otherwise stated, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. While only preferred methods and materials have been described herein, any methods and materials similar to or equivalent to those described herein may be used in the implementation or testing of this invention.

[0045] The technical terms mentioned in the text are explained below: Ferrimagnetic tunnel junction (FTJ): A three-layer structure consisting of two ferrimagnetic layers or one ferrimagnetic layer with a ferromagnetic layer as an electrode, separated by an insulating barrier layer. It utilizes the spin-dependent tunneling effect to generate tunnel magnetoresistance (TMR). Magnetic compensation temperature... TM In ferrimagnetic materials (such as rare earth-transition metal alloys), the temperature point at which the magnetic moments of the two sublattices are equal in magnitude and opposite in direction, resulting in zero net magnetization.

[0046] Tunneling magnetoresistance (TMR) refers to the relative rate of change of resistance of a tunnel junction when the magnetization directions of the two magnetic electrodes are parallel (P) and antiparallel (AP), and is defined as TMR = (R... AP -R P ) / R P ×100%.

[0047] Perpendicular magnetic anisotropy (PMA): refers to the direction in which a magnetic material is easily magnetized perpendicular to the plane of the thin film.

[0048] Non-volatile: refers to the ability of a device to maintain its resistance state after external stimuli (such as magnetic field, temperature, voltage) are removed.

[0049] The present invention will be described in detail below with reference to the embodiments.

[0050] Example 1 A method for fabricating a vertically magnetized subferromagnetic tunnel junction device (low-temperature device, x=18) includes the following steps: S1. Growth of the first electrode layer 1 and the insulating barrier layer 2 A pulsed laser deposition (PLD) system was used to epitaxially grow a first electrode layer 1 made of NiCo2O4 (NCO) and an insulating barrier layer 2 made of MgAl2O4 (MAO) on a (100) oriented MgAl2O4 (MAO) single crystal substrate (referred to as MAO substrate 8). The specific steps are as follows: S11. Substrate pretreatment: The MAO substrate is ultrasonically cleaned with acetone, isopropanol and deionized water in sequence, dried with nitrogen and then transferred to the PLD growth chamber.

[0051] S12. First electrode layer growth: An NCO ceramic target (solid-state reaction sintered, purchased from Beijing Zhongnuo New Material Technology Co., Ltd.) was used. The growth conditions were: substrate temperature 350°C, laser energy density 1.2 J / cm². 2 (KrF excimer laser, λ=248nm), pulse frequency 7Hz, oxygen pressure 200mTorr. Deposition thickness 16nm.

[0052] S13. Growth of the insulating barrier layer: Switched to a MgAl2O4 (MAO) ceramic target, growth conditions were: substrate temperature 350°C, laser energy density 1.2 J / cm².2 The pulse frequency was 7 Hz, and the oxygen pressure was 50 mTorr. The deposition thickness was 3 nm.

[0053] S14. In-situ post-annealing: After deposition, in-situ annealing is performed at an oxygen pressure of 50 mTorr for 15 minutes, followed by cooling to room temperature at an oxygen pressure of 1000 mTorr to reduce the oxygen vacancy concentration and obtain NCO / MAO epitaxial wafers.

[0054] S2. Device micro / nano fabrication, the specific steps are as follows: S21. Photolithography and Etching: Definition of the First Electrode Layer: Photoresist is spin-coated onto an NCO / MAO epitaxial wafer, and a strip pattern of the first electrode layer is formed by exposure using a maskless ultraviolet lithography machine (TuoTuo Technology). Inductively Coupled Plasma (ICP) etching removes the NCO layer not protected by the photoresist, forming the strip-shaped first electrode layer.

[0055] S22. Deposit insulating protective layer 5: In a specific area above the first electrode layer, a 30 nm thick insulating protective layer of SiO2 material is deposited using plasma-enhanced chemical vapor deposition (PECVD) or sputtering (its function is to prevent the first electrode layer from directly contacting the second electrode layer and causing a short circuit) to cover the first electrode layer in the area.

[0056] S23. Tunnel Junction Preparation: Define a tunnel junction pattern above the insulating protective layer, and use micro-nano fabrication technology to completely etch away the insulating protective layer at the junction location until the surface of the underlying MAO insulating barrier layer is exposed, forming a tunnel junction (i.e., forming a window to expose MAO in the SiO2 insulating protective layer).

[0057] S24. Create a first electrode layer contact window: Use photolithography and etching processes to remove the SiO2 insulating protective layer in the preset contact area to form a contact window for connecting the first electrode layer to external circuits.

[0058] S25. Patterning of the second electrode layer 3 and the top electrode 6: Using photolithography, a strip-shaped photoresist mask pattern of the top electrode is formed on the device surface, which is perpendicular to and intersects with the first electrode layer, to define the deposition areas of the second electrode layer and the top electrode.

[0059] S3. Second electrode layer (Co) 82 Gd 18 / Pt), top electrode and bottom electrode 7 deposition, the specific steps are as follows: The micro / nano-fabricated devices were then transferred to a magnetron sputtering system (base vacuum <5×10⁻⁶). -8 Torr), using a dual-target co-sputtering method to deposit Co material. 82 Gd 18 Second electrode layer: S31. Pre-cleaning: Before formal deposition, the device surface is bombarded and cleaned for 1 minute using the anti-sputtering function of the magnetron sputtering system to remove any photoresist substrate or surface contaminants that may remain in step S25.

[0060] S32. Second electrode layer deposition: Co-sputtering was performed using a Co target (DC power supply) and a Gd target (RF power supply), with the component ratio controlled to Co:Gd ≈ 82:18 (atomic ratio) by adjusting the power of each target. The deposition thickness was 5 nm.

[0061] S33. Top and Bottom Electrode Deposition: Under vacuum-free conditions, a 100 nm thick Pt metal layer is deposited using DC sputtering. This Pt metal layer serves as the top electrode above the tunnel junction region, connecting the second electrode layer to the external circuitry. Simultaneously, within the contact window of the first electrode layer, this Pt metal layer acts as the bottom electrode, connecting the first electrode layer to the external circuitry. In other words, the top electrode is covered and protected, and the bottom electrode contact window is filled with metal simultaneously, all through a single Pt metal layer deposition.

[0062] S34. Lift-off: After the top electrode deposition is completed, the device is placed in acetone for lift-off to remove residual photoresist and the overlying metal layer, ultimately obtaining a complete ferrimagnetic tunnel junction device. The junction region of this device is a circle with a diameter of 2 μm, or a square with a diameter of 2 μm × 2 μm.

[0063] S4. Device Characterization and Testing S41. Magnetic Properties: Using a superconducting quantum interference device (SQUID), out-of-plane / in-plane hysteresis loops of thin films and devices were measured to confirm perpendicular magnetic anisotropy and magnetic compensation temperature T. M ≈ 27K.

[0064] S42. Tunneling magnetoresistance (TMR): In the Physical Properties Measurement System (PPMS), the resistance-magnetic field (RH) loop at different temperatures is measured using the four-probe method. The external auxiliary magnetic field 4 is provided by an electromagnet in the PPM, with its direction perpendicular to the film surface and a fixed magnitude of 0.3T.

[0065] S43. Hot Write Cyclic Test: Under a fixed external auxiliary magnetic field of 0.3T, the sample is cyclically heated and cooled between 10K and 40K, and the zero-field resistance value is recorded at each temperature to verify the non-volatile switching.

[0066] Experimental results: At 10 K, TMR ≈ +26%; at 40 K, TMR ≈ -18%. Through temperature cycling from 10 K to 40 K, non-volatile switching between the low-resistivity state (~+26%) and the high-resistivity state (~-18%) is achieved, with no degradation after >100 switching cycles. The results are as follows... Figure 2As shown.

[0067] Example 2 A method for fabricating a vertically magnetized subferromagnetic tunnel junction device (room temperature tunable device, x ranging from 25 to 35) includes the following steps: By adjusting Co 100-X Gd X Increasing the medium x value to 25~35 can compensate for the temperature. T M Adjust to near room temperature. The preparation process is the same as in Example 1; The first electrode layer and the insulating barrier layer are the same as in Example 1; Top electrode: Co 75 Gd 25 (Thickness of 5 nm) or Co 70 Gd 30 (Thickness is 5 nm), otherwise the same as in Example 1; expected T M ≈ 280~320 K, operating temperature range 260 K~350 K.

[0068] External auxiliary magnetic field: 0.2~0.5 T.

[0069] Expected TMR value: approximately ~5% in absolute value at room temperature, with the sign varying with temperature. T M But then it reversed.

[0070] Expected hot write cycle test results: Achieve non-volatile switching between high and low resistance states through temperature cycling from 260 K to 350 K, with no degradation after more than 100 switching cycles.

[0071] Example 3 (Multi-level storage): A method for fabricating a vertically magnetized subferromagnetic tunnel junction device includes the following steps: The substrate 8 was replaced with (La,Sr)(Al,Ta)O3(LSAT), and the material of the first electrode layer 1 was replaced with La. 0.7 Sr 0.3 Mn 0.8 Ru 0.2 O3(LSMRO), the material of insulating barrier layer 2 is replaced with Pb(Zr) 0.2 Ti 0.8O3(PZT) was prepared using the method described in Example 1 to obtain a vertically magnetized ferrimagnetic-based tunnel junction device, which can also be called a vertically magnetized ferrimagnetic-based multiferroic tunnel junction device. By changing the ferroelectric polarization direction (upward or downward) in the insulating barrier layer 2 through an external circuit, multi-level non-volatile storage based on the ferrimagnetic-based multiferroic tunnel junction device can be achieved within a temperature range of 15 K to 70 K (35 K in this example).

[0072] The specific implementation or verification methods are as follows: At 35 K, a periodically varying pulsed electric field (- / +5 V) was applied to the device via an external circuit to switch the polarization direction of the ferroelectric barrier layer. The TMR values ​​of the device were measured under vertical external auxiliary magnetic fields at - / +1 T, +0.2 T, and +0.5 T, respectively.

[0073] The results are as follows Figure 3 As shown, when the external auxiliary magnetic field is - / +1 T, the change in TMR is determined solely by the polarization state of the ferroelectric barrier. When the polarization direction switches from downward to upward, the TMR periodically switches between a high-resistivity state and a low-resistivity state. The high-resistivity state has a resistance of approximately 1.85 MΩ, and the low-resistivity state has a resistance of approximately 0.255 MΩ. When the external auxiliary magnetic field is adjusted from -1 T to +0.2 T, the magnetic parallel state changes to an antiparallel state. Under this magnetic field condition, the low-resistivity state corresponding to upward polarization remains approximately 0.255 MΩ, while the high-resistivity state corresponding to downward polarization increases to approximately 1.95 MΩ. When the external auxiliary magnetic field is further increased to +0.5 T, the antiparallel state returns to a parallel state. Under this magnetic field, the high-resistivity state returns to approximately 1.85 MΩ, and the low-resistivity state decreases to approximately 0.248 MΩ.

[0074] In summary, by controlling the polarization direction of the ferroelectric barrier under different external auxiliary magnetic fields, multiple distinguishable magnetoresistive states with opposite polarization directions can be obtained at 35 K. Furthermore, by changing the operating temperature, even more resistive states can be controlled, thus verifying the application potential of this device in multi-level non-volatile memory.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A vertically magnetized subferromagnetic tunnel junction device, characterized in that: The subferromagnetic tunnel junction includes a first electrode layer, an insulating barrier layer, a second electrode layer, an insulating protective layer, a top electrode, and a bottom electrode formed on a substrate. The insulating barrier layer is disposed between the first electrode layer and the second electrode layer. The material of the first electrode layer is a ferromagnetic metal, a subferromagnetic metal, a ferromagnetic oxide, or a subferromagnetic oxide. The material of the second electrode layer is a rare earth-transition metal alloy. The material of the insulating barrier layer is an oxide insulating material, a ferroelectric material, or a multiferroic material. The two ends of the top electrode are respectively connected to the second electrode layer and an external circuit. The two ends of the bottom electrode are respectively connected to the first electrode layer and an external circuit. The insulating protective layer partially covers the surface of the first electrode layer to prevent the first electrode layer from contacting the second electrode layer and also to prevent the top electrode from contacting the first electrode.

2. The vertically magnetized subferromagnetic tunnel junction device according to claim 1, characterized in that: The material of the second electrode layer is Co. 100-X Gd X and / or Co 100-X Tb X , where x ranges from 10 to 35.

3. The vertically magnetized subferromagnetic tunnel junction device according to claim 1, characterized in that: The material of the first electrode layer is Co, CoFe, CoFeB, Ni, Py, Co 100-X Gd X Co 100-X Tb X NiCo2O4, La 0.7 Sr 0.3 Mn 0.8 Ru 0.2 One or more of O3 and SrRuO3, wherein Co 100-X Gd X Co 100-X Tb X The value of x in the equation ranges from 10 to 35.

4. The vertically magnetized subferromagnetic tunnel junction device according to claim 1, characterized in that: The thickness of the second electrode layer is 3~10 nm.

5. The vertically magnetized subferromagnetic tunnel junction device according to claim 1, characterized in that: The thickness of the first electrode layer is 10~100 nm; And / or, the thickness of the insulating barrier layer is 1~5 nm; And / or, the thickness of both the top electrode and the bottom electrode is 100~1000 nm.

6. The vertically magnetized subferromagnetic tunnel junction device according to claim 1, characterized in that: The insulating barrier layer is made of MgAl2O4, MgO, Al2O3, or Pb(Zr) 0.2 Ti 0.8 One or more of O3, BaTiO3, BiFeO3, and BiLaFeO3.

7. The vertically magnetized subferromagnetic tunnel junction device according to claim 1, characterized in that: The top electrode is made of one or more of Pt, Au, Ta, Ti, and Cu.

8. A method for fabricating a vertically magnetized subferromagnetic tunnel junction device according to any one of claims 1-7, characterized in that: The method includes the following steps: A first electrode layer and an insulating barrier layer are deposited on a substrate using pulsed laser deposition or magnetron sputtering; the first electrode layer and the insulating barrier layer are photolithographically and etched to define the bottom electrode pattern, and an insulating protective layer is deposited in a specific region thereon; a specific region in the insulating protective layer is etched down to the insulating barrier layer to form a tunnel junction region. A photolithography process is used to define the top electrode stripping mask pattern above the tunnel junction region; Subsequently, the second electrode layer and the top electrode are deposited sequentially using magnetron sputtering, while the bottom electrode is deposited simultaneously. Finally, the photoresist is removed by a stripping process to obtain the vertically magnetized subferromagnetic tunnel junction device.

9. The application of the vertically magnetized subferromagnetic tunnel junction device according to any one of claims 1-7 in non-volatile thermal storage devices.

10. A non-volatile hot-writing method, characterized in that: Includes the following steps: S1. When it is necessary to switch the resistive state of the memory device according to claim 9 from a low-resistance state to a high-resistance state, under the action of an external auxiliary magnetic field perpendicular to the film surface, the memory device is heated from a first temperature T1 to a second temperature T2, wherein T1 <T M T2 > T M T M For magnetic compensation temperature, due to the sign reversal of TMR, the resistance state of the storage device switches from a low resistance state to a high resistance state, and the high resistance state is maintained after the magnetic field is removed or the temperature drops to the first temperature T1. S2. When it is necessary to write the resistance state of the memory device according to claim 9 from the high resistance state back to the low resistance state, the memory device is cooled from T2 to T3, wherein T3 < T1, and the direction of the external auxiliary magnetic field remains unchanged, and the resistance state automatically switches back to the low resistance state.

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