A stripping method for micro-nano processing of a superconducting quantum chip and a superconducting quantum chip

Abstract

The application provides a peeling method for micro-nano processing of a superconducting quantum chip and the superconducting quantum chip. The peeling method comprises the following steps: spin-coating a first photoresist layer on the surface of a superconducting thin film, forming a first window after exposure, first development and etching; depositing an aluminum sacrificial layer on the surface of the first window and the first photoresist layer; spin-coating a second photoresist layer on the surface of the aluminum sacrificial layer, forming a second window after exposure and second development, wherein the second development simultaneously removes the aluminum sacrificial layer at the bottom of the first window; depositing a target metal layer in the second window; or depositing a target metal layer on the surface of the second window and the second photoresist layer; immersing the obtained chip into a peeling solution, wherein the peeling solution penetrates the weak part of the side wall of the first photoresist layer through the aluminum sacrificial layer, so that the first photoresist layer and each layer above the first photoresist layer are separated, and the target metal layer is retained and anchored on the substrate; and removing the residual aluminum sacrificial layer and the residual glue on the surface of the aluminum sacrificial layer.

Description

Technical Field

[0001] This invention belongs to the field of quantum bit chip design technology, and relates to a method for stripping superconducting quantum chip micro-nano fabrication and a superconducting quantum chip. Background Technology

[0002] The fabrication of superconducting quantum chips relies on micro- and nano-fabrication processes, among which stripping is a key step in metal patterning. As the structure of qubits becomes more complex, thick negative photoresists are often required to form heavy mask profiles to meet the needs of large-thickness metal deposition or special structures (such as air bridges and Josephson junction shielding layers).

[0003] However, when using high-thickness negative photoresist for stripping, the following technical problems exist: (1) Difficulty in stripping solution penetration: After exposure and development, the sidewall contour of high-thickness negative photoresist often presents an inverted trapezoidal or "T" shaped structure. The excessive thickness of the photoresist film leads to an excessively long solvent penetration path, and the continuity of the deposited metal film at the step is too good, making it difficult for the stripping solution to effectively penetrate into the interface between the photoresist and the substrate. This results in difficult stripping, serious residue, and even requires long-term ultrasonic or physical wiping. This can easily damage the fragile surface of the superconducting quantum chip (especially the Josephson junction region) or introduce additional impurities, seriously affecting the chip yield and coherence time. (2) Photolithography edge residue problem: Even if the main photoresist is swollen and removed by the stripping solution, there may still be a very thin layer of residual photoresist in the edge area of ​​the photoresist pattern (especially at the interface with the metal). These residual photoresists adhere to the chip surface, and conventional stripping solutions cannot completely remove them. (3) Residual contamination affects device performance: Residual adhesive, as an insulating organic contaminant, will introduce two-level system defects in superconducting circuits, resulting in a significant decrease in the coherence time of qubits.

[0004] To overcome the aforementioned technical problems, traditional solutions include extending the stripping time, adding ultrasonic assistance, or using oxygen plasma ashing. However, simply increasing the stripping time or temperature may corrode the formed superconducting film, ultrasonic-assisted stripping is prone to damaging the fragile Josephson junction, and oxygen plasma removal may affect the coherence of the qubits. In addition, several studies have attempted to improve the method by using pure wet cleaning, but with limited success.

[0005] Therefore, there is an urgent need for a non-destructive method to optimize surface cleanliness that can effectively assist in the peeling of thick adhesive and thoroughly remove residual adhesive from the edges. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a lift-off method for micro / nano fabrication of superconducting quantum chips and a superconducting quantum chip itself. By adding a thinner photoresist layer and an aluminum sacrificial layer, the aluminum sacrificial layer can form a discontinuous layer or extremely weak points on the sidewalls of the photoresist layer, providing a channel for subsequent stripping solution penetration and facilitating the complete removal of the upper thick resist and excess metal from the photoresist layer. Furthermore, by adding an aluminum etching step after stripping, the residual aluminum sacrificial layer at the photoresist edge, along with any residual resist adhering to it, is thoroughly removed, solving the technical problems of incomplete removal of thick negative resist and difficulty in removing residual resist at photoresist edges in existing technologies.

[0007] To achieve this objective, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a method for peeling off superconducting quantum chip micro / nano fabrication, the method comprising:

[0009] S1. A first photoresist layer is spin-coated onto the surface of a superconducting thin film, and a first window is formed after exposure, first development and etching.

[0010] S2. Deposit an aluminum sacrificial layer on the surface of the first window and the first photoresist layer;

[0011] S3. A second photoresist layer is spin-coated on the surface of the aluminum sacrificial layer. After exposure and second development, a second window is formed. The second development removes the aluminum sacrificial layer at the bottom of the first window, exposing the substrate area where the target metal to be deposited is to be deposited.

[0012] S4. Deposit a target metal layer in the second window; or, deposit a target metal layer on the surface of the second window and the second photoresist layer.

[0013] S5. Immerse the obtained chip in a stripping solution. The stripping solution penetrates through the weak points of the aluminum sacrificial layer on the sidewall of the first photoresist layer, causing the first photoresist layer and the layers above it to detach, while retaining the target metal layer anchored to the substrate.

[0014] S6. Remove the residual aluminum sacrificial layer and its surface adhesive residue.

[0015] In this invention, during step S2, when depositing the aluminum sacrificial layer, due to the directionality of deposition and the step coverage effect, the aluminum sacrificial layer will form a discontinuous layer or extremely weak points on the sidewall of the first photoresist layer, providing a channel for the subsequent stripping liquid to penetrate. The stripping liquid rapidly penetrates through the weak points on the sidewall of the first photoresist layer through the aluminum sacrificial layer, contacts and swells the first photoresist layer, and drives the upper second photoresist layer and its excess metal (target metal not anchored to the substrate, and the aluminum sacrificial layer that exists between the first and second photoresist layers after the second development) to be completely stripped, achieving preliminary metal patterning. At this time, the main photoresist has been removed, but an extremely thin incomplete adhesive layer may still remain in the edge area of ​​the photoresist pattern, adhering to the surface of the remaining aluminum sacrificial layer. In step S6, while removing the residual aluminum sacrificial layer, the residual adhesive attached to its surface can also be removed. At this time, regardless of whether the residual adhesive is directly dissolved by the aluminum etching solution, it will detach from the chip surface along with the aluminum sacrificial layer below. This step achieves a thorough cleaning, like "if the skin is gone, what will the hair cling to?", and finally obtains a superconducting circuit structure with clear patterns and atomically clean surfaces.

[0016] Understandably, commonly used developers typically have a certain etching effect on aluminum. Therefore, during the second development process, while the developer dissolves and removes the second photoresist layer in the exposed area (taking positive photoresist as an example) to form the second window, it also etches away the aluminum sacrificial layer exposed at the bottom of the first window, exposing the underlying superconducting film for subsequent direct deposition of the target metal (e.g., the pier portion of an air bridge or the bottom of an indium pillar). For example, the developer used for the second development includes any one or a combination of at least two of tetramethylammonium hydroxide (TMAH) developer, potassium hydroxide-based developer, or sodium hydroxide-based developer.

[0017] This invention does not limit the type of superconducting quantum chip substrate. Commonly used types in the art are applicable to this invention, such as high-resistivity silicon, sapphire, or SOI (silicon on insulating substrate).

[0018] The following are preferred technical solutions of the present invention, but are not intended to limit the technical solutions provided by the present invention. The technical objectives and beneficial effects of the present invention can be better achieved and realized through the following preferred technical solutions.

[0019] As a preferred technical solution, the thickness of the first photoresist layer in step S1 is less than the thickness of the second photoresist layer in step S3.

[0020] The thickness of the first photoresist layer is 1.2μm to 1.8μm, for example, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm or 1.8μm.

[0021] As a preferred technical solution, the thickness of the aluminum sacrificial layer in step S2 is 10nm~30nm, such as 10nm, 15nm, 20nm, 25nm or 30nm.

[0022] The surface roughness of the aluminum sacrificial layer in step S2 is 1.8nm~2.2nm, for example, 1.8nm, 1.9nm, 2nm, 2.1nm or 2.2nm.

[0023] In this invention, if the aluminum sacrificial layer is too thick, its coverage at the sidewall of the first photoresist layer tends to be continuous and dense, failing to form weak channels for the stripping fluid to penetrate. This makes it difficult for the stripping fluid to enter the interface between the first photoresist and the substrate, thus losing its function of assisting in stripping. However, if the aluminum sacrificial layer has a certain degree of roughness, it is more conducive to the penetration of subsequent stripping or etching fluids, which is beneficial to the subsequent stripping and etching processes.

[0024] As a preferred technical solution, the thickness of the second photoresist layer is ≥2.5μm, such as 2.5μm, 2.8μm, 3μm, 3.5μm or 4μm.

[0025] It is understood that in this invention, the first photoresist layer is only used to assist in the stripping process, while the second photoresist layer is used to define a specific target metal structure (such as an air bridge or an indium pillar). To facilitate patterning, a positive photoresist is generally selected when preparing the air bridge, and a negative photoresist is selected when preparing the indium pillar. The thickness of the photoresist layer can be set according to the height requirements of the target structure and is greater than the thickness of the first photoresist layer.

[0026] As a preferred technical solution, the target metal layer in step S4 includes an aluminum film or an indium pillar.

[0027] It is understood that when the target metal layer is an aluminum film, those skilled in the art can directly deposit aluminum onto specific surfaces of the second window and the second photoresist using a selective deposition process, based on the shape of the air bridge. However, to ensure the accuracy of the pattern definition and the stability of the process, as a preferred technical solution, the following steps are included after step S4 and before step S5:

[0028] A third photoresist layer is spin-coated onto the surface of the aluminum film. After exposure and third development, a protective layer is formed covering the bridge deck and piers of the air bridge, exposing the aluminum film outside the air bridge structure. Subsequently, aluminum etching solution is used to etch away the aluminum film not covered by the protective layer.

[0029] As a preferred technical solution, the thickness of the aluminum film is 300nm~600nm, such as 300nm, 350nm, 400nm, 450nm, 500nm, 550nm or 600nm.

[0030] The height of the indium pillar is ≥5μm, for example, 5μm, 5.5μm, 6μm, 6.5μm or 7μm.

[0031] As a preferred technical solution, the stripping liquid in step S5 includes NMP (N-methylpyrrolidone) or acetone.

[0032] The temperature of the stripping fluid is 60℃~80℃, for example, 60℃, 65℃, 70℃, 75℃ or 80℃.

[0033] As a preferred technical solution, the solution for removing the residual aluminum sacrificial layer and its surface residue in step S6 includes tetramethylammonium hydroxide solution or type A aluminum etching solution (TYPEA).

[0034] It should be noted that when removing the residual aluminum sacrificial layer, the chip surface can be visually observed. When the aluminum sacrificial layer is observed to have completely disappeared, an over-etching time of 8% to 12% is added to this endpoint time to achieve complete removal of the residual aluminum sacrificial layer. During this process, since the thickness of the aluminum sacrificial layer is very small, it will not affect the main metal layer.

[0035] As a preferred technical solution, after step S6, the obtained chip is sequentially cleaned, dehydrated and dried.

[0036] The drying process includes protective gas drying or supercritical CO2 drying, wherein the protective gas includes N2.

[0037] In a second aspect, the present invention provides a superconducting quantum chip obtained by the stripping method described in the first aspect.

[0038] The numerical range described in this invention includes not only the point values ​​listed above, but also any point values ​​within the numerical ranges not listed above. Due to space limitations and for the sake of brevity, this invention will not exhaustively list all the specific point values ​​included in the range.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] (1) Double protection, thorough cleaning: The first layer of aluminum sacrificial layer assists in the removal of thick adhesive, ensuring that the main photoresist is completely removed; the second layer removes the residual aluminum sacrificial layer, and at the same time removes the residual adhesive at the edge, achieving a thorough cleaning like "if the skin is gone, where will the hair attach?"

[0041] (2) Non-destructive process: The entire process is wet processing to avoid process steps such as oxygen plasma and ultrasound that may damage the superconducting junction and protect the core area of ​​the quantum bit.

[0042] (3) Strong process compatibility: No need to change the existing photolithography process line, only add one step of aluminum sacrificial layer deposition and one step of aluminum etching, both of which are within the capabilities of existing equipment and are easy to promote.

[0043] (4) Significantly improve quantum coherence time: Completely remove surface organic residues and reduce defects in the two-level system, which is expected to improve the coherence time of the quantum bit by 30%.

[0044] (5) High cost-effectiveness: The solution used to remove the residual aluminum sacrificial layer is a conventional consumable in the photolithography process, and there is no need to purchase special cleaning agents, so the process cost hardly increases. Attached Figure Description

[0045] Figure 1 This is a SEM image of the chip after the aluminum sacrificial layer is deposited in step S2 of Example 1.

[0046] Figure 2 This is an atomic force microscope image of the aluminum sacrificial layer in Example 1.

[0047] Figure 3 This is an SEM image of the chip after the photoresist is removed in step S7 of Example 1.

[0048] Figure 4 This is an SEM image of the chip after drying in step S9 of Example 1.

[0049] Figure 5 This is an SEM image of the chip after the photoresist is removed in step S5 of Example 2.

[0050] Figure 6 This is an SEM image of a single indium pillar after drying in step S7 of Example 2.

[0051] Figure 7 This is an SEM image of the chip after drying in step S7 of Example 2.

[0052] Figure 8 This is a SEM image of a single indium pillar after the photoresist was removed in Comparative Example 2.

[0053] Figure 9 This is a cleanliness image of the chip after drying in step S7 of Example 2, taken under a dark-field optical microscope. Detailed Implementation

[0054] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0055] "The scope of this invention can be defined by a lower limit and an upper limit. The selected lower limit and upper limit define the boundary of a specific range. The range defined in this way can be defined by the inclusion or exclusion of endpoints. Any endpoint can be independently selected for inclusion or exclusion, and all lower limit and upper limit values ​​can be arbitrarily combined to form a new range. That is, any lower limit value can be combined with any upper limit value to form an effective range. For example, if the ranges of 60~120 and 80~110 are listed for specific parameters, it should be understood that the ranges of 60~110 and 80~120 also fall within the scope of this invention. In addition, if the minimum range values ​​1 and 2 are listed, and the maximum range values ​​3, 4 and 5 are also listed, then 1~3, 1~4, and 2~3, 1~4, 2~5 ... All ranges from 1 to 5, 2 to 3, 2 to 4, and 2 to 5 fall within the scope of this invention. In this invention, the numerical range "a to b" represents a shortened representation of any combination of real numbers between a and b, where both a and b are real numbers. For example, the numerical range "0 to 5" indicates that all real numbers between 0 and 5 have been fully listed in this document; "0 to 5" is merely a shortened representation of this numerical combination. When a parameter is expressed as an integer ≥ 2, it is equivalent to listing positive integers that meet the requirements, such as 2, 3, 4, 5, 6, 7, 8, 9, and 10. When a parameter is expressed as an integer selected from "2 to 10", it is equivalent to listing any integer among 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0056] In this invention, "a combination of at least two" refers to a quantity greater than or equal to 2 unless otherwise specified. For example, "any one or a combination of at least two" means that any one of the listed items can be selected, or a combination of at least two of the listed items formed in a manner that does not conflict and enables the implementation of this invention. In this invention, unless otherwise specified, the features or solutions corresponding to "and / or" cover any one of two or more related listed items, as well as any and all combinations of the related listed items. The arbitrary and all combinations include any two related listed items, any more related listed items, or a combination of all related listed items. For example, "A and / or B" means a set consisting of A, B, and combinations of A and B, where "containing A and / or B" can be understood, depending on the context of the statement, as containing A, containing B, or simultaneously containing both A and B. In this invention, "optional" means that the corresponding feature, component, step or solution is not necessary, that is, it is selected from either "with" or "without". If there are multiple "optional" limitations in a technical solution, unless otherwise specified and there is no technical conflict or mutual constraint, each "optional" limitation is independent and does not affect the others.

[0057] In this invention, technical features or solutions described using open-ended terms such as "comprising" or "including" do not exclude additional non-conflicting elements beyond the listed elements unless otherwise specified. They are considered to disclose both closed-ended features or solutions consisting solely of the listed elements and open-ended features or solutions that may include additional non-conflicting elements beyond the listed elements. For example, if A includes a1, a2, and a3, unless otherwise specified, this means that A can consist only of a1, a2, and a3, or it can include other non-conflicting elements based on a1, a2, and a3. This corresponds to the disclosure of technical solutions such as "A consists of a1, a2, and a3," "A is selected from a1, a2, and a3," and "A not only includes a1, a2, and a3, but may also include other non-conflicting elements." All embodiments and optional embodiments of this invention, unless otherwise specified and without technical conflict, can be combined to form new technical solutions, and such combinations fall within the scope of this invention. The term "embodiment" as used in this invention means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment or implementation of the invention. The appearance of this phrase in various locations throughout the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand, explicitly and implicitly, that the embodiments described in this invention can be combined with other embodiments that do not conflict with the technology. The ordinal numbers "first," "second," "third," and "fourth," etc., used in the expressions "first aspect," "second aspect," "third aspect," and "fourth aspect" in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly specifying the importance or quantity of the indicated technical features. They serve only as a non-exhaustive enumeration and do not constitute a closed limitation on quantity.

[0058] In this invention, the order in which the steps are written in the methods described in each embodiment does not imply a strict execution order. The actual execution order of each step should be determined based on its function and possible internal logic. Unless otherwise specified, all steps of this invention can be executed in the order they are written, or in any order without technical conflict. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) executed sequentially, or it may include steps (b) and (a) executed sequentially. If the method also includes step (c), then step (c) can be added to the method in any order without conflict, including but not limited to the execution order of steps (a), (b), and (c), steps (a), (c), and (b), steps (c), (a), and (b), etc.

[0059] The term "embodiment" as used in this invention means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment or implementation of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0060] In this invention, "room temperature" generally refers to 4℃~35℃, and can refer to 20℃±5℃. In some embodiments of this invention, room temperature refers to 20℃~30℃.

[0061] Example 1

[0062] This embodiment provides a method for the peeling off of superconducting quantum chip micro / nano fabrication with an air bridge structure, including:

[0063] S1. A first positive photoresist layer with a thickness of 1.5 μm is spin-coated on the surface of the superconducting thin film. After exposure, development, etching and cleaning, a first window is formed. The first window consists of two separate square openings, which correspond to the two pier positions of the air bridge.

[0064] S2. A 20nm thick layer of high-purity aluminum is deposited as an aluminum sacrificial layer on the surface of the first window and the first positive photoresist layer using electron beam evaporation. Due to the directionality of deposition, the aluminum sacrificial layer forms thin or discontinuous weak regions on the sidewalls of the positive photoresist layer, providing channels for the subsequent penetration of the stripping solution, such as... Figure 1 As shown.

[0065] S3. A 3μm thick layer of second positive photoresist is spin-coated onto the surface of the 20nm aluminum sacrificial layer. Then, a photomask with an air bridge pier pattern is exposed, and developed using an alkaline developer (TMAH). During development, the positive photoresist in the exposed area is dissolved and removed, forming a second window. This ensures that the first window (i.e., the position of the two piers) falls within the opening range of the second window, while the second positive photoresist in the unexposed area is retained, forming a bridge deck support structure spanning between the two first windows.

[0066] Furthermore, the alkaline developer reacts with the aluminum sacrificial layer in the bottom region of the first window, etching away the aluminum sacrificial layer in that region. As a result, the superconducting thin film at the two pier locations is re-exposed, providing a clean contact surface for subsequent deposition of air bridge piers.

[0067] S4. Without disrupting the vacuum, deposit an aluminum film with a thickness of 450 nm on the surface of the second window and the second positive photoresist layer. The aluminum film forms an ohmic connection with the exposed superconducting film in the pier area, forming a continuous metal bridge deck above the bridge deck support structure.

[0068] S5. A 3μm thick third positive photoresist layer is spin-coated onto the surface of a 450nm thick aluminum film. After exposure, it is developed using an alkaline developer (TMAH). During development, the positive photoresist in the exposed area is dissolved and removed, exposing the aluminum film outside the air bridge structure. The third positive photoresist in the unexposed area is retained, protecting the bridge deck support and pier structure.

[0069] S6. Use type A aluminum etching solution to etch the obtained sample. When the aluminum film outside the air bridge structure is about to be etched, add 10% more time to ensure that the aluminum film outside the air bridge structure is removed.

[0070] S7. Immerse the obtained chip in an NMP-based stripping solution at 70°C. This stripping solution rapidly penetrates through the weak deposition points of the aluminum sacrificial layer at the sidewall of the first positive photoresist, contacting and swelling the first positive photoresist layer. As the first positive photoresist layer swells and detaches, the aluminum sacrificial layer and the second positive photoresist layer (bridge support structure) above it are stripped away, and the third positive photoresist layer is also stripped away. The aluminum film at the piers is anchored to the substrate, thus the bridge metal is retained, forming an air bridge structure fixed at both ends and suspended in the middle. However, because the aluminum sacrificial layer at the sidewall of the first positive photoresist layer is thin and discontinuous, during the stripping solution penetration process, the aluminum sacrificial layer and the photoresist residue adhering to its surface in this area are not completely removed. Figure 3 As shown.

[0071] S8. Immerse the chip treated in S5 into TMAH-based developer. After observing the removal of the aluminum sacrificial layer on the surface, extend the time by another 10% to completely remove it. Figure 3 The remaining aluminum sacrificial layer shown is extremely thin, so the etching solution can quickly dissolve it. At the same time, the trace amount of photoresist residue attached to its surface is also physically removed as the aluminum layer falls off, achieving thorough cleaning of the chip surface.

[0072] S9. The obtained chip is sequentially rinsed with deionized water, dehydrated with isopropanol, and dried with supercritical CO2 to obtain a superconducting quantum chip with an air-bridge structure, such as... Figure 4 As shown.

[0073] Example 2

[0074] This embodiment provides a method for the stripping of superconducting quantum chips with indium pillar structures in micro / nano fabrication, including:

[0075] S1. A 1.5 μm thick positive photoresist layer is spin-coated on the surface of the superconducting thin film. After exposure, first development, etching and cleaning, a first window is formed. The first window consists of several independent circular openings, each corresponding to the pad position of the indium pillar to be prepared.

[0076] S2. A 20 nm thick layer of high-purity aluminum is deposited as an aluminum sacrificial layer on the first window and the surface of the positive photoresist layer using magnetron sputtering. Due to the directionality of deposition, the aluminum sacrificial layer forms thin or discontinuous weak regions on the sidewalls of the positive photoresist layer, providing channels for the subsequent penetration of the stripping solution.

[0077] S3. A 20μm thick layer of negative photoresist is spin-coated onto the surface of the aluminum sacrificial layer. Then, a photomask with an indium pillar hole pattern is exposed, and developed using an alkaline developer (TMAH). During development, the negative photoresist in the unexposed areas is dissolved and removed, forming a second window corresponding to the area of ​​the first window (i.e., the pad location). The negative photoresist in the exposed areas remains, forming a large-area mask structure surrounding the indium pillar holes.

[0078] Furthermore, the alkaline developer reacts with the aluminum sacrificial layer exposed at the bottom of the first window, etching away the aluminum sacrificial layer in that area and re-exposing the pad area of ​​the superconducting thin film, providing a clean contact interface for the subsequent direct deposition of indium pillars. The aluminum sacrificial layer outside the indium pillar holes is retained because it is covered by negative photoresist.

[0079] S4. Without disrupting the vacuum, deposit an indium pillar with a height of 7 μm on the first window and the surface of the negative photoresist, which directly contacts the exposed patterned superconducting thin film to form an electrical connection. At the same time, indium metal also covers the upper surface of the negative photoresist.

[0080] S5. Immerse the obtained chip in an NMP-based stripping solution at 70°C. This stripping solution rapidly penetrates through the weak points in the deposition of the aluminum sacrificial layer on the sidewalls of the positive photoresist, contacting and swelling the positive photoresist. As the positive photoresist swells and detaches, the negative photoresist mask structure above it, as well as the excess indium metal covering the top of the negative photoresist, are also stripped away. The indium pillars at the pads are already anchored to the substrate and are therefore firmly retained during the stripping process. After stripping, several independent indium pillar bumps corresponding to the pads remain on the chip surface. However, because the aluminum sacrificial layer on the sidewalls of the positive photoresist layer is thin and discontinuous, the aluminum sacrificial layer and photoresist residues adhering to its surface are not completely removed during the stripping solution penetration process. Figure 5 As shown.

[0081] S6. Immerse the chip treated in S5 into TMAH-based developer to remove the residual aluminum sacrificial layer at the edge of the positive photoresist. Since the residual aluminum layer is extremely thin, the TMAH-based developer can quickly dissolve it. At the same time, the trace amount of photoresist residue attached to its surface is physically lifted off as the aluminum layer falls off, achieving thorough cleaning of the chip surface.

[0082] S7. The obtained chip is sequentially rinsed with deionized water, dehydrated with isopropanol, and dried with N2 to obtain a superconducting quantum chip with an indium pillar structure, such as Figure 6 and Figure 7 As shown.

[0083] Example 3

[0084] The difference between this embodiment and embodiment 1 is that the thickness of the aluminum sacrificial layer in step S2 is 10 nm, the thickness of the positive photoresist in step S3 is 2.5 μm, the thickness of the aluminum film in step S4 is 300 nm, and the temperature of the stripping solution in step S5 is 60 °C.

[0085] The remaining preparation methods and parameters are consistent with those in Example 1.

[0086] Example 4

[0087] The difference between this embodiment and embodiment 2 is that the thickness of the aluminum sacrificial layer in step S2 is 30 nm, the height of the indium pillar in step S4 is 5 μm, and the temperature of the stripping solution in step S5 is 80 °C.

[0088] The remaining preparation methods and parameters are consistent with those in Example 2.

[0089] Example 5

[0090] The difference between this embodiment and Embodiment 1 is that the thickness of the aluminum sacrificial layer is 50 nm;

[0091] The remaining preparation methods and parameters are consistent with those in Example 1.

[0092] Comparative Example 1

[0093] This comparative example provides a method for the exfoliation of superconducting quantum chip micro / nano fabrication with an air-bridge structure, including:

[0094] S1. A 3μm thick layer of negative photoresist is spin-coated onto the surface of a superconducting thin film substrate (high-resistivity silicon). Then, a photomask with an air bridge pattern is used for exposure. After exposure, development is performed to expose the substrate area where the bridge pier metal to be deposited (i.e., the position of the two bridge piers). The negative photoresist in the exposed area forms a bridge deck support structure spanning between the contact holes of the two bridge piers.

[0095] S2. A 450nm thick aluminum film is deposited at the locations of the two bridge piers and on the surface of the negative photoresist. After deposition, the aluminum film is in direct contact with the patterned superconducting film on the substrate in the bridge pier area, forming a continuous bridge deck metal above the bridge deck support structure.

[0096] S3. Immerse the obtained chip in an NMP-based stripping solution at 70°C for stripping to remove the photoresist.

[0097] S4. The obtained chip is sequentially rinsed with deionized water, dehydrated with isopropanol, and dried with supercritical CO2 to obtain a superconducting quantum chip with an air bridge structure.

[0098] Comparative Example 2

[0099] This comparative example provides a method for the exfoliation of a superconducting quantum chip with an indium pillar structure in micro / nano fabrication, including:

[0100] S1. A layer of 8μm thick negative photoresist is spin-coated onto the surface of a superconducting thin film substrate. Then, a photomask with an indium pillar hole pattern is used for exposure and development. During development, the negative photoresist in the unexposed areas is dissolved and removed, forming several independent deep holes. Each deep hole exposes a pad area for depositing indium pillars. The negative photoresist in the exposed areas is retained, forming a large-area mask structure surrounding the deep holes.

[0101] S2. An indium pillar with a height of 7 μm is deposited in a deep hole and brought into direct contact with a patterned superconducting thin film.

[0102] S3. Immerse the obtained chip in NMP-based stripping solution for stripping to remove the photoresist.

[0103] S4. The obtained chip is sequentially rinsed with deionized water, dehydrated with isopropanol, and dried with supercritical CO2 to obtain a superconducting quantum chip with an indium pillar structure. The structure of a single indium pillar is as follows: Figure 8 As shown.

[0104] Comparative Example 3

[0105] The difference between this comparative example and Example 1 is that step S2 is omitted, and step S3 directly deposits the second positive photoresist layer on the surface of the first window and the first positive photoresist layer.

[0106] The remaining preparation methods and parameters are consistent with those in Example 1.

[0107] Comparative Example 4

[0108] The difference between this comparative example and Example 1 is that step S8 is omitted;

[0109] The remaining preparation methods and parameters are consistent with those in Example 1.

[0110] Comparative Example 5

[0111] The difference between this comparative example and Example 1 is that step S6 is changed to use oxygen plasma to remove residual adhesive.

[0112] The remaining preparation methods and parameters are consistent with those in Example 1.

[0113] Structural characterization and performance testing

[0114] The chips obtained after steps S2, S7, and S9 of Example 1 and steps S5 and S7 of Example 2 were subjected to SEM testing, and the chip obtained after step S4 of Comparative Example 2 was subjected to SEM testing. The surface cleanliness of the final chip obtained in Example 2 was tested using the dark-field mode of an optical microscope to observe the effect of different steps on the chip surface cleanliness. Furthermore, the surface roughness of the aluminum sacrificial layer deposited in step S2 of Example 1 was tested using atomic force microscopy.

[0115] Figure 1 , Figure 3 and Figure 4 These are SEM images of the chip obtained after steps S2, S7, and S9 in Example 1. Figures 5-7 These are SEM images of the chip obtained after steps S5 and S7 in Example 2, respectively. Figure 1 It can be seen that after depositing an aluminum sacrificial layer on the first window and the surface of the first photoresist, due to the directionality of deposition and the step coverage effect, the aluminum sacrificial layer will form a discontinuous layer or extremely weak points on the sidewall of the first photoresist layer. Subsequent stripping solution can then rapidly penetrate from these points, thereby achieving rapid stripping of the first photoresist. Figure 3 and Figure 4 , Figures 5-7 The comparison shows that after the stripping process, the main photoresist is removed, but a small amount of photoresist and aluminum remain. Removing the aluminum allows for complete removal of the remaining photoresist, resulting in a clean surface (e.g., ...). Figure 9 This further proves that its surface is clean and free of residue. In addition, Figure 2 This reflects the roughness of the aluminum sacrificial layer. It can be seen that the surface of the aluminum sacrificial layer is rough, which is also conducive to the penetration of stripping fluid and etching fluid.

[0116] Figure 8 The image shows the SEM image of the chip obtained in Comparative Example 2. It can be seen that the chip obtained by the traditional stripping method has serious photoresist residue on the surface. At the same time, the test results of Comparative Example 1 also show that the chip surface has serious photoresist residue, which will seriously affect the chip performance.

[0117] Furthermore, the chips obtained in Examples 3 and 4 have high surface cleanliness, indicating that good results can be achieved within the preferred range of this application. The chip obtained in Example 5 has more photoresist residue on its surface, which indicates that the thicker aluminum sacrificial layer will make the coverage of the aluminum sacrificial layer at the sidewall of the first photoresist layer more continuous and dense, making it difficult for the stripping liquid to enter the interface between the first photoresist and the substrate, resulting in incomplete stripping.

[0118] The test results of the chips obtained in Comparative Examples 3-5 showed that there was a lot of residual adhesive on their surface. This indicates that without depositing an aluminum sacrificial layer, or without further removing the residual aluminum sacrificial layer after peeling, or by using other methods to remove the residual adhesive, it is impossible to completely remove the residual adhesive.

[0119] In summary, in this invention, the aluminum sacrificial layer not only assists in the removal of thick photoresist, ensuring complete removal of the main photoresist, but also simultaneously removes residual photoresist from the edges by etching the remaining aluminum sacrificial layer, achieving a thorough cleaning process akin to "without the skin, there is no place for the hair to attach." The resulting chip surface is clean, without damaging the core area of ​​the qubits, making it suitable for industrial applications.

[0120] The applicant declares that the above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A method for peeling off superconducting quantum chip micro / nano fabrication, characterized in that, The stripping method includes: S1. A first photoresist layer is spin-coated onto the surface of a superconducting thin film, and a first window is formed after exposure, first development and etching. S2. Deposit an aluminum sacrificial layer on the surface of the first window and the first photoresist layer; S3. A second photoresist layer is spin-coated on the surface of the aluminum sacrificial layer. After exposure and second development, a second window is formed. The second development removes the aluminum sacrificial layer at the bottom of the first window, exposing the substrate area where the target metal to be deposited is exposed. S4. Deposit a target metal layer in the second window; or, deposit a target metal layer on the surface of the second window and the second photoresist layer. S5. Immerse the obtained chip in a stripping solution. The stripping solution penetrates through the weak points of the aluminum sacrificial layer on the sidewall of the first photoresist layer, causing the first photoresist layer and the layers above it to detach, while retaining the target metal layer anchored to the substrate. S6. Remove the residual aluminum sacrificial layer and its surface adhesive residue.

2. The peeling method according to claim 1, characterized in that, In step S1, the thickness of the first photoresist layer is less than the thickness of the second photoresist layer in step S3; The thickness of the first photoresist layer is 1.2μm~1.8μm.

3. The peeling method according to claim 1, characterized in that, The thickness of the aluminum sacrificial layer in step S2 is 10nm~30nm; The surface roughness of the aluminum sacrificial layer is 1.8 nm to 2.2 nm.

4. The peeling method according to claim 1, characterized in that, The thickness of the second photoresist layer is ≥2.5μm.

5. The peeling method according to claim 1, characterized in that, The target metal layer in step S4 includes an aluminum film or an indium pillar.

6. The peeling method according to claim 5, characterized in that, The thickness of the aluminum film is 300nm~600nm; The height of the indium pillar is ≥5μm.

7. The peeling method according to claim 1, characterized in that, The stripping solution in step S5 includes NMP or acetone; The temperature of the stripping fluid is 60℃~80℃.

8. The peeling method according to claim 1, characterized in that, The solution used in step S6 to remove the residual aluminum sacrificial layer and its surface residue includes tetramethylammonium hydroxide solution or type A aluminum etching solution.

9. The peeling method according to claim 1, characterized in that, After step S6, the obtained chip is sequentially cleaned, dehydrated, and dried; The drying process includes protective gas drying or supercritical CO2 drying.

10. A superconducting quantum chip, characterized in that, The superconducting quantum chip is prepared by the stripping method described in any one of claims 1-9.

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