A process sheet and its preparation method and application method

Abstract

The application provides a process wafer and a preparation method and an application method thereof, and belongs to the technical field of semiconductor manufacturing. The process wafer comprises a substrate layer, the material of the substrate layer is silicon carbide with a purity greater than or equal to a preset purity, and a ceramic coating is arranged on the surface of the substrate layer, and the melting point of the ceramic coating is greater than or equal to a preset melting point. The technical scheme of the application can effectively inhibit the sublimation of the surface of the process wafer and reduce the risk of metal pollution.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a process wafer and its preparation and application methods. Background Technology

[0002] In the field of silicon carbide (SiC) device manufacturing, high-temperature activation annealing after ion implantation is a critical process step, typically carried out in an inert atmosphere (such as argon) at 1600°C to 1800°C. To maintain furnace tube cleanliness and thermal stability, a process wafer (also known as a dummy wafer, test wafer, or prototype wafer (DM)) needs to be introduced into the process, usually a SiC substrate wafer used as the DM.

[0003] However, existing SiC wafers exhibit the following significant drawbacks during repeated high-temperature activation: First, at temperatures above 1600℃, silicon atoms preferentially sublimate on the surface of the wafer, forming a carbon-rich layer (graphitized layer), leading to severe surface roughening. These graphitized layers may detach in subsequent processes, becoming particulate sources that contaminate the wafer and severely impact device yield. Second, at high temperatures, the diffusion activity of metallic impurities (such as iron (Fe), nickel (Ni), and chromium (Cr)) is significantly enhanced. The wafer surface easily adsorbs metallic impurities, which then diffuse into the gas phase during subsequent processes, contaminating the wafer, affecting the quality of the gate oxide layer, and causing device performance degradation. Third, existing wafers exhibit rapid surface degradation under high-temperature activation, resulting in a short lifespan. They typically require scrapping after no more than 50 cycles, leading to low material utilization and high costs.

[0004] Therefore, there is an urgent need to develop a process wafer that can effectively suppress surface sublimation, reduce the risk of metal contamination, and has a long lifespan. Summary of the Invention

[0005] This application provides a process sheet, its preparation method, and its application method, which can effectively inhibit surface sublimation of the process sheet and reduce the risk of metal contamination.

[0006] To achieve the above objectives, the technical solution adopted in the embodiments of this application is as follows: A process sheet, comprising: The substrate layer is made of silicon carbide with a purity greater than or equal to a preset purity. A ceramic coating is applied to the surface of the substrate layer, and the melting point of the ceramic coating is greater than or equal to a preset melting point.

[0007] In some embodiments, the substrate layer has a first coefficient of thermal expansion, the ceramic coating has a second coefficient of thermal expansion, and the difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion is less than a preset value.

[0008] In some embodiments, the ceramic coating includes at least one of the following: tantalum carbide, hafnium carbide, zirconium carbide, and niobium carbide.

[0009] In some embodiments, the ceramic coating is a single-layer structure, and the thickness of the ceramic coating is in the range of 1 μm to 10 μm.

[0010] In some embodiments, the ceramic coating is a multilayer structure composed of at least two materials, with the thickness of each layer ranging from 0.5 μm to 1 μm, and the total thickness of the ceramic coating ranging from 3 μm to 10 μm.

[0011] In some embodiments, the thickness of the substrate layer is in the range of 500 μm to 1000 μm.

[0012] In some embodiments, the density of the ceramic coating is greater than or equal to 98%, and / or the surface roughness of the ceramic coating is less than or equal to 1 nm.

[0013] This application also provides a method for preparing a process sheet, including: A substrate layer is provided, and the material of the substrate layer is silicon carbide with a purity greater than or equal to a preset purity; The surface of the substrate layer is pretreated, including cleaning and / or surface activation. A ceramic coating is deposited on the surface of the substrate layer, and the melting point of the ceramic coating is greater than or equal to the preset melting point.

[0014] In some embodiments, the ceramic coating is a tantalum carbide coating, which is deposited on the surface of the substrate layer to form the ceramic coating, including: A precursor is provided, comprising tantalum pentachloride and methane, wherein the molar ratio of tantalum pentachloride to methane is in the range of 1:2 to 1:5; Provide a carrier gas, which can be hydrogen or argon; Tantalum carbide coatings are formed by repeated precipitation within a temperature range of 1400°C to 1600°C and a pressure range of 50 Torr to 200 Torr.

[0015] In some embodiments, the ceramic coating is a hafnium carbide coating, which is deposited on the surface of the substrate layer to form the ceramic coating, including: A precursor is provided, comprising hafnium tetrachloride and methane, wherein the molar ratio of hafnium tetrachloride to methane is in the range of 1:1 to 1:1.2; Provide a carrier gas, which can be hydrogen or argon; Hafnium carbide coatings are formed by repeated precipitation within a temperature range of 1450°C to 1550°C and a pressure range of 15 Torr to 50 Torr.

[0016] In some embodiments, the ceramic coating is composed of a tantalum carbide coating and a hafnium carbide coating stacked together, and is deposited on the surface of the substrate layer to form the ceramic coating, including: A ceramic coating is formed by repeatedly performing tantalum carbide and hafnium carbide deposition steps in any order. The tantalum carbide layer deposition step includes: A precursor is provided, comprising tantalum pentachloride and methane, wherein the molar ratio of tantalum pentachloride to methane is in the range of 1:2 to 1:5; Provide a carrier gas, which can be hydrogen or argon; A tantalum carbide coating is formed by precipitation within a temperature range of 1400°C to 1600°C and a pressure range of 50 Torr to 200 Torr. The hafnium carbide layer deposition step includes: A precursor is provided, comprising hafnium tetrachloride and methane, wherein the molar ratio of hafnium tetrachloride to methane is in the range of 1:1 to 1:1.2; Provide a carrier gas, which can be hydrogen or argon; Hafnium carbide coatings are deposited within a temperature range of 1450°C to 1550°C and a pressure range of 15 Torr to 50 Torr.

[0017] In some embodiments, the method further includes: The process sheet is annealed for a preset duration in an argon atmosphere. The surface of the process sheet is chemically polished to reduce the surface roughness of the ceramic coating to 1 nm or less.

[0018] This application embodiment also provides a method for applying a process wafer, which is applied to the process wafer described above, including: The process wafer and the product wafer are placed in an annealing furnace for a high-temperature activation process. The product wafer is a wafer used in actual production. Surface condition inspection of the process sheet; When the surface condition of the process wafer is detected to meet the preset first condition, the target process is executed. The first condition includes at least one of the following: The amount of residual metal is greater than or equal to the first threshold. The thickness of the ceramic coating is less than or equal to the second threshold. Surface roughness is greater than or equal to the third threshold; The number of particles is greater than or equal to the fourth threshold; The target process includes: Remove the ceramic coating from the process sheet to expose the substrate layer of the process sheet; The exposed substrate layer is pretreated, including cleaning and / or surface activation. A ceramic coating is deposited on the surface of the substrate layer, and the melting point of the ceramic coating is greater than or equal to the preset melting point.

[0019] In some embodiments, the method for removing the ceramic coating of the process sheet includes: wet etching the ceramic coating of the process sheet in a temperature range of 80°C to 100°C, wherein the etching solution is a mixture of sulfuric acid and hydrogen peroxide; or, chemically mechanically polishing the surface of the process sheet.

[0020] In some embodiments, the method further includes: Based on the remaining thickness of the ceramic coating, the process sheets are divided into three grades: Grade 1, Grade 2, and Grade 3. The first-level process wafers are used for critical source / drain activation annealing processes, the second-level process wafers are used for non-critical processes, and the third-level process wafers are used to execute the target process. The first-level process sheet is defined as follows: the ratio of the remaining thickness of the ceramic coating to the initial thickness is greater than or equal to the first preset ratio. The second-level process sheet is: the ratio of the remaining thickness of the ceramic coating to the initial thickness is greater than the second preset ratio and less than the first preset ratio, and the second preset ratio is less than the first preset ratio; The third-level process sheet is defined as follows: the ratio of the remaining thickness of the ceramic coating to the initial thickness is less than or equal to the second preset ratio, or the coating has already peeled off.

[0021] The beneficial effects of this application are: In this embodiment, the process sheet is a composite structure consisting of a high-purity SiC substrate layer and a high-melting-point ceramic coating. During the high-temperature activation process, the high-melting-point ceramic coating on the surface of the process sheet can maintain chemical inertness in an ultra-high temperature environment, effectively inhibiting the sublimation and graphitization of the SiC substrate layer, eliminating particulate contamination sources from the source, reducing the risk of metal contamination, improving the service life of the process sheet, and reducing the cost of using the process sheet. Attached Figure Description

[0022] Figure 1 This is a schematic diagram showing the structure of the process sheet according to an embodiment of this application; Figure 2 A schematic flowchart illustrating the preparation method of the process sheet according to an embodiment of this application; Figure 3 A schematic diagram illustrating the process of depositing and forming a tantalum carbide coating according to an embodiment of this application; Figure 4 A schematic diagram illustrating the process of depositing a hafnium carbide coating according to an embodiment of this application; Figure 5This diagram illustrates the post-processing steps in an embodiment of this application. Figure 6 This is a flowchart illustrating the application method of the process sheet according to an embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application are within the scope of protection of this application.

[0024] To address the aforementioned technical problems, this application provides a process sheet, its preparation method, and its application method, which can effectively suppress surface sublimation of the process sheet and reduce the risk of metal contamination.

[0025] like Figure 1 As shown, this application provides a process sheet, including a substrate layer 100 and a ceramic coating 200.

[0026] The substrate layer 100 is made of silicon carbide (SiC) with a purity greater than or equal to a preset purity.

[0027] For example, the preset purity is 99.999%, that is, the substrate layer 100 is composed of high-purity SiC, and the purity of high-purity SiC is greater than or equal to 99.999%.

[0028] In some specific embodiments, the thickness of the substrate layer 100 is in the range of 500 μm to 1000 μm.

[0029] like Figure 1 As shown, a ceramic coating 200 is disposed on the surface of the substrate layer 100, and the melting point of the ceramic coating 200 is greater than or equal to a preset melting point.

[0030] For example, the preset melting point can be 3800°C. That is to say, the ceramic coating 200 is an ultra-high temperature ceramic coating.

[0031] For example, the ceramic coating 200 includes at least one of the following: tantalum carbide (TaC), hafnium carbide (HfC), zirconium carbide (ZrC), and niobium carbide (NbC).

[0032] It should be noted that the ceramic coating 200 may be composed of one or more of the above-mentioned ceramic materials.

[0033] In this embodiment, the process sheet is a composite structure consisting of a high-purity SiC substrate layer 100 and a high-melting-point ceramic coating 200. During the high-temperature activation process, the high-melting-point ceramic coating 200 on the surface of the process sheet can maintain chemical inertness under ultra-high temperature conditions, effectively inhibiting the sublimation and graphitization of the SiC substrate layer 100, eliminating particulate contamination sources from the source, reducing the risk of metal contamination, improving the service life of the process sheet, and reducing the cost of using the process sheet.

[0034] In some embodiments, the substrate layer 100 has a first coefficient of thermal expansion, the ceramic coating 200 has a second coefficient of thermal expansion, and the difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion is less than a preset value.

[0035] It should be noted that, in this embodiment, the first coefficient of thermal expansion of the material used in the substrate layer 100 needs to match the second coefficient of thermal expansion of the ceramic material used in the ceramic coating 200; that is, the difference between the two needs to be less than a preset value to prevent the ceramic coating 200 from peeling off during thermal cycling. For example, the preset value ranges from 0.5 × 10⁻⁶. -6 / K to -1.5×10 -6 / K. For example, the first coefficient of thermal expansion is approximately 4.5 × 10⁻⁶. -6 / K, the second coefficient of thermal expansion is 4×10 -6 / K to 6×10 -6 Within the range of / K.

[0036] In this embodiment, the ceramic coating 200 serves as the outer layer of the process sheet that directly contacts the process environment. Exemplarily, the ceramic coating 200 possesses the following characteristics: a melting point greater than or equal to 3800°C; the ability to maintain chemical stability and structural integrity during SiC high-temperature activation processes at 1600-1800°C; the thermal expansion coefficient of the ceramic material used in the ceramic coating 200 matches the thermal expansion coefficient of the material used in the substrate layer 100 (i.e., the difference between the two is less than a preset value); and a dense self-passivating layer is formed at high temperatures, preventing impurities in the substrate layer 100 from diffusing outwards and simultaneously blocking external contaminants from penetrating into the substrate layer 100.

[0037] In some embodiments, the ceramic coating 200 is a single-layer structure, and the thickness of the ceramic coating 200 is in the range of 1 μm to 10 μm.

[0038] In other words, the ceramic coating 200 in this embodiment can be a single-layer structure composed of ceramic material. For example, the ceramic coating 200 is a single-layer hafnium carbide coating or a single-layer tantalum carbide coating. Exemplarily, the thickness of the single-layer ceramic coating 200 ranges from 1 μm to 10 μm.

[0039] In some embodiments, the ceramic coating 200 is a multilayer structure composed of at least two materials, with the thickness of each layer ranging from 0.5 μm to 1 μm, and the total thickness of the ceramic coating 200 ranging from 3 μm to 10 μm.

[0040] In other words, the ceramic coating 200 in this embodiment can also be a multilayer composite structure composed of two or more ceramic materials. For example, the ceramic coating 200 can be a multilayer structure composed of alternating layers of tantalum carbide (TaC) and hafnium carbide (HfC).

[0041] In one specific embodiment, five layers each of tantalum carbide (TaC) and hafnium carbide (HfC) can be alternately deposited on the surface of the substrate layer 100 to form a ceramic coating 200, wherein each layer has a thickness of 0.6 μm, and the total thickness of the ceramic coating 200 is 6 μm. Experiments show that after 100 thermal cycles (e.g., cycling between room temperature and 1700°C) of the process wafer formed in this manner, the ceramic coating 200 did not peel off, the surface roughness Ra of the process wafer was 0.7 nm, and its resistance to crack propagation was superior to that of the ceramic coating 200 composed of a single material.

[0042] In some embodiments, the density of the ceramic coating 200 is greater than or equal to 98%, and / or the surface roughness Ra of the ceramic coating 200 is less than or equal to 1 nm.

[0043] It should be noted that the ceramic coating 200 can be made of high-melting-point dense ceramic material. High melting point means that this material has the characteristic of high temperature resistance, and dense means that this material has a compact texture.

[0044] In this embodiment, the ceramic coating 200 on the process wafer maintains chemical and structural stability during the high-temperature activation process at 1600~1800℃, effectively inhibiting sublimation and graphitization on the SiC substrate surface. Test results show that the surface roughness remains stably below 1.0 nm under the protection of the ceramic coating 200, while the surface roughness of the SiC substrate without the ceramic coating 200 protection deteriorates to above 50 nm, thus preventing particulate contamination caused by graphitization layer shedding from the source. The dense ceramic coating 200 forms a stable diffusion barrier layer, significantly inhibiting the diffusion of metal impurities from the furnace tube to the product wafer, effectively reducing the risk of metal contamination. Experiments show that after high-temperature activation, the metal residue on the surface of the product wafer in this embodiment is reduced by about 80%, effectively improving process cleanliness and device yield. By using a ceramic coating 200 with a coefficient of thermal expansion matching the substrate, combined with the multilayer composite structure design of the ceramic coating 200, the process wafer can maintain structural integrity during repeated high-temperature cycling. Experiments show that the ceramic coating of the process sheet in this application embodiment does not peel off after 100 thermal cycles, demonstrating excellent thermal shock resistance.

[0045] like Figure 2As shown in the embodiments of this application, a method for preparing a process sheet is also provided, comprising: Step 201: Provide a substrate layer, wherein the substrate layer 100 is made of silicon carbide with a purity greater than or equal to a preset purity.

[0046] In other words, the substrate layer 100 can be prepared using silicon carbide with a purity greater than or equal to the preset purity.

[0047] For example, in step 201, a high-purity SiC substrate layer 100 is provided, which is mechanically processed to form a disc shape with a thickness of 500 μm and a surface roughness Ra≤0.5 μm.

[0048] Step 202: Pre-treat the surface of the substrate layer 100. The pre-treatment includes cleaning treatment (such as RCA cleaning) and / or surface activation treatment (such as argon plasma treatment).

[0049] Specifically, the cleaning process involves sequentially using acetone, isopropanol, and deionized water for ultrasonic cleaning, followed by RCA standard cleaning to remove contaminants from the surface of the substrate layer 100. Afterward, argon plasma treatment is used to activate the surface of the substrate layer 100, improving the adhesion between the ceramic coating 200 and the substrate layer 100. For example, the radio frequency power in the surface activation treatment is in the range of 300W to 500W, and the treatment time is approximately 2 to 5 minutes.

[0050] Step 203: A ceramic coating 200 is deposited on the surface of the substrate layer 100, wherein the melting point of the ceramic coating 200 is greater than or equal to a preset melting point.

[0051] Here, a chemical vapor deposition (CVD) process can be used to deposit a ceramic coating 200 on the surface of the substrate layer 100. For example, the deposition temperature in this process is in the range of 1400°C to 1700°C.

[0052] In this embodiment, a composite structure process wafer is prepared by combining a high-purity SiC substrate layer with a high-melting-point ceramic coating. This allows the ceramic coating to maintain chemical and structural stability during the high-temperature activation process, effectively inhibiting the sublimation and graphitization of the SiC substrate layer. This keeps the surface roughness of the process wafer stably below 1.0 nm, fundamentally avoiding particulate contamination caused by graphitization layer shedding. In addition, the ceramic coating can form a diffusion barrier layer, inhibiting the migration of metal impurities from the furnace tube to the product wafer. This significantly reduces the amount of residual metal on the surface of the product wafer after high-temperature activation, improving process cleanliness and device yield, increasing the service life of the process wafer, and reducing the cost of using the process wafer.

[0053] like Figure 3As shown, in some embodiments, the ceramic coating 200 can be a tantalum carbide coating. The ceramic coating 200 is deposited on the surface of the substrate layer to form the ceramic coating, which may specifically include the following steps: Step 301: Provide a precursor comprising tantalum pentachloride (TaCl5) and methane (CH4), wherein the molar ratio of tantalum pentachloride to methane is in the range of 1:2 to 1:5; Step 302: Provide a carrier gas, which may be hydrogen or argon; Step 303: Repeatedly deposit tantalum carbide coating within a temperature range of 1400°C to 1600°C and a pressure range of 50 Torr to 200 Torr.

[0054] Here, Torr is a unit of pressure, 1 Torr ≈ 1 millimeter of mercury (mmHg).

[0055] In a specific example, when depositing a tantalum carbide (TaC) ceramic coating 200, the precursors include TaCl5 (evaporated by heating to 200°C to 300°C) and CH4, the carrier gas is H2, the total flow rate is in the range of 10 slm to 30 slm, the deposition temperature is in the range of 1400°C to 1600°C, the deposition pressure is in the range of 50 Torr to 200 Torr, the molar ratio of TaCl5 to methane is in the range of 1:2 to 1:5, the deposition time is in the range of 30 minutes to 120 minutes, and the deposition thickness is in the range of 1 μm to 10 μm.

[0056] like Figure 4 As shown, in some embodiments, the ceramic coating 200 can be a hafnium carbide coating. The ceramic coating 200 is deposited on the surface of the substrate layer to form the ceramic coating 200, which may specifically include the following steps: Step 401: Provide a precursor comprising hafnium tetrachloride and methane, wherein the molar ratio of hafnium tetrachloride to methane is in the range of 1:1 to 1:1.2; Step 402: Provide a carrier gas, which may be hydrogen or argon; Step 403: Repeatedly deposit hafnium carbide coating in a temperature range of 1450°C to 1550°C and a pressure range of 15 Torr to 50 Torr.

[0057] It should be noted that a lower deposition pressure is used here to better control the discharge of byproducts and prevent the hydrogen chloride (HCl) in the byproducts from reacting with the SiC substrate.

[0058] In some embodiments, the ceramic coating is composed of a tantalum carbide coating and a hafnium carbide coating stacked together, and the ceramic coating is deposited on the surface of the substrate layer to form the ceramic coating, including: performing the tantalum carbide layer deposition step and the hafnium carbide layer deposition step multiple times in any order to form the ceramic coating.

[0059] The tantalum carbide layer deposition step includes: providing a precursor comprising tantalum pentachloride and methane, wherein the molar ratio of tantalum pentachloride to methane is in the range of 1:2 to 1:5; providing a carrier gas, wherein the carrier gas is hydrogen or argon; and precipitating to form a tantalum carbide coating in a temperature range of 1400°C to 1600°C and a pressure range of 50 Torr to 200 Torr. The hafnium carbide layer deposition step includes: providing a precursor comprising hafnium tetrachloride and methane, wherein the molar ratio of hafnium tetrachloride to methane is in the range of 1:1 to 1:1.2; providing a carrier gas, wherein the carrier gas is hydrogen or argon; and precipitating to form a hafnium carbide coating in a temperature range of 1450°C to 1550°C and a pressure range of 15 Torr to 50 Torr.

[0060] In this embodiment, the order in which the tantalum carbide layer deposition step and the hafnium carbide layer deposition step are performed can be random or follow a specific pattern (such as alternating between them), and no specific limitation is made here. It is understood that the ceramic coating prepared by this embodiment includes at least one tantalum carbide coating and one hafnium carbide coating, and may also include multiple layers, specifically determined by the execution order of the tantalum carbide layer deposition step and the hafnium carbide layer deposition step.

[0061] It is understandable that this explanation only uses a ceramic coating composed of tantalum carbide and hafnium carbide as an example. In practical applications, the ceramic coating can use any one or more of the following materials: tantalum carbide, hafnium carbide, zirconium carbide, and niobium carbide.

[0062] like Figure 5 As shown, in some embodiments, the method further includes the following post-processing steps: Step 501: Perform a pre-set annealing treatment on the process sheet in an argon atmosphere.

[0063] For example, the preset duration is in the range of 1 to 2 hours.

[0064] In a specific example, after the chemical vapor deposition process, the process sheet can be annealed for 1 to 2 hours in an Ar atmosphere at 1600-1800°C to eliminate the internal stress of the ceramic coating and improve the density of the process sheet.

[0065] Step 502: Perform chemical polishing on the surface of the process sheet to reduce the surface roughness of the ceramic coating 200 to 1 nm or less.

[0066] In one specific embodiment, high-purity SiC is provided as a substrate layer 100, with a thickness of 700 μm, a diameter of 200 mm, a purity of 99.9995%, and a surface roughness Ra of 0.4 μm. After pretreatment of the substrate layer 100 (such as RCA cleaning and argon plasma treatment), a TaC ceramic coating 200 is deposited on the surface of the substrate layer 100 using a chemical vapor deposition process. Exemplarily, in this chemical vapor deposition process, the precursor includes tantalum pentachloride (TaCl5) (heated to 250°C to evaporate), with a flow rate of 50 sccm, a CH4 flow rate of 150 sccm, an H2 flow rate of 20 slm, a deposition temperature of 1500°C, a deposition pressure of 100 Torr, a deposition time of 60 minutes, and a deposition thickness (i.e., the thickness of the ceramic coating 200) of 5 μm. After the chemical vapor deposition process is completed, the wafer is annealed at 1700°C for 1.5 hours in an Ar atmosphere, and then chemical mechanical polishing (CMP) is performed on the wafer. The surface roughness Ra of the wafer is 0.6 nm and the density is 98.5%.

[0067] In another specific embodiment, the ceramic coating 200 uses hafnium carbide (HfC), with hafnium tetrachloride (HfCl4) as a precursor. The deposition temperature is 1600°C, and the deposition thickness is 5 μm. Other conditions are the same as in the previous embodiment. Experiments show that, tested in the same high-temperature activation process, the substrate layer 100 can be used 23 times per cycle, the ceramic coating 200 can be used an average of 52 times per cycle, and the entire process wafer can be used a total of 1196 times. The surface roughness of the process wafer remains below 0.8 nm, and its thermal shock resistance is comparable to that of the TaC ceramic coating 200.

[0068] like Figure 6 As shown, this application embodiment also provides a method for applying a process wafer to the process wafer described above, including: Step 601: Place the process wafer and the product wafer into an annealing furnace for a high-temperature activation process. The product wafer is a wafer used in actual production.

[0069] For example, in step 601, the process temperature of the high-temperature activation process is in the range of 1600°C to 1800°C, the atmosphere is Ar, and the processing time is in the range of 30 to 120 minutes.

[0070] Step 602: Surface condition inspection of the process sheet.

[0071] Here, indicators such as the amount of residual metal on the surface of the process sheet, the thickness of the ceramic coating 200, the surface roughness, and the number of particles can be detected to determine whether the target process needs to be executed.

[0072] Step 603: When the surface condition of the process wafer is detected to meet the preset first condition, the target process is executed.

[0073] The first condition includes at least one of the following: (1) The amount of metal residue is greater than or equal to the first threshold; Here, the first threshold represents the warning value reached by the ceramic coating 200 adsorbing metal impurities. If the metal residue is greater than or equal to the first threshold, it indicates that the process sheet has a high risk of metal contamination.

[0074] For example, the first threshold can be 1.0 × 10 10 atoms / cm 2 .

[0075] (2) The thickness of the ceramic coating 200 is less than or equal to the second threshold; Here, the second threshold represents the critical physical thickness required to maintain the effectiveness of the protective function of the ceramic coating 200. If the thickness of the ceramic coating 200 is lower than or equal to the second threshold, it indicates that the protective performance of the ceramic coating 200 has significantly deteriorated.

[0076] For example, the second threshold can be 0.5 μm.

[0077] (3) The surface roughness is greater than or equal to the third threshold; Here, the third threshold represents the critical value of the surface roughness of the ceramic coating 200. If the surface roughness of the ceramic coating 200 is greater than or equal to the third threshold, it indicates that the coating structure of the ceramic coating 200 has degraded and the coating has peeled off, resulting in an excessively rough surface. Continued use may exacerbate contamination.

[0078] For example, the third threshold could be 1 nm.

[0079] (4) The number of particles is greater than or equal to the fourth threshold.

[0080] Here, the fourth threshold represents the upper limit of particulate contamination allowed on the surface of the process sheet. If the number of particles is greater than or equal to the fourth threshold, it indicates that the process sheet no longer meets the requirements for process cleanliness.

[0081] For example, the fourth threshold can be 50 particles with a particle diameter ≥ 0.2 μm, that is, the process cleanliness requirement: the number of particles with a particle diameter ≥ 0.2 μm is at most 50.

[0082] It is understood that the first threshold, the second threshold, the third threshold and the fourth threshold can all be set according to the actual production situation. The above are just illustrative examples and the embodiments of this application are not limited thereto.

[0083] In this embodiment, by detecting indicators such as the amount of residual metal, the thickness of the ceramic coating 200, the surface roughness, and the number of particles on the surface of the process sheet, when any one of these indicators exceeds the corresponding threshold, the target process (i.e., the regeneration process) is executed on the process sheet. This means removing the ceramic coating 200 from the process sheet to expose its substrate layer 100, and then redepositing the ceramic coating 200 on the surface of the substrate layer 100, thereby achieving the regeneration of the process sheet.

[0084] In other specific embodiments, the target process can be executed on the process wafer after it has been used a predetermined number of times. This predetermined number of times can be set based on actual production experience. For example, the predetermined number of times is 100 to 200 times.

[0085] In a specific example, the target process includes: Step 1: Remove the ceramic coating 200 from the process sheet to expose the substrate layer 100 of the process sheet.

[0086] Here, a selective removal process can be used to remove (peel off) the ceramic coating 200 on the surface of the process sheet.

[0087] Step 2: Pre-treat the exposed substrate layer 100. The pre-treatment includes cleaning and / or surface activation.

[0088] Step 3: A ceramic coating 200 is deposited on the surface of the substrate layer 100, and the melting point of the ceramic coating 200 is greater than or equal to the preset melting point.

[0089] In step three, a ceramic coating 200 can be redeposited on the surface of the substrate layer 100 using a chemical vapor deposition process to form a regenerated process sheet (i.e., the regenerated process sheet). Chemical vapor deposition is a material preparation technology that utilizes a gaseous precursor to undergo a chemical reaction on the substrate surface to generate a solid thin film or ceramic coating 200.

[0090] In this embodiment, by introducing a multi-dimensional state detection mechanism based on metal residue, ceramic coating thickness, surface roughness, and particle count, the service wear of the process wafer in the high-temperature activation process can be accurately quantified, effectively avoiding material waste caused by blind replacement or process contamination caused by excessive wear. When the surface state meets the preset first condition, the target process is automatically executed to obtain a new process wafer. This method breaks the limitation of the traditional homogeneous process wafer being scrapped as a whole, realizes the reuse of high-purity SiC substrate and timely replacement of ceramic coating, significantly extends the cumulative service life of the process wafer, and significantly reduces consumable consumption and production costs.

[0091] In one specific embodiment, the process wafer provided in this application and the SiC product wafer are loaded together into a high-temperature annealing furnace for a high-temperature activation process. For example, the temperature is 1700°C, the atmosphere is Ar, and the processing time is 60 minutes. After the high-temperature activation process, it was found that no graphitization layer was formed on the surface of the process wafer, the surface roughness Ra = 0.7 nm, and the residual metal content Fe = 3 × 10⁻⁶. 9 atoms / cm 2 .

[0092] After 50 high-temperature activation cycles using this process wafer, surface inspection revealed that the remaining thickness of the ceramic coating 200 was 3.2 μm, the surface roughness Ra = 1.2 nm, and the residual metal Fe = 8 × 10⁻⁶. 9 atoms / cm 2 The particle count is 65 particles / piece, and a regeneration process (i.e., the target process) is performed on this process piece.

[0093] For example, in this regeneration process, a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (volume ratio 4:1) is used to etch the process wafer at 100°C for 30 minutes, which can completely remove the ceramic coating 200 (such as TaC ceramic coating 200) of the process wafer and expose the substrate layer 100.

[0094] Subsequently, after cleaning and activation treatment of the exposed aggregate layer, a ceramic coating 200 is redeposited to form a regenerated process sheet. The parameters used when depositing the ceramic coating 200 are similar to those in the embodiments described above for preparing the process sheet. Experiments show that the surface roughness Ra of the regenerated process sheet in this embodiment is 0.6 nm, and its performance is restored to its initial state.

[0095] It should be noted that after performing a cycle life test (i.e., repeatedly executing the above-described ceramic coating 200 peeling and regeneration process) on the process wafer provided in this application embodiment, the test results show that after 25 consecutive regeneration cycles, the substrate layer 100 of the process wafer in this application embodiment still maintains structural integrity without thickness loss, microcracks, or interface peeling; the average service life of each prepared ceramic coating 200 is 100-200 cycles. Through cumulative process verification, the total service life of the process wafer provided in this application embodiment can reach more than 2500-5000 cycles, which is significantly better than traditional homogeneous SiC process wafers (the conventional lifespan is usually less than 50 cycles) and also better than coated carbon films (the conventional lifespan is about 500 cycles). It can avoid the process of repeatedly coating carbon films, improve the utilization rate of the high-temperature activation furnace, and fully verify the long-term stability and regeneration feasibility of the permanent load-bearing substrate and replaceable surface structure in this application embodiment.

[0096] Experimental results show that, using a conventional homogeneous SiC wafer (500 μm thick, 99.999% purity), after 55 cycles of use with the same high-temperature activation annealing process as in the embodiments of this application, a significant graphitization layer appears on the surface, with a surface roughness Ra greater than 50 nm and a particle count greater than 200 particles per wafer, rendering it unusable. Similarly, using a SiC wafer coated with a C film (500 μm thick, C film thickness 0.2 μm, SiC purity 99.999%), after 20 cycles of repeated C film coating with the same high-temperature activation annealing process as in the embodiments of this application, a significant graphitization layer also appears on the surface, with a surface roughness Ra greater than 10 nm and a particle count greater than 200 particles per wafer, rendering it unusable.

[0097] It should be noted that high-purity SiC materials are expensive, and existing technologies scrap the entire process wafer, resulting in low material utilization and increased factory operating costs.

[0098] In this embodiment, the ceramic coating 200 is recyclable, making the substrate layer 100 reusable. This transforms the traditional SiC process wafer from a disposable material into a new structure where the substrate layer 100 is permanently usable and the ceramic coating 200 is recyclable. This improves the overall service life of the process wafer, reduces its material cost, and has significant industrial value.

[0099] In some embodiments, the method for removing the ceramic coating 200 of the process wafer includes: wet etching the ceramic coating 200 of the process wafer at a temperature range of 80°C to 100°C, wherein the etching solution is a mixture of sulfuric acid and hydrogen peroxide; or, chemically and mechanically polishing the surface of the process wafer to remove the ceramic coating 200 from the surface of the process wafer, thereby exposing the substrate layer 100.

[0100] For example, when using wet etching to remove the ceramic coating 200 of the process wafer, a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) is used to remove the ceramic coating 200 at a preset temperature (within the temperature range of 80°C to 100°C).

[0101] In one specific embodiment, CMP is used to remove the ceramic coating 200, wherein the preset temperature is 100°C and the polishing pressure is 300 g / cm. 2 A polishing slurry containing diamond abrasive was used at a removal rate of 0.5 μm / min for 12 minutes to remove a 6 μm ceramic coating 200. Experiments showed that the performance of the wafer after CMP removal of the ceramic coating 200 and subsequent regeneration (the target process) was comparable to that after wet etching and regeneration, with superior surface smoothness.

[0102] In some embodiments, the method further includes: Based on the remaining thickness of the ceramic coating 200, the process sheets are divided into first grade, second grade and third grade; The first-level process wafers are used for critical source / drain activation annealing processes, the second-level process wafers are used for non-critical processes, and the third-level process wafers are used to execute the target process. The first-level process sheet is characterized by a ratio of the remaining thickness of the ceramic coating 200 to the initial thickness that is greater than or equal to a first preset ratio. The second-level process sheet is: the ratio of the remaining thickness of the ceramic coating 200 to the initial thickness is greater than the second preset ratio and less than the first preset ratio, and the second preset ratio is less than the first preset ratio. The third-level process sheet is characterized by the ratio of the remaining thickness of the ceramic coating 200 to the initial thickness being less than or equal to the second preset ratio, or by the coating peeling phenomenon already occurring.

[0103] The purpose of introducing the first and second preset ratios here is to achieve graded utilization of process wafers, making risks controllable. Specifically, the first preset ratio is used to determine whether the process wafer still meets the cleanliness and surface integrity requirements of the critical source leak activation annealing process, ensuring that the highest-level process wafers can be used in core processes. The second preset ratio is used to set a safety line for process wafers that can be downgraded. That is, provided that the ceramic coating 200 has suffered some damage but has not lost its protective function, such process wafers are allowed to be used in non-critical processes, thereby maximizing the utilization of consumables without affecting the final yield. Once a process wafer is classified as level three, it means that it is no longer safe to use the process wafer and it needs to be regenerated by executing the target process.

[0104] Based on the above hierarchical management logic, for example, the first preset ratio can be set to 80% to distinguish the service boundary of the process sheet in critical and non-critical processes, and the second preset ratio can be set to 50% to define whether the ceramic coating 200 of the process sheet has reached the critical point where it must be regenerated.

[0105] In this embodiment, the service life of the process wafer is significantly extended, and the regeneration cost of the process wafer is greatly reduced. Specifically, the substrate layer 100 can be continuously recycled more than 20 times, and the average service life of a single ceramic coating 200 reaches 100-200 process cycles, significantly increasing the total number of service cycles of the overall process wafer. When the surface condition of the process wafer meets the preset first condition, the ceramic coating 200 can be peeled off by selective wet etching or chemical mechanical polishing. After cleaning and activating the exposed substrate layer 100, a ceramic coating can be redeposited on the surface of the substrate layer 100. This regeneration process effectively avoids the thickness loss and surface degradation problems caused by the overall scrapping or multiple mechanical polishing of traditional process wafers. Experimental verification shows that the application method of the process wafer provided in this embodiment can significantly improve the utilization rate of the substrate material, reduce the overall cost by about 60%, and effectively improve the economy and sustainability of industrial production.

[0106] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0107] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0108] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0109] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0110] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A process sheet, characterized in that, include: The substrate layer is made of silicon carbide with a purity greater than or equal to a preset purity. A ceramic coating is disposed on the surface of the substrate layer, wherein the melting point of the ceramic coating is greater than or equal to a preset melting point.

2. The process sheet according to claim 1, characterized in that, The substrate layer has a first coefficient of thermal expansion, and the ceramic coating has a second coefficient of thermal expansion. The difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion is less than a preset value.

3. The process sheet according to claim 1 or 2, characterized in that, The ceramic coating includes at least one of the following: tantalum carbide, hafnium carbide, zirconium carbide, and niobium carbide.

4. The process sheet according to claim 1 or 2, characterized in that, The ceramic coating is a single-layer structure, and the thickness of the ceramic coating is in the range of 1 μm to 10 μm.

5. The process sheet according to claim 1 or 2, characterized in that, The ceramic coating is a multilayer structure composed of at least two materials, with the thickness of each layer ranging from 0.5 μm to 1 μm, and the total thickness of the ceramic coating ranging from 3 μm to 10 μm.

6. The process sheet according to claim 1 or 2, characterized in that, The thickness of the substrate layer is in the range of 500 μm to 1000 μm.

7. The process sheet according to claim 1 or 2, characterized in that, The density of the ceramic coating is greater than or equal to 98%, and / or the surface roughness of the ceramic coating is less than or equal to 1 nm.

8. A method for preparing a process sheet, characterized in that, include: A substrate layer is provided, wherein the material of the substrate layer is silicon carbide with a purity greater than or equal to a preset purity; The surface of the substrate layer is pretreated, and the pretreatment includes: cleaning treatment and / or surface activation treatment; A ceramic coating is deposited on the surface of the substrate layer, wherein the melting point of the ceramic coating is greater than or equal to a preset melting point.

9. The method according to claim 8, characterized in that, The ceramic coating is a tantalum carbide coating, and the deposition of the ceramic coating on the surface of the substrate layer includes: A precursor is provided, the precursor comprising tantalum pentachloride and methane, wherein the molar ratio of tantalum pentachloride to methane is in the range of 1:2 to 1:5; Provide a carrier gas, wherein the carrier gas is hydrogen or argon; The tantalum carbide coating is formed by repeated precipitation within a temperature range of 1400°C to 1600°C and a pressure range of 50 Torr to 200 Torr.

10. The method according to claim 8, characterized in that, The ceramic coating is a hafnium carbide coating, and the deposition of the ceramic coating on the surface of the substrate layer includes: A precursor is provided, the precursor comprising hafnium tetrachloride and methane, wherein the molar ratio of hafnium tetrachloride to methane is in the range of 1:1 to 1:1.2; Provide a carrier gas, wherein the carrier gas is hydrogen or argon; The hafnium carbide coating is formed by repeated precipitation within a temperature range of 1450°C to 1550°C and a pressure range of 15 Torr to 50 Torr.

11. The method according to claim 8, characterized in that, The ceramic coating is composed of a tantalum carbide coating and a hafnium carbide coating stacked together, wherein the deposition of the ceramic coating on the surface of the substrate layer includes: The ceramic coating is formed by repeatedly performing tantalum carbide layer deposition and hafnium carbide layer deposition steps in any order. The tantalum carbide layer deposition step includes: A precursor is provided, the precursor comprising tantalum pentachloride and methane, wherein the molar ratio of tantalum pentachloride to methane is in the range of 1:2 to 1:5; Provide a carrier gas, wherein the carrier gas is hydrogen or argon; A tantalum carbide coating is formed by precipitation within a temperature range of 1400°C to 1600°C and a pressure range of 50 Torr to 200 Torr. The hafnium carbide layer deposition step includes: A precursor is provided, the precursor comprising hafnium tetrachloride and methane, wherein the molar ratio of hafnium tetrachloride to methane is in the range of 1:1 to 1:1.2; Provide a carrier gas, wherein the carrier gas is hydrogen or argon; Hafnium carbide coatings are deposited within a temperature range of 1450°C to 1550°C and a pressure range of 15 Torr to 50 Torr.

12. The method according to any one of claims 8 to 11, characterized in that, The method further includes: The process sheet is subjected to an annealing treatment of a preset duration, which is carried out in an argon atmosphere. The surface of the process sheet is chemically polished to reduce the surface roughness of the ceramic coating to 1 nm or less.

13. A method for applying a process sheet, characterized in that, Applied to the process wafer as described in any one of claims 1 to 7, comprising: The process wafer and the product wafer are placed in an annealing furnace for a high-temperature activation process. The product wafer is a wafer used in actual production. The surface condition of the process sheet is inspected; When the surface condition of the process wafer is detected to meet the preset first condition, the target process is executed. The first condition includes at least one of the following: The amount of residual metal is greater than or equal to the first threshold. The thickness of the ceramic coating is less than or equal to the second threshold. Surface roughness is greater than or equal to the third threshold; The number of particles is greater than or equal to the fourth threshold; The target process includes: Remove the ceramic coating from the process sheet to expose the substrate layer of the process sheet; The exposed substrate layer is pretreated, the pretreatment including: cleaning and / or surface activation. A ceramic coating is deposited on the surface of the substrate layer, wherein the melting point of the ceramic coating is greater than or equal to a preset melting point.

14. The method according to claim 13, characterized in that, The method for removing the ceramic coating from the process sheet includes: The ceramic coating of the process wafer is wet-etched within a temperature range of 80°C to 100°C, wherein the etching solution is a mixture of sulfuric acid and hydrogen peroxide. Alternatively, the surface of the process sheet may be chemically and mechanically polished.

15. The method according to claim 13, characterized in that, The method further includes: Based on the remaining thickness of the ceramic coating, the process sheet is divided into a first grade, a second grade, and a third grade; The first-level process wafer is used for the critical source / drain activation annealing process, the second-level process wafer is used for non-critical processes, and the third-level process wafer is used to execute the target process. The first-level process sheet is characterized by a ratio of the remaining thickness of the ceramic coating to the initial thickness that is greater than or equal to a first preset ratio. The second-level process sheet is characterized by the following: the ratio of the remaining thickness of the ceramic coating to the initial thickness is greater than a second preset ratio and less than a first preset ratio, wherein the second preset ratio is less than the first preset ratio. The third-level process sheet is defined as follows: the ratio of the remaining thickness of the ceramic coating to the initial thickness is less than or equal to the second preset ratio, or the coating has already peeled off.

Images