Patterning process method

Abstract

The application discloses a kind of patterning process methods, comprising: step one, the first film layer of needing patterning is formed on the bottom structure.Step two, SOC layer, SiARC layer and photoresist are coated in turn.Step three, photoetching is carried out to form first opening in photoresist.Step four, first etching is carried out, and first etching is etched to SOC layer, SiARC layer and first film layer in turn, to transfer the pattern of first opening to first film layer and form second opening in first film layer.Step five, photoresist, SiARC layer and SOC layer are removed.Step six, the second film layer that second opening is completely filled is formed, and the material of second film layer and the material of first film layer are different.Step seven, second etching is carried out to remove first film layer, and form the pattern structure composed of second film layer.Step eight, second film layer is trimmed to adjust the critical dimension of second film layer.The application can obtain pattern smaller than the limit of photoetching process, can eliminate pattern missing defect and improve CDU.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a patterning process method. Background Technology

[0002] As advanced process technology nodes evolve, the height of circuit cells, such as 6T cells, continues to shrink, and the size of the patterned mid-section metal layer also continues to shrink. Furthermore, as process nodes shrink, the pattern size tends to approach the limits of lithography and ion implantation (IMP) processes.

[0003] Current mid-section metal layer patterning processes employ a Litho -> Etching (ET) -> IMP approach, utilizing the different ET rates of boron-doped amorphous silicon (A-Si) in ammonia water to form pattern islands of varying sizes on A-Si. However, experimental data from process window analysis using CD size reduction shows that when the pattern is further scaled down using lithography or ET, there is a risk of insufficient IMP injection due to the small openings of the pattern islands, leading to island missing. Simultaneously, boron (B) IMP injection results in disordered diffusion, causing poor uniformity (U%) of the CDU (critical dimension duplex) when the target value of the pattern is reached. Therefore, the current Litho -> ET -> IMP patterning process has technological limitations, making it impossible to achieve smaller sizes without more advanced lithography equipment.

[0004] like Figures 1 to 5 The diagram shown illustrates the device structure in each step of the existing patterning process. The existing patterning process uses the Litho-Etch-IMP method to define the pattern, including the following steps: like Figure 1 As shown, an amorphous silicon layer 105 is formed on the underlying structure.

[0005] The underlying structure includes a first dielectric layer 102 formed on a semiconductor substrate (not shown).

[0006] The first dielectric layer 102 includes an oxide layer, such as a PEOX oxide layer formed by a PECVD process. A nitride layer 101 is also formed at the bottom of the first dielectric layer 102.

[0007] A hard mask layer is also formed on the top surface of the first dielectric layer 102. In some embodiments, the hard mask layer includes a second TiN layer 103 and a third oxide layer 104 stacked sequentially.

[0008] like Figure 1As shown, SOC layer 106, SiARC layer 107 and photoresist 108 are coated sequentially.

[0009] like Figure 2 As shown, exposure and development are performed to form a first opening 109 in the photoresist 108.

[0010] like Figure 3 As shown, the SiARC layer 107 and the SOC layer 106 are etched sequentially to form a second opening 110 at the bottom of the first opening 109 that passes through the SiARC layer 107 and the SOC layer 106.

[0011] like Figure 4 As shown, boron-containing ion implantation is performed to form a doped region in the amorphous silicon layer 105 at the bottom of the second opening 110. Figure 4 In the diagram, the ion implantation is shown as arrow line 111.

[0012] like Figure 5 As shown, the photoresist 108, the SiARC layer 107, and the SOC layer 106 are removed. Typically, the photoresist 108 is consumed during the first etching process, at which point only the SiARC layer 107 and the SOC layer 106 need to be removed, for example, using a wet etching process.

[0013] Subsequently, based on the number of split masks formed by splitting the pattern, each of the steps between coating the SOC layer 106, the SiARC layer 107, and the photoresist 108 and removing the photoresist 108, the SiARC layer 107, and the SOC layer 106 is repeated once for each of the split masks.

[0014] After the loop steps are completed, as follows Figure 5 As shown, a second selective etching is performed to remove the amorphous silicon layer 105 outside the doped region to form an amorphous silicon layer pattern consisting of the retained amorphous silicon layer 105. The second selective etching is performed using a wet etching solution comprising NH3OH. Summary of the Invention

[0015] The technical problem to be solved by the present invention is to provide a patterning process that can obtain patterns smaller than the limits of photolithography, and does not require ion implantation during the pattern definition process. It can eliminate the pattern missing defects caused by insufficient ion implantation when the pattern size is reduced, as well as the pattern CDU deterioration defects caused by the diffusion of implanted ions.

[0016] To solve the above-mentioned technical problems, the patterning process method provided by the present invention includes: Step 1: Form the first film layer that needs to be patterned on the underlying structure.

[0017] Step 2: Sequentially coat the SOC layer, SiARC layer, and photoresist.

[0018] Step 3: Perform photolithography to form a first opening in the photoresist.

[0019] Step 4: Perform the first etching, which sequentially etches the SiARC layer, the SOC layer, and the first film layer to transfer the pattern of the first opening into the first film layer and form the second opening in the first film layer.

[0020] Step 5: Remove the photoresist, the SiARC layer, and the SOC layer.

[0021] Step 6: Form a second membrane layer that completely fills the second opening, the material of the second membrane layer being different from the material of the first membrane layer.

[0022] Step 7: Perform a second etching to remove the first film layer and form a patterned structure composed of the second film layer.

[0023] Step 8: Trim the second membrane layer to adjust its critical dimensions.

[0024] A further improvement is that the material of the first film layer includes amorphous silicon.

[0025] A further improvement is that the material of the second film layer includes silicon nitride.

[0026] A further improvement is that step six includes the following sub-steps: A deposition process is performed to form the second film layer. During the deposition process, the second film layer grows simultaneously from the bottom surface and the side surface of the second opening, so that the second film layer growing on the side surface of the second opening merges in the middle of the second opening to completely fill the second opening; the second film layer also extends to the surface of the first film layer outside the second opening.

[0027] The second film layer is etched back to remove all of the second film layer outside the second opening, so that the second film layer is left only in the second opening.

[0028] A further improvement is that the patterned structure of the second film layer includes a truncated pattern of the middle metal layer.

[0029] A further improvement is that the underlying structure includes a first dielectric layer formed on a semiconductor substrate.

[0030] A further improvement is that the first dielectric layer includes an oxide layer.

[0031] A further improvement is that a hard mask layer is formed on the top surface of the first dielectric layer.

[0032] A further improvement is that the hard mask layer comprises a second TiN layer and a third oxide layer stacked sequentially.

[0033] A further improvement is that, before proceeding to step six, steps two through five are repeated multiple times. In each iteration, the photomask used in step three is a split photomask formed by splitting the graphic structure of the second film layer in step seven.

[0034] A further improvement is that the number of split photomasks includes four.

[0035] Compared to existing methods using litho-ET-IMP for patterning, this invention eliminates the IMP (ion implantation) process after litho and ET. Instead, it replaces IMP with film filling, specifically a second film filling the second opening. This second film filling eliminates pattern defects caused by insufficient ion implantation when the second opening shrinks. Simultaneously, the stable structure of the second film eliminates the CDU (Critical Dimension Duct Size) degradation caused by impurity diffusion from ion implantation. Furthermore, after the pattern structure of the second film is formed, the invention allows for trimming of the second film to adjust its critical dimensions, enabling them to shrink. Therefore, this invention can obtain patterns smaller than the limits of photolithography processes, and it eliminates the need for ion implantation during pattern definition, thus avoiding pattern defects caused by insufficient ion implantation when pattern size shrinks and CDU degradation caused by ion diffusion. Attached Figure Description

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figures 1-5 It is a schematic diagram of the device structure in each step of the existing graphical process method; Figure 6 This is a flowchart of the graphical process method according to an embodiment of the present invention; Figures 7-13 It is a schematic diagram of the device structure in each step of the existing graphical process method. Detailed Implementation

[0037] like Figure 6 The diagram shown is a flowchart of a graphical process method according to an embodiment of the present invention; as shown Figures 7 to 13 The diagram shown is a schematic representation of the device structure in each step of an existing patterning process; the patterning process of this invention includes: Step 1, such as Figure 7As shown, a first film layer 205, which requires patterning, is formed on the underlying structure.

[0038] In this embodiment of the invention, the material of the first film layer 205 includes amorphous silicon.

[0039] The underlying structure includes a first dielectric layer 202 formed on a semiconductor substrate.

[0040] In some embodiments, the first dielectric layer 202 includes an oxide layer, such as a PEOX oxide layer formed by a PECVD process. A nitride layer 201 is also formed at the bottom of the first dielectric layer 202.

[0041] A hard mask layer is also formed on the top surface of the first dielectric layer 202. In some embodiments, the hard mask layer includes a second TiN layer 203 and a third oxide layer 204 stacked sequentially.

[0042] Step 2, as follows Figure 7 As shown, SOC layer 206, SiARC layer 207 and photoresist 208 are coated sequentially.

[0043] Step 3, as Figure 8 As shown, photolithography is performed to form a first opening 209 in the photoresist 208.

[0044] The photolithography process includes exposure and development.

[0045] Step 4, as Figure 9 As shown, a first etching is performed, in which the SiARC layer 207, the SOC layer 206 and the first film layer 205 are etched sequentially to transfer the pattern of the first opening 209 into the first film layer 205 and form a second opening 210 in the first film layer 205.

[0046] Step 5, as follows Figure 9 As shown, the photoresist 208, the SiARC layer 207, and the SOC layer 206 are removed.

[0047] In some embodiments, the photoresist 208 is consumed in the first etching. In this case, only the SiARC layer 207 and the SOC layer 206 need to be removed in step five, for example, by using a wet process to remove the SiARC layer 207 and the SOC layer 206.

[0048] Step Six, as Figure 11 As shown, a second film layer 211 is formed to completely fill the second opening 210, and the material of the second film layer 211 is different from the material of the first film layer 205.

[0049] In this embodiment of the invention, step six includes the following sub-steps: like Figure 10 As shown, a deposition process is performed to form the second film layer 211. During the deposition process, the second film layer 211 grows simultaneously from the bottom surface and the side surface of the second opening 210, so that the second film layer 211 growing on the side surface of the second opening 210 merges in the middle of the second opening 210 to completely fill the second opening 210; the second film layer 211 also extends to the surface of the first film layer 205 outside the second opening 210.

[0050] In some embodiments, the material of the second film layer 211 includes silicon nitride.

[0051] like Figure 11 As shown, the second film layer 211 is etched back to remove all of the second film layer 211 outside the second opening 210, so that the second film layer 211 is only retained in the second opening 210.

[0052] Step 7, as follows Figure 12 As shown, a second etching is performed to remove the first film layer 205, forming a patterned structure composed of the second film layer 211.

[0053] Step 8, as follows Figure 13 As shown, the second film layer 211 is trimmed to adjust the critical dimensions of the second film layer 211. Figure 13 In the second film layer 211, the key dimension is the width d2, which, after trimming, Figure 13 The width d2 in the middle is less than Figure 12 The key dimension of the second membrane layer 211 before trimming is the width d1.

[0054] In some embodiments, the trimming is achieved by wet etching.

[0055] In this embodiment of the invention, before performing step six, steps two through five are repeated multiple times. In each iteration, the photomask used in step three is a split photomask formed from the split pattern of the patterned structure of the second film layer 211 in step seven. That is, this embodiment of the invention employs a multiple exposure process. In some embodiments, the patterned structure composed of the second film layer 211 includes a truncated pattern of the middle metal layer. The number of split photomasks includes four.

[0056] Compared to existing methods using litho-ET-IMP for patterning, this embodiment of the invention eliminates the IMP (ion implantation) process after litho and ET. Instead, it replaces IMP with film filling, specifically filling the second opening 210 with a second film layer 211. By using the second film layer 211 to fill the second opening 210, the pattern defects caused by insufficient ion implantation when the second opening 210 shrinks can be eliminated. Simultaneously, the stable structure of the second film layer 211 eliminates the CDU (Critical Duty Unit) degradation caused by impurity diffusion from ion implantation. Furthermore, after the pattern structure of the second film layer 211 is formed, this embodiment of the invention can trim the second film layer 211 to adjust its critical dimensions, allowing for a reduction in its critical dimensions. Therefore, this embodiment of the invention can obtain patterns smaller than the limits of photolithography processes, and it eliminates the pattern defects caused by insufficient ion implantation when the pattern size shrinks, as well as the CDU degradation caused by ion diffusion.

[0057] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A graphical process method, characterized in that, include: Step 1: Form the first film layer that needs to be patterned on the underlying structure; Step 2: Sequentially coat the SOC layer, SiARC layer, and photoresist; Step 3: Perform photolithography to form a first opening in the photoresist; Step 4: Perform the first etching, which sequentially etches the SiARC layer, the SOC layer, and the first film layer to transfer the pattern of the first opening into the first film layer and form the second opening in the first film layer. Step 5: Remove the photoresist, the SiARC layer, and the SOC layer; Step 6: Form a second film layer that completely fills the second opening, wherein the material of the second film layer is different from that of the first film layer; Step 7: Perform a second etching to remove the first film layer and form a patterned structure composed of the second film layer; Step 8: Trim the second membrane layer to adjust its critical dimensions.

2. The patterning process method as described in claim 1, characterized in that: The material of the first film layer includes amorphous silicon.

3. The patterning process method as described in claim 2, characterized in that: The material of the second film layer includes silicon nitride.

4. The patterning process method as described in claim 1, characterized in that: Step six includes the following sub-steps: A deposition process is performed to form the second film layer. During the deposition process, the second film layer grows simultaneously from the bottom surface and the side surface of the second opening, so that the second film layer growing on the side surface of the second opening merges in the middle of the second opening to completely fill the second opening; the second film layer also extends to the surface of the first film layer outside the second opening. The second film layer is etched back to remove all of the second film layer outside the second opening, so that the second film layer is left only in the second opening.

5. The patterning process method as described in claim 1, characterized in that: The patterned structure of the second film layer includes a truncated pattern of the middle metal layer.

6. The patterning process method as described in claim 5, characterized in that: The underlying structure includes a first dielectric layer formed on a semiconductor substrate.

7. The patterning process method as described in claim 6, characterized in that: The first dielectric layer includes an oxide layer.

8. The patterning process method as described in claim 7, characterized in that: A hard mask layer is also formed on the top surface of the first dielectric layer.

9. The patterning process method as described in claim 8, characterized in that: The hard mask layer comprises a second TiN layer and a third oxide layer stacked sequentially.

10. The patterning process method as described in claim 1, characterized in that: Before proceeding to step six, steps two through five are repeated multiple times. In each cycle, the photomask used in step three is a split photomask formed by splitting the graphic structure of the second film layer in step seven.

11. The patterning process method as described in claim 10, characterized in that: The number of split photomasks includes four.

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