Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure on a channel region of a pedestal structure, and the pedestal structure includes interleaved channel semiconductor portions and sacrificial material portions; etching source / drain regions of the pedestal structure to expose sidewalls of the channel semiconductor portions and the sacrificial material portions; selectively recessing the sacrificial material portions to form recesses; depositing a reticulated dielectric film to line the recesses, and the reticulated dielectric film includes a first density of porous dielectric material; removing the sacrificial material portions; performing a sealing web step on the reticulated dielectric film to form a treated reticulated dielectric film having a second density greater than the first density; depositing a dielectric layer on the treated reticulated dielectric film to fill the recesses; and etching back the treated reticulated dielectric film and the dielectric layer to form an inner spacer in the recesses.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to inner spacers formed of a mesh dielectric film and a dielectric layer. Background Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit wafer area) typically increases as the geometry (i.e., the smallest component or line that the manufacturing process can produce) shrinks. Shrinking the size of processes usually helps increase production capacity and reduce associated costs. Size reduction also increases the complexity of handling and manufacturing integrated circuits. Summary of the Invention

[0003] An embodiment of the present invention relates to a method for forming a semiconductor device. The method includes forming a sacrificial gate structure on a channel region of a substrate structure. The substrate structure includes a plurality of interleaved channel semiconductor portions and a plurality of sacrificial material portions. After etching a plurality of source / drain regions of the substrate structure to expose the sidewalls of the channel semiconductor portions and the sacrificial material portions, the sidewalls of the sacrificial material portions are selectively recessed to form a plurality of recesses. A mesh dielectric film is then deposited to pad the recesses. The mesh dielectric film includes a porous dielectric material of a first density. An etchant is then passed through the mesh dielectric film to remove the sacrificial material portions; a sealing mesh step is performed on the mesh dielectric film to form a treated mesh dielectric film of a second density, the second density being greater than the first density. A dielectric layer is then deposited on the treated mesh dielectric film to fill the recesses. The treated mesh dielectric film and dielectric layer are then etched back to form a plurality of inner spacers in the recesses.

[0004] Another embodiment of the present invention relates to a method for forming a semiconductor device. The method includes forming a stack on a substrate, the stack comprising a plurality of interleaved first semiconductor layers and a plurality of second semiconductor layers. After patterning the stack to form a base structure (which includes a plurality of interleaved first semiconductor portions and a plurality of second semiconductor portions), a sacrificial gate structure is formed (which includes a sacrificial gate stack located on a channel portion of the base structure, and a plurality of gate spacers located on the sidewalls of the sacrificial gate stack). The portion of the base structure not covered by the sacrificial gate structure is then removed to form a plurality of source / drain trenches. The sidewalls of the second semiconductor portions are then laterally etched to form a plurality of inner spacer recesses. A compliant mesh dielectric film is then deposited along the sacrificial gate structure, the inner spacer recesses, and the exposed surfaces of the first semiconductor portions. The mesh dielectric film includes a plurality of interconnected holes. An etchant is then passed through the mesh dielectric film to etch the second semiconductor portions to release the first semiconductor portions. After processing the mesh dielectric film to seal the interconnected holes, a dielectric layer is deposited on the mesh dielectric film to fill the inner spacer recesses. Remove the portion of the dielectric layer and mesh dielectric film outside the inner spacer recess.

[0005] Another embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a plurality of channel nanostructures located on a substrate; and a plurality of inner spacers interspersed with the channel nanostructures. Each inner spacer includes a mesh dielectric film portion and a dielectric portion, with the mesh dielectric film portion surrounding the dielectric portion. The mesh dielectric film portion has a porous structure, and the density of the porous structure is less than the density of the dielectric portion. Attached Figure Description

[0006] Figure 1 This is a flowchart of a method for forming a fully wound gate device in some embodiments of the present invention.

[0007] Figures 2 to 15 In some embodiments of the present invention, based on Figure 1 The method is used to create cross-sectional views of various stages of a fully wound gate device.

[0008] Figure 16 This is a flowchart illustrating a method for forming a fully wound gate device in some embodiments of the present invention.

[0009] Figures 17 to 20 In some embodiments of the present invention, based on Figure 16 The method is used to create cross-sectional views of various stages of a fully wound gate device.

[0010] The attached figures are labeled as follows: 100, 300: Method 102,104,106,108,109,110,111,112,113,114,116,118, 120,122,124,126,128: Steps 200: Fully wound gate device 202:Substrate 204: Stacking 206: Sacrificial Semiconductor Layer 206P: Sacrificial Semiconductor Section 208: Channel semiconductor layer 208C: Channel Nanostructure 208P: Channel Semiconductor Section 210: Fin-like structure 210B: Base portion 210S: Fin-shaped stacked portion 216: Isolation Structure 220: Sacrificial gate structure 222: Sacrificial gate dielectric layer 224: Sacrificial Gate 226: Gate spacer 228: Source / Drain Trench 229P sacrificial dielectric section 230: Inner spacer recess 232: Gap 240: Mesh dielectric film 242: The treated mesh dielectric film 242P: Mesh dielectric film portion 244: Dielectric layer 244P: Dielectric section 246: Gap 248: Inner spacer 250: Source / Drain Structure 252: Interlayer dielectric layer 254: Gate Trench 260: Gate Stack 262: Interface Layer 264: Gate dielectric layer 266: Work Function Layer 268: Gate layer Detailed Implementation

[0011] The following detailed description is illustrated with accompanying drawings to aid in understanding various aspects of the invention. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity.

[0012] The different embodiments or examples provided below can implement different structures of the present invention. The specific components and arrangements described below are intended to simplify the content of the present invention and not to limit it. For example, the description of forming a first component on a second component includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by other additional components and are not in direct contact. Furthermore, multiple embodiments of the present invention may use the same reference numerals repeatedly for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0013] In addition, spatial relative terms such as “below,” “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in the accompanying drawings and other elements or structures. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0014] Multi-gate devices, such as fully wound gate transistors, have been introduced to improve gate control by increasing gate-channel coupling, minimizing off-state current, and mitigating short-channel effects. The method for fabricating fully wound gate transistors involves forming a stacked structure of multiple interleaved channel layers and sacrificial layers. These sacrificial layers are selectively removed to release the channel layers as channel nanosheets. A metal gate structure consisting of multiple dielectric and conductive layers is then formed to encapsulate each channel nanosheet. The material of the sacrificial layers is carefully selected to avoid significant damage to the channel layers during selective removal of the sacrificial layers.

[0015] In known post-gate fabrication or gate replacement processes, the sacrificial layer is typically removed by dry etching after the epitaxial source / drain structure is formed. However, this approach can cause problems such as epitaxial damage and additional wafer loss. When the channel layer is composed of silicon and the sacrificial layer is composed of silicon-germanium, removing the silicon-germanium sacrificial layer after the epitaxial source / drain structure is formed may also cause mismatch between silicon and silicon-germanium during thermal annealing to activate the epitaxial source / drain structure, ultimately degrading device performance and reliability.

[0016] To address these challenges, embodiments of the present invention employ a mesh dielectric film surrounding a sacrificial layer. The mesh dielectric film structure has interconnecting holes that allow etchant species to pass through and remove the sacrificial layer, forming gas spacers between channel layers for integrating the metal gate. After removing the sacrificial layer, a sealing mesh step reduces the hole size to prevent precursor gases from permeating into the gas spacers during subsequent processes forming the inner spacers and epitaxial source / drain electrodes. This improves device performance and reliability.

[0017] The patterning method for the fully wrapped gate transistor described below can be any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual patterning or multi-patterning processes. Generally, dual patterning or multi-patterning processes combine photolithography with self-alignment processes, resulting in a smaller pattern pitch than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fully wrapped gate transistor.

[0018] Figure 1 This is a flowchart of a method 100 for forming a fully wound gate device 200 in some embodiments of the present invention. Figures 2 to 15 The images show cross-sectional views of the fully wound gate device 200 at various stages of method 100 in some embodiments. Some embodiments of method 100 will be paired with... Figures 2 to 15 The fully wound gate device 200 is described below. Method 100 is merely illustrative and not intended to limit the invention to the parts not actually described in the claims. Additional steps may be provided before, during, and after method 100, and additional embodiments of the method may substitute, omit, or interchange some of the steps described.

[0019] like Figure 1 and Figure 2 As shown, step 102 of method 100 provides an initial structure for the fully wound gate device 200. In some embodiments, the initial structure includes a substrate 202 and a stack 204 of staggered epitaxial semiconductor layers on the substrate 202. Figure 2 A cross-sectional view of the fully wound gate device 200 after the stack 204 of interlaced epitaxial semiconductor layers is formed on the substrate 202.

[0020] The substrate 202 can be any suitable substrate and can be processed to have various structures. In some embodiments, the substrate 202 can be a semiconductor substrate such as a silicon substrate. In some embodiments, the substrate 202 includes various layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate 202 can include various doping configurations. For example, different doping profiles (such as n-type wells and p-type wells) can be formed in regions on the substrate 202, and the regions are designed for different device types (such as n-type field-effect transistors and p-type field-effect transistors). Suitable doping can include ion implantation dopants and / or diffusion processes. The substrate 202 typically has isolation structures (such as shallow trench isolation structures) between the regions of different device types. The substrate 202 can include other semiconductors such as germanium or diamond. The substrate 202 may be replaced with semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide, or gallium arsenide phosphide), and / or other suitable materials. Furthermore, the substrate 202 may, as appropriate, include an epitaxial layer, be strainable to improve performance, may include a silicon-on-insulator structure, and / or may have other suitable enhancing structures.

[0021] A stack 204 of interleaved epitaxial semiconductor layers is deposited blanket-coatedly on a substrate 202. The stack 204 includes interleaved sacrificial semiconductor layers 206 and channel semiconductor layers 208, wherein the channel semiconductor layers 208 are the top layer and the sacrificial semiconductor layers 206 are the bottom layer. In some embodiments, the sacrificial semiconductor layer 206 comprises a first semiconductor material, the channel semiconductor layer 208 comprises a second semiconductor material, and the first semiconductor material is different from the second semiconductor material. The material selection of the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 ensures that their etch selectivity is different, making selective removal of the sacrificial semiconductor layer 206 feasible. For example, in some embodiments, the first semiconductor material may include germanium or silicon-germanium, while the second semiconductor material may include silicon. In some embodiments, the germanium content in the first semiconductor material may be between about 15 wt% and about 40 wt%. In some other embodiments, the first semiconductor material comprises silicon-germanium with a first germanium content, while the second semiconductor material comprises silicon-germanium with a second germanium content, and the second germanium content is lower than the first germanium content. In various embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are substantially undoped (e.g., the added dopant concentration is less than about 1 × 10⁻⁶). 17 cm -3 ).

[0022] In some embodiments, the sacrificial semiconductor layer 206 may be removed in a subsequent process while retaining the channel semiconductor layer 208, which defines the channel nanostructure used in the fully wound gate device 200 (e.g., Figure 8The channel nanostructure 208C is thus determined by the thickness of the sacrificial semiconductor layer 206. In some embodiments, the thickness of the sacrificial semiconductor layer 206 may be from about 8 nm to about 15 nm. For example, the thickness of the channel semiconductor layer 208 is chosen based on manufacturing considerations, transistor performance considerations, and similar considerations. In some embodiments, the thickness of the channel semiconductor layer 208 may be from about 4 nm to about 10 nm.

[0023] The number of sacrificial semiconductor layers 206 and channel semiconductor layers 208 depends on the number of channel nanostructures required in the fully wound gate device 200. In some embodiments, the number of channel semiconductor layers 208 may be 2 to 10 to form a stack of 2 to 10 vertically separated channel nanostructures. Figure 2 In some embodiments shown, stack 204 includes four sacrificial semiconductor layers 206 and four channel semiconductor layers 208. However, it should be understood that any number of sacrificial semiconductor layers 206 and channel semiconductor layers 208 can be formed in stack 204.

[0024] The sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are epitaxially grown layer by layer from the upper surface of the substrate 202. In some embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are grown by molecular beam epitaxy, chemical vapor deposition (such as metal-organic chemical vapor deposition), or other suitable epitaxial growth processes. The epitaxial growth results in the crystal orientation of the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 being the same as the crystal orientation of the substrate 202.

[0025] like Figure 1 , Figure 3A and Figure 3B In some embodiments shown, step 104 of method 100 forms a plurality of fin structures 210 from the stack 204 and the substrate 202. Figure 3A and Figure 3B A cross-sectional view of the fully wound gate device 200 after multiple fin structures 210 have been formed.

[0026] In some embodiments, portions of the stack 204 and the substrate 202 are patterned to form a fin structure 210. The fin structure 210 extends perpendicularly from the substrate 202 along the Z direction, has a length dimension extending along the X direction, and has a width dimension extending along the Y direction. In some embodiments, the width of the fin structure 210 is from about 1 nm to about 150 nm. The fin structure 210 may have a base structure containing fin stack portions 210S and a base portion 210B. The base portion 210B is formed from the substrate 202, and the fin stack portions 210S (containing a portion of the sacrificial semiconductor layer 206 (which can be considered here as sacrificial semiconductor portion 206P) and a portion of the channel semiconductor layer 208 (which can be considered here as channel semiconductor portion 208P)) are formed from the stack 204.

[0027] In some embodiments, the fin structure 210 may be formed using photolithography and etching processes. During photolithography, a hard mask layer (not shown) may first be formed on the topmost surface of the stack 204. In some embodiments, the hard mask layer includes a dielectric material such as silicon nitride, silicon carbonitride, silicon carbide, silicon carbonitride, or a combination thereof. In some embodiments, the hard mask layer is formed using chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition processes. In some embodiments, the hard mask layer may have a bilayer structure, including a pad oxide layer and a pad nitride layer on the pad oxide layer. In some embodiments, the pad oxide layer includes silicon oxide, which may be formed by thermal oxidation. The pad nitride layer includes silicon nitride, which may be formed using chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0028] Next, a photoresist layer is applied to the hard mask layer, and the application method can be spin coating. The photoresist layer is then exposed according to the photomask pattern and developed to form a pattern within the photoresist layer. The patterned photoresist layer can serve as an etching mask to pattern other layers. In some embodiments, the method for patterning the photoresist layer can employ extreme ultraviolet lithography. The patterned photoresist layer is then used to protect the area of ​​substrate 202 (on which the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are formed), while an etching process forms the fin structure 210. In some embodiments, the etching process can be a dry etching process such as plasma etching or reactive ion etching, a wet etching process, or a combination thereof.

[0029] In various other embodiments, the fin structure 210 can be formed using suitable processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography with self-alignment processes, resulting in a pattern spacing smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-alignment process is used to form a core along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining core serves as an etching mask for patterning the stack 204 and the substrate 202 to provide the fin structure 210.

[0030] Next, an isolation structure 216 can be formed around and adjacent to the base portion 210B of the fin structure 210. The isolation structure 216 is located between the fin structures 210, such as... Figure 3B As shown. The isolation structure 216 can also be considered as a shallow trench isolation structure. In an example of the process, a dielectric layer is first deposited on the substrate 202 to fill the trenches between the fin structures 210. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, a low dielectric constant dielectric layer, a combination of the above, and / or other suitable materials. In various embodiments, the dielectric layer deposition method may be chemical vapor deposition, sub-pressure chemical vapor deposition, flowable chemical vapor deposition, atomic layer deposition, physical vapor deposition, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized, for example by chemical mechanical polishing. The planarized dielectric layer may be further recessed to form the isolation structure 216, and the recessing method may be a dry etching process, a wet etching process, and / or a combination of the above. In some embodiments, the upper surface of the isolation structure 216 may be flush with or lower than the lower surface of the lowermost sacrificial semiconductor portion 206P, causing the fin stack portion 210S to bulge above the isolation structure 216. In some embodiments, the dielectric layer (towards the subsequently formed isolation structure 216) may include a multilayer structure, such as having one or more padding layers.

[0031] If the hard masking layer is not removed when forming the isolation structure 216, the hard masking layer is then removed from the topmost surface of the fin structure 210. The method for removing the hard masking layer can be anisotropic etching process. The etching process can be a dry etching process such as reactive ion etching, a wet etching process, or a combination thereof.

[0032] like Figure 1 and Figure 4 In some embodiments shown, step 106 of method 100 forms a sacrificial gate structure 220 on the fin structure 210. Figure 4A cross-sectional view of the fully wound gate device 200 after the silicon sacrificial gate structure 220 is formed. The sacrificial gate structure 220 extends along the topmost surface and sidewalls of each fin structure 210, passing over each fin structure 210.

[0033] The sacrificial gate structure 220 includes a sacrificial gate stack (222, 224) located above the channel region of each fin structure 210, and a gate spacer 226 located above the sidewalls of the sacrificial gate stack (222, 224). In an embodiment of the invention, the sacrificial gate stack (222, 224) is replaced with a metal gate stack.

[0034] In some embodiments, the sacrificial gate stack (222, 224) includes a sacrificial gate dielectric layer 222 and a sacrificial gate 224 located on the sacrificial gate dielectric layer 222. In some embodiments, the sacrificial gate stack (222, 224) may also include a sacrificial gate cap (not shown) on top of the sacrificial gate 224.

[0035] In some embodiments, the sacrificial gate dielectric layer 222 may be composed of silicon oxide, silicon nitride, or silicon oxynitride. The sacrificial gate 224 may be composed of silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate stack (222, 224) may be formed by first compliantly depositing a sacrificial gate dielectric layer on the fin structure 210 and the isolation structure 216. The term "compliant" is used herein to conveniently describe a layer with substantially uniform thickness in multiple regions. A sacrificial gate layer is then blanket-deposited on the sacrificial gate dielectric layer, such that the fin structure 210 is completely buried within the sacrificial gate layer. In some embodiments, the thickness of the sacrificial gate dielectric layer may be from about 1 nm to about 5 nm. In some embodiments, the thickness of the sacrificial gate layer may be from about 100 nm to about 200 nm. The deposition methods for the sacrificial gate dielectric layer and the sacrificial gate layer may employ chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition processes. In some embodiments, after deposition, the sacrificial gate layer may undergo a planarization step such as chemical mechanical polishing. The sacrificial gate dielectric layer and the sacrificial gate layer are then patterned using photolithography and etching processes. In some embodiments, a photoresist layer (not shown) is applied to the sacrificial gate layer, and photolithography exposure and development are performed to photolithographically pattern the photoresist layer. The pattern in the photoresist layer is sequentially transferred to the sacrificial gate layer and the sacrificial gate dielectric layer using at least one anisotropic etching process, thereby forming a sacrificial gate stack (222, 224) including retained portions of the sacrificial gate dielectric layer and the sacrificial gate layer. The anisotropic etching process may be a dry etching process such as reactive ion etching, a wet etching process, or a combination thereof. If the residual photoresist layer is not completely consumed, it may be removed by methods such as ashing after the formation of the sacrificial gate stack (222, 224).

[0036] Gate spacer 226 is located on the sidewalls of the sacrificial gate stack (222, 224). In some embodiments, gate spacer 226 may comprise a dielectric material such as an oxide, nitride, oxynitride, or a combination thereof. In some embodiments, gate spacer 226 is composed of silicon nitride. In some embodiments, gate spacer 226 is formed by first depositing a compliant gate spacer material layer on the exposed surfaces of the sacrificial gate stack (222, 224), fin structure 210, and isolation structure 216, and then etching the gate spacer material layer to remove the horizontal portion of the gate spacer material layer. In some embodiments, the gate spacer material layer may be deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition. In some embodiments, the gate spacer material layer may be etched by dry etching such as plasma etching or reactive ion etching. The vertical portion of the gate spacer material layer present on the sidewalls of the sacrificial gate stack (222, 224) constitutes gate spacer 226.

[0037] like Figure 1 and Figure 5 In some embodiments shown, step 108 of method 100 forms a source / drain trench 228 in the source / drain region of the fin structure 210. Figure 5 A cross-sectional view of the fully wound gate device 200 after the source / drain trench 228 is formed in the source / drain region of the fin structure 210.

[0038] In some embodiments, portions of the fin structure 210 in the source / drain region not covered by the sacrificial gate structure 220 are etched to form a source / drain trench 228. The etching method can be a dry etching process such as plasma etching or reactive ion etching. An exemplary dry etching process can be implemented using oxygen-containing gases, hydrogen, fluorine-containing gases (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, trifluoromethane, and / or hexafluoroethane), chlorine-containing gases (such as chlorine, chloroform, carbon tetrachloride, and / or boron trichloride), bromine-containing gases (such as hydrogen bromide and / or tribromomethane), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. Alternatively, a wet etching process can be performed, using an etchant such as a mixture of ammonium hydroxide and hydrogen peroxide rainwater, tetramethylammonium hydroxide, or ammonium hydroxide. In the etched source / drain trench 228, the sidewalls of the channel semiconductor portion 208P and the sacrificial semiconductor portion 206P are exposed. In some embodiments, the substrate 202 may also be partially etched so that the source / drain trench 228 extends below the bottommost sacrificial semiconductor portion 206P. In summary, the lower surface of the source / drain trench 228 may be flush with the upper surface of the substrate portion 210B (e.g., Figure 5 (as shown), or below the upper surface of the base portion 210B (not shown).

[0039] like Figure 1 and Figure 6 In some embodiments shown, step 110 of method 100 causes the sacrificial semiconductor portion 206P in the fin structure 210 to be recessed. Figure 6 A cross-sectional view of the fully wound gate device 200 after the sacrificial semiconductor portion 206P in the fin structure 210 is recessed.

[0040] In some embodiments, the exposed sacrificial semiconductor portion 206P in the source / drain trench 228 is selectively and partially recessed to form an inner spacer recess 230, while the exposed channel semiconductor portion 208P is not substantially etched. In embodiments where the channel semiconductor portion 208P is substantially composed of silicon and the sacrificial semiconductor portion 206P is substantially composed of silicon-germanium, the method of selectively recessing the sacrificial semiconductor portion 206P may include a silicon-germanium oxide process, followed by a silicon-germanium oxide removal process. In these embodiments, the silicon-germanium oxide process may employ ozone. In some embodiments, the selective recessing may be a selective isotropic etching process (such as a selective dry etching process or a selective wet etching process), and the amount of recess of the sacrificial semiconductor portion 206P may be controlled by the time of the etching process. In some embodiments, the selective wet etching process may employ hydrofluoric acid or ammonium hydroxide etchant. Figure 6 As shown, the inner spacer recess 230 is laterally recessed inward from the source / drain trench 228 into the fin structure 210. In some embodiments, the lateral etching distance is not greater than the width of the gate spacer 226, so that the sidewall of the inner spacer recess 230 is aligned with the inner sidewall of the gate spacer 226. In some embodiments, the lateral dimension of the inner spacer recess 230 is about 4 nm to about 10 nm.

[0041] like Figure 1 and Figure 7 In some embodiments shown, step 112 of method 100 compliantly deposits a mesh dielectric film 240 on the fully wound gate device 200, with the inner spacer recess 230 lining it. Figure 7 A cross-sectional view of the fully wound gate device 200 after the formation of the mesh dielectric film 240.

[0042] like Figure 7 As shown, a mesh dielectric film 240 is deposited on the exposed surfaces of the source / drain regions, the sacrificial semiconductor portion 206P, the channel semiconductor portion 208P, and the sacrificial gate structure 220. The mesh dielectric film 240 is a porous dielectric layer with interconnecting pores to form pathways through which etchant species can pass. During subsequent dry or wet etching processes, these interconnecting pores are large enough to allow etchant species to diffuse into the sacrificial semiconductor portion 206P. In some embodiments, the density of the mesh dielectric film 240 is about 1 g / cm³. 3 To approximately 2.5 g / cm 3 .

[0043] In some embodiments, the mesh dielectric film 240 may comprise porous silicon oxide, porous silicon nitride, porous silicon carbonitride, porous silicon carbonitride, porous silicon carbide, or other suitable porous dielectric materials. In some embodiments, the mesh dielectric film 240 comprises nitrogen-rich silicon carbonitride having a cage-like porous structure. In some embodiments, the silicon atom concentration of the nitrogen-rich silicon carbonitride is approximately 38 atomic% to 40 atomic% of nitrogen, the oxygen atom concentration is approximately 20 atomic% to 24 atomic% of nitrogen, and the carbon atom concentration is approximately 39 atomic% to 40 atomic% of nitrogen. In some embodiments, the mesh dielectric film 240 comprises silicon-rich silicon oxide with a silicon / oxygen ratio of less than 2.

[0044] In some embodiments, the deposition method of the mesh dielectric film 240 may employ an atomic layer deposition process in a single wafer chamber or a batch chamber (which may accommodate multiple wafers). The atomic layer deposition process is controlled to define the aperture size of the mesh dielectric film 240. In some embodiments, the atomic layer deposition process is a low-temperature process with a deposition temperature of about 200°C to about 500°C. The deposition rate may be about 0.01 Å / cycle to about 10 Å / cycle, and may be about 0.1 Å / min to about 20 Å / min. Furthermore, when using diluted hydrofluoric acid at a dilution ratio of 1:100 as an etchant, the wafer etch rate is controlled to exceed 100 Å / min. The thickness of the deposited mesh dielectric film 240 may be about 0.5 nm to about 5 nm. The root mean square surface roughness of the surface of the mesh dielectric film 240 is plated between 0.5 Å and 5 Å. In some embodiments, the mesh dielectric film 240 is a 1.5 nm thick porous silicon carbon nitride layer.

[0045] like Figure 1 and Figure 8 In some embodiments shown, step 114 of method 100 selectively removes the sacrificial semiconductor portion 206P. Figure 8 A cross-sectional view of the fully wound gate device 200 after selective removal of the sacrificial semiconductor portion 206P.

[0046] Step 114 removes the sacrificial semiconductor portion 206P surrounded by the mesh dielectric film 240. Selective removal of the sacrificial semiconductor portion 206P releases the channel semiconductor portion 208P, which then transforms into the channel nanostructure 208C.

[0047] In some embodiments, the sacrificial semiconductor portion 206P can be removed by a selective etching process, wherein an etchant penetrates the mesh dielectric film 240 to contact and selectively etch the sacrificial semiconductor portion 206P without substantially affecting the channel semiconductor portion 208P. In some embodiments, the etching process is an isotropic etching process, which can be a dry etching process or a wet etching process. In some embodiments, selective wet etching includes etching with a mixture of ammonium hydroxide and hydrogen peroxide and water. In some embodiments, selective removal includes silicon germanium oxidation and a subsequent silicon germanium oxide removal process. For example, the oxidation step can be ozone cleaning, and the subsequent removal of silicon germanium oxide can be achieved using an etchant such as ammonium hydroxide. In some embodiments, the method for selectively removing the sacrificial semiconductor portion 206P may involve applying hydrogen chloride gas at a temperature of about 500°C to about 700°C, or applying a gas mixture of carbon tetrafluoride, sulfur hexafluoride, and trifluoromethane.

[0048] In some embodiments, after removing the sacrificial semiconductor portion 206P to release the channel nanostructure 208C, a trimming step may be performed to reduce the thickness of the channel nanostructure 208C, thereby improving the gate fill allowance. The trimming step may employ any suitable etching process such as dry etching, wet etching, or a combination thereof. The final thickness of the channel nanostructure 208C may be 3 nm to 6 nm.

[0049] like Figure 8 As shown, the sacrificial semiconductor portion 206P and the modified nanosheet are removed to form gaps 232 between adjacent channel nanostructures 208C and between the bottommost channel nanostructure 208C and the substrate portion 210B. The gaps 232 surrounded by the mesh dielectric film 240 can serve as gas spacers, separating the channel nanostructures 208C from each other and from the substrate portion 210B. The gaps 232 define the space between adjacent channel nanostructures 208C. In some embodiments, the space between adjacent channel nanostructures 208C (which can also be considered as the space between sheets) can be from about 8 nm to about 15 nm.

[0050] After selectively removing the sacrificial semiconductor portion 206P, the mesh dielectric film 240 can be cleaned using a wet cleaning process employing one or more solutions such as Standard Cleaner 1, Standard Cleaner 2, a mixture of sulfuric acid and hydrogen peroxide, diluted hydrofluoric acid, hydrogen peroxide, a buffered oxide etching solution, hydrogen chloride, or combinations thereof. In some embodiments, the cleaning method for the mesh dielectric film 240 may first employ a wet cleaning process for 0.5 to 9 minutes using diluted hydrofluoric acid at a dilution ratio between about 1:500 and 1:100, followed by a dry cleaning process using fluorine gas. In some embodiments, the cleaning method for the mesh dielectric film 240 may first involve rinsing with hydrofluoric acid, followed by fluorine gas cleaning.

[0051] like Figure 1 and Figure 9 In some embodiments shown, step 116 of method 100 performs a sealing mesh step to reduce the pore size in the mesh dielectric film 240. Figure 9 A cross-sectional view of the fully wound gate device 200 after the sealing mesh step to reduce the pore size in the mesh dielectric film 240.

[0052] like Figure 9 As shown in the enlarged portion, the pores of the treated mesh dielectric film 242 formed in the sealing step are smaller than those of the mesh dielectric film 240. The smaller pores prevent dielectric precursor species from penetrating through the pores into the gaps 232 between the channel nanostructures 208C during the subsequent process of forming the inner spacers, which could otherwise increase the resistance of the metal gates formed therein and reduce device performance. In some embodiments, the density of the treated mesh dielectric film 242 increases to approximately 1.5 g / cm³ after the sealing step. 3 Approximately 3 g / cm 3 .

[0053] In some embodiments, when the mesh dielectric film 240 is composed of a nitrogen-rich dielectric layer such as nitrogen-rich silicon oxycarbonate or silicon nitride, a siloxane can be formed from the nitrogen-rich dielectric layer to seal the mesh according to Scheme 1.

[0054] Option 1

[0055] As shown in Scheme 1, the mesh dielectric film 240 is first exposed to an oxygen source for oxygen conversion treatment. Oxygen conversion treatment breaks down amine bonds (NH2 bonds) on the surface of the pores to convert amine groups into hydroxyl groups. The oxygen source used for oxygen conversion treatment may include oxygen, oxygen plasma, ozone, water vapor, or a combination thereof. The method of exposure to the oxygen source may be chemical treatment, plasma treatment, or wet annealing. Oxygen conversion treatment may occur in a single wafer chamber or a batch wafer chamber at a pressure of about 1 mTorr to about 2000 Torr. When oxygen plasma is used for the conversion treatment, the oxygen conversion treatment can be performed in a high-power microwave plasma or inductively coupled plasma chamber. In some embodiments, the flow rate of the oxygen source into the reaction chamber may be about 100 sccm (standard cubic centimeters per minute) to about 5000 sccm. In some embodiments, the temperature for performing the oxygen conversion treatment may be about 150°C to about 700°C. The oxygen conversion process is self-limiting, only occurring when unreacted amine groups remain on the porous surface of the mesh dielectric film 240.

[0056] A densification process is then performed to facilitate the reaction of hydroxyl groups between adjacent silicon-based compounds, forming siloxanes and reducing pore size (due to crosslinking and network densification). Thus, the pores in the network dielectric film 240 are sealed via crosslinked surface hydroxyl groups without the need for additional pore-shrinking agents. The densification process can be self-limiting, continuing as long as unreacted hydroxyl groups remain on the pore surface of the network dielectric film 240. In some embodiments, the densification process includes applying thermal energy, ultraviolet energy, or both. In some embodiments, the densification process can be a thermal annealing step in an inert gas (such as argon or nitrogen) environment. In some embodiments, the thermal annealing temperature is from about 300°C to 800°C, and the duration is from about 10 minutes to about 5 hours. In other embodiments, the densification process can be performed with ultraviolet light curing. The ultraviolet wavelength can be from 190 nm to 400 nm. Ultraviolet / thermal annealing tools can be used for the densification process of the network dielectric film 240.

[0057] In some more specific embodiments, the sealing process begins by exposing the mesh dielectric film 240 to oxygen for about 6 minutes at a pressure of about 1 Torr and a temperature of about 385°C to about 400°C, followed by exposing the oxygen-treated mesh dielectric film 240 to nitrogen for about 1 hour at a temperature of about 600°C. In these embodiments, after thermal annealing under nitrogen, the mesh dielectric film 240 is further irradiated with ultraviolet light at a temperature up to about 500°C for about 1 minute to about 60 minutes.

[0058] In some embodiments, when the mesh dielectric film 240 is composed of a nitrogen-free porous dielectric material such as silicon oxide, silicon carbide, or silicon carbide, a helium and ammonia plasma treatment can be combined to achieve a sealed mesh, facilitating the reorganization of the dielectric structure of the mesh dielectric film 240. In the combined treatment, the helium plasma treatment can break silicon-oxygen bonds and remove hydrogen atoms from methyl groups on the pore surface to activate the pore surface sites, while the subsequent ammonia plasma treatment can generate NHx (x=1 or 2) species under argon atmosphere. Silicon-nitrogen bonds and carbon-nitrogen bonds are formed at the helium plasma-activated sites to seal the pores, while the NHx species are adsorbed onto the surface. Then, N-N bonds are formed to connect the carbon or silicon atoms on both sides of the pore walls.

[0059] like Figure 1 and Figure 10 In some embodiments shown, step 118 of method 100 deposits a dielectric layer 244 on the treated mesh dielectric film 242 and within the inner spacer recess 230. Figure 10 This is a cross-sectional view of the fully wound gate device 200 after the dielectric layer 244 has been formed.

[0060] The dielectric layer 244 may include a dielectric nitride, such as silicon nitride, silicon carbonitride, silicon carbonitride, or any suitable dielectric material. In some embodiments, the dielectric material included in the dielectric layer 244 may be the same as or different from that in the mesh dielectric film 240. The method for compliantly depositing the dielectric layer 244 may be chemical vapor deposition, plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, or other suitable compliant deposition processes. The pore size of the treated mesh dielectric film 242 is reduced, which prevents the diffusion of dielectric precursor species into the gaps 232 during dielectric layer deposition. Thus, the dielectric layer 244 exists only on the treated mesh dielectric film 242 (including within the inner spacer recesses 230), but not within the gaps 232. In some embodiments, the thickness of the dielectric layer 244 may completely fill the inner spacer recesses 230. In some embodiments, slits 246 may be formed on the surface of dielectric layer 244 to align individual inner spacer recesses 230. The density of dielectric layer 244 is greater than the density of the processed mesh dielectric film 242.

[0061] like Figure 1 and Figure 11 In some embodiments shown, step 120 of method 100 forms an inner spacer 248 in an inner spacer recess 230. Figure 11 A cross-sectional view of the fully wrapped gate device 200 after the inner spacer 248 is formed.

[0062] Each inner spacer 248 includes a mesh dielectric film portion 242P to pave the inner spacer recess 230, and a dielectric portion 244P surrounded by the mesh dielectric film portion 242P. To form the inner spacers 248, at least one etching process, such as an isotropic etching process, is performed to remove portions of the dielectric layer 244 and the treated mesh dielectric film 242 outside the inner spacer recess 230. In some embodiments, the isotropic etching process may be a wet etching process, using an etchant such as buffered hydrofluoric acid, hydrofluoric acid, hydrofluoric acid in nitric acid, phosphoric acid, ethylene glycol-diluted hydrofluoric acid, hydrogen chloride, or a combination thereof. In some embodiments, the isotropic etching process may be a dry etching process, employing a absorbing gas, hydrogen, nitrogen, fluorine-containing gas (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, trifluoromethane and / or hexafluoroethane), chlorine-containing gas (such as chlorine, chloroform, carbon tetrachloride and / or boron trichloride), bromine-containing gas (such as hydrogen bromide and / or tribromomethane), iodine-containing gas (such as trifluoroiodomethane), other suitable gases and / or plasma and / or combinations thereof. In some embodiments, a single isotropic etching process is performed to etch back the dielectric layer 244 and the treated mesh dielectric film 242, thereby simultaneously forming the mesh dielectric film portion 242P and the dielectric portion 244P. In some other embodiments, a first isotropic etching process is performed to remove portions of the dielectric layer 244 outside the inner spacer recesses 230 relative to the processed mesh dielectric film 242, and a second isotropic etching process is performed to remove portions of the processed mesh dielectric film 242 outside the inner spacer recesses 230 relative to the retained portions of the dielectric layer 244 and the gate spacer 226. After the etching process, the sidewalls of the gate spacer 226 and the sidewalls of the channel nanostructure 208C are exposed. The retained portions of the processed mesh dielectric film 242 in each inner spacer recess 230 constitute mesh dielectric film portions 242P, and the retained portions of the dielectric layer 244 in each inner spacer recess 230 constitute dielectric portions 244P.

[0063] like Figure 1 and Figure 12 In some embodiments shown, step 122 of method 100 forms a source / drain structure 250 in a source / drain trench 228. Figure 12 A cross-sectional view of the fully wound gate device 200 after the source / drain structure 250 is formed.

[0064] like Figure 12 As shown, the source / drain structure 250 is located on both sides of the channel nanostructure 208C and the inner spacer 248, so that the source / drain structure 250 contacts the sidewalls of the channel nanostructure 208C and the inner spacer 248.

[0065] The source / drain structure 250 is epitaxially grown within the source / drain trench 228. Epitaxial processes may include chemical vapor deposition (e.g., vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, low-pressure chemical vapor deposition, or plasma-assisted chemical vapor deposition), molecular beam epitaxy, other suitable selective epitaxial growth processes, or combinations thereof. Because the isolation structure 216 covers the substrate 202 within the source / drain trench 228, there are no nucleation sites at the bottom during source / drain epitaxial growth. Thus, if the isolation structure 216 exposes the channel semiconductor portion 208P and the substrate portion 210B, the source / drain structure 250 is grown laterally from the exposed sidewalls of the channel semiconductor portion 208P and the substrate portion 210B.

[0066] The source / drain structure 250 may include any material suitable for an n-type or p-type field-effect transistor device. For example, when forming an n-type field-effect transistor, the source / drain structure 250 may include a material (such as silicon, silicon carbide, silicon carbide, silicon phosphide, or the like) to which tensile stress is applied in the channel region, and may be in-situ doped by introducing n-type dopants (such as phosphorus or arsenic) during epitaxial processing, or by performing an implantation process (i.e., a junction implantation process) on an undoped source / drain structure 250 for out-of-situ doping. Similarly, when forming a p-type field-effect transistor, the source / drain structure 250 may include a material (such as silicon, silicon germanium, silicon germanium boride, germanium, germanium tin, or the like) to which compressive stress is applied in the channel region, and may be in-situ doped by introducing p-type dopants (such as boron, aluminum, gallium, or indium) during epitaxial processing, or by performing an implantation process (i.e., a junction implantation process) on an undoped source / drain structure 250 for out-of-situ doping. In some embodiments, the source / drain structure 250 is a p-type source / drain structure and includes boron-doped silicon-germanium. In some embodiments, the source / drain structure 250 is an n-type source / drain structure and includes phosphorus-doped silicon.

[0067] In some embodiments, a thermal annealing process is performed after epitaxial growth and doping of the source / drain structure. This process allows the dopant to be injected into a portion of the channel nanostructure 208C contacting the source / drain structure 250. This annealing process effectively extends the source / drain structure 250 into the end portion of the channel nanostructure 208C to reduce the parasitic resistance of the nanosheet transistor. In other embodiments, the thermal annealing process is performed in a subsequent process (such as after forming a high-dielectric-constant gate dielectric layer) so that the same thermal annealing process can simultaneously achieve two purposes: driving the dopant into the channel nanostructure 208C and improving the reliability of the high-dielectric-constant gate dielectric layer. In some embodiments, after annealing, the sidewalls of the source / drain structure 250 are aligned with the inner sidewalls (not shown) of the gate spacer 226. In some other embodiments, the thermal annealing process is omitted, and the sidewalls of the source / drain structure 250 are aligned with the outer sidewalls of the gate spacer 226, such as... Figure 12As shown. The pore size of the mesh dielectric film portion 242P is reduced, and it can prevent the diffusion of source / drain precursor species into the gap 232 during the formation of the source / drain structure. In this embodiment of the invention, epitaxial damage to the source / drain structure and intermingling between the channel and the sacrificial semiconductor portion can be avoided by removing the sacrificial semiconductor portion 206P before source / drain epitaxy.

[0068] like Figure 1 and Figure 13 In some embodiments shown, step 124 of method 100 forms an interlayer dielectric layer 252 on the source / drain structure 250 and the isolation structure 216. Figure 13 This is a cross-sectional view of the fully wound gate device 200 after the formation of the interlayer dielectric layer 252.

[0069] In some embodiments, the interlayer dielectric layer 252 may include a low-dielectric-constant dielectric material with a dielectric constant lower than that of silicon dioxide (approximately 3.9). The low-dielectric-constant dielectric material may include silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, silicon oxycarbide, spin-coated glass, or combinations thereof. The interlayer dielectric layer 252 may include a multilayer structure having a variety of dielectric materials, and its formation method may be chemical vapor deposition, flowable chemical vapor deposition, spin coating, or other suitable deposition processes. In some embodiments, the method of forming the interlayer dielectric layer 252 further includes performing a chemical mechanical polishing process to planarize the upper surface of the interlayer dielectric layer 252 to expose the sacrificial gate 224. The upper surface of the interlayer dielectric layer 252 may be coplanar with the upper surfaces of the sacrificial gate 224 and the gate spacer 226.

[0070] like Figure 1 and Figure 14 In some embodiments shown, step 126 of method 100 removes the sacrificial gate stack (containing sacrificial gate dielectric layer 222 and sacrificial gate 224). Figure 14 A cross-sectional view of the fully wound gate device 200 after the sacrificial gate stack (222, 224) has been removed.

[0071] The sacrificial gate dielectric layer 222 and the sacrificial gate 224 are selectively removed by an etching process, thereby forming a gate trench 254 and exposing the channel nanostructure 208C in the channel region of the fully wound gate device 200. The interlayer dielectric layer 252 protects the source / drain structure 250 during the etching process. The etching process can be a dry etching process, a wet etching process, or a combination thereof. The etching process can be adjusted to remove the sacrificial gate dielectric layer 222 and the sacrificial gate 224 without etching or with minimal etching of other units in the fully wound gate device 200, such as the interlayer dielectric layer 252, the source / drain structure 250, and the gate spacer 226. For example, in an example where the sacrificial gate 224 is composed of polysilicon and the interlayer dielectric layer 252 is composed of silicon oxide, a wet etchant such as tetramethylammonium hydroxide solution can be used to selectively remove the sacrificial gate 224. Subsequently, plasma dry etching and / or wet etching are used to remove the sacrificial gate dielectric layer 222.

[0072] like Figure 1 and Figure 15 In some embodiments shown, step 128 of method 100 forms a gate stack 260 in the gate trench 254 and the gap 232. Figure 15 A cross-sectional view of the fully wound gate device 200 formed after the gate stack 260.

[0073] like Figure 15 As shown, a gate stack 260 is deposited on and between the channel nanostructure 208C. In some embodiments, the gate stack 260 includes an interface layer 262, a gate dielectric layer 264, a work function layer 266, and a gate layer 268.

[0074] An interface layer 262 is formed on the exposed surfaces of the channel nanostructure 208C and the substrate portion 210B. The interface layer 262 facilitates adhesion of the gate dielectric layer 264 to the channel nanostructure 208C. In some embodiments, the interface layer 262 may include a dielectric material such as silicon oxide. In some embodiments, the interface layer 262 may be formed by chemical oxidation or thermal oxidation of the surface portions of the channel nanostructure 208C and the substrate portion 210B. For example, in some embodiments, the interface layer 262 is formed using ozonated deionized water (containing ozone). The thickness of the interface layer 262 may be from about 0.5 nm to about 1.5 nm. In some embodiments, the interface layer 262 is about 1 nm thick and may be formed by oxidizing about 1 nm of the channel nanostructure 208C.

[0075] Next, a gate dielectric layer 264 is compliantly deposited on the interface layer 262. The gate dielectric layer 264 covers the channel nanostructure 208C and is located on the bottom and sidewalls of the gate trench 254. In some embodiments, the gate dielectric layer 264 may comprise a high-dielectric-constant dielectric material with a dielectric constant greater than that of silicon dioxide. Examples of high-dielectric-constant dielectric materials include, but are not limited to, hafnium oxide, hafnium silicon oxide, hafnium oxysilicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, titanium oxide, or hafnium oxide-aluminum oxide alloys. The gate dielectric layer 264 is formed by chemical vapor deposition, atomic layer deposition, or other suitable compliant deposition methods. In some embodiments, the gate dielectric layer 264 is formed by a compliant deposition process such as atomic layer deposition to ensure that the high-dielectric-constant gate dielectric layer 264 has a uniform thickness around each channel nanostructure 208C. The thickness of the gate dielectric layer 264 can be from about 1 nm to about 2.5 nm. In some embodiments, the thickness of the gate dielectric layer 264 is about 1.5 nm.

[0076] A work function layer 266 is then deposited on the gate dielectric layer 264. For an n-type field-effect transistor (FET), the work function layer 266 may include an n-type work function layer capable of adjusting the threshold voltage of the n-type FET. Suitable n-type work function materials include, but are not limited to, aluminum, titanium aluminum, titanium aluminum carbide, tantalum aluminum carbide, tantalum aluminum silicide, tantalum silicon carbide, tantalum silicide, hafnium carbide, or combinations thereof. For a p-type FET, the work function layer 266 may include a p-type work function layer capable of adjusting the threshold voltage of the p-type FET. In some embodiments, the p-type work function layer includes tungsten, molybdenum, tungsten nitride, tungsten carbonitride, tantalum silicon nitride, or tantalum nitride. For example, the work function layer is formed by a compliant deposition process such as atomic layer deposition or chemical vapor deposition. In some embodiments, the thickness of the work function layer 266 may be from about 1.5 nm to about 2.5 nm.

[0077] A gate layer 268 is then formed on the work function layer 266 to fill any remaining volume in the gate trench 254 and gap 232. The gate layer 268 may comprise a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. The gate layer 268 may be formed using any suitable deposition process such as chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, or electrochemical plating.

[0078] Next, a planarization process, such as chemical mechanical polishing, is performed to remove excess portions of the gate dielectric layer 264, work function layer 266, and gate layer 268 deposited on the upper surfaces of the interlayer dielectric layer 252 and the gate spacer 226, to form a gate stack 260. The upper surface of the gate stack 260 may be coplanar with the upper surfaces of the interlayer dielectric layer 252 and the gate spacer 226.

[0079] Therefore, a gate stack 260 is formed to surround the channel nanostructure 208C and fill the gaps 232 between the channel nanostructures 208C and between the bottommost channel nanostructure 208C and the substrate portion 210B. Between the channel nanostructures 208C, a gate layer 268 is surrounded by a work function layer 266 (in a cross-sectional view), and the work function layer 266 is surrounded by a gate dielectric layer 264. In the portion of the gate stack 260 on the topmost channel nanostructure 208C, the gate layer 268 is formed on the work function layer 266, the work function layer 266 surrounds the gate layer 268, and the gate dielectric layer 264 surrounds the work function layer 266.

[0080] Additional processes can be performed to fabricate the fully wound gate device 200. For example, gate contacts (not shown for simplicity) and source / drain contacts can be formed to electrically couple to the gate stack 260 and the source / drain structure 250, respectively. Interconnect structures are then formed on the source / drain contacts and the gate contacts. The interconnect structures may include multiple dielectric layers surrounding the metallized structure (including conductive traces and vias), which form electrical connections between devices such as the fully wound gate device 200 on the substrate 202.

[0081] Figure 16 This is a flowchart of a method 300 for forming a fully wound gate device 200 using a mesh dielectric film, as described in some embodiments of the present invention. Method 300 is merely illustrative and not limited to embodiments of the invention up to the point not explicitly stated in the claims. Additional steps may be provided before, during, and after method 300, and additional embodiments of the method may substitute, omit, or interchange some of the stated steps. Some embodiments of method 300 will be paired with... Figures 17 to 20 The following explains this. Some aspects of method 300 are the same as those of method 100, which will be briefly described below. Other aspects of method 300 differ from those of method 100, which will be described in detail below.

[0082] Method 300 includes steps 102 to 106, 112, and 116 to 128, in conjunction with Figure 1 The method described above is the same. The difference between method 300 and method 100 is that method 300 uses a dielectric material instead of a semiconductor material as a placeholder for forming the gas spacer of the metal gate. Method 300 is followed by additional steps to replace the sacrificial semiconductor portion 206P with the sacrificial dielectric portion 229P, and to remove these sacrificial dielectric portions 229P after forming the mesh dielectric film 240.

[0083] like Figure 16As shown, steps 102 to 106 of method 300 form a plurality of fin structures (each including a fin stack portion and a base portion) with the underlying substrate by stacking self-interlaced channels and sacrificial semiconductor layers, followed by forming a sacrificial gate structure on the fin structures. In some embodiments, after step 108 to form source / drain trenches 228 in each fin structure, step 109 of method 300 is performed to replace the sacrificial semiconductor portion 206P with a sacrificial dielectric portion 229P. Figure 17 A cross-sectional view of the fully wound gate device 200 formed after the sacrificial dielectric portion 229P is below the channel semiconductor portion 208P.

[0084] To form the sacrificial dielectric portion 229P, the sacrificial semiconductor portion 206P is first selectively removed relative to the channel semiconductor portion 208P. In some embodiments, the method for removing the sacrificial semiconductor portion 206P may be a selective etching process using an etchant that is selective to the material of the sacrificial semiconductor portion 206P, so as to remove the sacrificial semiconductor portion 206P without substantially affecting the channel semiconductor portion 208P. In some embodiments, the etching process is an isotropic etching process, which may be a dry etching process or a wet etching process. In some embodiments, the selective etching process may include using a suitable oxidant, such as ozone, to oxidize the sacrificial semiconductor portion 206P. The oxidized sacrificial semiconductor portion 206P may then be selectively removed. In some embodiments, when the channel semiconductor portion 208P comprises silicon and the sacrificial semiconductor portion 206P comprises silicon germanium, the method for selectively removing the sacrificial semiconductor portion 206P may involve applying hydrogen chloride gas at a temperature of about 500°C to about 700°C, or applying a mixture of carbon tetrafluoride, sulfur hexafluoride, and trifluoromethane. Selective removal of the sacrificial semiconductor portion 206P can release the channel semiconductor portion 208P to form gaps between adjacent channel semiconductor portions 208P, and between the bottommost channel semiconductor portion 208P and the substrate portion 210B in the fin structure 210.

[0085] A sacrificial dielectric layer is then compliantly deposited on the channel semiconductor portion 208P, the substrate portion 210B, and the sacrificial gate structure 220 to fill the gaps (i.e., spaces) between adjacent channel semiconductor portions 208P. In some embodiments, the sacrificial dielectric layer comprises a dielectric oxide such as silicon oxide, silicon dioxide, or silicon-rich oxide nitride. The sacrificial dielectric layer can be formed using compliant deposition processes such as chemical vapor deposition or atomic layer deposition. In some embodiments, the thickness of the sacrificial dielectric layer is controlled so that the sacrificial dielectric layer does not completely fill the gaps (not shown). In some embodiments, the sacrificial dielectric layer completely fills the gaps.

[0086] Next, an etching process, such as isotropic etching, is performed to remove portions of the sacrificial dielectric layer outside the gaps in the structure. In some embodiments, wet etching or diluted hydrofluoric acid cleaning is performed. The remaining portions of the sacrificial dielectric layer in the gaps form sacrificial dielectric portions 229P. In some embodiments, the sidewalls of sacrificial dielectric portions 229P are aligned with the sidewalls of channel semiconductor portions 208P.

[0087] like Figure 16 and Figure 18 In some embodiments shown, step 111 of method 300 then involves laterally etching the sacrificial dielectric portion 229P to form an inner spacer recess 230. Figure 18 A cross-sectional view of the fully wound gate device 200 after laterally etching the sacrificial dielectric portion 229P to form the inner spacer recess 230.

[0088] The sacrificial dielectric portion 229P is selectively etched laterally to form the inner spacer recess 230, while substantially not etching the channel semiconductor portion 208P. In some embodiments, the method of selectively etching the sacrificial dielectric portion 229P may be an isotropic dry etching process, employing an etching gas composition including halogen-containing compounds, ammonia, and amines. In some embodiments, the halogen-containing compound is a fluorine-containing compound. In some embodiments, the fluorine-containing compound may include, but is not limited to, hydrofluoric acid, carbon tetrafluoride, trifluoromethane, sulfur hexafluoride, difluoromethane, or hexafluoroethane. In some embodiments, the amine may include, but is not limited to, methylamine, dimethylamine, trimethylamine, ethylamine, diethylamine, triethylamine, methyl ethylamine, N,N-diethylmethylamine, N,N-dimethylethylamine, isopropylamine, N-ethyldiisopropylamine, or tributylamine. In some embodiments, the etching gas composition includes hydrofluoric acid, ammonia, and trimethylamine. In some embodiments, the lateral etching distance is equal to the thickness of the gate spacer 226. The sidewall of the retained sacrificial dielectric portion 229P is aligned with the inner sidewall of the gate spacer 226.

[0089] like Figure 16 and Figure 19 In some embodiments shown, step 112 of method 300 deposits a mesh dielectric film 240 on the fully wound gate device 200, with the inner spacer recess 230 lining it. Figure 19 This is a cross-sectional view of the fully wound gate device 200 after the formation of the mesh dielectric film 240. (See figure) Figure 19 As shown, a mesh dielectric film 240 is deposited on the source / drain regions, the sacrificial dielectric portion 229P, the channel semiconductor portion 208P, and the exposed surfaces of the sacrificial gate structure 220. The process for forming the mesh dielectric film 240 has been configured... Figure 7 The above explanation will not be elaborated upon here.

[0090] like Figure 16 and Figure 20In some embodiments shown, step 113 of method 300 removes the sacrificial dielectric portion 229P to release the channel nanostructure 208C. Figure 20 A cross-sectional view of the fully wound gate device 200 after the sacrificial dielectric portion 229P has been removed.

[0091] The selective removal of the sacrificial dielectric portion 229P releases the channel semiconductor portion 208P, which transforms into a channel nanostructure 208C. In some embodiments, the channel nanostructure 208C is a nanosheet. In some embodiments, the removal method of the sacrificial dielectric portion 229P may be a selective etching process, wherein the etchant used is selective to the material of the sacrificial dielectric portion 229P to remove the sacrificial dielectric portion 229P without substantially affecting the channel semiconductor portion 208P, the gate spacer 226, and the mesh dielectric film 240. In some embodiments, the etching process is an isotropic etching process, which may be a dry etching process or a wet etching process.

[0092] Some embodiments perform steps 116 to 128 of method 300 after removing the sacrificial dielectric portion 229P (which, in conjunction with...). Figure 1 Method 100 (same as described above) involves performing a mesh sealing step on the mesh dielectric film 240 to form a processed mesh dielectric film 242, forming a dielectric layer 244 on the processed mesh dielectric film 242 to fill the inner spacer recess 230, forming an inner spacer 248 in the inner spacer recess 230, forming a source / drain structure 250 in the source / drain trench 228, forming an interlayer dielectric layer 252 on the source / drain structure 250, removing the sacrificial gate stack (222, 224) to provide a gate trench 254, and forming a gate stack 260 in the gate trench 254 and the gap 232.

[0093] An embodiment of the present invention relates to a method for forming a semiconductor device. The method includes forming a sacrificial gate structure on a channel region of a substrate structure. The substrate structure includes a plurality of interleaved channel semiconductor portions and a plurality of sacrificial material portions. After etching a plurality of source / drain regions of the substrate structure to expose the sidewalls of the channel semiconductor portions and the sacrificial material portions, the sidewalls of the sacrificial material portions are selectively recessed to form a plurality of recesses. A mesh dielectric film is then deposited to pad the recesses. The mesh dielectric film includes a porous dielectric material of a first density. An etchant is then passed through the mesh dielectric film to remove the sacrificial material portions; a sealing mesh step is performed on the mesh dielectric film to form a treated mesh dielectric film of a second density, the second density being greater than the first density. A dielectric layer is then deposited on the treated mesh dielectric film to fill the recesses. The treated mesh dielectric film and dielectric layer are then etched back to form a plurality of inner spacers in the recesses.

[0094] In some embodiments, the step of depositing a mesh dielectric film includes using atomic layer deposition to deposit the mesh dielectric film.

[0095] In some embodiments, the mesh dielectric film includes porous silicon oxide, porous silicon nitride, porous silicon carbonitride, porous silicon carbonitride, or porous silicon carbide.

[0096] In some embodiments, the first density is 1 g / cm³. 3 Up to 2.5 g / cm 3 And the second density is 1.5 g / cm³. 3 Up to 3g / cm 3 .

[0097] In some embodiments, the step of sealing the mesh includes: treating the mesh dielectric film with an oxygen source to adjust the mesh dielectric film into an oxygen-treated mesh dielectric film; and annealing the oxygen-treated mesh dielectric film.

[0098] In some embodiments, the step of annealing the oxygen-treated mesh dielectric film includes applying thermal energy, ultraviolet energy, or both to the oxygen-treated mesh dielectric film.

[0099] In some embodiments, the step of sealing the mesh includes: performing helium plasma treatment on the mesh dielectric film; and performing ammonia plasma treatment on the helium plasma-treated mesh dielectric film.

[0100] In some embodiments, the sacrificial material portion is a plurality of sacrificial semiconductor portions.

[0101] In some embodiments, the method further includes forming a base structure, which includes forming a stack of multiple channel semiconductor layers and multiple sacrificial semiconductor layers with interlaced arrangement on a substrate; and patterning the stack.

[0102] In some embodiments, the sacrificial material portion is a plurality of sacrificial dielectric portions.

[0103] In some embodiments, the method further includes replacing a plurality of sacrificial semiconductor portions into sacrificial dielectric portions.

[0104] Another embodiment of the present invention relates to a method for forming a semiconductor device. The method includes forming a stack on a substrate, the stack comprising a plurality of interleaved first semiconductor layers and a plurality of second semiconductor layers. After patterning the stack to form a base structure (which includes a plurality of interleaved first semiconductor portions and a plurality of second semiconductor portions), a sacrificial gate structure is formed (which includes a sacrificial gate stack located on a channel portion of the base structure, and a plurality of gate spacers located on the sidewalls of the sacrificial gate stack). The portion of the base structure not covered by the sacrificial gate structure is then removed to form a plurality of source / drain trenches. The sidewalls of the second semiconductor portions are then laterally etched to form a plurality of inner spacer recesses. A compliant mesh dielectric film is then deposited along the sacrificial gate structure, the inner spacer recesses, and the exposed surfaces of the first semiconductor portions. The mesh dielectric film includes a plurality of interconnected holes. An etchant is then passed through the mesh dielectric film to etch the second semiconductor portions to release the first semiconductor portions. After processing the mesh dielectric film to seal the interconnected holes, a dielectric layer is deposited on the mesh dielectric film to fill the inner spacer recesses. Remove the portion of the dielectric layer and mesh dielectric film outside the inner spacer recess.

[0105] In some embodiments, the mesh dielectric film includes porous silicon oxide, porous silicon nitride, porous silicon carbonitride, porous silicon carbonitride, or porous silicon carbide.

[0106] In some embodiments, the density of the mesh dielectric film increases after the step of treating the mesh dielectric film.

[0107] In some embodiments, the step of processing the mesh dielectric film includes: treating the mesh dielectric film with an oxygen source; and thermally annealing the oxygen-treated mesh dielectric film to seal the pores in the mesh dielectric film.

[0108] In some embodiments, the step of treating the mesh dielectric film includes applying helium plasma to the mesh dielectric film; and applying ammonia plasma to the helium plasma-treated mesh dielectric film to seal the pores in the mesh dielectric film.

[0109] Another embodiment of the present invention relates to a semiconductor device. The semiconductor device includes a plurality of channel nanostructures located on a substrate; and a plurality of inner spacers interspersed with the channel nanostructures. Each inner spacer includes a mesh dielectric film portion and a dielectric portion, with the mesh dielectric film portion surrounding the dielectric portion. The mesh dielectric film portion has a porous structure, and the density of the porous structure is less than the density of the dielectric portion.

[0110] In some embodiments, the density of the mesh dielectric film portion is 1.5 g / cm³. 3 Up to 3 g / cm 3 .

[0111] In some embodiments, the mesh dielectric film portion comprises a material different from the material of the dielectric portion.

[0112] In some embodiments, the channel nanostructures are perpendicularly separated from each other.

[0113] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: A sacrificial gate structure is formed on a channel region of a base structure, the base structure including multiple interleaved channel semiconductor portions and multiple sacrificial material portions; Etch multiple source / drain regions of the base structure to expose the sidewalls of multiple channel semiconductor portions and multiple sacrificial material portions; Selectively recess the sidewalls of multiple sacrificial material portions to form multiple recesses; A mesh dielectric film is deposited to line the plurality of said depressions, and the mesh dielectric film comprises a porous dielectric material of a first density; An etchant is passed through the mesh dielectric film to remove multiple portions of the sacrificial material. The step of sealing the mesh dielectric film further forms a treated mesh dielectric film with a second density, and the second density is greater than the first density. A dielectric layer is deposited on the treated mesh dielectric film to fill the plurality of said depressions; and The treated mesh dielectric film and the dielectric layer are etched back to form a plurality of inner spacers in the plurality of said recesses.

2. The method for forming a semiconductor device as claimed in claim 1, wherein the step of depositing the mesh dielectric film includes using atomic layer deposition to deposit the mesh dielectric film.

3. The method for forming a semiconductor device as claimed in claim 1, wherein the mesh dielectric film comprises porous silicon oxide, porous silicon nitride, porous silicon carbonitride, porous silicon carbon oxynitride, or porous silicon carbide.

4. The method for forming a semiconductor device as claimed in claim 1, wherein the first density is 1 g / cm³. 3 Up to 2.5 g / cm 3 And the second density is 1.5 g / cm³. 3 Up to 3 g / cm 3 .

5. A method for forming a semiconductor device, comprising: A stack is formed on a substrate, and the stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers interleaved; The stack is patterned to form a base structure comprising multiple interleaved first semiconductor portions and multiple second semiconductor portions; A sacrificial gate structure is formed, comprising a sacrificial gate stack located on a channel portion of the base structure, and a plurality of gate spacers located on the sidewalls of the sacrificial gate stack; Remove the portion of the base structure not covered by the sacrificial gate structure to form multiple source / drain trenches; Laterally etch the sidewalls of multiple second semiconductor portions to form multiple inner spacer recesses; A conformable mesh dielectric film is deposited along the sacrificial gate structure, the plurality of inner spacer recesses, and the exposed surfaces of the plurality of first semiconductor portions, and the mesh dielectric film includes a plurality of interconnected pores. An etchant is passed through the mesh dielectric film to etch multiple second semiconductor portions, thereby releasing multiple first semiconductor portions; The mesh dielectric film is processed to seal the interconnected plurality of said pores; A dielectric layer is deposited on the mesh dielectric film to fill the plurality of the inner spacer recesses; as well as Remove portions of the dielectric layer and the mesh dielectric film outside the recesses of the multiple inner spacers.

6. The method for forming a semiconductor device as claimed in claim 5, wherein the mesh dielectric film comprises porous silicon oxide, porous silicon nitride, porous silicon carbonitride, porous silicon carbonitride, or porous silicon carbide.

7. The method for forming a semiconductor device as claimed in claim 5, wherein after the step of processing the mesh dielectric film, the density of the mesh dielectric film increases.

8. A semiconductor device, comprising: Multiple channel nanostructures are located on a substrate; as well as Multiple inner spacers are interspersed with multiple channel nanostructures, and each of the multiple inner spacers includes a mesh dielectric film portion and a dielectric portion, wherein the mesh dielectric film portion surrounds the dielectric portion, and the mesh dielectric film portion has a porous structure, and the density of the porous structure is less than the density of the dielectric portion.

9. The semiconductor device of claim 8, wherein the density of the mesh dielectric film portion is 1.5 g / cm³. 3 Up to 3 g / cm 3 .

10. The semiconductor device of claim 8, wherein the material of the mesh dielectric film portion is different from the material of the dielectric portion.

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