Semiconductor structure and method of manufacturing the same

Abstract

Semiconductor structures are provided. In some embodiments, a semiconductor structure includes a silicon-on-insulator (SOI) structure, and an optical device disposed on the SOI structure. In some embodiments, the SOI structure includes a silicon substrate, a tensile film located on the silicon substrate, a buried insulator layer located on the tensile film, and a top silicon layer including a silicon core structure located on the buried insulator layer. The tensile stress of the tensile film is different from the tensile stress of the silicon substrate. Embodiments of the present application also provide a method of fabricating a semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor structures and methods for manufacturing semiconductor structures. Background Technology

[0002] Semiconductor devices are used in a variety of electronic devices, such as mobile phones, laptops, desktops, tablets, watches, gaming systems, and a wide range of other industrial, commercial, and consumer electronics. Semiconductor devices typically consist of a semiconductor portion (such as a silicon waveguide) and wiring portions formed within the semiconductor portion (such as metal wiring layers and vias). Summary of the Invention

[0003] One embodiment of the present invention provides a semiconductor structure, including: a silicon-on-insulator (SOI) structure, including a silicon substrate, a stretched film on the silicon substrate, a buried insulating layer on the stretched film, and a top silicon layer on the buried insulating layer, wherein the tensile stress of the stretched film is different from the tensile stress of the silicon substrate; and an optical device disposed on the silicon-on-insulator structure.

[0004] Another embodiment of the present invention provides a semiconductor structure, including: a silicon substrate; a stack of stretched films disposed on the silicon substrate; a buried insulating layer disposed on the top surface of the stack of stretched films; and a top silicon layer including a silicon core structure disposed on the buried insulating layer, wherein the silicon substrate, the stack of stretched films, the buried insulating layer, and the silicon core structure together form a silicon-on-insulator (SOI) structure.

[0005] Another aspect of the present invention provides a method for manufacturing a semiconductor structure, comprising: depositing a stretched film on a silicon substrate; depositing a buried insulating layer on a top surface of the stretched film; depositing a top silicon layer on the buried insulating layer; and forming a silicon core structure by processing the top silicon layer, wherein the silicon core structure includes a first portion protruding from a second portion. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) structure according to some embodiments;

[0008] Figure 1A According to some embodiments Figure 1 A top view of the semiconductor structure in the image;

[0009] Figure 1B This is a graph illustrating the importance of maintaining the TE mode for the optical performance of optical devices;

[0010] Figure 1C This is a diagram showing the compressive stress caused by a metal layer (e.g., M1) on the optics beneath the metal layer;

[0011] Figure 1D This is a graph showing how the compressive stress caused by the induced stress leads to a decrease in the effective refractive index difference (Δn_eff) between the transverse electrical (TE) mode and the transverse magnetic (TM) mode in the optics;

[0012] Figure 1E This is a diagram showing the TM mode appearing due to the decrease of Δn_eff;

[0013] Figure 2A and Figure 2B These are cross-sectional views of semiconductor structures including SOI structures according to other embodiments;

[0014] Figures 3-13 These are a series of cross-sectional views of an intermediate semiconductor structure according to some embodiments, illustrating the fabrication process. Figure 1 Some exemplary steps of the method for constructing semiconductor structures in the process;

[0015] Figure 14 Manufacturing according to some embodiments Figure 1 Flowchart of the method for constructing semiconductor structures in the process;

[0016] Figures 15-27 These are a series of cross-sectional views of an intermediate semiconductor structure according to other embodiments, illustrating the fabrication process. Figure 2B Some exemplary steps of the method for constructing semiconductor structures in the process;

[0017] Figure 28 Manufacturing according to other embodiments Figure 2B The flowchart shows the method for constructing semiconductor structures. Detailed Implementation

[0018] This invention provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. Devices or apparatuses may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Moreover, the terms “first,” “second,” “third,” “fourth,” etc., are merely general identifiers and can be used interchangeably in various embodiments. For example, while an element (e.g., a wire) may be referred to as a “first” element in some embodiments, it may be referred to as a “second” element in other embodiments.

[0020] Semiconductor waveguides (such as silicon, indium phosphide (InP), gallium arsenide (GaAs), or silicon nitride (Si3N4)) are widely used in various photonics, optoelectronics, and microelectromechanical systems (MEMS) applications due to their high refractive index contrast, active and passive functionality, integration with electronics and photonics, and the versatility of the material. For example, semiconductor waveguides can be used in telecommunications, data centers and optical interconnects, sensing and lab-on-a-chip, quantum and nonlinear optics, and LiDAR and imaging. It should be noted that one or more metal layers, for example, placed above a semiconductor waveguide, may induce compressive stress on the semiconductor core of the waveguide. This can distort light propagation, for example, by rotating the polarization of light propagation from the transverse electrical (TE) mode to the transverse magnetic (TM) mode. This TE-TM mode rotation is undesirable, as it degrades optical signal quality, increases optical signal loss, and causes optical signal dispersion. Reduced or balanced compressive stress on the semiconductor core of the waveguide is desirable.

[0021] In view of the above, according to this disclosure, in some embodiments, a semiconductor structure is provided. The semiconductor structure includes a silicon-on-insulator (SOI) structure, which includes a silicon substrate, a buried insulating layer above the silicon substrate, and a top silicon layer on the buried insulating layer. The semiconductor structure also includes a stretched film extending laterally between the silicon substrate and the buried insulating layer, and optical devices disposed on the SOI structure. The tensile stress of the stretched film is greater than the tensile stress of the silicon substrate. The optical devices may be silicon waveguides.

[0022] In other embodiments, a semiconductor structure is provided. The semiconductor structure includes a silicon substrate, a stack of stretched films disposed on the silicon substrate, a buried insulating layer disposed on top of the stack of stretched films, a top silicon layer including a silicon core structure disposed on the buried insulating layer, and a top insulating layer disposed on the silicon core structure. The silicon substrate, the stack of stretched films, the buried insulating layer, and the silicon core structure together form a silicon-on-insulator (SOI) structure. The buried insulating layer, the silicon core structure, the top insulating layer, and a first interlayer dielectric (ILD) layer disposed on the top insulating layer together form a silicon waveguide.

[0023] In other embodiments, a method of fabricating a semiconductor structure is provided. The method includes depositing a stretched film on a silicon substrate, depositing a buried insulating layer on top of the stretched film, depositing a top silicon layer on the buried insulating layer, forming a silicon core structure including a first portion protruding from a second portion by processing the top silicon layer, depositing the top insulating layer on the silicon core structure, and depositing a first interlayer dielectric (ILD) layer on the top insulating layer. The buried insulating layer, the silicon core structure, the top insulating layer, and the first ILD layer together form a silicon waveguide.

[0024] In this way, a stretched film or a stack of stretched films is added under the buried insulator (e.g., buried oxide (BOX)) layer of the SOI structure to compensate for the compressive stress caused by one or more metal layers on the silicon waveguide to maintain its TE mode, thereby advantageously improving the optical performance of the silicon waveguide formed on the SOI structure.

[0025] Figure 1 This is a cross-sectional view of a semiconductor structure 100 including a silicon-on-insulator (SOI) structure 50 according to various embodiments of the present disclosure. An SOI structure is a layered semiconductor structure that can be used to improve the performance of integrated circuits. It typically includes three main layers: a silicon substrate (which can be used as a bottom processing wafer formed from bulk silicon material to provide mechanical support), a buried oxide (so-called "BOX") layer (as an intermediate insulating layer), and a top silicon layer (which can be used as an active silicon layer for forming active devices). SOI structures can offer benefits such as reduced parasitic capacitance, increased radiation hardness, better isolation, and reduced latch-up in CMOS circuits.

[0026] In some embodiments of this disclosure, the semiconductor structure 100 includes an SOI structure 50, which includes a silicon substrate 10, a stretched film 12 disposed on the top surface of the silicon substrate 10, a buried insulating layer 14 disposed on the top surface of the stretched film 12, and a top silicon layer 16' disposed on the top surface of the buried insulating layer 14. The top silicon layer 16' may be formed as a silicon core structure 16 (refer to later). Figure 5 and Figure 6 (To be explained). A silicon substrate 10, a stretched film 12, a buried insulating layer 14, and a top silicon layer 16' together constitute a silicon-on-insulator (SOI) structure 50. In some embodiments of this disclosure, the stretched film 12 extends completely between the silicon substrate 10 and the buried insulating layer 14 to completely cover the silicon substrate 10. In some embodiments of this disclosure, the tensile stress of the stretched film 12 is greater than the tensile stress of the silicon substrate 10.

[0027] In some embodiments of this disclosure, the silicon substrate 10 comprises a bulk silicon material. In some embodiments, the stretched film 12 comprises a stretched material selected from silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (e.g., SiC). In some embodiments, the buried insulating layer 14 is a buried oxide (BOX) layer comprising silicon oxide such as silicon dioxide (e.g., SiO2). In some embodiments, the top silicon layer 16' comprises a silicon material.

[0028] In some embodiments of this disclosure, the thickness T1 of the stretch film 12 is in the range of 0.01 μm to 10 μm. In some embodiments, the thickness T2 of the buried insulating layer 14 is in the range of 1 μm to 5 μm. In some embodiments, the ratio of the thickness T1 of the stretch film 12 to the thickness T2 of the buried insulating layer 14 is in the range of 0.005 to 5. In some embodiments, the tensile stress of the stretch film 12 is in the range of 0.1 GPa to 2 GPa. In some embodiments, for processes such as EPI and FEOL, the durability temperature of the stretch film 12 is greater than 1100°C.

[0029] In some embodiments of this disclosure, the semiconductor structure 100 includes an optical device 70 disposed on an SOI structure 50. In some embodiments, the optical device 70 is a silicon waveguide. In some embodiments, the semiconductor structure 100 further includes a top insulating layer 18 disposed on a silicon core structure 16, and a first interlayer dielectric (ILD) layer 20 disposed on the top insulating layer 18. In some embodiments, the top insulating layer 18 comprises borosilicate glass (BPSG). In some embodiments, the first ILD layer 20 comprises silicon oxide (e.g., SiO2). The buried insulating layer 14, the silicon core structure 16, the top insulating layer 18, and the first ILD layer 20 together constitute the silicon waveguide 70.

[0030] The silicon core structure 16 has a high refractive index, while the buried insulating layer 14, the top insulating layer 18, and the first ILD layer 20 surrounding the silicon core structure 16 have low refractive indices and can be used as covers for the silicon core structure 16. The buried insulating layer 14 can be used as a bottom cover for the silicon core structure 16, electrically and optically isolating the silicon core structure 16 from the silicon substrate 10 and playing a role in thermal and mechanical stress management. The top insulating layer 18 and the first ILD layer 20 can together be used as a top cover for the silicon core structure 16. In this way, the silicon waveguide 70 uses total internal reflection to confine light or radiation within the silicon core structure 16.

[0031] In some embodiments of this disclosure, the thickness T3 of the top insulating layer 18 is in the range of 0.2 μm to 0.4 μm. In some embodiments, the thickness T4 of the first ILD layer 20 is in the range of 0.5 μm to 0.7 μm. In some embodiments, the ratio of the thickness T3 of the top insulating layer 18 to the thickness T4 of the first ILD layer 20 is in the range of 0.3 to 0.8.

[0032] In some embodiments of this disclosure, the semiconductor structure 100 further includes a second ILD layer 22 disposed on the first ILD layer 20, a first conductive layer (e.g., M1) 24 embedded within the second ILD layer 22, a third ILD layer 26 disposed above the second ILD layer 22, and a second conductive layer (e.g., M2) 28 embedded within the third ILD layer 26. In some embodiments, the first conductive layer, the second conductive layer, and other conductive layers and conductive vias (not shown) may jointly form the interconnect structure (not shown) of the semiconductor structure 100.

[0033] In some embodiments of this disclosure, the second ILD layer 22 and the third ILD layer 26 may include silicon oxide (e.g., SiO2), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), silicon carbide hydride (SiCOH), etc. In some embodiments, the first conductive layer (e.g., M1) 24 and the second conductive layer (e.g., M2) 28 may include metallic materials, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), nickel (Ni), etc.

[0034] In some embodiments of this disclosure, the semiconductor structure 100 further includes a capping layer 25 vertically disposed between the second ILD layer 22 and the third ILD layer 26 to separate them from each other. In some embodiments, the capping layer 25 comprises, for example, silicon carbide (SiC).

[0035] Figure 1AAccording to some embodiments Figure 1 Top view 100A of semiconductor structure 100 in the image. Figure 1A The diagram shows the positional relationship between the silicon core structure 16, conductive layers (e.g., M1 and M2), and stretched film 12 of the silicon waveguide 70 along the X and Y directions. For the purpose of simplification and clarity, other components, such as the silicon substrate 10, buried insulating layer 14, top insulating layer 18, first ILD layer 20, second ILD layer 22, capping layer 25, and third ILD layer 26, are omitted.

[0036] As mentioned, one or more metal layers on the silicon waveguide 70, such as the first conductive wiring layer M1, may generate compressive stress in the silicon core structure 16 of the silicon waveguide 70. This can reduce the effective refractive index difference (Δn_eff) between the TE and TM modes of the silicon waveguide 70, potentially leading to the undesirable excitation of TM mode components. The second conductive wiring layer M2 on the first conductive layer 24 can help alleviate some of the undesirable compressive stress, but cannot completely eliminate it.

[0037] Thus, the stretch film 12 added below the buried insulator layer 14 of the SOI structure 50 of the semiconductor structure 100 can compensate for the compressive stress caused by one or more metal layers (e.g., M1) on the silicon waveguide 70, so as to advantageously restore the effective refractive index difference (Δn_eff), maintain the TE mode, and suppress the rotation from the TE mode to the TM mode, thereby advantageously improving the optical performance of the silicon waveguide 70.

[0038] Figure 1B This is a graph illustrating the importance of maintaining the TE mode for the optical performance of optical devices. Figure 1C This is a diagram showing the compressive stress caused by a metal layer (e.g., M1) on the optics beneath the metal layer. Figure 1D This is a graph showing how the compressive stress caused by the induced stress leads to a decrease in the effective refractive index difference (Δn_eff) between the transverse electrical (TE) mode and the transverse magnetic (TM) mode in the optics. Figure 1E This is a diagram showing the TM mode that appears due to the decrease in effective refractive index difference (Δn_eff).

[0039] It is important to note that maintaining the TE mode is crucial for optimal optical performance of silicon waveguides. The refractive index of the material is polarization-dependent, and the optical signals in the TE and TM modes propagate through the material at different speeds and directions. Therefore, the rotation from TE to TM can lead to dispersion and signal distortion. The TE mode is desirable because it offers advantages in optical confinement, allowing for, for example, smaller waveguide dimensions, lower propagation loss, and favorable lateral electric field alignment. It should also be noted that the M1 metal wiring layer induces compressive stress, which reduces the effective refractive index difference (Δn_eff) between the TE and TM modes, potentially leading to the excitation or generation of the undesirable TM mode. While the M2 wiring layer above the M1 layer can help reduce the induced compressive stress, it cannot completely eliminate it.

[0040] As mentioned, for example, introducing a stretch film under the BOX layer in SOI can effectively compensate for the compressive stress caused by one or more metal wirings and can help maintain the TE mode of the optics, thereby advantageously improving the optical performance of the optics.

[0041] Figure 2A This is a cross-sectional view of a semiconductor structure 200A including an SOI structure 50A according to other embodiments. In some embodiments, the semiconductor structure 200A includes a silicon substrate 10, a stack 12' of stretched films (e.g., 12A and 12B) disposed on the silicon substrate 10, a buried insulating layer 14 disposed on top of the stack 12' of stretched films, a top silicon layer 16' including a silicon core structure 16 disposed on the buried insulating layer, a top insulating layer 18 disposed on the silicon core structure 16, and a first interlayer dielectric (ILD) layer 20 disposed on the top insulating layer 18. The silicon substrate 10, the stack 12' of stretched films, the buried insulating layer 14, and the top silicon layer 16' together constitute the SOI structure 50A. The buried insulating layer 14, the silicon core structure 16, the top insulating layer 18, and the first ILD layer 20 together constitute the silicon waveguide 70.

[0042] In some embodiments of this disclosure, the stretched film 12A is formed of a stretching material selected from silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (SiC), and the stretched film 12B is formed of a stretching material selected from silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (SiC). In some embodiments, the stretched films 12A and 12B are formed of the same stretching material, while in other embodiments, the stretched films 12A and 12B are formed of different stretching materials. In some embodiments, the first ILD layer 20 is formed of silicon oxide (e.g., SiO2).

[0043] In some embodiments, the thickness T1' of the stacked members 12' of the stretched film is in the range of 0.01 μm to 10 μm. In some embodiments, the thickness T2 of the buried insulating layer 14 is in the range of 1 μm to 5 μm. In some embodiments, the ratio of the thickness T1' of the stacked members 12' of the stretched film to the thickness T2 of the buried insulating layer 14 is in the range of 0.005 to 5.

[0044] In some embodiments of this disclosure, the thickness T3 of the top insulating layer 18 is in the range of 0.2 μm to 0.4 μm. In some embodiments, the thickness T4 of the first ILD layer 20 is in the range of 0.5 μm to 0.7 μm. In some embodiments, the ratio of the thickness T3 of the top insulating layer 18 to the thickness T4 of the first ILD layer 20 is in the range of 0.3 to 0.8.

[0045] In some embodiments of this disclosure, the semiconductor structure 200A further includes a second ILD layer 22 disposed on the first ILD layer 20, a first conductive layer (e.g., M1) 24 embedded within the second ILD layer 22, a third ILD layer 26 disposed above the second ILD layer 22, and a second conductive layer (e.g., M2) 28 embedded within the third ILD layer 26. In some embodiments, the semiconductor structure 200A further includes a capping layer 25 formed of, for example, silicon carbide (SiC) and disposed between the second ILD layer 22 and the third ILD layer 26 to separate them from each other.

[0046] In this way, the stack 12' of the stretched films (e.g., 12A and 12B) added below the BOX layer 14 of the SOI structure 50A of the semiconductor structure 200A can compensate for the compressive stress caused by one or more conductive wiring layers (e.g., M1) on the silicon waveguide 70, thereby advantageously improving the optical performance of the silicon waveguide 70.

[0047] Figure 2B This is a cross-sectional view of a semiconductor structure 200B including an SOI structure 50B according to yet another embodiment. (And...) Figure 2A Similar to the implementation shown, the semiconductor structure 200B includes a silicon substrate 10, a stack 12' of stretched films (e.g., 12A, 12B, and 12C) disposed on the silicon substrate 10, a buried insulating layer 14 disposed on top of the stack 12' of the stretched films, a top silicon layer 16' including a silicon core structure 16 disposed on the buried insulating layer, a top insulating layer 18 disposed on the silicon core structure, and a first ILD layer 20 disposed on the top insulating layer 18.

[0048] Although Figure 2A and Figure 2BTwo stretched films (e.g., 12A-12B) and three stretched films (e.g., 12A-12C) are shown respectively, but in the stack 12', the number of stretched films (e.g., 12A, 12B, 12C) stacked on top of each other can be any integer greater than 2 without departing from the spirit of this disclosure. In some embodiments, the number of stretched films in the stack 12' can be in the range of 2 to 15. The silicon substrate 10, the stack of stretched films 12', the buried insulating layer 14, and the silicon core structure 16 together constitute the SOI structure 50B. The buried insulating layer 14, the top silicon layer 16', the top insulating layer 18, and the first ILD layer 20 together constitute the silicon waveguide 70.

[0049] In some embodiments of this disclosure, one of the stretched films (e.g., 12A, 12B, and 12C) is formed from a stretching material selected from silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (SiC). In some embodiments, the stretched films (e.g., 12A, 12B, and 12C) are formed from the same stretching material selected from silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (SiC), while in other embodiments, the stretched films (e.g., 12A, 12B, and 12C) are formed from different stretching materials selected from any combination of silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (SiC).

[0050] In some embodiments, the thickness T1' of the stacked members 12' of the stretched film is in the range of 0.01 μm to 10 μm. In some embodiments, the thickness T2 of the buried insulating layer 14 is in the range of 1 μm to 5 μm. In some embodiments, the ratio of the thickness T1' of the stacked members 12' of the stretched film to the thickness T2 of the buried insulating layer 14 is in the range of 0.005 to 5.

[0051] In some embodiments of this disclosure, the thickness T3 of the top insulating layer 18 is in the range of 0.2 μm to 0.4 μm. In some embodiments, the thickness T4 of the first ILD layer 20 is in the range of 0.5 μm to 0.7 μm. In some embodiments, the ratio of the thickness T3 of the top insulating layer 18 to the thickness T4 of the first ILD layer 20 is in the range of 0.3 to 0.8.

[0052] In some embodiments of this disclosure, similarly, the semiconductor structure 200B further includes a second ILD layer 22 disposed on the first ILD layer 20, a first conductive layer (e.g., M1) 24 embedded within the second ILD layer 22, a third ILD layer 26 disposed above the second ILD layer 22, and a second conductive layer (e.g., M2) 28 embedded within the third ILD layer 26. In some embodiments, the semiconductor structure 200A further includes a capping layer 25, such as silicon carbide (SiC), disposed between the second ILD layer 22 and the third ILD layer 26.

[0053] Thus, the stack 12' of the stretched films (e.g., 12A, 12B, and 12C) added under the buried insulating layer 14 (e.g., BOX layer) of the SOI structure 50B of the semiconductor structure 200B can compensate for the compressive stress caused by one or more conductive layers (e.g., M1) on the silicon waveguide 70, thereby maintaining its TE mode and thus advantageously improving the optical performance of the silicon waveguide 70.

[0054] Figures 3-13 These are a series of cross-sectional views 300-1300 of an intermediate semiconductor structure according to some embodiments, illustrating its use in manufacturing Figure 1 Some exemplary steps of the method for the semiconductor structure 100 in the process. Although Figures 3-13 It describes the method, but it should be understood that... Figures 3-13 The structures disclosed herein are not limited to this method, but can exist independently of this method.

[0055] like Figure 3 As shown in cross-sectional view 300, a silicon substrate 10 is provided, and a stretched film 12 is directly deposited on the front surface 10F of the silicon substrate 10 using a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, the silicon substrate 10 is formed of a silicon material. In some embodiments, the stretched film 12 is formed of a stretched material selected from silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (SiC). In some embodiments, the thickness T1 of the stretched film 12 is in the range of 0.01 μm to 10 μm.

[0056] like Figure 4As shown in cross-sectional view 400, a buried insulating layer 14 is directly deposited on top of the stretched film 12 using a deposition process, such as CVD or PVD. In some embodiments, the buried insulating layer 14 is a buried oxide (BOX) layer comprising silicon dioxide, such as silicon dioxide (SiO2). In some embodiments, the thickness T2 of the buried insulating layer 14 is in the range of 1 μm to 5 μm. In some embodiments, the ratio of the thickness T1 of the stretched film 12 to the thickness T2 of the buried insulating layer 14 is in the range of 0.005 to 5.

[0057] like Figure 5 As shown in cross-sectional view 500, a top silicon layer 16' is deposited directly on the buried insulating layer 14 using a deposition process, such as CVD or PVD. In some embodiments, the top silicon layer 16' comprises silicon material. In some embodiments, the silicon substrate 10, the stretched film 12, the buried insulating layer 14, and the top silicon layer 16' together form a silicon-on-insulator (SOI) structure 50.

[0058] like Figure 6 As shown in cross-sectional view 600, a portion of the top silicon layer 16' is removed by employing processes such as photolithography and etching (e.g., wet etching or dry etching) to form an opening 602 extending from the top surface of the top silicon layer 16' into the top silicon layer 16'. Thus, the remaining portion of the top silicon layer 16' forms the silicon core structure 16. In some embodiments, the silicon core structure 16 includes a first portion 16A that protrudes from a second portion 16B.

[0059] like Figure 7 As shown in cross-sectional view 700, a top insulating layer 18 is conformally deposited on the silicon core structure 16 using a deposition process, such as CVD or PVD. In some embodiments, the top insulating layer 18 comprises borosilicate glass (BPSG). In some embodiments, the buried insulating layer 14, the silicon core structure 16, and the top insulating layer 18 together form the silicon waveguide 70.

[0060] like Figure 8 As shown in cross-sectional view 800, a first interlayer dielectric (ILD) layer 20 is formed on the top insulating layer 18 using processes such as deposition (e.g., CVD or PVD) and chemical mechanical planarization (CMP). In some embodiments, the first ILD layer 20 comprises a dielectric material, such as silicon oxide (e.g., SiO2).

[0061] like Figure 9As shown in the cross-sectional view 900, a second ILD layer 22 is formed on the first ILD layer 20 by employing, for example, deposition (e.g., CVD and PVD) processes. In some embodiments, the second ILD layer 22 comprises a dielectric material, such as silicon oxide (e.g., SiO2), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), silicon carbide hydride (SiCOH), etc.

[0062] like Figure 10 As shown in the cross-sectional view 1000, a first conductive layer (e.g., M1) 24 is formed by employing processes such as photolithography, etching (e.g., wet etching or dry etching), deposition (e.g., CVD or PVD), and CMP, and is embedded within the second ILD layer 22. In some embodiments, the first conductive layer 24 comprises a metallic material, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), nickel (Ni), etc.

[0063] like Figure 11 As shown in the cross-sectional view 1100, a capping layer 25 is formed on the second ILD layer 22 by means of a deposition process, such as CVD or PVD. In some embodiments, the capping layer 25 comprises silicon carbide (SiC).

[0064] like Figure 12 As shown in cross-sectional view 1200, a third ILD layer 26 is formed on the capping layer 25 by employing, for example, deposition (e.g., CVD and PVD) processes. In some embodiments, the third ILD layer 26 comprises a dielectric material, such as SiO2, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), silicon carbide hydride (SiCOH), etc.

[0065] like Figure 13 As shown in cross-sectional view 1300, a second conductive layer (e.g., M2) 28 is formed by employing processes such as photolithography, etching (e.g., wet etching or dry etching), deposition (e.g., CVD or PVD), and CMP, and is embedded within a third ILD layer 26. In some embodiments, the second conductive layer 28 comprises a metallic material, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), nickel (Ni), etc.

[0066] Thus, a stretching film 12 is added below the buried insulator (e.g., BOX) layer 14 of the SOI structure 50 of the semiconductor structure 100 to compensate for the compressive stress caused by one or more metal layers (e.g., M1) on the silicon waveguide 70, so as to advantageously maintain its TE mode and thereby advantageously improve the optical performance of the silicon waveguide 70.

[0067] Figure 14 Manufacturing according to some embodiments Figure 1 A flowchart of method 1400 for a semiconductor structure is provided. It should be noted that method 1400 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that... Figure 14 The operation order of method 1400 can be changed, and can be... Figure 14 Method 1400 provides additional operations before, during, and after, and this document can briefly describe these additional operations.

[0068] refer to Figure 3 and Figure 14 Method 1400 begins with operation 1402, depositing a stretched film 12 on the front surface 10F of a silicon substrate 10. In some embodiments, the stretched film 12 is formed of a stretching material selected from silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (SiC). In some embodiments, the thickness T1 of the stretched film 12 is in the range of 0.01 μm to 10 μm.

[0069] refer to Figure 4 and Figure 14 Method 1400 proceeds to operation 1404, where a buried insulating layer 14 is deposited on the top surface of the stretched film 12. In some embodiments, the buried insulating layer 14 is a buried oxide (BOX) layer comprising silicon dioxide, such as silicon dioxide (SiO2). In some embodiments, the thickness T2 of the buried insulating layer 14 is in the range of 1 μm to 5 μm. In some embodiments, the ratio of the thickness T1 of the stretched film 12 to the thickness T2 of the buried insulating layer 14 is in the range of 0.005 to 5.

[0070] refer to Figure 5 and Figure 14 Method 1400 proceeds to operation 1406, where a top silicon layer 16' is deposited on the top surface of the buried insulating layer 14. In some embodiments, the silicon substrate 10, the stretched film 12, the buried insulating layer 14, and the top silicon layer 16' together form a silicon-on-insulator (SOI) structure 50.

[0071] refer to Figure 6 and Figure 14 Method 1400 proceeds to operation 1408, where the top silicon layer 16' is processed to form the silicon core structure 16. For example... Figure 6As shown, in some embodiments, a portion of the top silicon layer 16' is removed by employing, for example, photolithography and etching (e.g., wet etching or dry etching) processes to form an opening 602 extending from the top surface of the top silicon layer 16' into the top silicon layer 16', so that the remaining portion of the top silicon layer 16' forms a silicon core structure 16, which may include a first portion 16A that protrudes from a second portion 16B.

[0072] refer to Figure 7 and Figure 14 Method 1400 proceeds to operation 1410, where a top insulating layer 18 is conformally deposited on the silicon core structure 16 by employing, for example, deposition (e.g., CVD or PVD) processes.

[0073] refer to Figure 8 and Figure 14 Method 1400 proceeds to operation 1412, where a first interlayer dielectric (ILD) layer 20 is deposited on the top insulating layer 18 by employing, for example, a deposition process (e.g., CVD or PVD) followed by a CMP process. In some embodiments, the first ILD layer 20 comprises a dielectric material, such as silicon oxide (e.g., SiO2). In some embodiments, the buried insulating layer 14, the silicon core structure 16, the top insulating layer 18, and the first ILD layer 20 together form the silicon waveguide 70. In some embodiments, the buried insulating layer 14 serves as a bottom cover for the silicon waveguide 70, while the top insulating layer 18 and the first ILD layer 20 together serve as a top cover for the silicon waveguide 70.

[0074] refer to Figures 9-13 The method 1400 may further include the following operations: for example, depositing a second ILD layer 22 on the top surface of the first ILD layer 20 to form a first conductive layer (e.g., M1) 24 embedded in the second ILD layer 22, depositing a capping layer 25 on the top surface of the second ILD layer 22, depositing a third ILD layer 26 on the top surface of the capping layer 25, and forming a second conductive layer (e.g., M2) 28 embedded in the third ILD layer 26.

[0075] Thus, the stretch film 12 added below the BOX layer 14 of the SOI structure 50 of the semiconductor structure 100 can compensate for the compressive stress caused by at least one conductive layer (e.g., M1) on the silicon waveguide 70, thereby advantageously improving the optical performance of the silicon waveguide 70.

[0076] Figures 15-27 These are a series of cross-sectional views of an intermediate semiconductor structure according to other embodiments, illustrating its fabrication. Figure 2B Some exemplary steps of the method for constructing semiconductor structures. Although Figures 15-27 It describes the method, but it should be understood that... Figures 15-27The structures disclosed herein are not limited to this method, but can exist independently of this method.

[0077] like Figure 15 As shown in cross-sectional view 1500, a silicon substrate 10 is provided, and a first stretched film 12A is directly deposited on the front surface 10F of the silicon substrate 10 using a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, the silicon substrate 10 comprises a silicon material. In some embodiments, the first stretched film 12A comprises a stretched material selected from silicon, silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), or silicon carbide (SiC).

[0078] like Figure 16 As shown in the cross-sectional view 1600, the second stretch film 12B is directly deposited on the top surface of the first stretch film 12A by employing, for example, deposition (e.g., CVD or PVD) processes.

[0079] like Figure 17 As shown in cross-sectional view 1700, a third stretched film 12C is deposited directly on the top surface of the second stretched film 12B using a deposition process, such as CVD or PVD. In this way, stacks 12' of the stretched films (e.g., 12A, 12B, and 12C) are formed stacked on top of each other and deposited on the front surface 10F of the silicon substrate 10. Although Figure 17 The diagram shows a stack of three stretch films 12', but the number of stretch films in the stack 12' is not limited to three. In some embodiments, the number of stretch films in the stack 12' can be any integer in the range of 2 to 15 without departing from the spirit of this disclosure. In some embodiments, the thickness T1' of the stack 12' of the stretch films is in the range of 0.01 μm to 10 μm.

[0080] like Figure 18 As shown in cross-sectional view 1800, a buried insulating layer 14 is directly deposited on top of the stack 12' of stretched films (e.g., 12A, 12B, and 12C) using a deposition process, such as CVD or PVD. In some embodiments, the buried insulating layer 14 is a buried oxide (BOX) layer comprising silicon dioxide, such as silicon dioxide (SiO2). In some embodiments, the thickness T2 of the buried insulating layer 14 is in the range of 1 μm to 5 μm. In some embodiments, the ratio of the thickness T1' of the stack 12' of the stretched films to the thickness T2 of the buried insulating layer 14 is in the range of 0.005 to 5.

[0081] like Figure 19As shown in cross-sectional view 1900, a top silicon layer 16' is directly deposited on the buried insulating layer 14 using, for example, deposition (e.g., CVD or PVD) processes. In some embodiments, the top silicon layer 16' comprises silicon material. In some embodiments, the silicon substrate 10, the stack of stretched films 12', the buried insulating layer 14, and the top silicon layer 16' together produce a silicon-on-insulator (SOI) structure 50B of the semiconductor structure 100. Figure 2B middle).

[0082] like Figure 20 As shown in the cross-sectional view 2000, a portion of the top silicon layer 16' is removed by employing processes such as photolithography and etching (e.g., wet etching or dry etching) to form an opening 2202 extending from the top surface of the top silicon layer 16' into the top silicon layer 16'. In this way, the remaining portion of the top silicon layer 16' can form a silicon core structure 16, which may include, for example, a first portion 16A that protrudes from a second portion 16B.

[0083] like Figure 21 As shown in cross-sectional view 2100, a top insulating layer 18 is conformally deposited on the silicon core structure 16 using a deposition process, such as CVD or PVD. In some embodiments, the top insulating layer 18 comprises borosilicate glass (BPSG).

[0084] like Figure 22 As shown in cross-sectional view 2200, a first ILD layer 20 is deposited on the top insulating layer 18 using, for example, deposition (e.g., CVD or PVD) followed by a CMP process. In some embodiments, the first ILD layer 20 comprises a dielectric material such as silicon oxide (e.g., SiO2). In some embodiments, the buried insulating layer 14, the silicon core structure 16, the top insulating layer 18, and the first ILD layer 20 together form the silicon waveguide 70. The buried insulating layer 14 can be used as a bottom cover for the silicon waveguide 70, while the top insulating layer 18 and the first ILD layer 20 can be used as a top cover for the silicon waveguide 70.

[0085] like Figure 23 As shown in cross-sectional view 2300, a second ILD layer 22 is formed on the first ILD layer 20 by employing, for example, deposition (e.g., CVD and PVD) processes. In some embodiments, the second ILD layer 22 comprises an insulating material, such as SiO2, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), silicon carbide hydride (SiCOH), etc.

[0086] like Figure 24As shown in cross-sectional view 2400, a first conductive layer (e.g., M1) 24 is formed by employing processes such as photolithography, etching (e.g., wet etching or dry etching), deposition (e.g., CVD or PVD), and CMP, and is embedded within a second ILD layer 22. In some embodiments, the first conductive layer 24 comprises a metallic material, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), nickel (Ni), etc.

[0087] like Figure 25 As shown in cross-sectional view 2500, a capping layer 25 is formed on the second ILD layer 22 using a deposition process, such as CVD or PVD. In some embodiments, the capping layer 25 comprises, for example, silicon carbide (SiC).

[0088] like Figure 26 As shown in cross-sectional view 2600, a third ILD layer 26 is formed on the capping layer 25 by employing, for example, deposition (e.g., CVD and PVD) processes. In some embodiments, the third ILD layer 26 comprises an insulating material, such as SiO2, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass (USG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), silicon carbide hydride (SiCOH), etc.

[0089] like Figure 27 As shown in cross-sectional view 2700, a second conductive layer (e.g., M2) 28 is formed by employing processes such as photolithography, etching (e.g., wet etching or dry etching), deposition (e.g., CVD or PVD), and CMP, and is embedded within a third ILD layer 26. In some embodiments, the second conductive layer 28 comprises a metallic material, such as copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), nickel (Ni), etc.

[0090] Thus, in semiconductor structure 100 (in Figure 2B A stack of stretched films (e.g., 12A, 12B, and 12C) is added below the buried insulating layer 14 of the SOI structure 50B in the middle to compensate for the compressive stress caused by at least one metal layer (e.g., M1) on the silicon waveguide 70, so as to advantageously maintain its TE mode and thereby improve the optical performance of the silicon waveguide 70.

[0091] Figure 28 Manufacturing according to other embodiments Figure 2B The flowchart illustrates a method for constructing a semiconductor structure. It should be noted that method 2800 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that... Figure 28The operation order of method 2800 can be changed, and can be... Figure 28 Method 2800 provides additional operations before, during, and after, and this document can briefly describe these additional operations.

[0092] refer to Figures 15-17 and Figure 28 Method 2800 begins with operation 2802, depositing a stack 12' of stretched films (e.g., 12A, 12B, and 12C) on the front surface 10F of silicon substrate 10.

[0093] like Figure 15 As shown in the cross-sectional view 1500, a silicon substrate 10 is provided, and a first stretched film 12A is directly deposited on the front surface 10F of the silicon substrate 10 using, for example, deposition (e.g., CVD or PVD) processes. Figure 16 As shown in cross-sectional view 1600, the second stretched film 12B is deposited directly on the top surface of the first stretched film 12A. Figure 17 As shown in cross-sectional view 1700, a third stretch film 12C is deposited directly on the top surface of the second stretch film 12B. In some embodiments, such as Figure 17 As shown, the thickness T1' of the stacked part 12' of the stretched film is in the range of 0.01 μm to 10 μm.

[0094] refer to Figure 18 and Figure 28 Method 2800 proceeds to operation 2804, where a buried insulating layer 14 is directly deposited on top of the stack 12' of the stretched film using, for example, deposition (e.g., CVD or PVD) processes. In some embodiments, the buried insulating layer 14 is a buried oxide (BOX) layer comprising silicon dioxide such as silicon dioxide (SiO2). In some embodiments, the thickness T2 of the buried insulating layer 14 is in the range of 1 μm to 5 μm. In some embodiments, the ratio of the thickness T1' of the stack 12' of the stretched film to the thickness T2 of the buried insulating layer 14 is in the range of 0.005 to 5.

[0095] refer to Figure 19 and Figure 28 Method 2800 proceeds to operation 2806, where a top silicon layer 16' is deposited on the buried insulating layer 14 using, for example, a deposition process (e.g., CVD or PVD). In some embodiments, the top silicon layer 16' comprises silicon material. In some embodiments, the silicon substrate 10, the stack of stretched films 12', the buried insulating layer 14, and the top silicon layer 16' together form a silicon-on-insulator (SOI) structure 50B.

[0096] refer to Figure 20 and Figure 28Method 2800 proceeds to operation 2808, where the top silicon layer 16' is processed to form the silicon core structure 16. For example... Figure 20 As shown in the cross-sectional view 2000, a portion of the top silicon layer 16' is removed by employing processes such as photolithography and etching (e.g., wet etching or dry etching) to form an opening 2202 extending from the top surface of the top silicon layer 16' into the top silicon layer 16'. Thus, the remaining portion of the top silicon layer 16' forms a silicon core structure 16, which may include a first portion 16A protruding from a second portion 16B.

[0097] refer to Figure 21 and Figure 28 Method 2800 proceeds to operation 2810, where a top insulating layer 18 is conformally deposited on the silicon core structure 16 using, for example, a deposition process (e.g., CVD or PVD). In some embodiments, the top insulating layer 18 comprises borosilicate glass (BPSG).

[0098] refer to Figure 22 and Figure 28 Method 2800 proceeds to operation 2810, where a first ILD layer 20 is deposited on the top insulating layer 18 by employing, for example, a deposition process (e.g., CVD or PVD) followed by a CMP process. In some embodiments, the first ILD layer 20 comprises a dielectric material such as silicon oxide (e.g., SiO2). In some embodiments, the buried insulating layer 14, the silicon core structure 16, the top insulating layer 18, and the first ILD layer 20 together constitute the silicon waveguide 70. The buried insulating layer 14 can serve as a bottom cover for the silicon waveguide 70, while the top insulating layer 18 and the first ILD layer 20 can serve as a top cover for the silicon waveguide 70. In this way, the silicon waveguide 70 uses total internal reflection to confine light or radiation within the silicon core structure 16.

[0099] refer to Figures 23-27 The method 2800 may further include the following operations: depositing a second ILD layer 22 on the top surface of the first ILD layer 20 to form a first conductive layer (e.g., M1) 24 embedded in the second ILD layer 22, depositing a capping layer 25 on the top surface of the second ILD layer 22, depositing a third ILD layer 26 on the top surface of the capping layer 25, and forming a second conductive layer (e.g., M2) 28 embedded in the third ILD layer 26.

[0100] In this way, in semiconductor structure 200B (in Figure 2BA stack of stretched films (e.g., 12A, 12B, and 12C) is added below the buried insulating layer 14 of the SOI structure 50B in the middle to compensate for the compressive stress caused by one or more metal layers (e.g., M1) on the silicon waveguide 70, thereby advantageously improving the optical performance of the silicon waveguide 70.

[0101] Therefore, in some embodiments, a semiconductor structure is provided. The semiconductor structure includes a silicon-on-insulator (SOI) structure and optical devices disposed on the SOI structure. The SOI structure includes a silicon substrate, a stretched film on the silicon substrate, a buried insulating layer on the stretched film, and a top silicon layer on the buried insulating layer. The tensile stress of the stretched film is greater than the tensile stress of the silicon substrate. In some embodiments, a semiconductor structure is provided, including: a silicon-on-insulator (SOI) structure and optical devices disposed on the SOI structure, wherein the SOI structure includes a silicon substrate, a stretched film on the silicon substrate, a buried insulating layer on the stretched film, and a top silicon layer on the buried insulating layer, wherein the tensile stress of the stretched film is different from the tensile stress of the silicon substrate. In some embodiments, the stretched film includes a stretched material selected from silicon, silicon oxide, silicon nitride, or silicon carbide. In some embodiments, the thickness of the stretched film is in the range of 0.01 μm to 10 μm. In some embodiments, the thickness of the buried insulating layer is in the range of 1 μm to 5 μm. In some embodiments, the ratio of the thickness of the stretched film to the thickness of the buried insulating layer is in the range of 0.005 to 5. In some embodiments, the tensile stress of the stretched film is in the range of 0.1 GPa to 2 GPa, and the durability temperature of the stretched film is greater than 1100°C. In some embodiments, the stretched film extends completely between the silicon substrate and the buried insulating layer to completely cover the silicon substrate. In some embodiments, the semiconductor structure further includes: a top insulating layer on the silicon core structure; and a first interlayer dielectric (ILD) layer on the top insulating layer, wherein the top insulating layer comprises borosilicate glass (BPSG), and the first ILD layer comprises silicon oxide. In some embodiments, the semiconductor structure further includes: a top insulating layer on the top silicon layer; and a first interlayer dielectric (ILD) layer on the top insulating layer, wherein the top insulating layer comprises borosilicate glass (BPSG), and wherein the first interlayer dielectric layer comprises silicon oxide. In some embodiments, the top silicon layer includes a silicon core structure, and the optical device includes a silicon waveguide comprising a buried insulating layer, a silicon core structure, a top insulating layer, and a first ILD layer. In some embodiments, the semiconductor structure further includes: a second ILD layer disposed on the first ILD layer; a first conductive layer embedded within the second ILD layer; a third ILD layer disposed above the second ILD layer; and a second conductive layer embedded within the third ILD layer. In some embodiments, the semiconductor structure further includes: a capping layer vertically located between the second ILD layer and the third ILD layer to separate them, wherein the capping layer comprises silicon carbide.

[0102] In other embodiments, a semiconductor structure is provided. The semiconductor structure includes: a silicon substrate; a stack of stretched films disposed on the silicon substrate; a buried insulating layer disposed on the top surface of the stack of stretched films; and a top silicon layer including a silicon core structure disposed on the buried insulating layer, wherein the silicon substrate, the stack of stretched films, the buried insulating layer, and the silicon core structure together form a silicon-on-insulator (SOI) structure. In some embodiments, the stack of stretched films includes at least a first stretched film of a first stretched material and a first ILD layer of a second stretched material different from the first stretched material. In some embodiments, the stack of stretched films includes at least a first stretched film of a first stretched material and a second stretched film of a second stretched material different from the first stretched material. In some embodiments, the first stretched material is selected from silicon, silicon oxide, silicon nitride, or silicon carbide, and the second stretched material is selected from silicon, silicon oxide (e.g., SiO2), silicon nitride, or silicon carbide. In some embodiments, the semiconductor structure further includes: a top insulating layer disposed on the silicon core structure; and a first interlayer dielectric (ILD) layer disposed on the top insulating layer, wherein the buried insulating layer, the silicon core structure, the top insulating layer, and the first ILD layer together form a silicon waveguide.

[0103] In other embodiments, a method of fabricating a semiconductor structure is provided. The method includes: depositing a stretched film on a silicon substrate; depositing a buried insulating layer on a top surface of the stretched film; and depositing a top silicon layer on the buried insulating layer; forming a silicon core structure by processing the top silicon layer, wherein the silicon core structure includes a first portion protruding from a second portion. In some embodiments, the method further includes: depositing a top insulating layer on the silicon core structure; and depositing a first interlayer dielectric (ILD) layer on the top insulating layer. In some embodiments, the silicon substrate, the stretched film, the buried insulating layer, and the top silicon layer together form a silicon-on-insulator (SOI) structure, and the buried insulating layer, the silicon core structure, the top insulating layer, and the first ILD layer together form a silicon waveguide. In some embodiments, the stretched film is formed of a stretched material selected from silicon, silicon oxide, silicon nitride, or silicon carbide, and wherein the buried insulating layer includes a buried oxide (BOX) formed of silicon oxide. In some embodiments, the thickness of the stretched film is in the range of about 0.01 μm to about 10 μm, and the ratio of the thickness of the stretched film to the thickness of the buried insulating layer is in the range of about 0.005 to about 5. In some embodiments, the method further includes: depositing a second ILD layer on a first ILD layer; forming a first conductive layer within the second ILD layer; depositing a capping layer on the second ILD layer; depositing a third ILD layer on the capping layer; and forming a second conductive layer within the third ILD layer.

[0104] It should be understood that while exemplary structures are referenced throughout in discussing aspects of the methods described herein, these methods are not limited to the respective structures presented. Rather, these methods (and structures) should be considered independent of each other, capable of existing independently, and practiced without regard to any particular aspect depicted in the figures. Furthermore, the layers described herein can be formed in any suitable manner, such as spin coating, sputtering, growth, and / or deposition techniques.

[0105] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: A silicon-on-insulator (SOI) structure includes a silicon substrate, a stretched film on the silicon substrate, a buried insulator layer on the stretched film, and a top silicon layer on the buried insulator layer, wherein the tensile stress of the stretched film is different from the tensile stress of the silicon substrate; and Optical devices are disposed on the silicon-on-insulator structure.

2. The semiconductor structure according to claim 1, wherein, The stretching membrane comprises a stretching material selected from silicon, silicon oxide, silicon nitride, or silicon carbide.

3. The semiconductor structure according to claim 1, wherein, The thickness of the stretched film is in the range of 0.01 μm to 10 μm.

4. The semiconductor structure according to claim 1, wherein, The thickness of the buried insulating layer is in the range of 1 μm to 5 μm.

5. The semiconductor structure according to claim 1, wherein, The ratio of the thickness of the stretching membrane to the thickness of the buried insulating layer is in the range of 0.005 to 5.

6. The semiconductor structure according to claim 1, wherein, The tensile stress of the stretch membrane is in the range of 0.1 GPa to 2 GPa, and the durability temperature of the stretch membrane is greater than 1100°C.

7. The semiconductor structure according to claim 1, wherein, The stretch film is configured to extend completely between the silicon substrate and the buried insulating layer to completely cover the silicon substrate.

8. The semiconductor structure according to claim 1, further comprising: A top insulating layer is located on the top silicon layer; and The first interlayer dielectric (ILD) layer is located on the top insulating layer. The top insulating layer comprises borosilicate glass (BPSG), and the first interlayer dielectric layer comprises silicon oxide.

9. A semiconductor structure, comprising: silicon substrate; A stack of stretched films is disposed on the silicon substrate; An insulating layer is buried on the top surface of the stack of the stretch film; as well as The top silicon layer includes a silicon core structure disposed on the buried insulator layer, wherein the silicon substrate, the stack of the stretched films, the buried insulator layer, and the silicon core structure together form a silicon-on-insulator (SOI) structure.

10. A method for manufacturing a semiconductor structure, comprising: Depositing a stretched film on a silicon substrate; A buried insulating layer is deposited on the top surface of the stretched membrane; A top silicon layer is deposited on the buried insulating layer; as well as A silicon core structure is formed by processing the top silicon layer, wherein the silicon core structure includes a first portion protruding from the second portion.

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