Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the manufacturing method of the semiconductor device comprising: providing a substrate, the substrate having a metal layer, an etching stop layer and an insulating layer thereon; forming a via hole penetrating through the etching stop layer and the insulating layer, the via hole exposing the metal layer; filling an etching blocking layer in the via hole, and the etching blocking layer exposing a sidewall of an end of the via hole away from the substrate; and using a micro-sculpture technique to perform directional etching on the sidewall of the via hole not covered by the etching blocking layer, and expand the end of the via hole away from the substrate in a direction parallel to the substrate. The manufacturing method of the embodiment of the application uses the micro-sculpture technique to expand the upper part of the via hole, which not only saves a mask, but also realizes self-alignment of the lower part and the upper part of the via hole, and enhances the reliability of the product.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. The manufacturing method of the semiconductor device uses micro-engraving technology to expand the upper part of the via, which not only saves a photomask, but also enables the self-alignment of the lower and upper parts of the via, thereby enhancing the reliability of the product.

[0006] This application provides a method for manufacturing a semiconductor device, the method comprising:

[0007] A substrate is provided, wherein the substrate has a metal layer, an etch stop layer and an insulating layer;

[0008] A via is formed that penetrates the etch stop layer and the insulating layer, and the via exposes the metal layer;

[0009] An etch barrier layer is filled into the via, and the etch barrier layer is exposed on the sidewall of the via away from the substrate.

[0010] Micro-engraving technology is used to directionally etch the sidewalls of the via that are not covered by the etching barrier layer, thereby expanding the end of the via away from the substrate in a direction parallel to the substrate.

[0011] In some embodiments of this application, the step of using micro-engraving technology to directionally etch the sidewalls of the via not covered by the etching barrier layer includes:

[0012] A plasma beam with a specific direction is used to perform directional etching on the sidewalls of the via that are not covered by the etching barrier layer.

[0013] In some embodiments of this application, the step of using micro-engraving technology to directionally etch the sidewalls of the via not covered by the etching barrier layer includes:

[0014] Multiple directional etching operations were performed using plasma beams with different incident directions.

[0015] In some embodiments of this application, the via forming through the etch stop layer and the insulating layer includes:

[0016] A photolithography process is used to etch the etch stop layer and the insulating layer along the direction toward the substrate to form a via through the etch stop layer and the insulating layer.

[0017] In some embodiments of this application, the method for manufacturing the semiconductor device further includes: after obtaining the expanded via,

[0018] Remove the etching barrier layer; form pads in the expanded vias;

[0019] Two semiconductor structures to be bonded and having the pads are bonded together using the pads.

[0020] In some embodiments of this application, the depth of the expanded portion of the via is H1, and the depth of the unexpanded portion of the via is H2, where 0.6 ≤ H1 / H2 ≤ 0.8.

[0021] In some embodiments of this application, the maximum width of the expanded portion of the via is W1, and the maximum width of the unexpanded portion of the via is W2, where 1.5 ≤ W1 / W2 ≤ 2.2.

[0022] In some embodiments of this application, the incident direction of the plasma beam has an angle θ with the horizontal direction, where 30°≤θ<90°.

[0023] In some embodiments of this application, the plasma beam contains fluorine.

[0024] This application also provides a semiconductor device, the semiconductor device comprising: a first semiconductor structure and a second semiconductor structure stacked and bonded together; the first semiconductor structure having a first via and a first pad disposed therein, the second semiconductor structure having a second via and a second pad disposed therein; the first semiconductor structure and the second semiconductor structure being bonded together via the first pad and the second pad;

[0025] The first pad and the second pad may have the same or different dimensions;

[0026] Both the first via and the second via have interconnected etched holes and expanded holes. The expanded holes are obtained by etching part of the sidewalls of the etched holes using micro-engraving technology.

[0027] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the method described above.

[0028] The semiconductor device manufacturing method of this application embodiment first forms vias, and then uses micro-engraving technology to perform directional etching on the upper part of the vias based on the existing vias, thereby increasing the size of the upper part of the vias. Since micro-engraving technology does not require the use of a photomask, it can save one photomask; moreover, the directional etching is performed on the existing vias, so the self-alignment between the initially formed vias and the holes formed by micro-engraving technology can be achieved, avoiding the problem of overlay deviation and enhancing the reliability of the product.

[0029] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0030] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0031] Figure 1 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application;

[0032] Figure 2 This is a schematic diagram illustrating the directional etching process using micro-engraving technology in the manufacturing method of the semiconductor device according to an embodiment of this application.

[0033] Figure 3 A schematic longitudinal section of a first semiconductor structure in a method for manufacturing a semiconductor device according to an exemplary embodiment of this application, shown in the diagram.

[0034] Figure 4 This is a schematic longitudinal section view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, taken on a cross section perpendicular to the substrate after the formation of vias.

[0035] Figure 5 This is a schematic longitudinal section view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of an etch barrier layer, on a section perpendicular to the substrate.

[0036] Figure 6A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming an expansion hole, is shown in a cross section perpendicular to the substrate.

[0037] Figure 7 for Figure 6 A magnified view of a portion of the image;

[0038] Figure 8 This is a schematic longitudinal section view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of the pads, on a section perpendicular to the substrate.

[0039] Figure 9 A schematic longitudinal section of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after bonding is completed;

[0040] Figure 10 This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application, in which the process parameters of micro-engraving are adjusted based on alignment error. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0042] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0043] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0044] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0045] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0046] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0047] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0048] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0049] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0050] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0051] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0052] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0053] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0054] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0055] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0056] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0057] In this application, "film" and "layer" can be interchanged. For example, "insulating layer" can sometimes be replaced with "insulating film".

[0058] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functional circuits are already distributed. The devices involved in the inventive construction of the embodiments of this application are disposed on the main surface of the support structure.

[0059] In this application, the spacing distribution can be understood as a separate, independent distribution. This spacing can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors can be modified to achieve insulation, thus creating an electrical gap between the two channels.

[0060] In hybrid bonding processes, to achieve functional electrical interconnection between two functional wafers, it is often necessary to fabricate bonding structures on the top metal layers of the two wafers, which already possess their respective functions. These bonding structures mainly include vias (VIAs) and pads (Pads). Whether using a single-damascene or double-damascene process, at least two masks are required to fabricate these via and pad structures. Taking the VIAfirst double-damascene process as an example, firstly, a via mask is used to form the photolithographic pattern of the via, followed by etching to create the via. Then, a bottom anti-reflective coating (BARC) is formed at the bottom of the via. Finally, the pads are patterned and etched to create the pads. To bond two wafers together, four masks are needed, one for forming the vias and one for the pads of the two stacked wafers. Furthermore, the overlay alignment (OVL) of the pads and vias also needs to be carefully controlled, especially with small linewidths (pitch). When performing the stacking process of two wafers, the bonding pads of the two wafers must also be aligned. As the linewidth decreases, the requirements for alignment accuracy become increasingly higher.

[0061] This application provides a method for manufacturing a semiconductor device. Figure 1 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application.

[0062] like Figure 1 As shown, the method for manufacturing the semiconductor device includes:

[0063] A substrate is provided, wherein the substrate has a metal layer, an etch stop layer and an insulating layer;

[0064] A via is formed that penetrates the etch stop layer and the insulating layer, and the via exposes the metal layer;

[0065] An etch barrier layer is filled into the via, and the etch barrier layer is exposed on the sidewall of the via away from the substrate.

[0066] Micro-engraving technology is used to directionally etch the sidewalls of the via that are not covered by the etching barrier layer, thereby expanding the end of the via away from the substrate in a direction parallel to the substrate.

[0067] The semiconductor device manufacturing method of this application embodiment first forms vias, and then uses micro-engraving technology to perform directional etching on the upper part of the vias based on the existing vias, thereby increasing the size of the upper part of the vias. Since micro-engraving technology does not require the use of a photomask, it can save one photomask; moreover, the directional etching is performed on the existing vias, so the self-alignment between the initially formed vias and the holes formed by micro-engraving technology can be achieved, avoiding the problem of overlay deviation and enhancing the reliability of the product.

[0068] In some embodiments of this application, the step of using micro-engraving technology to directionally etch the sidewalls of the via not covered by the etching barrier layer includes:

[0069] A plasma beam with a specific direction is used to perform directional etching on the sidewalls of the via that are not covered by the etching barrier layer.

[0070] Figure 2 This is a schematic diagram illustrating the directional etching technique used in the manufacturing method of the semiconductor device according to an embodiment of this application. Figure 2 As shown, in the micro-engraving technology used in this application, the incident direction of the plasma in a single directional etching process is the same, i.e., directional etching.

[0071] In some embodiments of this application, the step of using micro-engraving technology to directionally etch the sidewalls of the via not covered by the etching barrier layer includes:

[0072] Multiple directional etching operations were performed using plasma beams with different incident directions.

[0073] For example, if you want to expand the upper part of the via along the horizontal X and Y directions to obtain a square hole, you can perform four directional etchings in different directions along the X, -X, Y and -Y directions.

[0074] In some embodiments of this application, the via forming through the etch stop layer and the insulating layer includes:

[0075] A photolithography process is used to etch the etch stop layer and the insulating layer along the direction toward the substrate to form a via through the etch stop layer and the insulating layer.

[0076] In some embodiments of this application, the method for manufacturing the semiconductor device further includes: after obtaining the expanded via,

[0077] Remove the etching barrier layer;

[0078] Pads are formed in the expanded vias;

[0079] Two semiconductor structures to be bonded and having the pads are bonded together using the pads.

[0080] The semiconductor device manufacturing method of this application embodiment can be used for bonding semiconductor structures such as wafers. For example, the semiconductor device manufacturing method may include:

[0081] A semiconductor structure located on a substrate is provided, the semiconductor structure including a metal layer, an etch stop layer and an insulating layer;

[0082] The etch stop layer and the insulating layer are etched along the direction toward the substrate to form a via through the etch stop layer and the insulating layer, the via exposing the metal layer;

[0083] An etch barrier layer is filled into the via, and the etch barrier layer is exposed on the sidewall of the via away from the substrate.

[0084] Using micro-engraving technology, the sidewalls of the via that are not covered by the etching barrier layer are oriented to be etched, thereby expanding the via in a direction parallel to the substrate;

[0085] Remove the etching barrier layer;

[0086] Pads are formed in the expanded vias;

[0087] Two semiconductor structures to be bonded are bonded together using the pads.

[0088] The semiconductor device manufacturing method of this application is used for wafer bonding. Since micro-engraving technology is used instead of photolithography to enlarge the vias, no photomask is needed, thus saving one photomask. Moreover, the initially formed vias and the holes formed by micro-engraving technology can be self-aligned, avoiding overlay deviation problems and enhancing product reliability.

[0089] In addition, the semiconductor device manufacturing method of this application embodiment can also optimize the alignment effect of the bonding process by adjusting the parameters of micro-engraving technology, such as etching time and etching angle, based on the alignment error during bonding.

[0090] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0091] like Figures 3 to 9 As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0092] S10: Provides a first semiconductor structure 20 and a second semiconductor structure located on a substrate 10.

[0093] For example, such as Figure 3 As shown, along the direction away from the substrate 10, the first semiconductor structure 20 may sequentially include a stacked insulating layer 11, a metal layer 12, an etch stop layer 13, and an insulating layer 11, as shown. Figure 3 As shown.

[0094] The structure of the second semiconductor structure (not shown in the figure) can be the same as that of the first semiconductor structure 20.

[0095] S20: Using photolithography, the first semiconductor structure 20 and the second semiconductor structure are etched along the direction toward the substrate 10 to form a via K1. The via K1 has a first end away from the substrate 10 and a second end close to the substrate 10. The first end is exposed by the first semiconductor structure 20 and the second semiconductor structure, and the second end extends to the surface of the metal layer 12 away from the substrate 10, i.e., the via K1 exposes the metal layer 12. Figure 4 As shown.

[0096] S30: Fill the second end of via K1 with an etching barrier layer 14, and expose the sidewall of the first end of via K1, such as... Figure 5 As shown.

[0097] The function of the etching barrier layer 14 is to fill the second end of the via K1, preventing the entire via K1 from expanding during subsequent micro-engraving processes. The etching barrier layer 14 can be made of bottom anti-reflective coating (BARC) material.

[0098] S40: Using micro-engraving technology, a plasma beam with a specific direction is used to directionally etch the film layer (insulating layer 11 in this embodiment) surrounding the first end of the via K1. Through multiple directional etchings in different directions, the first end of the via K1 expands in a direction parallel to the substrate 10. The expanded first end is named the expanded hole K2, and the unexpanded second end of the via K1 is named the etched hole K3. Figure 6 As shown.

[0099] For example, such as Figure 7 As shown, the depth of the expansion hole K2 in the direction perpendicular to the substrate 10 is H1, and the depth of the etching hole K3 is H2.

[0100] H1 / H2 satisfies: 0.6≤H1 / H2≤0.8.

[0101] For example, such as Figure 7 As shown, the maximum width of the expansion hole K2 is W1, and the maximum width of the etching hole K3 is W2;

[0102] W1 / W2 satisfies: 1.5≤W1 / W2≤2.2.

[0103] When 0.6≤H1 / H2≤0.8 and 1.5≤W1 / W2≤2.2, the expanded hole K2 can be obtained using simple process conditions, which is beneficial to improving the reliability of subsequent bonding.

[0104] Figure 6 The incident direction of the plasma beam during a single directional etching is shown only.

[0105] For example, the incident direction of the plasma beam has an angle θ with the horizontal direction, and the angle θ can satisfy 30°≤θ<90°.

[0106] For example, the insulating layer of silicon oxide material can be micro-engraved using a fluorine-containing plasma.

[0107] S50: Remove the etch barrier layer 14; form pads 30 in the expansion hole K2 and the etched hole K3, such as Figure 8 As shown.

[0108] For example, the material of pad 30 can be copper.

[0109] S60: Invert the second semiconductor structure 40 so that its substrate 10 is on top and the pads 30 are facing down. Bond the second semiconductor structure 40 and the first semiconductor structure 20 together face-to-face through the pads 30. Figure 9 As shown.

[0110] The semiconductor device manufacturing method of this application embodiment can optimize the alignment effect of the bonding process by adjusting the parameters of the micro-engraving technology based on the alignment error during bonding. For example, as Figure 10 As shown, if there is a systematic deviation in bonding alignment in the X direction and the process window is small, the etching time in the X direction can be increased and the etching time in the -X direction can be decreased, thereby reducing the alignment error.

[0111] Because the parameters of the micro-engraving technology can be adjusted, the sizes of the upper and lower pads can be different.

[0112] This application also provides a semiconductor device, such as... Figure 9As shown, the semiconductor device includes: a first semiconductor structure 20 and a second semiconductor structure 40 stacked and bonded together; the first semiconductor structure 20 has a first via and a first pad 31 disposed therein; the second semiconductor structure 40 has a second via and a second pad 32 disposed therein; the first semiconductor structure 20 and the second semiconductor structure 40 are bonded together through the first pad 31 and the second pad 32.

[0113] The first pad 31 and the second pad 32 may have the same or different dimensions;

[0114] Both the first via and the second via have interconnected expansion holes K2 and etching holes K3. The expansion holes K2 are obtained by etching part of the sidewalls of the etching holes K3 using micro-engraving technology.

[0115] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the method described above.

[0116] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0117] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, wherein the substrate has a metal layer, an etch stop layer and an insulating layer; A via is formed that penetrates the etch stop layer and the insulating layer, and the via exposes the metal layer; An etch barrier layer is filled into the via, and the etch barrier layer is exposed on the sidewall of the via away from the substrate. Micro-engraving technology is used to directionally etch the sidewalls of the via that are not covered by the etching barrier layer, thereby expanding the end of the via away from the substrate in a direction parallel to the substrate.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The step of using micro-engraving technology to perform directional etching on the sidewalls of the vias not covered by the etching barrier layer includes: A plasma beam with a specific direction is used to perform directional etching on the sidewalls of the via that are not covered by the etching barrier layer.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The step of using micro-engraving technology to perform directional etching on the sidewalls of the vias not covered by the etching barrier layer includes: Multiple directional etching operations were performed using plasma beams with different incident directions.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The via formed through the etch stop layer and the insulating layer includes: A photolithography process is used to etch the etch stop layer and the insulating layer along the direction toward the substrate to form a via through the etch stop layer and the insulating layer.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Also includes: After obtaining the expanded via Remove the etching barrier layer; Pads are formed in the expanded vias; Two semiconductor structures to be bonded and having said pads are bonded together by said pads.

6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that, The depth of the expanded portion of the via is H1, and the depth of the unexpanded portion of the via is H2, where 0.6 ≤ H1 / H2 ≤ 0.

8.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that, The maximum width of the expanded portion of the via is W1, and the maximum width of the unexpanded portion of the via is W2, where 1.5 ≤ W1 / W2 ≤ 2.

2.

8. The method for manufacturing a semiconductor device according to claim 2 or 3, characterized in that, The incident direction of the plasma beam has an angle θ with the horizontal direction, where 30°≤θ<90°.

9. The method for manufacturing a semiconductor device according to claim 2 or 3, characterized in that, The plasma beam contains fluorine.

10. A semiconductor device, characterized in that, include: A first semiconductor structure and a second semiconductor structure stacked and bonded together; The first semiconductor structure has a first via and a first pad is disposed therein; the second semiconductor structure has a second via and a second pad is disposed therein; the first semiconductor structure and the second semiconductor structure are bonded together through the first pad and the second pad. The first pad and the second pad may have the same or different dimensions; Both the first via and the second via have interconnected etched holes and expanded holes. The expanded holes are obtained by etching part of the sidewalls of the etched holes using micro-engraving technology.

11. An electronic device, characterized in that, It includes semiconductor devices obtained by the method of any one of claims 1 to 9, or semiconductor devices according to claim 10.

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