Semiconductor device package and method of manufacturing the same

Abstract

Embodiments of the present application relate to semiconductor device packages and methods of manufacturing the same. A semiconductor device package includes a substrate, a first coil, a dielectric layer, and a second coil. The first coil is disposed on the substrate. The first coil includes a first conductive segment and a second conductive segment. The dielectric layer covers the first conductive segment of the first coil and the second conductive segment of the first coil and defines a first recess between the first conductive segment of the first coil and the second conductive segment of the first coil. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment disposed within the first recess.

Description

[0001] Information related to divisional application This application is a divisional application of the invention patent application filed on July 20, 2018, with application number "201810801578.5" and invention title "Semiconductor Device Packaging and Manufacturing Method Thereof". Technical Field

[0002] This disclosure relates to a semiconductor device package and a method for manufacturing the same, and more specifically, to a patterned semiconductor device package and a method for manufacturing the same. Background Technology

[0003] With the development of System-in-Package (SIP), passive electronic components (such as capacitors, inductors, or transformers) can be integrated within the package (i.e., Integrated Passive Device, IPD). To increase the inductance of an inductor integrated into the package, the number of turns of the inductor should be increased. However, this will also increase the size of the package. Another method is to stack two coils. However, this will increase the thickness of the package. Summary of the Invention

[0004] According to some embodiments of this disclosure, a semiconductor device package includes a substrate, a first coil, a dielectric layer, and a second coil. The first coil is disposed on the substrate. The first coil includes a first conductive segment and a second conductive segment. The dielectric layer covers the first conductive segment and the second conductive segment of the first coil and defines a first recess between the first conductive segment and the second conductive segment of the first coil. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment disposed within the first recess.

[0005] According to some embodiments of this disclosure, a semiconductor device package includes a substrate, a first coil, a dielectric layer, and a second coil. The substrate has a top surface. The first coil is disposed on the top surface of the substrate. The first coil has a first conductive segment. The dielectric layer covers the first conductive segment and a second conductive segment. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment. The first conductive segment of the first coil and the first conductive segment of the second coil overlap in a direction substantially parallel to the top surface of the substrate.

[0006] According to some embodiments of this disclosure, a semiconductor device package includes a substrate, a first coil, a dielectric layer, and a second coil. The substrate has a top surface. The first coil is disposed on the top surface of the substrate. The first coil has a plurality of conductive segments. The dielectric layer covers the first coil and defines a recess between two adjacent conductive segments of the first coil. The second coil is disposed on the dielectric layer. The second coil has a plurality of conductive segments. One of the plurality of conductive segments of the second coil is disposed within the recess. Attached Figure Description

[0007] Figure 1A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0008] Figure 1B Description of some embodiments according to this disclosure Figure 1A A top view of a semiconductor device package.

[0009] Figure 2 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0010] Figure 3A A perspective view illustrating an inductor according to some embodiments of the present disclosure.

[0011] Figure 3B Description of some embodiments according to this disclosure Figure 3A A cross-sectional view of the inductor in the image.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure.

[0013] Figure 5A and Figure 5B This invention describes a semiconductor manufacturing method according to some embodiments of the present disclosure.

[0014] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0015] Figure 1A The illustration shows a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes: a substrate 10, patterned conductive layers 11 and 12, a dielectric layer 13, and a package body 14.

[0016] The substrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber copper foil laminate. In some embodiments, the substrate 10 may be, for example, a glass substrate. The substrate 10 may include interconnect structures (or electrical connections), such as a redistribution layer (RDL) or a grounding element. The substrate 10 may include a surface 101 and a surface 102 opposite to the surface 101.

[0017] A patterned conductive layer 11 is disposed on the surface 101 of the substrate 10. The patterned conductive layer 11 is a conductive material such as a metal or metal alloy, or contains a conductive material such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof. Figure 1A As shown, the patterned conductive layer 11 includes a plurality of segments 11a, 11b, and 11c from a cross-sectional view of the semiconductor device package 1. Segments 11a, 11b, and 11c are separated from each other. For example, segment 11a is spaced apart from its adjacent segment (e.g., segment 11b), and segment 11b is spaced apart from its adjacent segments (e.g., segments 11a and 11c). For example, a recess (or gap) is defined between two adjacent segments (e.g., segment 11a and segment 11b, or segment 11b and segment 11c).

[0018] A dielectric layer 13 (or passivation layer) is disposed on surface 101 of substrate 10 and patterned conductive layer 11. For example, dielectric layer 13 is conformally disposed on patterned conductive layer 11. In some embodiments, the thickness of dielectric layer 13 is substantially uniform. Dielectric layer 13 covers at least a portion of patterned conductive layer 11. For example, dielectric layer 13 covers the top surface and sidewalls (side surfaces) of segments 11a and 11c of patterned conductive layer 11. For example, dielectric layer 13 covers a portion of the top surface and sidewalls of segment 11b of patterned conductive layer 11, and exposes the remaining portion of the top surface of segment 11b for electrical connection. In some embodiments, dielectric layer 13 comprises a polymer, silicon oxide, oxide nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide.

[0019] A patterned conductive layer 12 is disposed on the dielectric layer 13. The patterned conductive layer 12 is a conductive material such as a metal or metal alloy, or contains a conductive material such as a metal or metal alloy. In some embodiments, the patterned conductive layer 12 and the conductive layer 11 may contain the same material. Alternatively, the patterned conductive layer 12 and the conductive layer 11 may contain different materials. Figure 1AAs shown, the patterned conductive layer 12 includes a plurality of segments 12a, 12b, and 12c from a cross-sectional view of the semiconductor device package 1. Segments 11a, 11b, and 11c are disposed within recesses or gaps defined by the patterned conductive layer 11. For example, segment 12a is disposed within a recess defined by segment 11a and its adjacent segment of the patterned conductive layer 11; segment 12b is disposed within a recess defined by segments 11a and 11b of the patterned conductive layer 11; and segment 12c is disposed within a recess defined by segments 11b and 11c of the patterned conductive layer 11. For example, a portion of the patterned conductive layer 12 (including segments 12a, 12b, and 12c) and a portion of the patterned conductive layer 11 (including segments 11a, 11b, and 11c) overlap in a direction substantially parallel to the surface 101 of the substrate 10. For example, the distance between the surface 111 (also called the top surface) of each of the segments 11a, 11b, 11c of the patterned conductive layer 11 and the surface 101 of the substrate 10 is greater than the distance between the surface 122 (also called the bottom surface) of each of the segments 12a, 12b, 12c of the patterned conductive layer 12 and the surface 101 of the substrate 10.

[0020] Segments 12a, 12b, and 12c are physically spaced apart from each other. For example, segment 12a is spaced apart from its neighboring segment (e.g., segment 1bb), and segment 12b is spaced apart from its neighboring segments (e.g., segments 12a and 12c). In some embodiments, segments 12b and 12c are electrically connected via a connection structure 15. A patterned conductive layer 12 is spaced apart from a patterned conductive layer 11 via a dielectric layer 13. For example, the dielectric layer 13 is disposed between the patterned conductive layer 12 and the patterned conductive layer 11. In some embodiments, the patterned conductive layer 12 and the patterned conductive layer 11 are electrically connected via a connection structure 15 to form or define, for example, Figure 1B The inductor (or coil) shown, the Figure 1B This illustration shows a top view of a semiconductor device package 1 according to some embodiments of the present disclosure. For example, a connection structure 15 is disposed across a segment 11b of a patterned conductive layer 11 to connect segments 12b and 12c of a patterned conductive layer 12. For example, as... Figure 1B As shown, one end of the patterned conductive layer 11 is electrically connected to one end of the patterned conductive layer 12 to define an inductor. In some embodiments, the thickness D11 of the connection structure 15 is less than the thickness D12 of the segment 11a, 11b or 11c of the patterned conductive layer 11 or the thickness D13 of the segment 12a, 12b or 12c of the patterned conductive layer 12.

[0021] Patterned conductive layers 11 and 12 together define an inductor that can be magnetically coupled to a magnetic field to induce current within the patterned conductive layers 11 and 12. For example, the current in the patterned conductive layers 11 and 12 flows in the same direction (e.g., clockwise or counterclockwise). Because the patterned conductive layers 11 and 12 are connected, the total number of turns of the inductor defined by the patterned conductive layers 11 and 12 increases, which in turn increases the inductance of the inductor.

[0022] In some embodiments, the inductance of an inductor with a single coil can be increased by increasing the number of turns in the single coil. However, this also increases the size (e.g., area) of the inductor. In some embodiments, two coils can be directly stacked and connected to increase the inductance of the inductor. For example, one coil is placed on top of another coil in a direction parallel to the top surface of the substrate on which the coil is placed, without any overlap; this will increase the thickness of the inductor. Figure 1A and 1B In one embodiment, an upper coil (e.g., patterned conductive layer 12) is disposed above a lower coil (e.g., patterned conductive layer 11), while segments of the upper coil (e.g., segments 12a, 12b, 12c) are joined to recesses or gaps defined by segments of the lower coil (e.g., segments 11a, 11b, 11c). This allows the inductor (comprising the upper and lower coils) to increase its inductance without increasing the area or thickness of the semiconductor device package 1. In some embodiments, compared to stacked coils without overlapping portions, such as Figure 1A The thickness of the inductor shown can be reduced by approximately 30% to 35%.

[0023] The package 14 is disposed on the substrate 10 to cover patterned conductive layers 11, 12, dielectric layer 13, and interconnection structure 15. In some embodiments, the package 14 comprises an epoxy resin containing a filler, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material containing silicone dispersed therein, or a combination thereof.

[0024] Figure 2 This illustration shows a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure. The semiconductor device package 2 is similar to... Figure 1A In semiconductor device package 1, except in semiconductor device package 2, the conductive patterning layer 12 is separated from the conductive patterning layer 11. For example, the conductive patterning layer 12 is not electrically connected to the conductive patterning layer 11. For example, omitted. Figure 1AThe connection structure 15 is described above. In some embodiments, the conductive patterned layer 12 is magnetically coupled to the conductive patterned layer 11 to form or define a transformer. For example, the conductive patterned layer 11 is the primary winding of the transformer, and the conductive patterned layer 12 is the secondary winding of the transformer, and vice versa.

[0025] Figure 3A A perspective view of an inductor 3 according to some embodiments of the present disclosure is shown. The inductor 3 includes coils 31a, 31b, 32a, and 32b disposed in a stacked structure. A cross-sectional view of the inductor 3 is also shown. Figure 3B As shown, coils 31a and 32a are arranged in a manner similar to... Figure 1A The patterned conductive layers 11 and 12 are arranged in a manner similar to that of coil 31a and coil 31b. For example, a portion of coil 31a and a portion of coil 31b overlap. For example, a segment of coil 31b is disposed within a recess or gap defined by a segment of coil 31a. Structure 32, which includes coils 32a and 32b, is similar to structure 31, which includes coils 31a and 31b. (The last sentence appears to be incomplete and possibly refers to a different structure.) Figure 1A and 1B Compared to the inductor with two stacked coils (i.e., patterned conductive layer 11 and patterned conductive layer 12) shown, the inductor 3 containing four stacked coils 31a, 31b, 32a and 32b has more turns, which will increase the inductance of the inductor 3.

[0026] Figure 4A , 4B 4C, 4D, 4E, and 4F illustrate semiconductor manufacturing methods according to some embodiments of the present disclosure. In some embodiments, implementation Figure 4A The operation in manufacturing Figure 1A and 1B Semiconductor device package 1 in the middle. Alternatively, it can be implemented Figure 4A The operation is used to manufacture other semiconductor device packages or sensors or transformers (e.g., Figure 2 Semiconductor device packaging and Figure 3A and 3B Inductor 3 in the middle.

[0027] refer to Figure 4A A substrate 10 is provided. A patterned conductive layer 11 is formed on the substrate 10. The patterned conductive layer 11 is a conductive material such as a metal or metal alloy, or contains a conductive material such as a metal or metal alloy. A top view illustrating the patterned conductive layer 11 is shown below. Figure 5A As shown, the patterned conductive layer 11 defines the spiral inductor. Figure 4A As shown, the patterned conductive layer 11 comprises multiple segments separated from each other. Multiple recesses (or gaps) 11h are defined between two adjacent segments.

[0028] A dielectric layer 13 (or passivation layer) is formed on the substrate 10 and the patterned conductive layer 11. For example, the dielectric layer 13 is conformally formed on the patterned conductive layer 11. In some embodiments, the dielectric layer 13 has a substantially uniform thickness. In some embodiments, the dielectric layer 13 comprises a polymer, silicon oxide, oxide nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide.

[0029] refer to Figure 4B A photoresist (or mask) 49 is disposed on the dielectric layer 13. An opening 49h1 is formed to remove the photoresist 49 and a portion of the dielectric layer 13 to expose the substrate 10. An opening 49h2 is formed to remove the photoresist 49 and a portion of the dielectric layer 13 to expose a portion of a segment 11b of the patterned conductive layer 11. In some embodiments, openings 49h1 and 49h2 may be formed by drilling, laser drilling, etching, or other suitable processes. In some embodiments, openings 49h1 and 49h2 may be formed by a single removal operation. In some embodiments, openings 49h1 and 49h2 may be formed by two removal operations. For example, a first removal operation is performed to remove the photoresist 49, and a second removal operation is subsequently performed to remove the dielectric layer 13.

[0030] refer to Figure 4C The photoresist 49 is removed, and a seed layer 49s is formed on the dielectric layer 13 and a portion and segment 11b of the substrate 10 exposed from the dielectric layer 13. In some embodiments, the seed layer 49s is formed by, for example, sputtering or other suitable processes.

[0031] refer to Figure 4D A photoresist 48 (or mask) is disposed on a seed layer 49s, and a portion of the photoresist 48 is removed to expose a recess 11h defined by segments 11a, 11b, and 11c of the patterned conductive layer 11, a portion of the seed layer 49s disposed on segment 11b, and the substrate 10. In some embodiments, a portion of the photoresist 48 may be formed by drilling, laser drilling, etching, or other suitable processes. In some embodiments, a portion of the photoresist 48 may be removed by a single removal operation or multiple removal operations, depending on design requirements.

[0032] refer to Figure 4E The patterned conductive layer 12 and the connection structure 15 are formed by, for example, electroplating or other suitable processes. For example, a top view illustrating the patterned conductive layer 12 is shown. Figure 5B As shown, the patterned conductive layer 12 defines a spiral inductor disposed within a recess 11h defined by a segment of the patterned conductive layer 11. For example, as Figure 4EAs shown, the patterned conductive layer 12 includes a plurality of segments 12a, 12b, 12c disposed within recesses defined by segments of the patterned conductive layer 11. The patterned conductive layer 12 is a conductive material such as a metal or metal alloy, or contains a conductive material such as a metal or metal alloy.

[0033] refer to Figure 4F A portion of the seed layer 49s that does not contact the patterned conductive layer 12 is removed by, for example, etching (e.g., wet etching) or other suitable processes. Subsequently, the package 14 is formed to cover the patterned conductive layers 11, 12, the dielectric layer 13, and the interconnect structure 15 to form a semiconductor device package 4. In some embodiments, the package 14 can be formed by molding techniques such as transfer molding or compression molding. The semiconductor device package 4 is similar to... Figure 1A Semiconductor device package 1, except for semiconductor device package 4, further includes a seed layer 49s between a patterned conductive layer 12 and a dielectric layer 13.

[0034] As used herein, the terms “substantially,” “generally,” “approximately,” and “about” are used to indicate and explain small variations. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, “substantially homogeneous” film or layer thickness may refer to a standard deviation of the average thickness of the film or layer less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces lying along the same plane within a few micrometers, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm. If the angle between two surfaces or components is, for example, 90° ± 10°, or, for example, ± 5°, ± 4°, ± 3°, ± 2°, ± 1°, ± 0.5°, ± 0.1°, or ± 0.05°, then the two surfaces or components can be considered "substantially perpendicular." When used in conjunction with an event or situation, the terms "substantially," "substantially," "approximately," and "about" can refer to examples where the event or situation occurs precisely, as well as examples where the event or situation occurs very approximately.

[0035] In the description of some embodiments, a component provided "on" another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0036] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0037] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. Those skilled in the art will readily understand that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. The drawings may not be drawn to scale. There may be differences between the artistic representation in this disclosure and actual equipment due to variations in manufacturing processes, etc. Other embodiments of this disclosure may exist that are not specifically described. This specification and the drawings should be considered illustrative rather than restrictive. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: Substrate; A first patterned conductive layer is disposed on the substrate, the first patterned conductive layer comprising a first conductive segment and a second conductive segment; A dielectric layer that contacts the first patterned conductive layer; A second patterned conductive layer is disposed on the dielectric layer, the second patterned conductive layer comprising a first conductive segment and a second conductive segment spaced apart from each other, wherein the second conductive segment of the first patterned conductive layer is adjacent to the second conductive segment of the second patterned conductive layer. as well as A connecting structure that directly contacts the second conductive segment of the second patterned conductive layer, wherein the connecting structure is located above the second conductive segment of the first patterned conductive layer, and the thickness of the connecting structure is less than the thickness of the second conductive segment of the first patterned conductive layer or the thickness of the second conductive segment of the second patterned conductive layer.

2. The semiconductor device package of claim 1, wherein the connection structure overlaps the dielectric layer in the horizontal direction.

3. The semiconductor device package of claim 1, wherein a portion of the connection structure covers the stepped structure of the dielectric layer.

4. The semiconductor device package of claim 3, wherein the stepped structure of the dielectric layer covers a portion of the top surface and a portion of the side surface of the second conductive segment of the first patterned conductive layer.

5. The semiconductor device package of claim 1, wherein a portion of the connection structure is embedded in the dielectric layer.

6. The semiconductor device package of claim 5, wherein a portion of the connection structure is located between the first conductive segment and the second conductive segment of the second patterned conductive layer.

7. The semiconductor device package of claim 1, wherein the connection structure is located between the second conductive segment of the first patterned conductive layer and the second conductive segment of the second patterned conductive layer.

8. The semiconductor device package of claim 1, wherein the distance between the bottom surface of the connection structure and the top surface of the second conductive segment of the first patterned conductive layer is less than the distance between the bottom surface of the connection structure and the top surface of the second conductive segment of the second patterned conductive layer.

9. A semiconductor device package comprising: A substrate having a top surface; A first patterned conductive layer is disposed on the top surface of the substrate, the first patterned conductive layer comprising a first conductive segment. A dielectric layer that contacts the first conductive segment of the first patterned conductive layer; A second patterned conductive layer is disposed on the dielectric layer, the second patterned conductive layer comprising a first conductive segment, wherein the first conductive segment of the first patterned conductive layer overlaps with the first conductive segment of the second patterned conductive layer in a direction parallel to the top surface of the substrate. as well as The connection structure is located above the first conductive segment of the first patterned conductive layer, and its thickness is less than the thickness of the first conductive segment of the first patterned conductive layer or the thickness of the first conductive segment of the second patterned conductive layer.

10. The semiconductor device package of claim 9, wherein the connection structure overlaps with the first conductive segment of the second patterned conductive layer in the horizontal direction.

11. The semiconductor device package of claim 9, wherein the second patterned conductive layer further comprises a second conductive segment, and the connection structure overlaps with the second conductive segment of the second patterned conductive layer in a horizontal direction.

12. The semiconductor device package of claim 9, wherein a portion of the connection structure protrudes from the side of the first conductive segment of the first patterned conductive layer and contacts the dielectric layer.

13. The semiconductor device package of claim 9, further comprising a package body covering the first patterned conductive layer and the second patterned conductive layer.

14. The semiconductor device package of claim 13, further comprising a seed layer disposed between the second patterned conductive layer and the dielectric layer, wherein the package body overlaps the first patterned conductive layer in a horizontal direction.

15. A semiconductor device package comprising: A substrate having a top surface; A first patterned conductive layer is disposed on the top surface of the substrate, the first patterned conductive layer comprising a plurality of conductive segments. A dielectric layer that contacts the first patterned conductive layer and defines a recess between two adjacent conductive segments of the first patterned conductive layer. A second patterned conductive layer is disposed on the dielectric layer, the second patterned conductive layer comprising a plurality of conductive segments, wherein one of the plurality of conductive segments of the second patterned conductive layer is disposed within the recess; as well as A connection structure that connects to one of the plurality of conductive segments of the second patterned conductive layer and spans one of the plurality of conductive segments of the first patterned conductive layer, wherein the thickness of the connection structure is less than the thickness of any one of the plurality of conductive segments of the first patterned conductive layer or the thickness of any one of the plurality of conductive segments of the second patterned conductive layer, and the connection structure is located above the one of the plurality of conductive segments spanning the first patterned conductive layer.

16. The semiconductor device package of claim 15, wherein the side surface of the connection structure contacts one of the plurality of conductive segments of the second patterned conductive layer, and the bottom surface of the connection structure contacts one of the plurality of conductive segments of the first patterned conductive layer.

17. The semiconductor device package of claim 15, further comprising a package covering the first patterned conductive layer and the second patterned conductive layer.

18. The semiconductor device package of claim 17, wherein the bottom surface of the package is substantially not lower than the bottom surface of the first patterned conductive layer.

19. The semiconductor device package of claim 17, wherein the contact area between the package body and one side of one of the plurality of conductive segments of the first patterned conductive layer is greater than the contact area between the package body and another side of the plurality of conductive segments of the first patterned conductive layer.

20. A method for manufacturing a semiconductor device package, comprising: Provide substrate; A first patterned conductive layer is formed on the substrate. The first patterned conductive layer includes a plurality of conductive segments, and recesses are defined between adjacent conductive segments. A dielectric layer is formed on the substrate and the first patterned conductive layer; An opening is formed that exposes a portion of one of the plurality of conductive segments of the first patterned conductive layer; A seed layer is formed on the dielectric layer and the exposed first patterned conductive layer; A second patterned conductive layer and a connection structure are formed on the seed layer, wherein the connection structure spans one of the plurality of conductive segments of the first patterned conductive layer; Remove a portion of the seed layer that is not covered by the second patterned conductive layer; as well as An encapsulation is formed to cover the first patterned conductive layer, the second patterned conductive layer, the dielectric layer, and the connection structure.

Images