Semiconductor device and method of manufacturing a semiconductor device

Abstract

Disclosed is a semiconductor device capable of preventing defects caused by damage due to plasma and a method of manufacturing the semiconductor device. The semiconductor device includes a dummy gate structure including a dummy gate dielectric layer and a dummy gate electrode disposed over a scribe lane region of a substrate, a first contact penetrating through the dummy gate dielectric layer to contact the dummy gate electrode and the substrate, an interlayer dielectric layer disposed over the dummy gate structure, a metal interconnect disposed over the interlayer dielectric layer, and a second contact penetrating through the interlayer dielectric layer to electrically connect the gate and the metal interconnect.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0037267, filed on March 24, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0002] Exemplary embodiments of this disclosure relate to a semiconductor device, and more specifically, to a semiconductor device including metal contacts in a scribe line, and a method of manufacturing the semiconductor device. Background Technology

[0003] Plasma-based processes (hereinafter referred to as plasma processes) are known to be used in many semiconductor manufacturing processes. Plasma processes are primarily used for depositing or etching multiple layers of material. Device characteristics may be degraded due to the electrons generated by the plasma used. Summary of the Invention

[0004] Embodiments of this disclosure relate to a semiconductor device capable of preventing defects that may be caused by plasma-induced damage, and a method of manufacturing the semiconductor device.

[0005] According to one embodiment of the present disclosure, a semiconductor device includes: a dummy gate structure including a dummy gate dielectric layer and a dummy gate electrode disposed on a scribe region of a substrate; a first contact penetrating the dummy gate dielectric layer to connect the dummy gate electrode and the substrate; an interlayer dielectric layer disposed on the dummy gate structure; a metal interconnect disposed on the interlayer dielectric layer; and a second contact penetrating the interlayer dielectric layer to electrically connect the gate electrode and the metal interconnect.

[0006] According to another embodiment of this disclosure, a semiconductor device includes: a substrate including a memory cell region and a scribe region; a bit line structure including bit line contacts disposed on the substrate of the memory cell region; a dummy gate structure including a dummy gate dielectric layer and a dummy gate electrode disposed on the substrate of the scribe region; a first contact penetrating the dummy gate dielectric layer to connect the dummy gate electrode and the substrate; a peripheral interlayer dielectric layer disposed on the dummy gate structure; a peripheral metal interconnect disposed on the peripheral interlayer dielectric layer; and a second contact penetrating the peripheral interlayer dielectric layer to electrically connect the dummy gate electrode and the peripheral metal interconnect.

[0007] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device includes: forming a first dielectric material layer over a scribe region of a substrate; forming a second dielectric material layer over a memory cell region of the substrate and over the first dielectric material layer in the scribe region; etching the second dielectric material layer in the memory cell region and the first and second dielectric material layers in the scribe region to form a contact hole; and filling the contact hole with a conductive material gap to form a bit line contact in the memory cell region and a dummy contact in the scribe region. Attached Figure Description

[0008] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 3A to 3H This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0011] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the scope of the disclosure to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same components in the various drawings and embodiments.

[0012] Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0013] The accompanying drawings are not necessarily drawn to scale, and in some cases may be enlarged to clearly illustrate the features of the embodiments. When referring to a first layer being "on" a second layer or "on" a substrate, it means not only that the first layer is formed directly on the second layer or substrate, but also that a third layer exists between the first layer and the second layer or substrate.

[0014] Figure 1 To illustrate a plan view of a semiconductor device according to an embodiment of the present disclosure, Figure 2 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0015] See Figure 1The substrate may include a main chip region (MC) and a scribe line region (SL). The MC may include memory cell regions and peripheral circuit regions. The scribe line regions (SL) may be located between adjacent MCs to separate the chips from each other. The scribe line regions (SL) may include test patterns and overlay keys, or dummy patterns used to prevent roading during etching and chemical mechanical polishing (CMP) processes when forming components in the MCs.

[0016] refer to Figure 2 The substrate 101 may include a first region R1 and a second region R2. The first region R1 may be a memory cell region. This memory cell region may be formed on... Figure 1 The main chip region MC. The second region R2 can be the scribing region SL (see...). Figure 1 ).

[0017] The first region R1 of substrate 101 may include a memory cell region in which elements such as buried gate structures BG, bit line structures BL, and memory elements CAP are formed. The second region R2 of substrate 101 may be a region in the scribe region SL in which a dummy pattern is formed for the purpose of preventing road effects (e.g., uneven or irregular etching) during etching and chemical mechanical polishing (CMP) processes.

[0018] Substrate 101 may be a material suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. Substrate 101 may be formed of a silicon-containing material. Substrate 101 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. Substrate 101 may also include other semiconductor materials, such as germanium. Substrate 101 may also include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 101 may also include a silicon-on-insulator (SOI) substrate.

[0019] The first region R1 and the second region R2 may be separated by an isolation layer 102, and each region may include an active region 103 defined by the isolation layer 102. The isolation layer 102 may be a shallow trench isolation region (STI), which is formed by a trench etching process. The isolation layer 102 may include silicon oxide, silicon nitride, or a combination thereof.

[0020] A buried gate structure BG may be provided in the substrate 101 of the first region R1. The buried gate structure BG may include a buried gate structure disposed at a level below the top surface of the substrate 101. The embodiments of this disclosure illustrate a buried gate structure disposed at a level below the top surface of the substrate 101, but the concept and spirit of the embodiments of this disclosure are not limited thereto. The embodiments of this disclosure can be applied to all gate structures, including recessed gates, fin gates, planar gates, etc.

[0021] The buried gate structure BG may include a gate dielectric layer 105 formed on the surface of the gate trench 104, a gate electrode 106 formed on the gate dielectric layer 105 to fill the gate trench 104, and a gate capping layer 107.

[0022] Specifically, a linear gate trench 104 can be formed in the substrate 101, intersecting the active region 103 and the isolation layer 102 in one direction. The bottom surface of the gate trench 104 can be disposed at a level higher than the bottom surface of the isolation layer 102. In other words, the depth of the gate trench 104 can be shallower than the depth of the isolation layer 102. The bottom of the gate trench 104 can have curvature. According to another embodiment of the present disclosure, the isolation layer 102 can be etched to a predetermined depth in the direction in which the gate trench 104 extends to form fins in the active region 103.

[0023] A gate dielectric layer 105 may be formed on the surface of a gate trench 104. A gate electrode 106, filling a portion of the gate trench 104, may be formed on the gate dielectric layer 105. A gate capping layer 107 (also referred to as a sealing layer) filling the remaining portion of the gate trench 104 may be formed on the gate electrode 106. The top surface of the gate capping layer 107 may be at the same level as the top surface of the substrate 101. The top surface of the gate electrode 106 may be at a level lower than the top surface of the substrate 101. The gate electrode 106 may comprise a low-resistance metal material. The gate electrode 106 may comprise a combination of at least one of a metal material, a metal nitride, and polysilicon, or a stacked structure thereof. For example, the gate electrode 106 may be formed by sequentially stacking titanium nitride and tungsten. According to another embodiment of this disclosure, the gate electrode 106 may be formed solely of titanium nitride (TiN only). According to another embodiment of this disclosure, the gate electrode 106 may comprise a stacked structure of a metal material and polysilicon.

[0024] A first impurity region 108 and a second impurity region 109 can be formed in the substrate 101. The first impurity region 108 and the second impurity region 109 can be referred to as the "source region" and "drain region". The first impurity region 108 and the second impurity region 109 can be separated from each other by a gate trench 104. Therefore, the gate electrode 106 and the first impurity region 108 and the second impurity region 109 can constitute a single-cell transistor. Since the gate electrode 106 has a buried gate structure, this single-cell transistor can improve the short-channel effect.

[0025] A first unit interlayer dielectric layer 110 can be formed on the substrate 101.

[0026] Bit line contact 120 can be formed to extend through the first interlayer dielectric layer 110 over the substrate 101 to couple to the substrate 101. Bit line contact 120 can be coupled to a first impurity region 108. Bit line contact 120 can be disposed in a bit line contact hole BH. Bit line contact hole BH can expose the first impurity region 108. The bottom surface of bit line contact 120 can be lower than the top surface of substrate 101. Bit line contact 120 can be formed of polysilicon or a metallic material. The linewidth of a portion of bit line contact 120 can be smaller than the diameter of bit line contact hole BH. Therefore, a gap can be formed on each side of bit line contact 120. The gap can be formed independently on both sides of bit line contact 120. As a result, a bit line contact 120 and a pair of gaps can be disposed in bit line contact hole BH, and the pair of gaps can be separated by bit line contact 120.

[0027] A bitline structure BL can be formed on bitline contact 120. The bitline structure BL can be coupled to an active region through bitline contact 120. The bitline structure BL may include bitlines 121, 122, and 123 and a bitline hard mask 124 located on bitlines 121, 122, and 123. A portion of bitlines 121, 122, and 123 can be coupled to bitline contact 120.

[0028] The linewidths of bit lines 121, 122, and 123 and bit line contact 120 may be the same. Bit lines 121, 122, and 123 may include a metallic material. Bit lines 121, 122, and 123 may include a stacked structure of different metallic materials. Bit line hard mask 124 may include a dielectric material.

[0029] Bit line spacer 125 can be formed on the sidewall of bit line contact 120 and bit line structure BL. Bit line spacer 125 can extend from the sidewall of bit line structure BL to bit line contact 120. Bit line spacer 125 can fill the gap between bit line contact 120 and bit line contact hole BH.

[0030] Bit line spacer 125 can be a single-layer or multi-layer structure. Bit line spacer 125 may include a dielectric material. Bit line spacer 125 may include at least one of silicon oxide, silicon nitride, and low-k materials, or a combination of one or more of them.

[0031] The memory node contact 130 can be formed between adjacent bit line structures BL. The memory node contact 130 can be coupled to the second impurity region 109.

[0032] An inter-cell dielectric layer 131 may be formed on the memory node contact 130. The inter-cell dielectric layer 131 may include landing pads 132 that overlap at least a portion of the memory node contact 130. The landing pads 132 may extend through the inter-cell dielectric layer 131.

[0033] The memory element CAP can be formed on the landing pad 132. According to embodiments of the present disclosure, the memory element CAP may include a capacitor. The capacitor may include a stacked structure of a lower electrode 140, a dielectric layer 141, and an upper electrode 142. The capacitor can be coupled to the substrate 101 of the first region R1 through the landing pad 132 and the memory node contact 130.

[0034] The lower electrode 140 may be columnar. According to another embodiment of this disclosure, the lower electrode 140 may include a cylindrical or prismatic shape. According to another embodiment of this disclosure, the lower electrode 140 may include a stacked structure of different materials. The lower electrode 140 may be a metal-based material. A metal-based material can refer to a material containing metal.

[0035] The dielectric layer 141 may comprise a single-layer structure, a multilayer structure, or a laminated structure. The dielectric layer 141 may be a doped structure or a hybrid structure. The dielectric layer 141 may comprise a high-k material. The dielectric constant of the dielectric layer 141 may be higher than that of silicon oxide (SiO2). The dielectric constant of silicon oxide may be about 3.9, while the dielectric layer 141 may comprise a material with a dielectric constant of about 4 or greater. The dielectric constant of the high-k material may be about 20 or greater. The high-k material may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or titanium strontium oxide (SrTiO3). According to another embodiment of this disclosure, the dielectric layer 141 may be formed from a composite layer comprising two or more layers of the aforementioned high-k material. The dielectric layer 141 may be formed from a zirconium-based oxide. The dielectric layer 141 may have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) can include ZA (ZrO2 / Al2O3) or ZAZ (ZrO2 / Al2O3 / ZrO2). ZA can be a structure in which alumina is stacked on top of zirconium oxide. ZAZ can be a structure in which zirconium oxide, alumina, and zirconium oxide are sequentially stacked. ZrO2, ZA, and ZAZ can be referred to as zirconium oxide (ZrO2)-based layers. According to another embodiment of this disclosure, dielectric layer 141 can be formed of hafnium (Hf)-based oxide. Dielectric layer 141 can be a stacked structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO2) can include HA (HfO2 / Al2O3) or HAH (HfO2 / Al2O3 / HfO2). HA can be a structure in which alumina is stacked on top of hafnium oxide. HAH can be a structure in which hafnium oxide, alumina, and hafnium oxide are sequentially stacked. HfO2, HA, and HAH can be referred to as hafnium oxide (HfO2) based layers.

[0036] In ZA, ZAZ, HA, and HAH, the band gap of alumina (Al2O3) can be larger than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of alumina (Al2O3) can be lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, dielectric layer 141 can include a stack of high-k materials and high-bandgap materials with band gaps larger than those of the high-k materials. In addition to alumina, dielectric layer 141 can also include silicon oxide (SiO2) as another high-bandgap material. Dielectric layer 141 can suppress leakage current by including high-bandgap materials. High-bandgap materials can be very thin. High-bandgap materials can be thinner than high-k materials.

[0037] According to another embodiment of this disclosure, dielectric layer 141 may include a laminated structure of alternating stacks of high-k materials and high-bandgap materials. For example, it may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stacks. In the above laminated structures, the thickness of alumina (Al2O3) can be very thin. According to another embodiment of this disclosure, dielectric layer 141 may include a structure in which a first high-k material is doped with a second high-k material. For example, dielectric layer 141 may include titanium oxide-doped zirconium oxide (TiO2-doped ZrO2), wherein zirconium oxide (ZrO2) is doped with titanium oxide (TiO2). According to another embodiment of this disclosure, dielectric layer 141 may include a structure of a mixture of different high-k materials. For example, it may include TiZrAlO, wherein zirconium oxide (ZrO2), titanium oxide (TiO2), and aluminum oxide (Al2O3) are mixed.

[0038] The upper electrode 142 may include silicon-containing materials, germanium-containing materials, metallic materials, or combinations thereof. The upper electrode 142 may include metals, metal nitrides, metal carbides, conductive metal oxides, or combinations thereof. The upper electrode 142 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), or combinations thereof. The upper electrode 142 may include a silicon layer (Si layer), a germanium layer (Ge layer), a silicon-germanium layer (SiGe layer), or combinations thereof. The upper electrode 142 can be formed by stacking a silicon-germanium layer (Si / SiGe) on top of a silicon layer. The upper electrode 142 can be formed by stacking a silicon-germanium layer (Ge / SiGe) on top of a germanium layer. The upper electrode 142 may include a stack of silicon-containing materials and metallic materials. The upper electrode 142 can be formed by stacking a silicon-germanium layer and a metal nitride. The upper electrode 142 can be formed by stacking silicon germanium and tungsten nitride (TiN / SiGe / WN) on titanium nitride.

[0039] The cell metal interconnect 153 can be disposed above the memory element CAP in the first region R1. The cell metal interconnect 153 can be disposed at a level higher than the top surface of the memory element CAP. The etch stop layer 150 and the third cell interlayer dielectric layer 151 can be disposed between the cell metal interconnect 153 and the memory element CAP.

[0040] The cell metal interconnect 153 can be coupled to the memory element CAP via the cell metal interconnect contact 152. The cell metal interconnect contact 152 can penetrate the third cell interlayer dielectric layer 151, and one end of it contacts the upper electrode 142 of the memory element CAP, and the other end contacts the cell metal interconnect 153.

[0041] The substrate 101 of the second region R2 may include a dummy gate PG and a peripheral metal interconnect 236.

[0042] A dummy gate PG can be used to prevent road effects during etching and planarization processes when forming the device in the first region R1. The dummy gate PG may include a stacked structure of a dummy gate dielectric layer 201, dummy gate electrodes (221, 222, and 223), and a dummy gate hard mask 224. A first peripheral interlayer dielectric layer 210 may be disposed between the dummy gate dielectric layer 201 and the dummy gate electrodes 221, 222, and 223. According to another embodiment of this disclosure, the first peripheral interlayer dielectric layer 210 may be removed. Dummy gate spacers 225 may be formed on the sidewalls of the dummy gate PG.

[0043] Specifically, according to embodiments of the present disclosure, dummy contacts 220 may be formed below dummy gate electrodes 221, 222 and 223 to electrically connect the dummy gate electrodes 221, 222 and 223 to the substrate 101.

[0044] The dummy contact 220 can penetrate the first peripheral interlayer dielectric layer 210 and the dummy gate dielectric layer 201, and can be disposed between the dummy gate electrodes 221, 222 and 223 and the substrate 101 so that both ends of the dummy contact 220 are in contact with the dummy gate electrodes 221, 222 and 223 and the substrate 101.

[0045] The dummy contact 220 may have an inclined profile, and its width narrows as it approaches the substrate 101. That is, the width of the dummy contact 220 can narrow from the top surface of the dummy contact 220 to the bottom surface of the dummy contact 220. The width of the top surface of the dummy contact 220 may be greater than the width of the bottom surface of the dummy contact 220.

[0046] The dummy contact 220 can be formed simultaneously with the bit line contact 120 during the manufacturing process. The dummy contact 220 may include the same material as the bit line contact 120. For example, the dummy contact 220 may include polysilicon.

[0047] The dummy gate spacer 225 can be formed on the two sidewalls of the dummy gate PG.

[0048] A second peripheral interlayer dielectric layer 226 can be formed on the substrate 101 between the dummy gates PG.

[0049] The third to fifth peripheral interlayer dielectric layers 230, 232 and 234 can be formed on the second peripheral interlayer dielectric layer 226 and the dummy gate PG.

[0050] A first peripheral metal interconnect 233 can be formed on the third peripheral interlayer dielectric layer 230, and a second peripheral metal interconnect 236 can be formed on the fifth peripheral interlayer dielectric layer 234.

[0051] The second peripheral metal interconnect 236 and the first peripheral metal interconnect 233 can be electrically connected via a second peripheral metal contact 235 that penetrates the fifth peripheral interlayer dielectric layer 234. The first peripheral metal interconnect 233 can be electrically connected to the dummy gate electrodes 221, 222 and 223 of the dummy gate PG via a first peripheral metal contact 231 that penetrates the third peripheral interlayer dielectric layer 230 and the dummy gate hard mask 224.

[0052] As described above, according to embodiments of the present disclosure, by forming dummy contacts 220 between dummy gate electrodes 221, 222 and 223 and substrate 101, a current path from the second peripheral metal interconnect 236 to substrate 101 can be formed.

[0053] Therefore, by naturally releasing plasma ions from the top to the substrate 101 via this current path, defects caused by plasma-induced damage can be prevented.

[0054] Figures 3A to 3H A cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0055] refer to Figure 3A The substrate 11 may include a first region R1 and a second region R2. The first region R1 may be a memory cell region. The second region R2 may be a scribing region.

[0056] Substrate 11 may be a material suitable for semiconductor processing. Substrate 11 may include a semiconductor substrate. Substrate 11 may be formed of a silicon-containing material. Substrate 11 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multiples thereof. Substrate 11 may also include another semiconductor material, such as germanium. Substrate 11 may also include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 11 may also include a silicon-on-insulator (SOI) substrate.

[0057] First region R1 and second region R2 may be isolated by isolation layer 12, and each region may include an active region 13 defined by isolation layer 12. Isolation layer 12 may be a shallow trench isolation region (STI), which is formed by a trench etching process. Isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be performed to fill the isolation trench with dielectric material. Planarization processes such as chemical mechanical polishing (CMP) may also be used.

[0058] Subsequently, a buried gate structure BG can be formed in the substrate 11 of the first region R1. The buried gate structure BG may include a gate trench 14, a gate dielectric layer 15 covering the bottom surface and sidewalls of the gate trench 14, a gate electrode 16 filling a portion of the gate trench 14 on the gate dielectric layer 15, and a gate capping layer 17 formed on the gate electrode 16.

[0059] The method for forming a buried grid structure (BG) can be as follows.

[0060] First, a gate trench 14 can be formed in the substrate 11. The gate trench 14 can be linear, spanning the active region 13 and the isolation layer 12. The gate trench 14 can be formed by forming a mask pattern (not shown) on the substrate 11 and using the mask pattern as an etching mask for an etching process. The gate trench 14 can be formed shallower than the isolation trench. In other words, the bottom surface of the gate trench 14 can be set at a level higher than the bottom surface of the isolation layer 12. The depth of the gate trench 14 can be deep enough to increase the average cross-sectional area of ​​the gate electrode 16. Therefore, the resistance of the gate electrode 16 can be reduced. According to another embodiment of this disclosure, the bottom edge of the gate trench 14 can have curvature. By forming the bottom edge of the gate trench 14 with curvature, the unevenness of the bottom of the gate trench 14 can be minimized, thereby facilitating the filling of the gate electrode 16.

[0061] Subsequently, a gate dielectric layer 15 can be formed on the bottom surface and sidewalls of the gate trench 14. Before forming the gate dielectric layer 15, etching damage on the surface of the gate trench 14 can be repaired. For example, the sacrificial oxide can be removed after forming it through a thermal oxidation process.

[0062] The gate dielectric layer 15 can be formed by a thermal oxidation process. For example, the gate dielectric layer 15 can be formed by oxidizing the bottom surface and sidewalls of the gate trench 14.

[0063] According to another embodiment of this disclosure, the gate dielectric layer 15 can be formed by a deposition method, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 15 may include a high-k material, an oxide, a nitride, an oxide oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium oxynitride silicon, or a combination thereof. According to another embodiment of this disclosure, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium oxynitride silicon, aluminum oxide, or a combination thereof. Other known high-k materials may also be selectively used as high-k materials.

[0064] According to another embodiment of this disclosure, the gate dielectric layer 15 can be formed by depositing a pad polysilicon layer and then subjecting the pad polysilicon layer to free radical oxidation.

[0065] According to another embodiment of this disclosure, the gate dielectric layer 15 can be formed by forming a pad silicon nitride layer and then subjecting the pad silicon nitride layer to free radical oxidation.

[0066] Subsequently, a gate electrode 16 can be formed on the gate dielectric layer 15. To form the gate electrode 16, a conductive layer (not shown) can be formed to fill the gate trench 14, and then a recess process can be performed. The recess process can be performed by performing an etch-back process or by sequentially performing a chemical mechanical polishing (CMP) process and an etch-back process. The gate electrode 16 can have a recessed shape that fills a portion of the gate trench 14. In other words, the top surface of the gate electrode 16 can be disposed at a level below the top surface of the substrate 11. The gate electrode 16 can include a metal, a metal nitride, or a combination thereof. For example, the gate electrode 16 can be formed from a stack of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). The titanium nitride / tungsten (TiN / W) stack can have a structure in which titanium nitride is first conformally formed, and then a portion of the gate trench 14 is filled with tungsten. Titanium nitride can be used alone as the gate electrode 16, which can be referred to as a gate electrode 16 with a "TiN-only" structure. According to another embodiment of this disclosure, the gate electrode 16 may include a stacked structure of metal and polysilicon.

[0067] Subsequently, a gate capping layer 17 may be formed over the gate electrode 16. The gate capping layer 17 may include a dielectric material. The remaining portion of the gate trench 14 over the gate electrode 16 may be filled by the gate capping layer 17. The gate capping layer 17 may include silicon oxide. According to another embodiment of this disclosure, the gate capping layer 17 may have a nitride-oxide-nitride (NON) structure. The top surface of the gate capping layer 17 may be disposed at the same level as the top surface of the substrate 11.

[0068] After forming the buried gate structure as described above, a first source / drain region 18 and a second source / drain region 19 can be formed. The first source / drain region 18 and the second source / drain region 19 can be formed by a doping process (such as implantation). The first source / drain region 18 and the second source / drain region 19 can have the same depth. According to another embodiment of this disclosure, the first source / drain region 18 can be deeper than the second source / drain region 19. The first source / drain region 18 can be a region coupled to a bit line contact. The second source / drain region 19 can be a region coupled to a memory contact.

[0069] The unit transistor of the memory cell can be formed by a gate electrode 16, a first source / drain region 18, and a second source / drain region 19.

[0070] refer to Figure 3B A first dielectric material layer 20 can be formed on the substrate 11 of the second region R2. The first dielectric material layer 20 can be a dielectric material used to form the peripheral gate dielectric layer. The first dielectric material layer 20 can be formed by a thermal oxidation process, but the concept and spirit of the embodiments of this disclosure are not limited thereto.

[0071] A second dielectric material layer 21 can be formed on the substrate 11 of the first region R1 and the substrate 11 of the second region R2, which includes the first dielectric material layer 20. The second dielectric material layer 21 can be a mold layer for providing interlayer dielectric layers and contact areas. The second dielectric material layer 21 can be a single-layer structure or a multilayer structure.

[0072] A mask pattern 22 may be formed on the second dielectric material layer 21. The mask pattern 22 may define bit line contact areas. According to embodiments of the present disclosure, the mask pattern 22 may be formed in each of the first region R1 and the second region R2.

[0073] refer to Figure 3C Contact holes 23 and 23P of the exposed substrate 11 can be formed by etching the second dielectric material layer 21 of the first region R1 and the second dielectric material layer 21 and the first dielectric material layer 20 of the second region R2.

[0074] Contact holes 23 and 23P can be circular or elliptical. A portion of the substrate 11 of the first region R1 and the second region R2 can be exposed through contact holes 23 and 23P. Contact holes 23 and 23P can be formed as part of the active region 13 exposing each region.

[0075] The contact hole 23 in the first region R1 can be called the "bit line contact hole 23". The contact hole 23P in the second region R2 can be called the "dummy contact hole 23P".

[0076] The bit line contact hole 23 can expose the first doped region 18. In the etching process used to form the bit line contact hole 23, a portion of the first doped region 18, the isolation layer 12, and the gate capping layer 17 can be etched. In other words, the gate capping layer 17, the first doped region 18, and the isolation layer 12 located below the bit line contact hole 23 can be recessed to a predetermined depth. Therefore, the bottom of the bit line contact hole 23 can extend into the substrate 11. As the bit line contact hole 23 extends, the first doped region 18 can be recessed, and the top surface of the first doped region 18 can be positioned below the level of the top surface of the second doped region 19.

[0077] The dummy contact hole 23P can expose the active region of the second region R2. In the etching process used to form the dummy contact hole 23P, the substrate 11 of the second region R2 can be partially etched. In other words, the bottom surface of the dummy contact hole 23P can be set at a lower level than the top surface of the substrate 11.

[0078] Bit line contact hole 23 and dummy contact hole 23P can be formed simultaneously using the same etching process. Bit line contact hole 23 and dummy contact hole 23P can be formed into the same shape using the same mask process. The bottom surface of bit line contact hole 23 and the bottom surface of dummy contact hole 23P can be set at the same level, but the concept and spirit of the embodiments disclosed herein are not limited thereto, and the height of the bottom surface can vary depending on the etching selectivity of each layer.

[0079] refer to Figure 3D A conductive material 24 can be formed to fill the gaps in the bit line contact holes 23 and the dummy contact holes 23P. The conductive material 24 can fill the gaps in the bit line contact holes 23 and the dummy contact holes 23P, and can be formed on the mask pattern 22. For example, the conductive material 24 can include polysilicon.

[0080] refer to Figure 3E Bit line contacts 24C and dummy contacts 24P can be formed in the first region R1 and the second region R2, respectively. To form the bit line contacts 24C and dummy contacts 24P, conductive material 24 (see...) can be used. Figure 3D The etching process is performed to expose the top surface of the second dielectric material layer 21. For example, the etching of the conductive material 24 may include a chemical mechanical polishing (CMP) process or an etch-back process.

[0081] The dummy contact 24P may have a sloping profile, and its width narrows as it approaches the substrate 11. That is, the width of the dummy contact 24P can narrow from the top surface of the dummy contact 24P to the bottom surface of the dummy contact 24P. The width of the top surface of the dummy contact 24P may be greater than the width of the bottom surface of the dummy contact 24P.

[0082] refer to Figure 3FA dummy gate structure PG can be formed in the second region R2. The dummy gate structure PG may include a stacked structure of dummy gate electrodes 24P, 25P, 26P and a dummy gate hard mask 28P. Dummy gate spacers 29 may be formed on the two sidewalls of the dummy gate structure PG.

[0083] The method for forming a dummy gate structure PG can be as follows.

[0084] First, a first conductive material to a third conductive material 25, 26, and 27 can be sequentially formed on a second interlayer dielectric layer 21, including bit line contacts 24C and dummy contacts 24P. The first conductive material to the third conductive material 25, 26, and 27 can have a stacked structure for forming the bit lines of the first region R1 and the dummy gate electrodes of the second region R2.

[0085] Subsequently, a hard mask layer 28 can be formed on the third conductive material 27.

[0086] Subsequently, a mask pattern can be formed on the hard mask layer 28 of the second region R2. This mask pattern can define a dummy gate in the second region R2. The mask pattern can be formed on the outline of the hard mask layer 28 of the first region R1.

[0087] Subsequently, the hard mask layer 28, the first to third conductive materials (25, 26 and 27), the second dielectric material layer 21 and the first dielectric material layer 20 of the second region R2 can be sequentially etched using a mask pattern.

[0088] Subsequently, dummy gate spacers 29 can be formed on the two sidewalls of the dummy gate structure PG.

[0089] Specifically, according to embodiments of this disclosure, in the dummy gate structure PG, the dummy contact 24P can electrically connect the dummy gate electrodes 24P, 25P, and 26P to the substrate 11. Therefore, when only the dummy gate dielectric layer 20P is provided between the dummy gate electrodes 24P, 25P, and 26P and the substrate 11, arcing phenomena that may occur due to plasma-induced damage can be prevented.

[0090] refer to Figure 3G A first peripheral interlayer dielectric layer 30 can be formed on a substrate 11 including a second region R2 of a dummy gate structure PG.

[0091] Subsequently, a cell opening mask 31 for opening the first region R1 can be formed on the first peripheral interlayer dielectric layer 30.

[0092] Subsequently, a bit line structure BL can be formed on the substrate 11 of the first region R1.

[0093] Bit line contact 24C can electrically connect bit line structure BL to substrate 11. Bit line structure BL may include bit lines 25C, 26C and 27C, and a bit line hard mask 32 located above bit lines 25C, 26C and 27C. A portion of bit lines 25C, 26C and 27C may be coupled to bit line contact 24C.

[0094] Subsequently, bit line spacers 33 can be formed on the sidewalls of bit line contact 24C and bit line structure BL. Bit line spacers 33 can extend from the sidewalls of bit line structure BL to bit line contact 24C.

[0095] Bit line spacer 33 may include a single-layer structure or a multi-layer structure. Bit line spacer 33 may include a dielectric material. Bit line spacer 33 may include at least one of silicon oxide, silicon nitride, and low-k materials, or a combination thereof.

[0096] Subsequently, memory node contacts 34 can be formed between adjacent bit line structures BL. Memory node contacts 34 can be coupled to the second impurity region 19.

[0097] refer to Figure 3H A second peripheral interlayer dielectric layer 31 can be formed on the first peripheral interlayer dielectric layer 30, which includes the dummy gate structure PG.

[0098] Subsequently, a first peripheral metal interconnect contact 35 can be formed that penetrates the second peripheral interlayer dielectric layer 31 and the dummy gate hard mask 28P.

[0099] Subsequently, a first unit interlayer dielectric layer 36 and a third peripheral interlayer dielectric layer 36P can be formed on the bit line structure BL including the storage node contact 34 in the first region R1 and on the second peripheral interlayer dielectric layer 31 in the second region R2, respectively.

[0100] Subsequently, a landing pad 37C can be formed that penetrates the first unit interlayer dielectric layer 36 and overlaps with at least a portion of the memory node contact 34. Simultaneously, a first peripheral metal interconnect 37P can be formed that penetrates the third peripheral interlayer dielectric layer 36P and contacts the first peripheral metal interconnect contact 35.

[0101] Subsequently, a capacitor CAP can be formed that contacts the landing pad 37C of the first region R1. The capacitor CAP may include a stacked structure of a lower electrode 38, a dielectric layer 39, and an upper electrode 40.

[0102] Subsequently, an etch stop layer 41 and a second unit interlayer dielectric layer 42 can be sequentially formed on the capacitor CAP in the first region R1. Here, a fourth peripheral interlayer dielectric layer 45 can be formed on the third interlayer dielectric layer 36P in the second region R2.

[0103] Subsequently, the unit metal interconnect contact 43 can be formed to be electrically connected to the capacitor CAP through the second unit interlayer dielectric layer 42 and the etch stop layer 41. Here, the second peripheral metal interconnect contact 46 can be formed to be coupled to the first peripheral metal interconnect 37P through the fourth peripheral interlayer dielectric layer 45 through the second region R2.

[0104] Subsequently, a unit metal interconnect 44 can be formed on the second unit interlayer dielectric layer 42 to contact the unit metal interconnect contact 43. Here, a second peripheral metal interconnect 47 can be formed on the fourth peripheral interlayer dielectric layer 45 of the second region R2 to couple to the second peripheral metal interconnect contact 46.

[0105] According to embodiments of this disclosure, by forming a path for releasing plasma-induced electrons into the substrate, defects that may be caused by plasma-induced damage can be prevented.

[0106] Although this disclosure has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of this disclosure as defined in the appended claims.

Claims

1. A semiconductor device, comprising: A dummy gate structure includes a dummy gate dielectric layer and a dummy gate electrode, wherein the dummy gate dielectric layer and the dummy gate electrode are disposed on a scribe region of a substrate; A first contact extends through the dummy gate dielectric layer to connect the dummy gate electrode to the substrate; An interlayer dielectric layer is disposed on the dummy gate structure; Metal interconnects are disposed on the interlayer dielectric layer; as well as The second contact extends through the interlayer dielectric layer to electrically connect the gate electrode to the metal interconnect.

2. The semiconductor device according to claim 1, wherein, The bottom surface of the first contact is positioned at a level lower than the top surface of the substrate.

3. The semiconductor device according to claim 1, wherein, The first contact has a width that narrows as it approaches the substrate.

4. The semiconductor device according to claim 1, wherein, The first contact comprises polycrystalline silicon.

5. The semiconductor device according to claim 1, wherein, The second contact element comprises a metallic material.

6. A semiconductor device, comprising: The substrate includes memory cell regions and scribe lines; Bit line structure, which includes bit line contacts disposed above the memory cell region; A dummy gate structure includes a dummy gate dielectric layer and a dummy gate electrode disposed above the scribe region. A first contact extends through the dummy gate dielectric layer to connect the dummy gate electrode to the substrate; An outer interlayer dielectric layer is disposed on the dummy gate structure; Peripheral metal interconnects are disposed above the peripheral interlayer dielectric layer; and The second contact extends through the peripheral interlayer dielectric layer to electrically connect the dummy gate electrode to the peripheral metal interconnect.

7. The semiconductor device according to claim 6, wherein, The bit line contact and the first contact are positioned at the same horizontal level.

8. The semiconductor device according to claim 6, wherein, The bottom surface of the first contact is positioned at a level lower than the top surface of the substrate.

9. The semiconductor device according to claim 6, wherein, The first contact comprises polycrystalline silicon.

10. The semiconductor device according to claim 6, wherein, The second contact element comprises a metallic material.

11. The semiconductor device according to claim 6, further comprising: A buried gate structure is disposed within the storage cell area; A storage element disposed on the bit line structure of the storage cell region; as well as Cell metal interconnects are disposed on the storage element.

12. A method for manufacturing a semiconductor device, the method comprising: A first dielectric material layer is formed on the scribe region of the substrate; A second dielectric material layer is formed on the memory cell region of the substrate and on the first dielectric material layer in the scribe region; The second dielectric material layer of the memory cell region and the first dielectric material layer and the second dielectric material layer of the scribe region are etched to form contact holes; as well as The contact holes are filled with conductive material gaps to form bit line contacts in the memory cell region and dummy contacts in the scribing region.

13. The method of claim 12, further comprising: A bit line structure is formed on the bit line contact member; A capacitor is formed on the bit line structure; as well as A unit metal interconnect is formed on the capacitor.

14. The method of claim 12, further comprising: A dummy gate structure including a dummy gate electrode is formed on the dummy contact; as well as A peripheral metal interconnect coupled to the dummy gate electrode is formed on the dummy gate structure.

15. The method according to claim 12, wherein, The bit line contact and the dummy contact are formed simultaneously using the same process.

16. The method according to claim 12, wherein, The conductive material includes polycrystalline silicon.

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