Semiconductor device and method of forming the same

Abstract

Deep trench capacitors (DTCs) are formed in a wafer having notches. The notches are formed to point in a third direction between a first direction and a second direction of a lattice grid of semiconductor material at a surface of the wafer. The DTCs are formed in different regions of the wafer. The DTCs in adjacent regions have longitudinal axes that are perpendicular to each other, which reduces warpage of the wafer. Interconnect structures are formed over the DTCs, and the wafer is cut along the notch direction to create independent semiconductor devices. The disclosed semiconductor devices have improved substrate strength, reduced stress, and higher capacitance for the DTCs. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. To a large extent, this improvement in integration density comes from the iterative reduction in the size of the smallest component, which allows more components to be integrated into a given area.

[0003] With the growing demand for miniaturized electronic devices, there is a need for smaller and more innovative packaging technologies for semiconductor dies. One example of such packaging technology is PoP (PoS) packaging. In a PoP semiconductor package, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. As another example, a multilayer semiconductor package (e.g., a chip-on-a-substrate (CoWoS) package) is formed by attaching one or more semiconductor chips to a wafer (e.g., an interposer) to form a first semiconductor structure; and then attaching the first semiconductor structure to a substrate (e.g., a printed circuit board). These and other advanced packaging technologies enable the production of semiconductor devices with enhanced functionality and small coverage areas. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device comprising: a substrate comprising a semiconductor material, wherein a lattice of the semiconductor material at a main upper surface of the substrate extends along a first direction and a second direction perpendicular to the first direction, wherein, in a top view, the sidewalls of the semiconductor device extend along a third direction different from the first direction and the second direction; a deep trench capacitor embedded in the substrate; and an interconnect structure located above the main upper surface of the substrate, wherein the interconnect structure is electrically coupled to the deep trench capacitor.

[0005] Other embodiments of this application provide a semiconductor device comprising: a substrate comprising a semiconductor material having a lattice structure, wherein the lattice grid orientation of the semiconductor material at a main upper surface of the substrate includes a first direction and a second direction perpendicular to the first direction, wherein, in a top view, the sidewalls of the semiconductor device extend along a third direction between the first direction and the second direction; a deep trench capacitor embedded in the substrate, wherein the deep trench capacitor comprises a first plurality of deep trench capacitors embedded in a first region of the substrate, wherein, in the top view, a first longitudinal axis of the first plurality of deep trench capacitors extends along a fourth direction different from the first direction and the second direction; and an interconnect structure located above the main upper surface of the substrate, wherein the interconnect structure is electrically coupled to the deep trench capacitor.

[0006] Further embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a deep trench capacitor in a wafer having slots, wherein the wafer is formed of a semiconductor material, wherein a lattice of the semiconductor material at the surface of the wafer extends along a first direction and a second direction perpendicular to the first direction; forming an interconnect structure electrically coupled to a corresponding deep trench capacitor over the wafer, wherein each of the interconnect structures is formed to include a plurality of dielectric layers and conductive components located in the plurality of dielectric layers; and after forming the interconnect structure, dicing the wafer along a third direction and a fourth direction perpendicular to the third direction to form a plurality of semiconductor devices, wherein the third direction and the fourth direction are different from the first direction and the second direction. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A three-dimensional (3D) view of a semiconductor ingot for semiconductor manufacturing according to an embodiment is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9 and Figure 10Various views of a semiconductor device according to an embodiment are shown at various manufacturing stages.

[0010] Figure 11 A cross-sectional view of a semiconductor device according to another embodiment is shown.

[0011] Figure 12 , Figure 13 , Figure 14 and Figure 15 Various views of a semiconductor device according to another embodiment are shown.

[0012] Figure 16 A cross-sectional view of a semiconductor device according to yet another embodiment is shown.

[0013] Figure 17 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0014] Figure 18 A flowchart of a method for forming a semiconductor device is shown in some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. Throughout the description, unless otherwise stated, the same reference numerals in different figures refer to the same or similar components formed using the same or similar materials by the same or similar forming methods. In the discussion herein, figures having the same reference numerals but different letters (e.g., Figure 7A , Figure 7B and Figure 7C (This shows different views of the same device at the same processing stage.)

[0016] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] In some embodiments, the location of the wafer notch is chosen such that, in a top view, the notch direction lies between a first direction and a second direction, wherein the first and second directions are the directions of the grid lines of the semiconductor material's lattice at the wafer surface. In some embodiments, deep trench capacitors (DTCs) are formed in different regions of the wafer, wherein the longitudinal axis of DTCs formed in the same region extends parallel to the first or second direction, and the longitudinal axes of DTCs formed in different, adjacent regions extend perpendicularly to each other to reduce warpage. Interconnect structures electrically coupled to the DTCs are formed over the DTCs and the wafer. A dicing process is then performed along the notch direction and in a direction perpendicular to the notch direction, thereby separating multiple semiconductor devices formed on the wafer into independent semiconductor devices. The disclosed semiconductor devices have improved substrate strength, reduced stress, and higher capacitance for the DTCs.

[0018] Figure 1 A semiconductor ingot 11 (also referred to as ingot 11) is shown as a starting material for wafer production in semiconductor manufacturing. Ingot 11 is formed from a semiconductor material (e.g., silicon, germanium, etc.) having a lattice structure that defines the basic arrangement of atoms within the semiconductor material. Ingot 11 typically has a cylindrical shape that exposes the principal facet of the underlying crystal structure of the semiconductor material. Ingot 11 is then sliced ​​to form a wafer, and thus the principal facet of ingot 11 becomes the principal surface of the formed wafer. Semiconductor devices are then formed on the wafer.

[0019] In the illustrated embodiment, the semiconductor material (e.g., silicon) at the main surface of the ingot 11 exhibits a lattice grid pattern 18 (also referred to as lattice grid 18) including grid lines 17 and 19. The ingot 11 includes a notch 13 formed along the edge of the ingot 11 to provide an orientation reference during subsequent processing steps (e.g., dicing).

[0020] exist Figure 1 In this example, slot 13 extends along direction 15, which is positioned between (for example, in the middle) the direction along grid line 17 (also referred to as the direction of grid line 17) and the direction along grid line 19 (also referred to as the direction of grid line 19). Direction 15 may also be referred to as the direction of the slot, the slot orientation, or the direction the slot points to. See below for reference. Figure 2Further details are discussed regarding the notch orientation 15. In an embodiment, the notch orientation 15 forms an angle α with the direction of the grid line 17, wherein the angle α is greater than zero degrees and less than or equal to 45 degrees (e.g., 0 degrees < α ≤ 45 degrees). In an exemplary embodiment, the angle α is approximately 45 degrees. In the discussion herein, when the terms “approximately” or “substantially” are used to describe a value (e.g., approximately 45 degrees), it means that the described value is at or near a nominal value (e.g., 45 degrees) and may deviate from the nominal value by a small percentage, such as 10%, 5%, 3%, or less. As will be readily understood by those skilled in the art, deviations from the nominal value may be due to, for example, manufacturing process limitations. The angular relationship described above between the notch orientation 15 and the direction of the grid line 17 (or 19) of the lattice grid 18 (e.g., approximately 45 degrees) advantageously improves wafer strength and reduces stress in semiconductor devices (e.g., 100, 100A, 100B, and 100C) subsequently formed after the dicing process. Details are discussed below. In some embodiments, non-zero values ​​of angle α within the range of 0 degrees and 45 degrees provide benefits such as improved wafer strength; however, angle α with a value of 45 degrees achieves better wafer strength than other angle values ​​within that range. Therefore, angle α with a value of 45 degrees is used as an example in the discussion herein, and it should be understood that angle α can have other values ​​between 0 degrees and 45 degrees, such as 10 degrees, 25 degrees, 30 degrees, etc.

[0021] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9 and Figure 10 Various views (e.g., top view, cross-sectional view) of the semiconductor device 100 according to an embodiment are shown at various manufacturing stages. In the illustrated embodiment, the semiconductor device 100 is a local silicon interposer (LSI) with embedded deep trench capacitors (DTC), and therefore, the semiconductor device 100 may also be referred to as interposer 100. Interposer 100 can be used to form semiconductor packages, such as... Figure 17 Semiconductor package 500.

[0022] Figure 2 A top view of wafer 101 is shown, which is constructed by... Figure 1 The wafer is formed by slicing the crystal rod 11 in the middle. Figure 2 A lattice grid 18 at the wafer surface is also shown. The lattice grid 18 is shown as being composed of... Figure 2Grid lines 17 and 19 are formed in the lattice. A lattice grid 18 defines a regular (e.g., repeating) array of atomic positions, with semiconductor atoms 21 (e.g., silicon atoms) located at the intersections of grid lines 17 and 19. Atomic bonds extend between adjacent semiconductor atoms 21 to link adjacent atoms in the lattice structure. For simplicity, in this discussion, the reference numerals for grid lines 17 and 19 are also used to indicate the directions in which grid lines 17 and 19 extend. Therefore, the lattice grid 18 is also referred to as extending along direction 17 and in direction 19 perpendicular to direction 17.

[0023] also, Figure 2 A notch 13 and notch orientation 15 at the edge of wafer 101 are shown. The notch orientation 15 can be defined as a direction from an inner vertex 13A of the notch 13 towards the center of wafer 101, where inner vertex 13A is one of the three vertices of the notch 13 (e.g., 13A, 13B, and 13C) that is not located on the edge of wafer 101. The notch orientation 15 can also be defined along a first line perpendicular to a second line connecting the two outer vertices 13B and 13C of the notch 13 (e.g., vertices located on the edge of wafer 101) and passing through the inner vertex 13A of the notch 13. Figure 2 As shown, the slot direction 15 forms an angle α (e.g., 45 degrees) with the direction 17 of the lattice grid 18.

[0024] Figure 2 The boundaries (e.g., sidewalls) of the plurality of semiconductor devices 100 subsequently formed on wafer 101 are also shown in dashed lines. Figure 2 In one example, the semiconductor device 100 has rectangular (or square) boundaries in a top view and is formed on wafer 101 in an array, such as by row and column alignment. In subsequent processing, after the semiconductor device 100 is formed on wafer 101, a dicing process is performed along dicing region 25 to separate the semiconductor device 100 into individual (e.g., separate) semiconductor devices 100. Dicing region 25 is... Figure 2 The diagram shows a dashed line along the boundary of the semiconductor device 100. It should be noted that the cut region 25 extends in two perpendicular directions, one of which is the notch direction 15.

[0025] In this embodiment, the crystal planes at the main face of the ingot 11 are formed along the <110> direction. By moving the position of the notch 13 such that the notch direction 15 forms a 45-degree angle with the direction 17 (or direction 19) of the lattice grid at the <110> crystal plane, the wafer 101 achieves improved strength. Without the currently disclosed method, to achieve the same wafer strength for a wafer with notches having a notch direction along one of the lattice grid directions (e.g., 17 or 19), the main face of the ingot 11 might have to be formed along the <100> direction. However, forming an ingot 11 with <100> crystal planes at its main face is more expensive than forming an ingot 111 with <110> crystal planes at its main face. Therefore, the currently disclosed method achieves improved wafer strength at a lower cost.

[0026] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9 and Figure 10 Various views (e.g., top view, cross-sectional view) of the semiconductor device 100 during subsequent manufacturing stages are shown. For simplicity, only a portion of one of the plurality of semiconductor devices 100 formed on wafer 101 is shown in the figures. The cross-sectional view of the semiconductor device 100 is a section passing through the longitudinal axis of the DTC, which extends along direction 17 (or 19) of the lattice grid 18.

[0027] exist Figure 3 An opening 102 is formed in a wafer 101 (also referred to as substrate 101). The opening 102 extends from the upper surface 101U of the wafer 101 into the wafer 101. The opening 102 exposes the sidewalls 101S and surfaces 101B of the wafer 101. The opening 102 can be formed using photolithography and etching techniques known and used in semiconductor manufacturing, and therefore details are not discussed here. In the illustrated embodiment, the opening 102 is formed having a longitudinal axis extending in a direction 17 or 19 along the lattice grid 18 in a top view (see example...). Figure 7B (102L in the middle). Figure 3 A cross-sectional view of opening 102 along its longitudinal axis is shown. In subsequent processing, a deep trench capacitor (DTC) 106 is formed in opening 102, and thus, DTC 106 also has a longitudinal axis extending along direction 17 or 19 of the lattice grid 18 (see, for example, 106L). More details are discussed below.

[0028] Next, (e.g., conformally) a pad layer 103 is formed to line the sidewalls 101S, surface 101B, and top surface 101U of the wafer 101. In some embodiments, the pad layer 103 is formed of a dielectric material (e.g., silicon oxide) by a suitable formation method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or combinations thereof. In embodiments, the pad layer 103 is an oxide (e.g., silicon oxide) of the material (e.g., silicon) of the wafer 101 formed by an oxidation process (e.g., a thermal oxidation process). The oxidation process transforms the outer portions (e.g., exposed portions) of the wafer 101 into the pad layer 103. It should be noted that in Figure 3 In one example, the horizontal portion of the gasket layer 103 (e.g., the portion along the upper surface 101U and surface 101B of wafer 101) has a thickness T2, and the vertical portion of the gasket layer 103 (e.g., the portion along the sidewall 101S of wafer 101) has a thickness T1 greater than the thickness T2. As an example, the ratio between thickness T1 and thickness T2 can be between about 1.5 and about 2.0. The greater thickness T1 reduces the width of the opening 102 and helps to form a low-stress sealing structure for DTC 106 (see example...). Figure 8A (108 in the text), details are discussed below.

[0029] In some embodiments, the greater thickness T1 of the pad layer 103 is due to the higher atomic density (e.g., silicon atoms) at the sidewalls 101S of the wafer 101, and therefore, the oxidation process used to form the pad layer 103 causes more oxide of the material of the wafer 101 to form along the sidewalls 101S of the wafer 101. It should be noted that the higher atomic density (e.g., silicon atoms) along the sidewalls 101S of the wafer 101 is due to the formation of more oxides of the material along the sidewalls 101S of the wafer 101. Figure 2 The result is an opening 102 extending along the longitudinal axis of the lattice mesh 18 in direction 17 or 19. In other words, if the longitudinal axis of the opening 102 is not along direction 17 or 19, but along, for example, the slot direction 15 (or a direction perpendicular to the slot direction 15), the thicknesses T1 and T2 can be substantially the same (see, for example...). Figure 15 (and its discussion).

[0030] Next step, in Figure 4In this process, conductive layers 105 (e.g., 105A, 105B, and 105C) and dielectric layers 107 (e.g., 107A, 107B, and 107C) are formed to line the upper surface of wafer 101 and to line the sidewalls and bottom of opening 102. The conductive layers 105 are formed interleaved with the dielectric layers 107, wherein conductive layers 105A contact the pad layer 103 and extend along the pad layer 103. In the illustrated embodiment, each conductive layer 105 has a corresponding dielectric layer 107 formed thereon. In some embodiments, the conductive layers 105 are formed of a conductive material, such as polycrystalline silicon or a metallic material (e.g., copper), and the dielectric layers 107 are formed of a suitable dielectric material, such as a high-k dielectric material. Suitable formation methods for forming the conductive layers 105 and dielectric layers 107 include physical vapor deposition (PVD), CVD, ALD, combinations thereof, etc. Figure 4 Three conductive layers 105 and three dielectric layers 107 are shown as a non-limiting example. As will be readily understood by those skilled in the art, the number of conductive layers 105 and the number of dielectric layers 107 can be any suitable number.

[0031] Next step, in Figure 5 In this process, the dielectric layer 107 and the conductive layer 105 are patterned, for example, by using multiple anisotropic etching processes performed using multiple etch masks that expose different portions of the dielectric layer 107 and the conductive layer 105. The multiple anisotropic etching processes can be controlled (e.g., timed) to achieve different etching depths, such that after the multiple anisotropic etching processes are completed, the remaining portions of the dielectric layer 107 and the remaining portions of the conductive layer 105 have a stepped cross-section.

[0032] exist Figure 5 In this structure, the remaining portions of dielectric layer 107 and conductive layer 105 form DTC 106. The remaining portions of conductive layers 105C, 105B, and 105A can be referred to as the top electrode 105C (or top plate), middle electrode 105B (or middle plate), and bottom electrode 105A (or bottom plate) of DTC 106, respectively. The top electrode 105C, middle electrode 105B, and bottom electrode 105A can be collectively referred to as electrode 105. The remaining portions of dielectric layers 107C, 107B, and 107A can be referred to as the top dielectric layer 107C, middle dielectric layer 107B, and bottom dielectric layer 107A of DTC 106, respectively. The top dielectric layer 107C, middle dielectric layer 107B, and bottom dielectric layer 107A can be collectively referred to as dielectric layer 107.

[0033] Next step, in Figure 6 In this process, a gap-filling material 109 is formed in the opening 102 and above the dielectric layer 107C. In some embodiments, the gap-filling material 109 is a dielectric material, such as silicon oxide, and is formed by a suitable formation method, such as CVD. Figure 6In this example, an air gap 110 is formed in the portion of the gap filler material 109 disposed in the opening 102. In some embodiments, the large thickness T1 of the sidewall portion of the padding layer 103 reduces the width of the opening 102 and makes it more difficult for the gap filler material 109 to fill the opening 102, thus promoting the formation of the air gap 110. Although one air gap 110 is shown, more than one air gap 110 may be formed in the gap filler material 109.

[0034] Next step, in Figure 7A In the next step, the portion of the gap filler material 109 disposed outside the opening 102 is removed. For example, a planarization process such as chemical mechanical planarization (CM) is performed to remove a portion of the gap filler material 109 from the upper surface of the dielectric layer 107C. Next, a patterned mask layer is formed to cover the portion of the gap filler material 109 located inside the opening 102, and to expose the remaining portion of the gap filler material 109. Next, one or more etching processes are performed to selectively remove the exposed portions of the gap filler material 109. The patterned mask layer is then removed by a suitable removal process, thus leaving a portion of the gap filler material 109 in the opening 102, such as... Figure 7A As shown in the diagram. In addition to the processing steps described above, any other suitable processing steps may be used to remove the portion of the gap filler material 109 located outside the opening 102 and to retain a portion of the gap filler material 109 within the opening 102.

[0035] exist Figure 7A In this configuration, the remaining portion of the gap-filling material 109, together with the air gap 110, forms a sealing structure 108 for the DTC 106. In some embodiments, the sealing structure 108 can be considered part of the DTC 106. In some embodiments, the air gap 110 in the gap-filling material 109 helps reduce stress in the sealing structure 108, which in turn helps prevent or reduce the occurrence of peeling or delamination of material layers (e.g., 107 and 105) in the DTC 106. Therefore, the sealing structure 108 can also be referred to as a low-stress sealing structure 108.

[0036] exist Figure 7AIn this example, the top dielectric layer 107C and the top electrode 105C have the same width, such that the sidewalls of the top dielectric layer 107C are perpendicularly aligned with the corresponding sidewalls of the top electrode 105C. Similarly, the intermediate dielectric layer 107B and the intermediate electrode 105B have the same width, such that the sidewalls of the intermediate dielectric layer 107B are perpendicularly aligned with the corresponding sidewalls of the intermediate electrode 105B. Furthermore, the bottom dielectric layer 107A and the bottom electrode 105A have the same width, such that the sidewalls of the bottom dielectric layer 107A are perpendicularly aligned with the corresponding sidewalls of the bottom electrode 105A. It should be noted that the intermediate dielectric layer 107B and the intermediate electrode 105B extend laterally from the sealing structure 108 further than the top dielectric layer 107C and the top electrode 105C. Similarly, the bottom dielectric layer 107A and the bottom electrode 105A extend laterally from the sealing structure 108 further than the intermediate dielectric layer 107B and the intermediate electrode 105B.

[0037] Figure 7B It shows Figure 7A A top view of the structure. Figure 7B In the diagram, the sidewall of opening 102 (which is also the sidewall 101S of wafer 101 exposed by opening 102) is shown in dashed lines. Figure 7B The sidewalls of the top dielectric layer 107C, the middle dielectric layer 107B, and the bottom dielectric layer 107A are also shown. The middle dielectric layer 107B extends further from the sealing structure 108 along the longitudinal axis 106L of the DTC 106 than the top dielectric layer 107C, and the bottom dielectric layer 107A extends further from the sealing structure 108 along the longitudinal axis 106L than the middle dielectric layer 107B. Figure 7B In this embodiment, the longitudinal axis 106L of DTC 106 is the same as the longitudinal axis 102L of opening 102. In some embodiments, the first dimension W1 of opening 102 (measured along the longitudinal axis 102L between opposite sidewalls of opening 102) is between about 3 µm and about 4 µm. The second dimension W2 of opening 102 (measured along a direction perpendicular to the longitudinal axis 102L between opposite sidewalls of opening 102) is between about 0.1 µm and about 0.4 µm.

[0038] Figure 7C A top view of wafer 101 after DTC 106 has been formed is shown. It should be noted that, although... Figure 7A and Figure 7B Only a portion of wafer 101 with DTC 106 formed is shown, but Figure 7C A complete wafer 101 with tens, hundreds, thousands or more DTC 106 is shown. Figure 7C In the diagram, each DTC 106 is shown as a line extending along the vertical axis 106L of the DTC 106. Figure 7CThe notch orientation 15 of wafer 101 and the orientations 17 and 19 of the lattice grid 18 are also shown. For simplicity, Figure 7C (And other subsequent top views) only show the boundary of one of the semiconductor devices 100 formed on wafer 101 in dashed lines, and omit the boundaries of other semiconductor devices. Figure 2 The cut area 25 in the text should be understood. Figure 7C The boundaries of the semiconductor device 100 and the cut region 25 in (and other subsequent top views) are... Figure 2 The same as those shown.

[0039] like Figure 7C As shown, DTC 106 is formed in different regions 23 (e.g., 23A and 23B) of wafer 101. Within each region 23, a plurality of parallel-extending DTCs 106 are formed, for example, extending along direction 17 or direction 19 of the lattice grid 18 at the surface of wafer 101. It should be noted that the longitudinal axes of the DTCs 106 in two adjacent regions (e.g., 23A and 23B) extend perpendicularly to each other. For example, the longitudinal axis of the DTC 106 in region 23A extends along direction 17, and the longitudinal axis of the DTC 106 in region 23B extends along direction 19. By alternating the orientation of the longitudinal axes of the DTCs 106 in adjacent regions 23, the warpage of wafer 101 is advantageously reduced. Furthermore, as discussed above, by aligning the longitudinal axis 106L of the DTC 106 along the directions of the lattice grid 18 (e.g., 17 and 19), a low-stress sealing structure 108 for the DTC 106 is formed, which helps to reduce stress in the DTC 106 and prevent delamination of the material layers of the DTC 106.

[0040] Next step, in Figure 8A In this process, a dielectric layer 111 is formed over DTC 106 and wafer 101. The dielectric layer 111 can be formed from a suitable dielectric material such as silicon oxide, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, or a combination of these materials, and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). A planarization process, such as CMP, can be performed next to achieve a flush top surface of the dielectric layer 111.

[0041] Next, vias 115 (e.g., 115A, 115B, and 115C) are formed in the dielectric layer 111 to connect to the electrodes 105 of the DTC 106. The vias 115 may also be referred to as electrode contacts 115 of the DTC 106. In some embodiments, each electrode contact 115 extends through a corresponding dielectric layer 107 to connect to the corresponding underlying electrode 105. Figure 8AIn this example, vias 115C, 115B, and 115A extend through the top dielectric layer 107C, the middle dielectric layer 107B, and the bottom dielectric layer 107A, respectively, to connect to the top electrode 105C, the middle electrode 105B, and the bottom electrode 105A. Electrode contacts 115C and 115A are connected together via subsequently formed wires 117, details of which are discussed below.

[0042] The via 115 can be formed by: forming a via opening in the dielectric layer 111 to expose the underlying electrode 105; and filling the via opening with a conductive material (e.g., copper, tungsten, cobalt, etc.). Before filling the via opening with the conductive material, a barrier layer, such as titanium, titanium nitride, tantalum, tantalum nitride, etc., can be formed along the sidewalls of the via opening. Methods for forming vias are known and used in industry, and therefore details are not discussed here.

[0043] Figure 8A A via 113 is also shown extending from the upper surface of dielectric layer 111 through pad layer 103 and into wafer 101. At this stage of processing, via 113 does not extend through wafer 101. Via 113 may be wider than electrode contact 115. In a subsequent process, after a thinning process, via 113 extends through (thinned) wafer 101 and is exposed at the lower surface of wafer 101. In some embodiments, approximately 60% to approximately 90% of the surface area of ​​wafer 101 is used to form DTC 106, and the remaining surface area of ​​wafer 101 is used to form via 113.

[0044] Next, an etch stop layer (ESL) 119 and a dielectric layer 121 are sequentially formed over the dielectric layer 111. The ESL 119 can be formed from silicon nitride using PECVD, but alternatively, other dielectric materials such as silicon nitride, silicon carbide, combinations thereof, etc., and alternative techniques for forming the ESL 119, such as low-voltage CVD (LPCVD), ALD, etc., can be used. The dielectric layer 121 can be formed from any suitable dielectric material different from that of the ESL 119, such as silicon oxide, silicon nitride, low-k dielectric materials, etc. Suitable formation methods (such as CVD, PECVD, ALD, combinations thereof, etc.) can be used to form the dielectric layer 121. Figure 8A The dielectric layer 121 in the figure can also be referred to as the M1 layer. In some embodiments, the ESL 119 has a higher dielectric constant than the dielectric layer 121.

[0045] Next step, such as Figure 8AAs shown, conductive components 117 are formed in ESL 119 and dielectric layer 121 using, for example, a damascene process or a double damascene process. In the illustrated embodiment, conductive components 117 are wires, and therefore, conductive components 117 can also be referred to as wires 117. In some embodiments, each wire 117 includes a diffusion barrier and a filler metal formed over the diffusion barrier. The diffusion barrier (also referred to as a barrier layer) can be, for example, Ta, Ti, TaN, TiN, etc. The filler metal can be, for example, Cu, Co, Ru, Mo, etc. In some embodiments, the diffusion barrier separates the filler metal from dielectric layer 121 and ESL 119 and has a lower conductivity than the filler metal. In some embodiments, the wire 117 is along... Figure 8A The wires extend horizontally, and at least some of the wires 117 have different lengths. In some embodiments, the wires 117 include a first group of wires having a first spacing between first groups of wires, and a second group of wires having a second spacing between second groups of wires, wherein the first spacing is different from the second spacing.

[0046] exist Figure 8A In the example, electrode contacts 115C and 115A of DTC 106 are connected together via wire 117. Electrode contact 115B is connected to another wire 117. Using this electrical connection, DTC 106 is functionally equivalent to a first capacitor coupled in parallel with a second capacitor, wherein the first capacitor is formed by a bottom electrode 105A, an intermediate electrode 105B, and a bottom dielectric layer 107A disposed in the middle, and the second capacitor is formed by an intermediate electrode 105B, a top electrode 105C, and an intermediate dielectric layer 107B disposed in the middle. Therefore, the capacitance of DTC 106 is equivalent to the sum of the capacitances of the first and second capacitors. The disclosed structure for DTC 106 achieves higher capacitance by forming multiple electrode layers 105 interleaved with multiple dielectric layers 107. Although three electrode layers 105 and three dielectric layers 107 are shown in the figures, DTC 106 with even higher capacitance can be formed using more than three electrode layers 105 and more than three dielectric layers 107. These and other changes are entirely intended to be included within the scope of embodiments disclosed herein.

[0047] Figure 8B Wafer 101 is shown in Figure 8A A top view of the same processing stage. Figure 8B In this example, wire 117 extends along the direction 19 of the lattice grid. In other words, the vertical axis of wire 117 is aligned with the direction 19 of the lattice grid. Figure 8BIn one example, a conductive pattern 118 is formed in the M1 layer. The conductive pattern 118 is shown as a short segment of a wire perpendicular to and connected to a corresponding wire 117. In some embodiments, the conductive pattern 118 (e.g., a conductive pad) is used to accommodate... Figure 8A The connection of electrode contacts 115 in the M1 layer. It should be noted that, in the top view, the conductor 117 in the M1 layer forms an angle α of 45 degrees with respect to the slot direction 15. In other words, in the top view, similar to DTC 106, the longitudinal axis of conductor 117 is rotated relative to the slot direction 15 and forms an angle α with a nominal value of 45 degrees with respect to the slot direction 15. By rotating conductor 117 relative to the slot direction 15, greater wiring flexibility and easier connection to electrode contacts 115 are achieved, which helps to reduce the interconnect structure formed above DTC 106 (see...). Figure 9 The resistor is 120.

[0048] Next step, in Figure 9 In this configuration, an additional dielectric layer 121 is formed above the M1 layer, and vias 115 and conductors 117 are formed in alternating layers of the additional dielectric layer 121. The additional dielectric layer 121 in which the conductors 117 are formed is referred to as the M2 layer, M3 layer, etc., and the additional dielectric layer 121 in which the vias 115 are formed is referred to as the V1 layer, V2 layer, etc., wherein the dielectric layer 121 furthest from wafer 101 has a larger designation. Dielectric layers 111 and 121, vias 115, and conductors 117 are collectively referred to as interconnect structure 120 (also referred to as front-side interconnect structure 120). Interconnect structure 120 is electrically coupled to a DTC 106 and vias 113 embedded in wafer 101. In some embodiments, for each semiconductor device 100 formed above wafer 101, interconnect structure 120 is formed above the DTC 106 formed within the semiconductor device 100.

[0049] For simplicity, Figure 9 Only the ESL 119 formed below the M1 layer is shown. It should be understood that a corresponding ESL that is the same as or similar to ESL 119 can be formed below each additional dielectric layer 121 formed above the M1 layer. Figure 9 The number of dielectric layers 121 in the interconnect structure 120 shown is illustrative and not limiting, and any other suitable number may be used for the interconnect structure 120.

[0050] like Figure 9As shown, each conductor 117 in the interconnect structure 120 is embedded in a corresponding dielectric layer 121. The conductors 117 in different dielectric layers 121 are separated by at least one intermediate dielectric layer 121 and electrically coupled together by vias 115 formed at least in the intermediate dielectric layer 121. In some embodiments, alternating layers of conductors 117 in the interconnect structure 120 extend in different (e.g., orthogonal) directions. For example, the conductors 117 in layer M1 may extend along… Figure 9 Extending horizontally, while wires 117 in layer M2 can extend in and out. Figure 9 In some embodiments, the dielectric layers 121 in the interconnect structure 120 have different thicknesses. For example, the higher dielectric layer 121 (e.g., farther from wafer 101) may have a greater thickness than the lower dielectric layer 121 (e.g., closer to wafer 101). In some embodiments, the wires 117 embedded in the dielectric layers 121 of the interconnect structure 120 have different thicknesses. For example, the wires 117 in the higher dielectric layer 121 may have a greater thickness than the wires 117 in the lower dielectric layer 121.

[0051] In some embodiments, the interconnect structure 120 is formed using back-end processes (BEOL) in semiconductor manufacturing, and therefore can be formed using advanced processing nodes, such as 7 nm nodes, 3 nm nodes, etc. This allows for very small critical dimensions (CD) (e.g., minimum linewidth) of components formed in the interconnect structure 120, thus enabling high-density interconnects using the interconnect structure 120. See below for reference. Figure 17 As discussed, semiconductor device 100 (e.g., LSI chip) is used to form an interposer layer 300 that allows for high-density interconnections between two semiconductor chips 401 and 403. Such high-density interconnections would likely not be achievable by using only redistribution structures (RDS) (see, for example, 306A), which have linewidths that are much higher (e.g., orders of magnitude higher) than the interconnect structure 120 of semiconductor device 100.

[0052] Next, a passivation layer 123 is formed over the interconnect structure 120. The passivation layer 123 can be formed from a suitable dielectric material, such as a polymer material (e.g., polyimide), silicon oxide, silicon nitride, etc., using a suitable formation method such as PVD, CVD, spin coating, etc. Next, a bump under-metallurgy (UBM) structure 125 electrically coupled to conductive components (e.g., wires) of the interconnect structure 120 is formed over the passivation layer 123. In an embodiment, the UBM structure 125 includes three conductive material layers, such as a titanium layer, a copper layer, and a nickel layer. However, many suitable arrangements of materials and layers exist for forming the UBM structure 125, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement. Any suitable material or material layer that can be used for the UBM structure 125 is fully intended to be included within the scope of embodiments of this disclosure.

[0053] Next, a connector 127 is formed on top of the UBM structure 125. The connector 127 can be a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-palladium immersion gold (ENEPIG) technology, or a combination thereof (e.g., a metal pillar with a solder ball attached thereto). The connector 127 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof.

[0054] Next, a back-side thinning process is performed on the back side of wafer 101, for example, using etching, polishing, CMP, or combinations thereof, to reduce the thickness of wafer 101 and expose vias 113 on the back side of wafer 101. Next, an interconnect structure 130 (also referred to as a back-side interconnect structure 130) electrically coupled to vias 113 is formed on the back side of wafer 101. The interconnect structure 130 includes a dielectric layer 131 and conductive components (e.g., vias 133 and wires 135) formed in the dielectric layer 131. Next, a passivation layer 137 is formed on the interconnect structure 130, and a UBM structure 139 electrically coupled to the conductive components of the interconnect structure 130 is formed on the interconnect structure 130. Then, an interconnect 141 is formed on the UBM structure 139. The materials and forming methods used for interconnect structure 130, passivation layer 137, UBM structure 139 and connector 141 may be the same as or similar to those discussed above for interconnect structure 120, passivation layer 123, UBM structure 125 and connector 127, and therefore details will not be repeated.

[0055] Depending on how semiconductor device 100 is used to form a semiconductor package, it can be omitted. Figure 9Some of the components shown are omitted. For example, some or all of the passivation layer 123, UBM structure 125, and connector 127 may be omitted. Similarly, some or all of the interconnect structure 130, passivation layer 137, UBM structure 139, and connector 141 may be omitted. These and other variations are fully intended to be included within the scope of embodiments of this disclosure.

[0056] Figure 10 A top view of the wafer 101 and wires 117 in the M2 layer of the interconnect structure 120 is shown. In some embodiments, Figure 10 Corresponding to along Figure 9 A cross-sectional view of the horizontal section through which the cut passes. Figure 10 In this example, wire 117 extends along the direction 17 of the lattice grid and forms an angle α with a nominal value of 45 degrees with the slot direction 15. It should be noted that... Figure 10 The conductor 117 in the middle is perpendicular to Figure 8B The wire 117 extends in the direction of (e.g., 19) of (e.g., 17).

[0057] In a reference design without the currently disclosed structure, one of the directions 17 and 19 of the lattice mesh 18 is aligned with the notch direction 15, the conductor 117 in layer M1 extends along one of directions 17 and 19, and the conductor 117 in layer M2 extends perpendicular to the conductor 117 in layer M1. One difference between the reference design and the currently disclosed design is that the lattice mesh 18 in the currently disclosed design is rotated 45 degrees relative to the notch direction 15. By maintaining the conductor 117 in layer M2 perpendicular to the conductor 117 in layer M1 in the currently disclosed design, the reference design can be easily reused in the currently disclosed design. Although Figure 10 The examples in the text allow for easy reuse of the reference design, but other considerations may lead to different choices for the wires 117 in the M2 layer. For example, if the semiconductor device 100 is used to replace a reference device in an existing semiconductor package (e.g., formed using a reference design), pin compatibility may be a consideration, in which case alternative designs for the wires 117 in the M2 layer may be used (see example...). Figure 14 It may be advantageous that the wires 117 in the M2 layer extend perpendicular to the slot direction 15, making it easier to form the connector 127 at the same location as the reference device that will be replaced by the semiconductor device 100.

[0058] After completion Figure 10 After processing in the middle, along the cutting area 25 (see Figure 2A dicing process is performed to separate multiple semiconductor devices 100 formed on wafer 101 into individual (e.g., independent) semiconductor devices 100. Each semiconductor device 100 includes a substrate 101 (e.g., a portion of wafer 101), multiple DTCs 106 and vias 113 embedded in the substrate 101, and an interconnect structure 120 located above the substrate 101. Additionally, the semiconductor device 100 may optionally include any of the following: a passivation layer 123, a UBM structure 125, an interconnect 127, a back-side interconnect structure 130, a passivation layer 137, a UBM structure 139, and an interconnect 141.

[0059] Figure 11 A cross-sectional view of a semiconductor device 100A according to another embodiment is shown. The semiconductor device 100A is similar to... Figure 9 The semiconductor device 100 is present, but no air gap 110 is formed in the gap filling material 109, and therefore, the remaining portion of the gap filling material 109 forms a sealing structure 109. Figure 11 In this example, semiconductor device 100A is formed using the same processing steps as semiconductor device 100, but the aspect ratio (e.g., the ratio of depth to width) of the opening 102 for semiconductor device 100A can be smaller than that of semiconductor device 100A. Figure 2 The aspect ratio of the opening 102 is such that the relatively shallow opening 102 is completely filled with the gap filler material 109, without any air gap 110. It should be noted that the ratio between the thickness T1 and the thickness T2 of the pad layer is the same as the ratio between the thickness T1 and the thickness T2 of the pad layer of the semiconductor device 100 (e.g., between about 1.5 and about 2.0).

[0060] Figure 12 , Figure 13 , Figure 14 and Figure 15 Various views (e.g., top view, cross-sectional view) of a semiconductor device 100B according to another embodiment are shown. The semiconductor device 100B can be formed using a similar forming method to that of the semiconductor device 100, but with some modifications. For simplicity, the discussion herein emphasizes some, but not all, aspects of the forming process for the semiconductor device 100B. Those skilled in the art will be able to readily modify the forming process of the semiconductor device 100A used to form the semiconductor device 100B after reading this disclosure.

[0061] To form semiconductor device 100B, the lattice grid 18 at the surface of wafer 101 is rotated by a nominal angle of 45 degrees relative to the notch direction 15, such that the notch direction 15 forms a 45-degree angle with the direction 17 (or 19) of the lattice grid 18. This process is the same as that of semiconductor device 100, and therefore, the top view of semiconductor device 100B showing the lattice grid 18 and the notch direction 15 is the same as that of semiconductor device 100B. Figure 2 Same. For simplicity, this top view of semiconductor device 100B will not be repeated.

[0062] Figure 12 A top view of wafer 101 with DTC 106 is shown. (Compared to...) Figure 7C different, Figure 12 The vertical axis of the DTC 106 extends along direction 17' and perpendicular to direction 17'. It should be noted that direction 19' is the same as (e.g., parallel to) the slot direction 15. Therefore, the vertical axis of the DTC 106 of the semiconductor device 100B extends either along or perpendicular to the slot direction 15. Similar to... Figure 7C DTC 106 formed in the same region (e.g., 23A or 23B) extends parallel to each other, but DTC 106 formed in different, adjacent regions (e.g., 23A and 23B) extends perpendicular to each other.

[0063] Figure 13 A top view of a wafer 101 having wires 117 in the M1 layer of the interconnect structure 120 of semiconductor device 100B is shown. Figure 8B Unlike other semiconductor devices, the conductors 117 in the M1 layer of semiconductor device 100B extend parallel to the slot direction 15.

[0064] Figure 14 A top view of a wafer 101 having wires 117 in the M2 layer of the interconnect structure 120 of semiconductor device 100B is shown. Figure 14 In one example, the wire 117 in the M2 layer of the semiconductor device 100B extends perpendicularly to the slot direction 15 (and also perpendicularly to the wire 117 in the M1 layer of the semiconductor device 100B).

[0065] Figure 15A cross-sectional view of semiconductor device 100B is shown. The cross-sectional view extends along a section passing through DTC 106 and in direction 17' (or 19'). Semiconductor device 100B is similar to semiconductor device 100, but without the air gap 110 formed in the gap filling material 109. Therefore, the remaining portion of the gap filling material 109 forms the sealing structure 109. It should be noted that the thickness T1 of the sidewall portion of the pad layer 103 (the portion along the sidewall 101S of the substrate 101) is substantially the same as the thickness T2 of the horizontal portion of the pad layer 103 (the portion along the upper surface of the substrate 101 and the bottom surface of DTC 106). In some embodiments, since the longitudinal axis of the opening 102 (formed during the formation process of the semiconductor device 100B) is parallel (or perpendicular) to the slot direction 15, the atomic (e.g., silicon atom) density at the sidewalls and bottom of the opening 102 and at the upper surface of the substrate 101 is substantially the same, and therefore, the pad layer 103 formed by oxidizing the exposed portion of the substrate 101 has a substantially uniform thickness. In some embodiments, the thickness T1 of the pad layer 103 of the semiconductor device 100B is less than the thickness of the pad layer 103 of the semiconductor device 100, which creates a wider opening 102 after the formation of the pad layer 103, and the wider opening 102 allows the gap filling material 109 to completely fill the opening 102, thereby preventing air gaps 110 from forming in the gap filling material 109.

[0066] Figure 16 A cross-sectional view of semiconductor device 100C is shown. Semiconductor device 100C is similar to semiconductor device 100B, but has an air gap 110 formed in the gap filling material 109, and therefore, the remaining portion of the gap filling material 109 and the air gap 110 form a sealing structure 108. Figure 16 In one example, semiconductor device 100C is formed using the same processing steps as semiconductor device 100B. However, the aspect ratio (e.g., the ratio of depth to width) of the opening 102 in semiconductor device 100C can be greater than that of the opening 102 in semiconductor device 100B. This allows the relatively deeper opening 102 to be partially filled with gap-filling material 109, thus forming an air gap 110 in the gap-filling material 109. It should be noted that... Figure 16 The ratio between the thickness T1 and the thickness T2 of the pad layer 103 in the semiconductor device 100B is the same as the ratio between the thickness T1 and the thickness T2 of the pad layer 103 in the semiconductor device 100B (e.g., about 1.0).

[0067] Figure 17 A cross-sectional view of a semiconductor package 500 according to an embodiment is shown. Figure 17In this process, a semiconductor device 100 (or 100A, or 100B, or 100C) is used to form an interposer 300. The interposer 300 can be formed by embedding the semiconductor device 100 in a sealant 301, such as a molding material or a polymer material. The upper surface of the sealant 301 is formed substantially flush with the upper surface of the semiconductor device 100, thereby allowing the interconnects of the semiconductor device 100 (see example...) Figure 9 127) is exposed on the upper surface of sealant 301. A redistribution structure (RDS) 306A for a connector electrically coupled to semiconductor device 100 is formed on a first side of sealant 301. RDS 306A includes a dielectric layer and conductive components (e.g., wires and vias) formed in the dielectric layer. Similarly, RDS 306B is formed on a second opposite side of sealant 301. A via 303 is formed to extend through sealant 301 and to electrically couple RDS 306A and RDS 306B. RDS is known and used in industry, so details are not discussed here.

[0068] Next, semiconductor chips 401, 403, and 405 are attached to a first side of the interposer 300 and electrically coupled together via RDS 306A. In some embodiments, die connectors 407 of semiconductor chips 401, 403, and 405 are bonded to conductive pads 307 on the upper surface of RDS 306A via solder regions 409. In some embodiments, no solder regions are used for bonding semiconductor chips 401, 403, and 405. Instead, direct metal-to-metal bonding is used to bond the die connectors 407 of semiconductor chips 401, 403, and 405 to the conductive pads 307. Semiconductor chip 403 may be, for example, a microcontroller, signal processor, etc., and semiconductor chip 401 may be, for example, a high-bandwidth memory (HBM) chip. Semiconductor device 100 (e.g., an LSI chip) provides high-density connectivity between semiconductor chips 401 and 403, which would otherwise be impossible using only RDS 306A due to the relatively large linewidth of RDS 306A. Figure 17 The number of semiconductor chips and the interconnections between them shown are illustrative and not limiting.

[0069] Next, the second side of the interposer 300 is attached to the substrate 200. The substrate 200 can be, for example, a printed circuit board (PCB). For example, the substrate 200 may include one or more dielectric layers 201 formed of bismaleimide triazine (BT) resin, FR-4 (a composite material consisting of woven glass fiber cloth with a flame-retardant epoxy resin adhesive), ceramic, glass, plastic, tape, film, or other support material. The substrate 200 may include conductive components (e.g., wires 203 and vias 205) formed in the dielectric layer 201. Figure 17As shown, the substrate 200 has conductive pads 207 formed on the upper surface and the lower surface of the substrate 200. The conductive pads 207 are electrically coupled to conductive components of the substrate 200. In some embodiments, the conductive pads 307 on the lower surface of the RDS 306B are bonded to the conductive pads 207 on the upper surface of the substrate 200, for example, through solder regions 309.

[0070] Advantages are achieved through the disclosed embodiments. For example, warping may occur in the semiconductor package 500 due to the mismatch of the coefficients of thermal expansion (CTE) of the different materials in the semiconductor package 500, and cause stress in the semiconductor device 100. This stress in the semiconductor package 500 could lead to cracks in the LSI interposer without the currently disclosed structure. The disclosed embodiments (by rotating the lattice grid at the surface of the substrate 101 relative to the sidewalls of the semiconductor device 100) increase the strength of the substrate 101 and reduce die cracking. Furthermore, by forming the DTC 106 to extend along the grid line direction of the lattice grid, a low-stress sealing structure 108 for the DTC 106 is formed, which helps reduce stress in the DTC 106 and helps prevent material peeling in the DTC 106, thus improving production yield. Furthermore, the disclosed DTC structure provides high capacitance by forming multiple layers of dielectric layer 107 interleaved with multiple layers of conductive layer 105 in the opening 102. Although embodiments of this disclosure are discussed in the context of forming an LSI interposer, the methods for increasing the strength of substrate 101 are applicable to manufacturing processes for forming other types of semiconductor devices, such as controllers, signal processors, memory devices, and the like.

[0071] Figure 18 A flowchart of a method 1000 for forming a semiconductor package is shown in some embodiments. It should be understood that... Figure 18 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, options, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 18 The steps shown are as follows.

[0072] refer to Figure 18In block 1010, a deep trench capacitor (DTC) is formed in a wafer with slots, wherein the wafer is formed of a semiconductor material, and the lattice of the semiconductor material at the surface of the wafer extends along a first direction and a second direction perpendicular to the first direction. In block 1020, an interconnect structure electrically coupled to a corresponding DTC is formed over the wafer, wherein each interconnect structure is formed to include multiple dielectric layers and conductive components located within the multiple dielectric layers. In block 1030, after forming the interconnect structure, the wafer is diced along a third direction and a fourth direction perpendicular to the third direction to form multiple semiconductor devices, wherein the third direction and the fourth direction are different from the first direction and the second direction.

[0073] According to an embodiment, a semiconductor device includes: a substrate comprising a semiconductor material, wherein a lattice of the semiconductor material at a main upper surface of the substrate extends along a first direction and a second direction perpendicular to the first direction, wherein, in a top view, sidewalls of the semiconductor device extend along a third direction different from the first and second directions; a deep trench capacitor (DTC) embedded in the substrate; and an interconnect structure located above the main upper surface of the substrate, wherein the interconnect structure is electrically coupled to the DTC. In an embodiment, the angle between the third direction and the first direction is greater than zero degrees and less than or equal to forty-five degrees. In an embodiment, the DTC includes a first plurality of DTCs embedded in a first region of the substrate and a second plurality of DTCs embedded in a second region of the substrate adjacent to the first region, wherein, in a top view, a first longitudinal axis of the first plurality of DTCs extends along the first direction, and a second longitudinal axis of the second plurality of DTCs extends along the second direction. In an embodiment, the interconnect structure includes: a first dielectric layer located above the substrate and the DTC; a first via embedded in the first dielectric layer, wherein the first via is connected to the DTC; a second dielectric layer located above the first dielectric layer; and a first conductor embedded in the second dielectric layer, wherein at least some of the first conductors are connected to the first via, wherein, in a top view, the longitudinal axis of the first conductor extends along a first direction. In an embodiment, each DTC includes: a first conductive layer; a first dielectric layer located above the first conductive layer; a second conductive layer located above the first dielectric layer; a second dielectric layer located above the second conductive layer; a third conductive layer located above the second dielectric layer; and a third dielectric layer located above the third conductive layer, wherein the first conductive layer and the third conductive layer are electrically coupled together through the interconnect structure. In an embodiment, the first dielectric layer, the second dielectric layer, and the third dielectric layer comprise the same high-k dielectric material, wherein the first conductive layer, the second conductive layer, and the third conductive layer comprise the same conductive material. In an embodiment, each of the first dielectric layer, second dielectric layer, third dielectric layer, first conductive layer, second conductive layer, and third conductive layer of the DTC includes: a first portion extending from a major upper surface of the substrate into the substrate; and a second portion extending along the major upper surface of the substrate. In an embodiment, the semiconductor device further includes a gap-filling material surrounded by the first portion of the third dielectric layer, wherein the gap-filling material is a dielectric material. In an embodiment, for each DTC, the second portion of the second dielectric layer and the second portion of the second conductive layer extend laterally from the gap-filling material further than the second portions of the third dielectric layer and the second portion of the third conductive layer, wherein for each DTC, the second portion of the first dielectric layer and the second portion of the first conductive layer extend laterally from the gap-filling material further than the second portions of the second dielectric layer and the second portion of the second conductive layer. In an embodiment, the semiconductor device further includes an air gap located in the gap-filling material.In one embodiment, the semiconductor device further includes a pad layer located between the substrate and the DTC, wherein, for each DTC, a first portion of the pad layer disposed along the sidewall of the substrate facing the DTC has a first thickness, and a second portion of the pad layer disposed along the bottom surface of the DTC has a second thickness, wherein the ratio between the first thickness and the second thickness is between about 1.5 and about 2.0. In another embodiment, the semiconductor device further includes a pad layer located between the substrate and the DTC, wherein, for each DTC, a first portion of the pad layer disposed along the sidewall of the substrate facing the DTC has a first thickness, and a second portion of the pad layer disposed along the bottom surface of the DTC has a second thickness, wherein the second thickness is substantially the same as the first thickness.

[0074] According to an embodiment, a semiconductor device includes: a substrate comprising a semiconductor material having a lattice structure, wherein the lattice orientation of the semiconductor material at a main upper surface of the substrate includes a first direction and a second direction perpendicular to the first direction, wherein, in a top view, the sidewalls of the semiconductor device extend along a third direction between the first and second directions; a deep trench capacitor (DTC) embedded in the substrate, wherein the DTC includes a first plurality of DTCs embedded in a first region of the substrate, wherein, in a top view, a first longitudinal axis of the first plurality of DTCs extends along a fourth direction different from the first and second directions; and an interconnect structure located above the main upper surface of the substrate, wherein the interconnect structure is electrically coupled to the DTCs. In an embodiment, the third direction is located exactly between the first and second directions. In an embodiment, the fourth direction is perpendicular to the third direction, wherein the DTC includes a second plurality of DTCs embedded in a second region of the substrate, wherein the second region is adjacent to the first region, wherein a second longitudinal axis of the second plurality of DTCs extends along the third direction. In one embodiment, the interconnect structure includes via layers interleaved with the conductive layers, wherein a first conductive layer of the interconnect structure extends closer to the substrate than the other conductive layers of the interconnect structure, and wherein, in a top view, the longitudinal axis of the first conductive layer extends parallel to a third direction.

[0075] According to an embodiment, a method of forming a semiconductor device includes: forming a deep trench capacitor (DTC) in a wafer having a notch, wherein the wafer is formed of a semiconductor material, wherein a lattice of the semiconductor material at the surface of the wafer extends along a first direction and a second direction perpendicular to the first direction; forming an interconnect structure electrically coupled to a respective DTC above the wafer, wherein each interconnect structure is formed to include a plurality of dielectric layers and conductive components located in the plurality of dielectric layers; and after forming the interconnect structure, dicing the wafer along a third direction and a fourth direction perpendicular to the third direction to form a plurality of semiconductor devices, wherein the third direction and the fourth direction are different from the first direction and the second direction. In an embodiment, the third direction is located between the first direction and the second direction, wherein the notch is formed to point towards the third direction. In an embodiment, forming a DTC includes forming a first DTC in a first region of the wafer and forming a second DTC in a second region of the wafer adjacent to the first region, wherein a first longitudinal axis of the first DTC is formed to extend along the first direction, and a second longitudinal axis of the second DTC is formed to extend along the second direction. In one embodiment, forming an interconnect structure includes: forming a first via layer connected to the DTC above the DTC; and forming a first conductor layer connected to the first via layer above the first via layer, wherein the longitudinal axis of the first conductor layer is formed to extend along a first direction.

[0076] Some embodiments of this application provide a semiconductor device comprising: a substrate comprising a semiconductor material, wherein a lattice of the semiconductor material at a main upper surface of the substrate extends along a first direction and a second direction perpendicular to the first direction, wherein, in a top view, the sidewalls of the semiconductor device extend along a third direction different from the first direction and the second direction; a deep trench capacitor embedded in the substrate; and an interconnect structure located above the main upper surface of the substrate, wherein the interconnect structure is electrically coupled to the deep trench capacitor.

[0077] In some embodiments, the angle between the third direction and the first direction is greater than zero degrees and less than or equal to forty-five degrees. In some embodiments, the deep trench capacitor includes a first plurality of deep trench capacitors embedded in a first region of the substrate and a second plurality of deep trench capacitors embedded in a second region of the substrate adjacent to the first region, wherein, in the top view, a first longitudinal axis of the first plurality of deep trench capacitors extends along the first direction, and a second longitudinal axis of the second plurality of deep trench capacitors extends along the second direction. In some embodiments, the interconnect structure includes: a first dielectric layer located above the substrate and the deep trench capacitor; a first via embedded in the first dielectric layer, wherein the first via is connected to the deep trench capacitor; a second dielectric layer located above the first dielectric layer; and a first conductor embedded in the second dielectric layer, wherein at least some of the first conductors are connected to the first via, wherein, in the top view, the longitudinal axis of the first conductor extends along the first direction. In some embodiments, each deep trench capacitor includes: a first conductive layer; a first dielectric layer above the first conductive layer; a second conductive layer above the first dielectric layer; a second dielectric layer above the second conductive layer; a third conductive layer above the second dielectric layer; and a third dielectric layer above the third conductive layer, wherein the first conductive layer and the third conductive layer are electrically coupled together through the interconnect structure. In some embodiments, the first dielectric layer, the second dielectric layer, and the third dielectric layer comprise the same high-k dielectric material, wherein the first conductive layer, the second conductive layer, and the third conductive layer comprise the same conductive material. In some embodiments, each of the first dielectric layer, the second dielectric layer, the third dielectric layer, the first conductive layer, the second conductive layer, and the third conductive layer of the deep trench capacitor includes: a first portion extending from the main upper surface of the substrate into the substrate; and a second portion extending along the main upper surface of the substrate. In some embodiments, the semiconductor device further includes a gap-filling material surrounded by the first portion of the third dielectric layer, wherein the gap-filling material is a dielectric material. In some embodiments, for each deep trench capacitor, the second portion of the second dielectric layer and the second portion of the second conductive layer extend laterally from the gap-filling material further than the second portion of the third dielectric layer and the second portion of the third conductive layer, wherein, for each deep trench capacitor, the second portion of the first dielectric layer and the second portion of the first conductive layer extend laterally from the gap-filling material further than the second portion of the second dielectric layer and the second portion of the second conductive layer. In some embodiments, the semiconductor device further includes an air gap located in the gap-filling material.In some embodiments, the semiconductor device further includes a pad layer between the substrate and the deep trench capacitor, wherein, for each deep trench capacitor, a first portion of the pad layer along the sidewall of the substrate facing the deep trench capacitor has a first thickness, and a second portion of the pad layer along the bottom surface of the deep trench capacitor has a second thickness, wherein the ratio between the first thickness and the second thickness is between about 1.5 and about 2.0. In some embodiments, the semiconductor device further includes a pad layer between the substrate and the deep trench capacitor, wherein, for each deep trench capacitor, a first portion of the pad layer along the sidewall of the substrate facing the deep trench capacitor has a first thickness, and a second portion of the pad layer along the bottom surface of the deep trench capacitor has a second thickness, wherein the second thickness is substantially the same as the first thickness.

[0078] Other embodiments of this application provide a semiconductor device comprising: a substrate comprising a semiconductor material having a lattice structure, wherein the lattice grid orientation of the semiconductor material at a main upper surface of the substrate includes a first direction and a second direction perpendicular to the first direction, wherein, in a top view, the sidewalls of the semiconductor device extend along a third direction between the first direction and the second direction; a deep trench capacitor embedded in the substrate, wherein the deep trench capacitor comprises a first plurality of deep trench capacitors embedded in a first region of the substrate, wherein, in the top view, a first longitudinal axis of the first plurality of deep trench capacitors extends along a fourth direction different from the first direction and the second direction; and an interconnect structure located above the main upper surface of the substrate, wherein the interconnect structure is electrically coupled to the deep trench capacitor.

[0079] In some embodiments, the third direction is located exactly midway between the first direction and the second direction. In some embodiments, the fourth direction is perpendicular to the third direction, wherein the deep trench capacitor includes a second plurality of deep trench capacitors embedded in a second region of the substrate, wherein the second region is adjacent to the first region, and wherein the second longitudinal axis of the second plurality of deep trench capacitors extends along the third direction. In some embodiments, the interconnect structure includes via layers interleaved with conductive layers, wherein a first conductive layer of the interconnect structure extends closer to the substrate than other conductive layers of the interconnect structure, and wherein, in the top view, the longitudinal axis of the first conductive layer extends parallel to the third direction.

[0080] Further embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a deep trench capacitor in a wafer having slots, wherein the wafer is formed of a semiconductor material, wherein a lattice of the semiconductor material at the surface of the wafer extends along a first direction and a second direction perpendicular to the first direction; forming an interconnect structure electrically coupled to a corresponding deep trench capacitor over the wafer, wherein each of the interconnect structures is formed to include a plurality of dielectric layers and conductive components located in the plurality of dielectric layers; and after forming the interconnect structure, dicing the wafer along a third direction and a fourth direction perpendicular to the third direction to form a plurality of semiconductor devices, wherein the third direction and the fourth direction are different from the first direction and the second direction.

[0081] In some embodiments, the third direction is located between the first direction and the second direction, wherein the notch is formed pointing towards the third direction. In some embodiments, forming the deep trench capacitor includes forming a first deep trench capacitor in a first region of the wafer and forming a second deep trench capacitor in a second region of the wafer adjacent to the first region, wherein a first longitudinal axis of the first deep trench capacitor is formed to extend along the first direction, and a second longitudinal axis of the second deep trench capacitor is formed to extend along the second direction. In some embodiments, forming the interconnect structure includes: forming a first via layer connected to the deep trench capacitor above the deep trench capacitor; and forming a first conductive layer connected to the first via layer above the first via layer, wherein the longitudinal axis of the first conductive layer is formed to extend along the first direction.

[0082] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: A substrate comprising a semiconductor material, wherein a lattice of the semiconductor material at the main upper surface of the substrate extends along a first direction and a second direction perpendicular to the first direction, wherein, in a top view, the sidewalls of the semiconductor device extend along a third direction different from the first direction and the second direction; Deep trench capacitors, embedded in the substrate; and An interconnect structure is located above the main upper surface of the substrate, wherein the interconnect structure is electrically coupled to the deep trench capacitor.

2. The semiconductor device according to claim 1, wherein, The angle between the third direction and the first direction is greater than zero degrees and less than or equal to forty-five degrees.

3. The semiconductor device according to claim 2, wherein, The deep trench capacitor includes a first plurality of deep trench capacitors embedded in a first region of the substrate and a second plurality of deep trench capacitors embedded in a second region of the substrate adjacent to the first region, wherein, in the top view, a first longitudinal axis of the first plurality of deep trench capacitors extends along the first direction, and a second longitudinal axis of the second plurality of deep trench capacitors extends along the second direction.

4. The semiconductor device according to claim 3, wherein, The interconnection structure includes: A first dielectric layer is located above the substrate and the deep trench capacitor; A first through-hole is embedded in the first dielectric layer, wherein the first through-hole is connected to the deep trench capacitor; A second dielectric layer is located above the first dielectric layer; and A first conductor is embedded in the second dielectric layer, wherein at least some of the first conductors are connected to the first via, wherein, in the top view, the longitudinal axis of the first conductor extends along the first direction.

5. The semiconductor device according to claim 4, wherein, Each deep trench capacitor of the deep trench capacitor includes: First conductive layer; The first dielectric layer is located above the first conductive layer; The second conductive layer is located above the first dielectric layer; The second dielectric layer is located above the second conductive layer; A third conductive layer is located above the second dielectric layer; and A third dielectric layer is located above the third conductive layer, wherein the first conductive layer and the third conductive layer are electrically coupled together through the interconnect structure.

6. The semiconductor device according to claim 5, wherein, The first dielectric layer, the second dielectric layer, and the third dielectric layer comprise the same high-k dielectric material, wherein the first conductive layer, the second conductive layer, and the third conductive layer comprise the same conductive material.

7. The semiconductor device according to claim 5, wherein, Each of the first dielectric layer, the second dielectric layer, the third dielectric layer, the first conductive layer, the second conductive layer, and the third conductive layer of the deep trench capacitor includes: The first portion extends from the main upper surface of the substrate into the substrate; and The second part extends along the main upper surface of the substrate.

8. The semiconductor device of claim 7, further comprising a gap-filling material surrounded by the first portion of the third dielectric layer, wherein, The gap-filling material is a dielectric material.

9. A semiconductor device, comprising: A substrate comprising a semiconductor material having a lattice structure, wherein the lattice grid orientation of the semiconductor material at the main upper surface of the substrate includes a first direction and a second direction perpendicular to the first direction, wherein, in a top view, the sidewalls of the semiconductor device extend along a third direction between the first direction and the second direction; A deep trench capacitor, embedded in the substrate, wherein the deep trench capacitor includes a first plurality of deep trench capacitors embedded in a first region of the substrate, wherein, in the top view, a first longitudinal axis of the first plurality of deep trench capacitors extends along a fourth direction different from the first direction and the second direction; and An interconnect structure is located above the main upper surface of the substrate, wherein the interconnect structure is electrically coupled to the deep trench capacitor.

10. A method of forming a semiconductor device, the method comprising: A deep trench capacitor is formed in a wafer with a slot, wherein the wafer is formed of a semiconductor material, and wherein the lattice grid of the semiconductor material at the surface of the wafer extends along a first direction and a second direction perpendicular to the first direction; An interconnect structure electrically coupled to a corresponding deep trench capacitor is formed over the wafer, wherein each of the interconnect structures is formed to include a plurality of dielectric layers and conductive components located within the plurality of dielectric layers; and After the interconnect structure is formed, the wafer is cut along a third direction and a fourth direction perpendicular to the third direction to form a plurality of semiconductor devices, wherein the third direction and the fourth direction are different from the first direction and the second direction.

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