Semiconductor device and semiconductor memory device

Abstract

A semiconductor device and a semiconductor storage device capable of suppressing temperature rise of semiconductor chips are provided. The semiconductor device includes a plurality of first semiconductor chips stacked in an up-down direction, a first chip upper member provided to an upper surface of a lower one of two first semiconductor chips adjacent in the up-down direction, and a plurality of second semiconductor chips provided to upper surfaces of the plurality of first semiconductor chips, the first chip upper member including a heat conduction member having a higher thermal conductivity than that of the second semiconductor chips.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a semiconductor memory device. Background Technology

[0002] In semiconductor devices, there are devices that mount multiple stacked semiconductor chips on a mounting substrate.

[0003] Patent Document 1: US Patent Application Publication No. US2022 / 0157783

[0004] Patent Document 2: US Patent Application Publication No. US2022 / 0173090

[0005] Patent Document 3: US Patent Application Publication No. US2016 / 0247786

[0006] Patent Document 4: Japanese Patent Application Publication No. 2024-118858

[0007] We look forward to technologies that can suppress the temperature rise of semiconductor chips. Summary of the Invention

[0008] The purpose of this disclosure is to provide a semiconductor device and a semiconductor memory device capable of suppressing temperature rise in semiconductor chips.

[0009] The semiconductor device disclosed herein includes: a plurality of first semiconductor chips stacked in a vertical direction; a first on-chip component disposed on the upper surface of the lower first semiconductor chip between two adjacent first semiconductor chips in the vertical direction; and a plurality of second semiconductor chips disposed on the upper surface of each of the plurality of first semiconductor chips, wherein the first on-chip component includes a thermally conductive component having a thermal conductivity higher than that of the second semiconductor chips.

[0010] The semiconductor memory device disclosed herein includes the semiconductor device, the second semiconductor chip including a memory circuit having a non-volatile memory region, and the first semiconductor chip including a control circuit for controlling the memory circuit. Attached Figure Description

[0011] Figure 1 This is a schematic diagram showing a cross-section of the semiconductor device 11 of the first embodiment, parallel to the YZ plane.

[0012] Figure 2 This is a schematic diagram showing in detail the cross section of the stacked unit 411a of the first embodiment, parallel to the YZ plane.

[0013] Figure 3 This is a schematic diagram showing in detail the cross section of the stacked unit 411b of the first embodiment, parallel to the YZ plane.

[0014] Figure 4 This is a schematic diagram showing a cross-section of the semiconductor device 11B of the second example of the first embodiment, parallel to the YZ plane.

[0015] Figure 5 This is a schematic diagram showing in detail the cross section of the stacked unit 411c of the second example of the first embodiment, parallel to the YZ plane.

[0016] Figure 6 This is a schematic diagram showing a cross-section of the semiconductor device 11C of the third example of the first embodiment, parallel to the YZ plane.

[0017] Figure 7 This is a schematic diagram showing a cross-section of the semiconductor device 11D of the fourth example of the first embodiment, parallel to the YZ plane.

[0018] Figure 8 This is a schematic diagram showing a cross-section of the semiconductor device 12 of the first example of the second embodiment, parallel to the YZ plane.

[0019] Figure 9 This is a schematic diagram showing in detail the cross section of the stacked unit 412a of the first example of the second embodiment, parallel to the YZ plane.

[0020] Figure 10 This is a schematic diagram showing a cross-section of the semiconductor device 12B of the second embodiment, parallel to the YZ plane.

[0021] Figure 11 This is a schematic diagram showing in detail the cross section of the stacked unit 412b of the second embodiment, parallel to the YZ plane.

[0022] Figure 12 This is a schematic diagram showing a cross-section of the semiconductor device 12C of the third example of the second embodiment, parallel to the YZ plane.

[0023] Figure 13 This is a schematic diagram showing in detail the cross section of the stacked unit 412c of the third example of the second embodiment, parallel to the YZ plane.

[0024] Figure 14 This is a schematic diagram showing a cross-section of the semiconductor device 12D of the fourth example of the second embodiment, parallel to the YZ plane.

[0025] Figure 15 This is a schematic diagram showing a cross-section of the semiconductor device 12E of the fifth example of the second embodiment, parallel to the YZ plane.

[0026] Figure 16 This is a schematic diagram showing a cross-section of the semiconductor device 13 of the first example of the third embodiment, parallel to the YZ plane.

[0027] Figure 17 This is a schematic diagram showing in detail the cross section of the stacked unit 413a of the first example of the third embodiment, parallel to the YZ plane.

[0028] Figure 18 This is a schematic diagram showing in detail the cross section of the stacked unit 413c of the second example of the third embodiment, parallel to the YZ plane.

[0029] Explanation of reference numerals in the attached figures

[0030] 11, 11B, 11C, 11D, 12, 12B, 12C, 12D, 12E, 13… Semiconductor devices

[0031] 25… Wiring substrate

[0032] 25a… Upper surface

[0033] 26…Substrate Electrode

[0034] 65…sealing resin

[0035] 81…bonding wire

[0036] Components on the 101, 102... chips

[0037] 111, 111h, 111m… metal plates

[0038] 111a… Upper surface

[0039] 112, 112s, 112t… columnar portion

[0040] 112a… Upper end

[0041] 113, 113h… columnar portion

[0042] 113a…Metal section

[0043] 113b…CNT Department

[0044] 401…Laminated body

[0045] 411, 411a, 411b, 411c, 412, 412a, 412b, 412c, 412d, 413, 413a, 413b, 413c… stacked units

[0046] 421…CMOS chip

[0047] 421a… Upper surface

[0048] 421b…lower surface

[0049] 421c… control circuit

[0050] 421h…Heating section

[0051] 421d…Laminated pad

[0052] 422…memory chip

[0053] 422a… Upper surface

[0054] 422b…lower surface

[0055] 422c… Memory Circuit

[0056] 422d…Laminated pad

[0057] 423…Electrode pad

[0058] 424… Devices

[0059] 431… Bare die bonding film

[0060] 432, 432n, 432h… resin layer

[0061] 432a… Upper surface

[0062] 432b…lower surface

[0063] 433… Adhesive film Detailed Implementation

[0064] Hereinafter, this embodiment will be described with reference to the accompanying drawings. To facilitate understanding, the same reference numerals will be used as much as possible to refer to the same constituent elements in each drawing, and repeated descriptions will be omitted.

[0065] [First Implementation Method]

[0066] The configuration of the semiconductor device according to the first embodiment will now be described. In the accompanying drawings, the X-axis, Y-axis, and Z-axis are sometimes shown. The X-axis, Y-axis, and Z-axis form a right-handed three-dimensional orthogonal coordinate system. Hereinafter, the direction of the arrow on the X-axis is sometimes referred to as the X-axis+ direction, and the direction opposite to the arrow is sometimes referred to as the X-axis- direction; the same applies to the other axes. Furthermore, the Z-axis+ direction and the Z-axis- direction are sometimes referred to as "above" and "below," respectively. Additionally, the plane orthogonal to the X-axis, Y-axis, or Z-axis is sometimes referred to as the YZ plane, ZX plane, or XY plane. Furthermore, the Z-axis direction is sometimes referred to as the "vertical direction." "Above," "below," and "vertical direction" are merely terms indicating relative positional relationships within the accompanying drawings and are not terms defining an orientation based on the vertical direction.

[0067] In addition, except where specifically described, for ease of understanding, the dimensions of the constituent elements shown in the figures are sometimes shown differently from the actual dimensions.

[0068] In this specification, "connection" includes not only physical connections but also electrical connections, and unless otherwise specified, it includes not only direct connections but also indirect connections.

[0069] In this specification, "formed above" includes not only the case where it is formed in contact with the ground above, but also the case where it is formed above with other objects in between, unless otherwise specified. The same applies to cases such as "formed below".

[0070] Hereinafter, a first example of the semiconductor device according to the first embodiment (hereinafter, sometimes referred to as the first example of the first embodiment) will be described.

[0071] (First Example of First Embodiment)

[0072] Figure 1 This is a schematic diagram showing a cross-section of the semiconductor device 11 of the first embodiment, parallel to the YZ plane. (See diagram below.) Figure 1 As shown, the semiconductor device 11 includes a wiring substrate 25, a sealing resin 65, a bonding wire 81, and a laminate 401.

[0073] The wiring substrate 25 has an upper surface 25a that intersects the vertical direction (Z-axis direction). In this embodiment, the upper surface 25a is substantially parallel to the XY plane. An electrode pattern (not shown) is formed on the wiring substrate 25.

[0074] A plurality of substrate electrodes 26 are disposed on the upper surface 25a. The plurality of substrate electrodes 26 are arranged in a row along the X-axis direction, thereby forming bonding fingers. The bonding fingers of the substrate electrodes 26 are located on the Y-axis+ direction side of the laminate 401.

[0075] In the first example of the first embodiment, the laminate 401 includes three laminated units 411a and 411b. Hereinafter, laminated units 411a and 411b will sometimes be referred to as laminated units 411. In addition, the laminate 401 may also be configured to include two, three, or five or more laminated units 411.

[0076] The laminate 401 is disposed on the upper surface 25a of the wiring substrate 25. The laminate units 411a, 411a, 411a and 411b are stacked sequentially from bottom to top.

[0077] Figure 2This is a schematic diagram showing in detail a cross-section parallel to the YZ plane of the stacked unit 411a in the first example of the first embodiment. (See attached diagram.) Figure 1 and Figure 2 As shown, the stacked unit 411a includes components on or above the chip 101 (an example of a "first component on the chip"), a CMOS (Complementary Metal-Oxide-Semiconductor) chip 421 (an example of a "first semiconductor chip"), a memory chip 422 (an example of a "second semiconductor chip"), an electrode pad 423, a die-attach film 431 (an example of a "second resin layer"), and an adhesive film 433. The CMOS chip 421 and the memory chip 422, for example, comprise silicon.

[0078] The memory chip 422 includes a memory circuit 422c having a non-volatile memory region. The memory circuit 422c is, for example, a memory cell array formed on the lower surface 422b of the memory chip 422. The memory circuit 422c is, for example, formed on a silicon-containing semiconductor substrate.

[0079] Specifically, memory chip 422 is a memory chip that includes NAND flash memory. Memory circuit 422c can also be a three-dimensional memory cell array composed of multiple memory cells arranged in three dimensions.

[0080] The CMOS chip 421 includes a control circuit 421c that controls the memory circuit 422c in the memory chip 422. The control circuit 421c is, for example, a CMOS circuit formed on the upper surface 421a of the CMOS chip 421. The control circuit 421c is, for example, formed on a silicon-containing semiconductor substrate. The width of the CMOS chip 421 in the Y-axis direction is greater than the width of the memory chip 422.

[0081] The lower surface 422b of the memory chip 422 and the upper surface 421a of the CMOS chip 421 are bonded. Specifically, a bonding pad 421d (an example of a "first pad") is provided on the upper surface 421a of the CMOS chip 421. A bonding pad 422d (an example of a "second pad") is provided on the lower surface 422b of the memory chip 422.

[0082] The CMOS chip 421 and the memory chip 422 are bonded together by bonding pads 421d and 422d. Thus, the CMOS chip 421 and the memory chip 422 are mechanically bonded, and the memory circuit 422c and the control circuit 421c are electrically connected.

[0083] The CMOS chip 421 also includes electrode pads 423 (an example of a "bonding pad") disposed on its upper surface 421a. The number of electrode pads 423 may also be the same as the number of substrate electrodes 26 forming the bonding fingers. Multiple electrode pads 423 are disposed on the upper surface 421a of the CMOS chip 421, on the Y-axis+ direction side of the memory chip 422. The multiple electrode pads 423 are arranged in a row along the X-axis direction. The electrode pads 423 are electrically connected, for example, to a control circuit 421c.

[0084] A die attachment film 431 is disposed below the CMOS chip 421 and is in contact with the lower surface 421b of the CMOS chip 421. The die attachment film 431 is, for example, a thermosetting resin, which is an adhesive that fixes components together by heating.

[0085] The on-chip component 101 includes a metal plate 111 (an example of a "thermal conductive component" and a "conductive component") and an adhesive film 433. The metal plate 111 is a plate-shaped component extending along the XY plane and disposed on the Y-axis side of the memory chip 422.

[0086] The widths of the metal plate 111 and the adhesive film 433 are, for example, approximately the same. The width of the metal plate 111 is greater than the width of the memory chip 422. The width of the adhesive film 433 is greater than the width of the memory chip 422. Furthermore, the width obtained by adding the width of the metal plate 111 or the width of the adhesive film 433 to the width of the memory chip 422 is less than the width of the CMOS chip 421.

[0087] The metal plate 111 is bonded to the upper surface 421a of the CMOS chip 421 via the adhesive film 433. To improve thermal conductivity, the adhesive film 433 may also contain metal fillers such as silver, copper, or gold.

[0088] The metal plate 111 has a higher thermal conductivity than the die bonding film 431. Preferably, the metal plate 111 has a higher thermal conductivity than the memory chip 422 or the CMOS chip 421. Alternatively, the metal plate 111 may also have a thermal conductivity higher than 100 W / m / K.

[0089] Specifically, the metal plate 111 contains, for example, silver, copper, or gold. Here, the thermal conductivity of silver, copper, gold, and silicon is approximately 418, 394, 320, and 168 W / m / K, respectively.

[0090] The metal plate 111 is electrically connected, for example, to a terminal in the CMOS chip 421 that is supplied with a reference potential. The reference potential is, for example, the ground potential in the control circuit 421c. Alternatively, the reference potential can be the power supply voltage of the transistor in the control circuit 421c, such as VCC or VDD. Furthermore, the metal plate 111 can also be in a floating state.

[0091] With this structure, the metal plate 111 can function as a shielding layer, thus reducing the impact of noise leaking from the stacked cell 411 on other stacked cells 411. Additionally, the metal plate 111 can be used as part of the power supply wiring, thereby enhancing the power supply.

[0092] The upper ends of the metal plate 111 and the memory chip 422 are aligned. Specifically, the thickness of the metal plate 111, including its vertical dimension and the thickness of the adhesive film 433, is approximately the same as the thickness of the memory chip 422. With the upper surface 421a of the CMOS chip 421 as a reference, the height of the on-chip component 101 is approximately the same as the height of the memory chip 422. The upper surface 111a of the metal plate 111 and the upper surface 422a of the memory circuit 422c are surfaces approximately parallel to the XY plane. The vertical positions of the upper surface 111a and the upper surface 422a are approximately the same.

[0093] Figure 3 This is a schematic diagram showing in detail a cross-section parallel to the YZ plane of the stacked unit 411b in the first example of the first embodiment. (See attached diagram.) Figures 1-3 As shown, the stacked unit 411b and Figure 2 Compared to the stacked unit 411a shown, it includes an on-chip component 102 (an example of a "second on-chip component") instead of an on-chip component 101.

[0094] On-chip component 102 is disposed on the upper surface 421a of the uppermost CMOS chip 421. On-chip component 102 includes a metal plate 111h and an adhesive film 433. The thickness of the metal plate 111h in on-chip component 102 is greater than the thickness of the metal plate 111 in on-chip component 101.

[0095] In the stacked cell 411b, the vertical position of the upper surface 111a of the metal plate 111h is higher than the vertical position of the upper surface 422a of the memory chip 422. With the upper surface 421a of the CMOS chip 421 as a reference, the vertical height of the chip component 102 is higher than the height of the memory chip 422.

[0096] In the stack 401, multiple CMOS chips 421 are stacked in the vertical direction (see reference). Figure 1The on-chip component 101 is disposed between two adjacent CMOS chips 421 in the vertical direction, on the upper surface 421a of the lower CMOS chip 421.

[0097] The on-chip component 101 is connected to the lower surface 421b of the CMOS chip 421 disposed above it via the bare die adhesive film 431. Specifically, the upper surface 111a of the on-chip component 101 is in contact with the lower surface of the bare die adhesive film 431.

[0098] Multiple memory chips 422 are disposed on the upper surface 421a of each of the multiple CMOS chips 421.

[0099] The wiring substrate 25 is disposed below the CMOS chip 421 in the bottommost stacked unit 411a. The bottommost stacked unit 411a is fixed to the upper surface 25a of the wiring substrate 25 via the bare die adhesive film 431.

[0100] The second, third, and topmost stacked units 411 from the bottom are fixed to the stacked unit 411a of the layer directly below by the bare die adhesive film 431.

[0101] The bare die adhesive film 431 in the second, third and topmost stacked units 411 from the bottom is in contact with the metal plate 111a and the memory chip 422a in the stacked unit 411a directly below it.

[0102] The Y-axis + direction side and Y-axis - direction side of the laminate 401 are stepped. Each electrode pad 423 is located on the step surfaces of the steps.

[0103] The bonding wire 81 electrically connects the substrate electrode 26 in the wiring substrate 25 to the multiple electrode pads 423 included in each of the multiple CMOS chips 421.

[0104] In detail, the number of bonding wires 81 can also be the same as the number of substrate electrodes 26 forming bonding fingers. The multiple substrate electrodes 26 are electrically connected to multiple electrode pads 423 via bonding wires 81.

[0105] Sealing resin 65 seals at least four CMOS chips 421. Metal plates 111 in on-chip components 102 are exposed from the sealing resin 65.

[0106] Specifically, the sealing resin 65 embeds the laminate 401, excluding the upper surface 111a of the metal plate 111h in the on-chip component 102, above the wiring substrate 25. More specifically, the laminate 401, excluding the upper surface 111a of the metal plate 111h in the on-chip component 102, and the upper surface 25a of the wiring substrate 25 are insulated and sealed by the sealing resin 65.

[0107] The sealing resin 65, the bare chip adhesive film 431, and the adhesive film 433 have different compositions.

[0108] (Effect)

[0109] By placing a metal plate 111 with high thermal conductivity between two adjacent CMOS chips 421 in the vertical direction, the thermal resistance along the heat dissipation path in the vertical direction can be reduced. As a result, the heat generated in the high-heat CMOS chip 421 can be properly dissipated through the metal plate 111, and the supply of heat to the memory chip 422 can be suppressed.

[0110] Furthermore, by having a shape that extends along the XY plane, i.e., the metal plate 111, which is configured as a heat conductor, heat from the heat source can be dissipated in the direction in the XY plane, for example, when a heat source is locally present in the CMOS chip 421. As a result, the temperature rise near the heat source can be mitigated.

[0111] Furthermore, by exposing the upper surface 111a of the metal plate 111 in the uppermost stacked unit 411b through the sealing resin 65, heat generated in the semiconductor device 11 can be dissipated from the upper surface 111a to the outside of the semiconductor device 11. Specifically, for example, heat dissipation can be effectively achieved by connecting a heat sink or heat pipe to the upper surface 111a.

[0112] Furthermore, by ensuring that the vertical position of the upper surface 111a of the metal plate 111 is approximately the same as the vertical position of the upper surface 422a of the memory circuit 422c, surfaces without step differences can be bonded together, making the thickness of the bare die adhesive film 431 approximately uniform. This improves the adhesion of the bare die adhesive film 431.

[0113] (Second example of the first implementation method)

[0114] Figure 4 This is a schematic diagram showing a cross-section of the semiconductor device 11B of the second example of the first embodiment, parallel to the YZ plane. Figure 5 This is a schematic diagram showing in detail a cross-section parallel to the YZ plane of the stacked unit 411c in the second example of the first embodiment. (See attached diagram.) Figure 4 and Figure 5As shown, semiconductor device 11B is similar to the point where the metal plate penetrates the bare die adhesive film 431. Figures 1-3 The semiconductor device 11 in the first embodiment shown is different.

[0115] In semiconductor device 11B, laminate 401 and Figure 1 Compared to the stacked body 401 shown, it includes three stacked units 411c instead of three stacked units 411a. Stacked units 411c and... Figure 2 Compared to the stacked unit 411a shown, it includes a metal plate 111m instead of a metal plate 111.

[0116] In the stacked unit 411c, the upper end of the chip component 101 disposed above the CMOS chip 421 is positioned vertically above the upper end of the memory chip 422 disposed on the upper surface 421a of the CMOS chip 421.

[0117] In detail, the vertical position of the upper surface 111a of the metal plate 111m is higher than the vertical position of the upper surface 422a of the memory chip 422. The thickness of the metal plate 111m plus the thickness of the adhesive film 433 is greater than the thickness of the memory chip 422. With the upper surface 421a of the CMOS chip 421 as a reference, the height of the on-chip component 102 is greater than the height of the memory chip 422. The difference between the vertical positions of the upper surface 111a and the upper surface 422a, i.e., the difference between the thickness (height) of the on-chip component 101 and the thickness (height) of the memory chip 422, is approximately the thickness of the bare chip adhesive film 431.

[0118] In semiconductor device 11B, on-chip component 101 is in contact with the lower surface 421b of the CMOS chip 421 disposed above it. Specifically, the upper surface 111a of metal plate 111m is in contact with the lower surface 421b of the CMOS chip 421 in the stacked unit 411 of the layer directly above it. Alternatively, a thin film of bare die adhesive film 431 may be disposed between the upper surface 111a of metal plate 111m and the lower surface 421b of CMOS chip 421.

[0119] (Effect)

[0120] By connecting the upper surface 111a of the metal plate 111 to the lower surface 421b of the CMOS chip 421, the thermal resistance along the heat dissipation path in the vertical direction can be further reduced.

[0121] (Third example of the first embodiment)

[0122] Figure 6This is a schematic diagram showing a cross-section parallel to the YZ plane of the semiconductor device 11C in the third example of the first embodiment. (As shown) Figure 6 As shown, semiconductor device 11C and Figures 1-3 The difference between the semiconductor device 11 of the first embodiment shown is that the upper surface 111a of the metal plate 111 in the chip component 102 is not exposed from the sealing resin 65.

[0123] In semiconductor device 11C, laminate 401 and Figure 1 Compared to the stacked body 401 shown, it includes a stacked unit 411a instead of a stacked unit 411b.

[0124] In the semiconductor device 11C, the sealing resin 65 completely embeds the laminate 401 above the wiring substrate 25.

[0125] (Fourth example of the first implementation method)

[0126] Figure 7 This is a schematic diagram showing a cross-section parallel to the YZ plane of the semiconductor device 11D in the fourth example of the first embodiment. Figure 7 As shown, semiconductor device 11D and Figure 4 and Figure 5 The difference between the semiconductor device 11B of the second example of the first embodiment shown is that the upper surface 111a of the metal plate 111 in the chip component 102 is not exposed from the sealing resin 65.

[0127] In semiconductor device 11D, laminate 401 and Figure 4 Compared to the stacked body 401 shown, it includes a stacked unit 411c instead of a stacked unit 411b.

[0128] In the semiconductor device 11D, the sealing resin 65 completely embeds the laminate 401 above the wiring substrate 25.

[0129] [Second Implementation]

[0130] The semiconductor device 12 according to the second embodiment will be described. Following the second embodiment, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same effects obtained through the same structure will not be described in detail in each embodiment.

[0131] (First example of the second implementation method)

[0132] Figure 8 This is a schematic diagram showing a cross-section of the semiconductor device 12 of the first example of the second embodiment, parallel to the YZ plane. Figure 9 This is a schematic diagram showing in detail the cross section of the stacked unit 412a of the first example of the second embodiment, parallel to the YZ plane.

[0133] like Figure 8 and Figure 9 As shown, the difference between the semiconductor device 12 of the second embodiment and the semiconductor device 11 of the first embodiment is that multiple columnar heat conduction components are provided on the upper surface 421a of the CMOS chip 421.

[0134] In semiconductor device 12, laminate 401 and Figures 1-3 Compared to the stack 401 shown, it includes four stack units 412a instead of four stack units 411. Hereinafter, stack unit 412a will sometimes be referred to as stack unit 412.

[0135] On-chip component 101 in stacked cell 412a and Figures 1-3 Compared to the on-chip component 101 in the stacked unit 411a shown, a plurality of pillar-shaped parts 112t (an example of "thermal conductive parts" and "conductive parts") are included instead of the metal plate 111 and the adhesive film 433. Hereinafter, the pillar-shaped parts 112t will sometimes be referred to as pillar-shaped parts 112.

[0136] The columnar portion 112t has a higher thermal conductivity than the bare die adhesive film 431. Preferably, the columnar portion 112t has a higher thermal conductivity than the memory chip 422 or the CMOS chip 421. Alternatively, the columnar portion 112t may also have a thermal conductivity higher than 100 W / m / K. Specifically, the columnar portion 112t contains metals such as silver, copper, or gold.

[0137] The columnar portion 112t, for example, standardizes the bonding wires to a specified length. Multiple columnar portions 112t are disposed on the Y-axis side of the memory chip 422.

[0138] The lower end of the columnar portion 112t is in contact with the upper surface 421a of the CMOS chip 421. The columnar portion 112t extends in the vertical direction. In this embodiment, the columnar portion 112t extends approximately parallel to the Z-axis.

[0139] The vertical position of the upper end 112a of the columnar portion 112t is higher than the vertical position of the upper surface 422a of the memory chip 422. With the upper surface 421a of the CMOS chip 421 as a reference, the height of the columnar portion 112t is higher than the height of the memory chip 422. The difference between the vertical position of the upper end 112a and the vertical position of the upper surface 422a, i.e., the difference between the height of the columnar portion 112t and the height of the memory chip 422, is approximately the thickness of the die-attach film 431.

[0140] Alternatively, the chip component 101 may be configured as a U-shaped bonding line that replaces the columnar portion 112t and includes the upper ends 112a of the two columnar portions 112t bridging each other and having both ends connected to the upper surface 421a of the CMOS chip 421.

[0141] In the semiconductor device 12, the columnar portion 112t is in contact with the lower surface 421b of the CMOS chip 421 disposed above it. Specifically, the columnar portion 112t penetrates the bare die adhesive film 431 in the stacked unit 412 of the layer directly above it and is in contact with the lower surface 421b of the CMOS chip 421. Alternatively, a thin film of the bare die adhesive film 431 may be disposed between the upper end 112a of the columnar portion 112t and the lower surface 421b of the CMOS chip 421.

[0142] In the semiconductor device 12, the structure of the on-chip component 102 in the uppermost stacked unit 412a is the same as that of the on-chip component 101.

[0143] The upper end 112a of the columnar portion 112t in the chip component 102 is exposed from the sealing resin 65.

[0144] (Effect)

[0145] By providing a flexible columnar portion 112t instead of a metal plate 111, the thermal stress generated during heat treatment involving temperature cycling can be mitigated by the difference between the thermal expansion coefficient of the chip (e.g., silicon) and the thermal expansion coefficient of the columnar portion 112t (e.g., metal).

[0146] Furthermore, by configuring the columnar portion 112t to penetrate the bare chip adhesive film 431, and having the upper end 112a of the columnar portion 112t in contact with the lower surface 421b of the CMOS chip 421, the thermal resistance along the heat dissipation path in the vertical direction can be further reduced.

[0147] (Second Example of Second Implementation)

[0148] Figure 10 This is a schematic diagram showing a cross-section of the semiconductor device 12B of the second embodiment, parallel to the YZ plane. Figure 11 This is a schematic diagram showing in detail the cross section of the stacked unit 412b of the second embodiment, parallel to the YZ plane.

[0149] like Figure 10 and Figure 11 As shown, in semiconductor device 12B, the laminate 401 and Figure 8 and Figure 9 The difference between the semiconductor device 12 of the first example of the second embodiment shown is that it has four stacked units 412b instead of four stacked units 412a. The stacked unit 412b is an example of the stacked unit 412.

[0150] On-chip component 101 in stacked cell 412b and Figure 8 and Figure 9 Compared to the on-chip component 101 in the stacked unit 412a shown, a plurality of columnar portions 112s (an example of "thermal conductive component" and "conductive component") are included instead of a plurality of columnar portions 112t.

[0151] The columnar portion 112s is an example of the columnar portion 112. The vertical length of the columnar portion 112s is shorter than the vertical length of the columnar portion 112t.

[0152] The vertical position of the upper end 112a of the columnar portion 112s is approximately the same as the vertical position of the upper surface 422a of the memory chip 422. With the upper surface 421a of the CMOS chip 421 as a reference, the height of the columnar portion 112s is approximately the same as the height of the memory chip 422.

[0153] The bare die adhesive film 431 in the second, third and topmost stacked units 411 from the bottom layer is connected to the upper end 112a of the columnar portion 112s in the stacked unit 411 of the layer directly below and the upper surface 422a of the memory chip 422.

[0154] In semiconductor device 12B, the structure of on-chip component 102 in the uppermost stacked unit 412b is the same as that of on-chip component 101.

[0155] The upper end 112a of the columnar portion 112t in the chip component 102 does not protrude from the sealing resin 65. That is, the sealing resin 65 completely embeds the laminate 401 above the wiring substrate 25.

[0156] (Effect)

[0157] By having the upper end 112a of the columnar portion 112s in contact with the lower surface of the bare die adhesive film 431, it is possible to suppress physical damage to the CMOS chip 421 caused by contact between the columnar portion 112s and the CMOS chip 421.

[0158] (Third example of the second implementation method)

[0159] Figure 12 This is a schematic diagram showing a cross-section of the semiconductor device 12C of the third example of the second embodiment, parallel to the YZ plane. Figure 13 This is a schematic diagram showing in detail the cross section of the stacked unit 412c of the third example of the second embodiment, parallel to the YZ plane.

[0160] like Figure 12 and Figure 13 As shown, semiconductor device 12C and Figure 8 and Figure 9 The difference between the semiconductor device 12 of the first example of the second embodiment shown is that the columnar portions 112t and 112s are mixed together.

[0161] In semiconductor device 12C, laminate 401 and Figure 8 and Figure 9 Compared to the stack 401 shown, it includes four stack units 412c instead of four stack units 412a. Stack unit 412c is an example of stack unit 412.

[0162] On-chip component 101 in stacked cell 412c and Figure 8 and Figure 9 Compared to the on-chip component 101 in the stacked unit 412a shown, it also includes a plurality of columnar portions 112s.

[0163] The columnar portions 112t and 112s are disposed together on the upper surface 421a of the CMOS chip 421. In this embodiment, the columnar portions 112t and 112s are arranged alternately.

[0164] In semiconductor device 12C, the structure of on-chip component 102 in the uppermost stacked unit 412c is the same as that of on-chip component 101.

[0165] The upper end 112a of the columnar portion 112t in the chip component 102 is exposed from the sealing resin 65.

[0166] (Effect)

[0167] By configuring columnar portions 112t and 112s to coexist on the upper surface 421a of the CMOS chip 421, a balance can be achieved between reducing the thermal resistance of columnar portion 112t to the heat dissipation path along the vertical direction and reducing the physical damage of columnar portion 112s to the CMOS chip 421.

[0168] (Second Implementation Method, Fourth Example)

[0169] Figure 14 This is a schematic diagram showing a cross-section parallel to the YZ plane of the semiconductor device 12D in the fourth example of the second embodiment. (As shown...) Figure 14 As shown, semiconductor device 12D and Figure 10 and Figure 11 The difference between the semiconductor device 12B of the second embodiment shown is that the columnar portion 112s is not provided above the CMOS chip 421 in the uppermost stacked unit.

[0170] In semiconductor device 12D, laminate 401 and Figure 10 as well as Figure 11Compared to the stack 401 shown, the topmost stack unit 412b is replaced by a stack unit 412d. Stack unit 412d is an example of stack unit 412.

[0171] Stacked element 412d and Figure 10 and Figure 11 Compared to the stacked unit 412b shown, it does not include the on-chip component 102.

[0172] That is, in the uppermost stacked unit 412d, no columnar portion 112 is provided on the upper surface 421a of the CMOS chip 421. The sealing resin 65 completely embeds the stack 401 above the wiring substrate 25.

[0173] (Effect)

[0174] By configuring the entire laminate 401 to be covered by the sealing resin 65, a certain amount of heat dissipation and moisture resistance can be ensured, thus ensuring reliability. In addition, compared with the semiconductor device 12B, the degree of freedom in adjusting the thickness of the sealing resin 65 above the CMOS chip 421 in the laminate 412d can be increased, thus controlling the warpage of the semiconductor device 12D.

[0175] Additionally, for example, when the heat sink or heat pipe is connected to the wiring substrate 25, the heat generated in the semiconductor device 12D can be dissipated to the heat sink or heat pipe in a simple structure.

[0176] (Fifth example of the second implementation method)

[0177] Figure 15 This is a schematic diagram showing a cross-section parallel to the YZ plane of the semiconductor device 12E in the fifth example of the second embodiment. Figure 15 As shown, semiconductor device 12E and Figure 8 and Figure 9 The difference between the semiconductor device 12 of the first example of the second embodiment shown is that a portion of the upper part of the columnar portion 112t protrudes from the upper surface of the sealing resin 65.

[0178] The semiconductor device 12E is formed, for example, by providing a film on the inner surface of a mold for molding, and filling the mold with sealing resin 65 while the front end of the columnar portion 112t is inserted into the film, thereby forming the semiconductor device 12E.

[0179] By grinding the upper surface of the sealing resin 65 in the semiconductor device 12E, it is possible to form Figure 8 The semiconductor device 12 shown.

[0180] [Third Implementation Method]

[0181] The semiconductor device 13 of the third embodiment will be described. Figure 16 This is a schematic diagram showing a cross-section of the semiconductor device 13 of the first example of the third embodiment, parallel to the YZ plane. Figure 17 This is a schematic diagram showing in detail the cross section of the stacked unit 413a of the first example of the third embodiment, parallel to the YZ plane.

[0182] like Figure 16 and Figure 17 As shown, the semiconductor device 13 of the third embodiment differs from the semiconductor device 11 of the first embodiment in that the chip components 101 and 102 include a resin layer on which a wire-shaped heat-conducting component is disposed.

[0183] In semiconductor device 13, laminate 401 and Figures 1-3 Compared to the semiconductor device 11 shown, it includes three stacked units 413a and 413b instead of three stacked units 411a and 411b. Hereinafter, stacked units 413a and 413b will sometimes be referred to as stacked unit 413.

[0184] The stacked units 413a, 413a, 413a and 413b are stacked sequentially from bottom to top.

[0185] On-chip component 101 in stacked cell 413a and Figures 1-3 Compared to the chip-on-chip component 101 in the stacked unit 411a shown, instead of the metal plate 111 and adhesive film 433, it includes a resin layer 432 (an example of a "first resin layer") and a plurality of columnar portions 113 (an example of a "thermal conductive component" and a "conductive component").

[0186] The columnar portion 113 has a higher thermal conductivity than the bare die adhesive film 431. Preferably, the columnar portion 113 has a higher thermal conductivity than the memory chip 422 or the CMOS chip 421. Alternatively, the columnar portion 113 may also have a thermal conductivity higher than 100 W / m / K.

[0187] Specifically, the columnar portion 113 may contain metals such as silver, copper, or gold. Furthermore, the columnar portion 113 may also contain carbon nanotubes (hereinafter sometimes referred to as CNTs). The thermal conductivity of CNTs is generally greater than 1000 W / m / K.

[0188] The columnar portion 113 extends in the vertical direction. In this embodiment, the columnar portion 113 extends substantially parallel to the Z-axis. The resin layer 432 is penetrated by a plurality of columnar portions 113. The upper end and lower end of the columnar portion 113 are exposed from the upper surface 432a and lower surface 432b of the resin layer 432, respectively.

[0189] The resin layer 432 is an elastomer or viscoelastic material that is thermoplastic and thermosetting. The elastic modulus of the resin layer 432 is, for example, 1 to 100 MPa. This ensures the orientation of the columnar portion 113 and maintains its flexibility. Alternatively, the elastic modulus of the resin layer 432 can be as high as approximately 5 GPa.

[0190] The resin layer 432 has a different composition from that of the sealing resin 65, the bare die adhesive film 431, and the adhesive film 433.

[0191] The upper surface 432a and the lower surface 432b are flat surfaces that are approximately parallel to the XY plane. The upper surface 432a and the lower surface 432b of the resin layer 432 are respectively in contact with the lower surface 421b of the CMOS chip 421 disposed above the resin layer 432 and the upper surface 421a of the CMOS chip 421 disposed below the resin layer 432.

[0192] The vertical position of the upper surface 432a of resin layer 432 is higher than the vertical position of the upper surface 422a of memory chip 422. The thickness of resin layer 432 is greater than the thickness of memory chip 422. With the upper surface 421a of CMOS chip 421 as a reference, the resin layer 432 is higher than the height of memory chip 422. The difference between the vertical position of upper surface 432a and upper surface 422a, i.e., the difference between the thickness (height) of resin layer 432 and the thickness (height) of memory chip 422, is approximately the thickness of the die bonding film 431.

[0193] The resin layer 432 penetrates the bare die adhesive film 431 in the stacked unit 413 of the layer directly above it and is in contact with the lower surface 421b of the CMOS chip 421. Alternatively, a thin film of the bare die adhesive film 431 may be provided between the upper surface 432a of the resin layer 432 and the lower surface 421b of the CMOS chip 421.

[0194] That is, two adjacent CMOS chips 421 in the vertical direction are bonded together by the resin layer 432.

[0195] Compared to the on-chip component 101 in the stacked unit 413a, the on-chip component 102 in the stacked unit 413b includes a resin layer 432h instead of a resin layer 432.

[0196] The resin layer 432h in the on-chip component 102 is thicker than the resin layer 432 in the on-chip component 101. With the upper surface 421a of the CMOS chip 421 as a reference, the height of the resin layer 432h is greater than the height of the memory chip 422. The other structures of the resin layer 432h are the same as those of the resin layer 432.

[0197] (Effect)

[0198] Compared to the semiconductor device 12, a resin layer 432 with a composition different from that of the sealing resin 65 can be provided between two adjacent CMOS chips 421 in the vertical direction.

[0199] For example, a flexible resin layer 432 can be provided between two adjacent CMOS chips 421 in the vertical direction. This improves the flexibility of the laminate 401, thus preventing the CMOS chips 421 from breaking during assembly.

[0200] In addition, by adjusting the glass transition temperature Tg of the resin layer 432 or by using a thermoplastic resin layer 432, the resin layer 432 can be softened by increasing the temperature.

[0201] The laminate 401 of the chip component 102, excluding the upper surface 432a of the resin layer 432h, and the upper surface 25a of the wiring substrate 25 are sealed with sealing resin 65.

[0202] (Second example of the third implementation method)

[0203] Figure 18 This is a schematic diagram showing in detail a cross-section parallel to the YZ plane of the stacked unit 413c in the second example of the third embodiment. (See attached diagram.) Figure 18 As shown, the stacked unit 413c and Figure 17 The difference between the stacked unit 413a of the first example of the third embodiment shown is that the size of the resin layer 432 is reduced, and other components are installed in the space freed up.

[0204] Stacked unit 413c and Figure 17 Compared to the stacked unit 413a shown, it includes a resin layer 432n and a device 424 instead of a resin layer 432.

[0205] Resin layer 432n and Figure 17 Compared to the resin layer 432 shown, the multiple columnar portions 113 are penetrated by the multiple columnar portions 113h instead of the multiple columnar portions 113.

[0206] The control circuit 421c in the CMOS chip 421 includes a heat-generating unit 421h. The heat-generating unit 421h can also be a boost circuit.

[0207] A resin layer 432n is disposed above the heating element 421h. The width of the resin layer 432n in the Y-axis direction is smaller than the width of the resin layer 432 in the Y-axis direction. The width of the resin layer 432n and the width of the device 424 are approximately the same as, for example, the width of the memory chip 422. The width of the resin layer 432n and the width of the device 424 are smaller than the width of the CMOS chip 421. The columnar portion 113h includes a metal portion 113a (an example of the "first portion") and a CNT portion 113b (an example of the "second portion").

[0208] The upper ends of the on-chip component 101 and the memory chip 422 are aligned. Specifically, the thickness of the on-chip component 101 is approximately the same as the thickness of the memory chip 422. With the upper surface 421a of the CMOS chip 421 as a reference, the height of the on-chip component 101 is approximately the same as the height of the memory chip 422. The upper surface 432a of the resin layer 432n and the upper surface 422a of the memory circuit 422c are surfaces approximately parallel to the XY plane. The vertical positions of the upper surface 432a and the upper surface 422c are approximately the same.

[0209] The metal portion 113a contains metals such as gold, silver, and copper. A CNT portion 113b is disposed between the metal portion 113a and the CMOS chip 421. The CNT portion 113b contains CNTs. Thus, by configuring the CNT portion 113b at both ends of the columnar portion 113h, the CMOS chip 421 can come into contact with the CNTs, thereby reducing the thermal contact resistance between the CMOS chip 421 and the columnar portion 113h.

[0210] Device 424 is an active component, a passive component, or a chip comprising both. Device 424 is disposed on the Y-axis side of resin layer 432n. Device 424 is bonded to the upper surface 421a of CMOS chip 421.

[0211] In the semiconductor device 13, a stacked unit 413c may be provided instead of at least one of the stacked units 413a and 413b.

[0212] Furthermore, in the semiconductor device 11, it is described that the stacked unit 411 is mounted across the upper surface 422a of the memory chip 422 in the lower stacked unit 411 and the upper surface of the on-chip component 101, but it is not limited to this. The stacked unit 411 may also be configured to be mounted on the upper surface of the on-chip component 101.

[0213] The following notes further disclose the description of the above-described embodiments.

[0214] [Postscript]

[0215] (a) A semiconductor device comprising:

[0216] Multiple first semiconductor chips are stacked vertically.

[0217] A first chip component is disposed on the upper surface of the lower first semiconductor chip between two adjacent first semiconductor chips in the vertical direction; and

[0218] Multiple second semiconductor chips are disposed on the upper surface of each of the multiple first semiconductor chips.

[0219] The first chip-on-a-chip component includes a thermally conductive component having a higher thermal conductivity than the first semiconductor chip.

[0220] (b) A semiconductor device comprising:

[0221] Multiple first semiconductor chips are stacked vertically.

[0222] A first chip component is disposed on the upper surface of the lower first semiconductor chip between two adjacent first semiconductor chips in the vertical direction; and

[0223] Multiple second semiconductor chips are disposed on the upper surface of each of the multiple first semiconductor chips.

[0224] The first chip-on-chip component includes a thermally conductive component with a thermal conductivity higher than 100 W / m / K.

[0225] (c) A semiconductor device comprising:

[0226] Multiple first semiconductor chips are stacked vertically.

[0227] A conductive component is disposed between two adjacent first semiconductor chips in the vertical direction; and

[0228] Multiple second semiconductor chips are disposed on the upper surface of each of the multiple first semiconductor chips.

[0229] The conductive component has a higher thermal conductivity than the second semiconductor chip.

[0230] (d) A semiconductor device comprising:

[0231] Multiple first semiconductor chips are stacked vertically.

[0232] The second resin layer is in contact with the lower surface of the first semiconductor chip;

[0233] A first chip component is disposed on the upper surface of the lower first semiconductor chip between two adjacent first semiconductor chips in the vertical direction; and

[0234] Multiple second semiconductor chips are disposed on the upper surface of each of the multiple first semiconductor chips.

[0235] The first chip-on-a-chip component includes a thermally conductive component having a higher thermal conductivity than the second resin layer.

[0236] The embodiments described above have been explained with reference to specific examples. However, this disclosure is not limited to these specific examples. Any design modifications made to these specific examples by those skilled in the art that possess the features of this disclosure are also included within the scope of this disclosure. The elements, their configurations, conditions, shapes, etc., of each of the above-described specific examples are not limited to the illustrated content and can be appropriately modified. The elements of each of the above-described specific examples can be appropriately combined as long as they do not create technical contradictions.

Claims

1. A semiconductor device comprising: Multiple first semiconductor chips are stacked vertically. A first chip component is disposed on the upper surface of the lower first semiconductor chip between two adjacent first semiconductor chips in the vertical direction; and Multiple second semiconductor chips are disposed on the upper surface of each of the multiple first semiconductor chips. The first on-chip component includes a thermally conductive component having a higher thermal conductivity than the second semiconductor chip.

2. The semiconductor device according to claim 1, wherein, The heat conduction component is a metal plate.

3. The semiconductor device according to claim 1, wherein, The heat-conducting component includes a columnar portion extending along the vertical direction.

4. The semiconductor device according to claim 3, wherein, The columnar portion contains metal.

5. The semiconductor device according to claim 3, wherein, The columnar portion contains carbon nanotubes.

6. The semiconductor device according to claim 3, wherein, The columnar portion includes: The first part contains metal; and The second part, disposed between the first part and the first semiconductor chip, contains carbon nanotubes.

7. The semiconductor device according to claim 3, wherein, The component on the first chip also includes a first resin layer penetrated by the columnar portion.

8. The semiconductor device according to claim 7, wherein, The upper and lower surfaces of the first resin layer are respectively in contact with the lower surface of the first semiconductor chip disposed above the first resin layer and the upper surface of the first semiconductor chip disposed below the first resin layer.

9. The semiconductor device according to claim 1, wherein, The component on the first chip is in contact with the lower surface of the first semiconductor chip disposed above it.

10. The semiconductor device according to claim 1, wherein, The components on the first chip are connected to the lower surface of the first semiconductor chip disposed above it via a second resin layer.

11. The semiconductor device according to claim 1, wherein, The top ends of the first on-chip component and the second semiconductor chip, which are positioned above the first semiconductor chip, are aligned.

12. The semiconductor device according to claim 1, wherein, The vertical position of the upper end of the first chip component disposed above the first semiconductor chip is higher than the vertical position of the upper end of the second semiconductor chip disposed on the upper surface of the first semiconductor chip.

13. The semiconductor device according to claim 2, wherein, The metal plate is electrically connected to the terminal in the first semiconductor chip that is supplied with a reference potential.

14. The semiconductor device according to claim 2, wherein, The metal plate is in an electro-floating state.

15. The semiconductor device according to claim 1, wherein, The semiconductor device also includes: Sealing resin, for sealing at least a plurality of first semiconductor chips; and The second chip component is disposed on the upper surface of the first semiconductor chip, which is the topmost layer. The components on the second chip are exposed from the sealing resin.

16. The semiconductor device according to claim 1, wherein, The first semiconductor chip includes bonding pads disposed on its upper surface. The semiconductor device also includes: A wiring substrate is disposed below the bottommost first semiconductor chip; and Bonding wires connect the multiple bonding pads and wiring substrates of each of the multiple first semiconductor chips.

17. The semiconductor device according to claim 1, wherein, A first pad is provided on the upper surface of the first semiconductor chip. A second pad is provided on the lower surface of the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are bonded together by joining the first pad and the second pad.

18. A semiconductor memory device, Having the semiconductor device of claim 1, The second semiconductor chip includes a memory circuit having a non-volatile memory region. The first semiconductor chip includes a control circuit for controlling the memory circuit.

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