Wafer structure and method for manufacturing power semiconductor device

Abstract

The disclosure provides a wafer structure and a power semiconductor device manufacturing method, and belongs to the field of semiconductor devices. The wafer structure comprises: a plurality of chips, each of which is provided with a sealing ring at the periphery, and a dicing lane is arranged between two adjacent chips; at least one temporary connection structure is arranged in the dicing lane, and the two ends of the temporary connection structure are electrically connected to the sealing rings of two adjacent chips respectively; wherein the temporary connection structure maintains the equipotential state between the sealing rings of two adjacent chips before the wafer dicing process, and the temporary connection structure is configured to be cut off in the wafer dicing process, so that the sealing rings of each chip are electrically isolated from each other after dicing, and the temporary connection structure no longer exists in any chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor devices, and in particular to a wafer structure and a method for fabricating power semiconductor devices. Background Technology

[0002] Gallium nitride on silicon is widely used in the semiconductor field, such as in power semiconductor devices.

[0003] In the manufacturing process of gallium nitride power semiconductor devices, dielectric etching (for SiO2, SiN) is crucial. x (x > 0) passivation and dielectric layer are key process steps to ensure device insulation, etc. At present, the industry generally uses inductively coupled plasma (ICP) or capacitively coupled plasma (CCP) dry etching technology. This process is also the core link that leads to electrostatic breakdown between chips (dies). Summary of the Invention

[0004] After wafer fabrication, a dicing process is required to divide the wafer into individual chips. During dicing, the seal rings of each chip are electrically suspended. Because each chip may have accumulated static charges at different potentials during previous manufacturing processes (such as plasma etching, ion implantation, and chemical mechanical polishing), electrostatic discharge (ESD) can occur during dicing when there is a potential difference between the seal rings, damaging the internal structure of the chip. Current process technologies can only mitigate charge accumulation by fine-tuning etching parameters, but cannot eliminate the potential difference between the seal rings, thus failing to completely solve the ESD problem. This has become a core process bottleneck in the mass production of gallium nitride (GaN) devices.

[0005] This disclosure provides a wafer structure and a method for fabricating power semiconductor devices. During wafer dicing, it addresses the electrostatic breakdown (ESD) problem caused by the potential difference between the electrically floating sealing rings of each chip during the die dicing process, thus mitigating the risk of ESD during dielectric etching. The technical solution is as follows: On one hand, a wafer structure is provided, the wafer structure comprising: Multiple chips, each chip having a sealing ring around its periphery, and a dicing track between two adjacent chips; At least one temporary connection structure is disposed within the dicing channel, and the two ends of the temporary connection structure are electrically connected to the sealing rings of two adjacent chips, respectively; The temporary connection structure maintains an equipotential state between the sealing rings of two adjacent chips before the wafer dicing process. The temporary connection structure is configured to be cut off during the wafer dicing process, so that the sealing rings of each chip are electrically isolated from each other after dicing, and the temporary connection structure no longer exists in any of the chips.

[0006] Optionally, the wafer structure includes a channel layer, a barrier layer, a source / drain metal layer, and a passivation layer; The channel layer includes multiple chip active regions arranged in an array, and multiple sealing ring active regions arranged around the multiple chip active regions respectively. The source and drain metal layer includes multiple sets of source and drain electrodes that are in contact with the active regions of the multiple chips respectively, and multiple sealing rings that are in contact with the active regions of the multiple sealing rings respectively. Any two adjacent sealing rings are electrically connected through a temporary connection structure.

[0007] Optionally, the temporary connection structure is a connection active region in the channel layer, and the connection active region and the two sealing ring active regions corresponding to the two adjacent sealing rings are an integral structure.

[0008] Optionally, the temporary connection structure is a connecting metal in the source / drain metal layer, and the connecting metal and the two adjacent sealing rings are an integral structure.

[0009] Optionally, the temporary connection structure is elongated, with a width of 200 nanometers to 500 micrometers and a length of 30 to 150 micrometers.

[0010] On the other hand, a method for fabricating a power semiconductor device is provided, the method comprising: A wafer is provided, on which a plurality of chips are formed, each chip having a sealing ring around its periphery and a dicing track being provided between two adjacent chips; A temporary connection structure is formed within the dicing channel, and the two ends of the temporary connection structure are electrically connected to the sealing rings of two adjacent chips, so that the sealing rings of the two adjacent chips maintain an equipotential state. The wafer dicing process is performed, cutting the wafer along the dicing track. During the dicing process, the temporary connection structure is cut off, so that the sealing rings of each chip are electrically isolated from each other after dicing, and the temporary connection structure no longer exists in any of the chips.

[0011] Optionally, the wafer structure includes a channel layer, a barrier layer, a source / drain metal layer, and a passivation layer; The channel layer includes multiple chip active regions arranged in an array, and multiple sealing ring active regions arranged around the multiple chip active regions respectively. The source and drain metal layer includes multiple sets of source and drain electrodes that are in contact with the active regions of the multiple chips respectively, and multiple sealing rings that are in contact with the active regions of the multiple sealing rings respectively. Any two adjacent sealing rings are electrically connected through a temporary connection structure.

[0012] Optionally, the temporary connection structure is a connection active region in the channel layer, and the connection active region and the two sealing ring active regions corresponding to the two adjacent sealing rings are an integral structure.

[0013] Optionally, the temporary connection structure is a connecting metal in the source / drain metal layer, and the connecting metal and the two adjacent sealing rings are an integral structure.

[0014] Optionally, the temporary connection structure is elongated, with a width of 200 nanometers to 500 micrometers and a length of 30 to 150 micrometers.

[0015] The beneficial effects of the technical solutions provided in this disclosure are: In this embodiment, any two adjacent seal rings are electrically connected via a temporary connection structure, temporarily electrically connecting the seal rings of all dies on the wafer. This ensures that all seal rings form an equipotential whole during the dielectric etching process, completely eliminating the potential difference caused by charge accumulation and mitigating the risk of electrostatic breakdown at its source. This temporary connection structure is only a temporary process protection structure and will be completely severed during subsequent dicing. It does not affect the final electrical isolation and normal function of a single chip, leaves no residue in any chip, introduces no permanent structure, and has zero impact on the normal operation of the chip. The temporary connection structure of this embodiment is fully compatible with existing processes: Scheme 1 is formed simultaneously with the active region implantation process, and Scheme 2 is formed simultaneously with the metal interconnect process, both requiring no additional process steps. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a power semiconductor device provided in an embodiment of this disclosure; Figure 2 yes Figure 1 A schematic diagram of the cross-section of line A-A'; Figure 3 This is a schematic diagram of the structure of a channel layer provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of a source / drain metal layer provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of another power semiconductor device provided in an embodiment of this disclosure; Figure 6 yes Figure 5 A schematic diagram of a cross section of line A-A'; Figure 7 This is a schematic diagram of another channel layer structure provided in an embodiment of this disclosure; Figure 8 yes Figure 5 Another cross-sectional diagram of line A-A'; Figure 9 This is a schematic diagram of another source / drain metal layer structure provided in an embodiment of this disclosure; Figure 10 This is a flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of this disclosure; Figure 11 This is a flowchart of another method for fabricating a power semiconductor device provided in this disclosure.

[0018] Figure label: 100: Chip; 101: Channel layer; 102: Barrier layer; 103: Source / drain metal layer; 104: Passivation layer; 111: Active region of chip; 112: Active region of sealing ring; 131: Source / drain; 200: Sealing ring; 300: Die-etching track; 400: Temporary connection structure. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] Figure 1 This is a schematic diagram of a wafer structure provided in an embodiment of this disclosure. See also... Figure 1 The wafer structure is the structure during the wafer manufacturing process, that is, it is not the final structure of the device. During the wafer manufacturing process, multiple chips 100 are formed. Each chip 100 is provided with a sealing ring 200 around its periphery, and a dicing track 300 is provided between two adjacent chips.

[0021] Figure 2 yes Figure 1 A schematic diagram of the cross-section of line A-A'. (See diagram below.) Figure 2 As shown, the wafer structure includes a channel layer 101, a barrier layer 102, a source / drain metal layer 103, and a passivation layer 104.

[0022] The barrier layer 102 is located on the channel layer 101. The source / drain metal layer 103 is in contact with the barrier layer 102 or passes through the barrier layer 102 to contact the channel layer 101. The passivation layer 104 is located on the barrier layer 102 and covers the portion of the source / drain metal layer 103 that is exposed on the barrier layer 102.

[0023] Figure 3 This is a schematic diagram of a channel layer structure provided in an embodiment of this disclosure. Figure 3 As shown, the channel layer 101 includes a plurality of chip active regions 111 arranged in an array, and a plurality of sealing ring active regions 112 arranged around the plurality of chip active regions 111 respectively.

[0024] Figure 4 This is a schematic diagram of the structure of a source / drain metal layer provided in an embodiment of this disclosure. For example... Figure 4 As shown, the source / drain metal layer 103 includes multiple sets of source / drain electrodes 131 that are respectively in contact with the multiple active regions 111 of the chips, and multiple sealing rings 200 that are respectively in contact with the multiple active regions 112 of the sealing rings.

[0025] In this embodiment of the disclosure, the chip 100 on the wafer is isolated from other chips through the chip active region 111 and the source-drain electrode 131.

[0026] In this embodiment of the disclosure, the sealing ring 200 and the active region 112 of the sealing ring on the wafer together constitute an isolation structure.

[0027] In this embodiment, the dicing channel 300 is formed on the passivation layer 104, i.e., it is formed by etching through ICP or CCP process.

[0028] During the aforementioned dry dielectric etching process, the radio frequency power supply ionizes the reactive gas within the cavity to form high-energy plasma. Electrons and ions, accelerated by the electric field, continuously bombard the wafer surface, completing the dielectric layer etching while simultaneously generating a large amount of non-equilibrium free charge on the wafer surface. The sealing rings surrounding each chip within the wafer dicing channel are made of metal and possess parasitic capacitance characteristics, acting as natural charge accumulation carriers. Since each sealing ring is segmented and isolated from the others, with no electrical connection, the charge cannot be discharged and continues to accumulate on individual sealing rings (as shown in Figure B). Furthermore, the plasma etching process itself introduces in-wafer surface uniformity differences, resulting in significant differences in charge accumulation and charge polarity between different sealing ring regions, directly leading to a significant potential difference between adjacent sealing rings. When this potential difference exceeds the breakdown field strength of the intermediate insulating dielectric layer (typically SiO2 and SiN), the charge can accumulate. xWhen the dielectric breakdown field strength is 5~10MV / cm, irreversible electrostatic breakdown of the dielectric will be triggered, forming a conductive channel (as shown by the dashed line between B and B in the figure), which directly causes the failure of internal devices of the chip and short circuits between chips, significantly reducing the overall yield of the wafer and seriously affecting the stability of mass production.

[0029] In conventional technologies, charge accumulation can be mitigated by fine-tuning etching parameters, but the potential difference between the sealing rings cannot be eliminated, and the electrostatic breakdown problem cannot be completely solved, making it a core process pain point in the mass production of gallium nitride (GaN) devices.

[0030] Therefore, this disclosure provides another wafer structure, which, compared to... Figures 1 to 4 The device also includes at least one temporary connection structure disposed within the dicing channel, wherein the two ends of the temporary connection structure are electrically connected to the sealing rings of two adjacent chips, respectively.

[0031] The temporary connection structure maintains an equipotential state between the sealing rings of two adjacent chips before the wafer dicing process. The temporary connection structure is configured to be cut off during the wafer dicing process, so that the sealing rings of each chip are electrically isolated from each other after dicing, and the temporary connection structure no longer exists in any of the chips.

[0032] Temporary connection structures refer to temporary structures that exist during wafer manufacturing and are cut off during dicing.

[0033] It should be noted that "the temporary connection structure no longer exists in any of the chips" means that the complete temporary connection structure no longer exists in any of the chips, but some of it will remain near the sealing ring of the chip after dicing.

[0034] In this embodiment, any two adjacent seal rings are electrically connected via a temporary connection structure, temporarily electrically connecting the seal rings of all dies on the wafer. This ensures that all seal rings form an equipotential whole during the dielectric etching process, completely eliminating the potential difference caused by charge accumulation and mitigating the risk of electrostatic breakdown at its source. This temporary connection structure is only a temporary process protection structure and will be completely severed during subsequent dicing. It does not affect the final electrical isolation and normal function of a single chip, leaves no residue in any chip, introduces no permanent structure, and has zero impact on the normal operation of the chip. The temporary connection structure of this embodiment is fully compatible with existing processes: Scheme 1 is formed simultaneously with the active region implantation process, and Scheme 2 is formed simultaneously with the metal interconnect process, both requiring no additional process steps.

[0035] Figure 5 This is a schematic diagram of another wafer structure provided in an embodiment of this disclosure. See also... Figure 5The wafer structure is a structure formed during the wafer manufacturing process, that is, it is not the final structure of the device. During the wafer manufacturing process, multiple chips 100 and sealing rings 200 surrounding the multiple chips 100 are formed. The sealing rings 200 are separated by dicing channels 300. The temporary connection structure 400 passes through the dicing channels 300 and is electrically connected to two adjacent sealing rings 200.

[0036] Figure 6 yes Figure 5 A schematic diagram of a cross-section of line A-A'. For example... Figure 6 As shown, the temporary connection structure 400 is the active connection region in the channel layer 101.

[0037] Figure 7 This is a schematic diagram of another channel layer structure provided in an embodiment of this disclosure. For example... Figure 7 As shown, the channel layer 101 includes a plurality of chip active regions 111 arranged in an array, a plurality of sealing ring active regions 112 arranged around the plurality of chip active regions 111 respectively, and a connection active region (temporary connection structure 400) that is an integral structure of two sealing ring active regions 112 corresponding to two adjacent sealing rings 200.

[0038] In this implementation, during the device layout design phase, active region connection structures are deployed within the dicing lanes. When the active region ion implantation process is carried out, adjacent sealing rings are connected, and all sealing rings on the entire wafer form a continuous closed equipotential network through the channel layer.

[0039] It should be noted that the channel layer 111 is a full-length mask layer. Figure 7 The shape shown is the active region shape. The active region refers to the area that has not undergone ion implantation, while the area outside the active region is the ion implantation region, also known as the insulating region. He, N, B, and other ions can be used for ion implantation.

[0040] like Figure 7 As shown, the active area (temporary connection structure 400) can be of any shape, such as a long strip, or the active area (temporary connection structure 400) can be covered with the slab track.

[0041] When the active connection region (temporary connection structure 400) can be elongated, the width of the elongated active connection region can be 200 nanometers to 500 micrometers, and the length can be 30 to 150 micrometers.

[0042] For example, the width of the elongated active region is 10 or 100 micrometers, and the length is 50 or 100 micrometers.

[0043] In this implementation, the temporary connection structure is located entirely within the dicing channel, and its width and length conform to the Design Rule Checking (DRC) to ensure that a low-resistance conductive channel is formed after injection, achieving stable conduction between the sealing rings. After the dielectric etching is completed, during subsequent mechanical or laser dicing, the injected temporary connection structure will be completely cut off along with the dicing channel, and each sealing ring will return to an independent isolation state, without affecting the single-chip performance.

[0044] In other embodiments, the active connection area (temporary connection structure 400) may also be of other shapes, such as arcs, wavy lines, etc.

[0045] like Figure 7 As shown, an active connection region (temporary connection structure 400) may also be included between adjacent isolation rings.

[0046] In other embodiments, adjacent isolation rings may also include multiple spaced-apart active connection regions (temporary connection structures 400).

[0047] like Figure 7 As shown, the active region 111 of the chip is rectangular in shape, and the active region 112 of the sealing ring is a rectangular ring.

[0048] The length direction of the active area (temporary connection structure 400) is perpendicular to the side of the active area 112 of the sealing ring.

[0049] In other embodiments, the length direction of the active region (temporary connection structure 400) may not be perpendicular to the side of the active region 112 of the sealing ring.

[0050] In other embodiments, the active region 111 of the chip can be other shapes, such as a circle; the active region 112 of the sealing ring can be other shapes, such as a ring.

[0051] exist Figure 6 In the wafer structure shown, the shape of the source / drain metal layer 103 can be consistent with... Figure 4 same.

[0052] like Figure 4 As shown, the sealing ring 200 is a rectangular ring.

[0053] In other embodiments, the sealing ring 200 may be other shapes, such as a circular ring.

[0054] Figure 8 yes Figure 5 Another cross-sectional diagram of line A-A'. (See diagram below.) Figure 8 As shown, the temporary connection structure 400 is the connection metal in the source / drain metal layer 103.

[0055] Figure 9 This is a schematic diagram of another source / drain metal layer structure provided in an embodiment of this disclosure. For example... Figure 9 As shown, the source / drain metal layer 103 includes multiple sets of source / drain electrodes 131 that are respectively in contact with the multiple active regions 111 of the chips, multiple sealing rings 200 that are respectively in contact with the multiple active regions 112 of the sealing rings, and a connecting metal (temporary connection structure 400) that is integral with two adjacent sealing rings 200.

[0056] In this implementation, during the device layout design phase, connecting metals are deployed in the dicing lanes to connect adjacent sealing rings, and all sealing rings on the entire wafer form a continuous closed equipotential network through the source and drain metal layers.

[0057] exist Figure 8 In the wafer structure shown, the shape of the channel layer 101 can be consistent with... Figure 3 same.

[0058] like Figure 9 As shown, the connecting metal (temporary connection structure 400) can be elongated, with a width of 200 nanometers to 500 micrometers and a length of 30 to 150 micrometers.

[0059] For example, the width of the elongated active region is 10 or 100 micrometers, and the length is 50 or 100 micrometers.

[0060] In this implementation, the temporary connection structure is located entirely within the dicing channel, and its width and length conform to DRC, ensuring the formation of a low-resistance conductive channel after injection and achieving stable conduction between the sealing rings. After the dielectric etching is completed, during subsequent mechanical or laser dicing processes, the injection temporary connection structure will be completely cut off along with the dicing channel, and each sealing ring will return to an independent isolation state, without affecting the single-chip performance.

[0061] In other embodiments, the connecting metal (temporary connection structure 400) may also be in other shapes, such as arcs, wavy lines, etc.

[0062] like Figure 9 As shown, a connecting metal (temporary connection structure 400) may also be included between adjacent isolation rings.

[0063] In other embodiments, adjacent isolation rings may also include multiple spaced-apart connecting metals (temporary connection structures 400).

[0064] like Figure 9 As shown, the sealing ring 200 is a rectangular ring.

[0065] The length direction of the connecting metal (temporary connection structure 400) is perpendicular to the connected side of the sealing ring 200.

[0066] In other embodiments, the length direction of the connecting metal (temporary connection structure 400) may not be perpendicular to the side of the sealing ring 200 that is connected to it.

[0067] In other embodiments, the sealing ring 200 may be other shapes, such as a circular ring.

[0068] like Figure 8 As shown, the source / drain metal layer 103 can be a multi-layer structure, that is, the source / drain metal layer 103 includes multiple stacked metal layers.

[0069] For example, Figure 8 The source drain metal layer 103 includes four stacked metal layers, which are designated as the first layer, second layer, third layer, and fourth layer from closest to furthest from the channel layer. Figure 8 The intermediate connecting metal (temporary connection structure 400) is arranged on the second layer.

[0070] In other embodiments, the connecting metal (temporary connection structure 400) may be arranged in other metal layers, such as the first layer, the third layer, or the fourth layer.

[0071] also, Figure 6 and Figure 8 The solutions can be used in combination, that is, the temporary connection structure 400 is designed in both the channel layer and the source / drain metal layer.

[0072] In addition to the film layers included in the above figures, the wafer structure also includes a gate metal layer located on the barrier layer, which includes a gate corresponding to each chip.

[0073] The wafer structure may also include a substrate, with the channel layer located on the substrate.

[0074] The wafer structure may also include a buffer layer located between the substrate and the channel layer.

[0075] The wafer structure may also include other film layers, which will not be elaborated here.

[0076] In this embodiment of the disclosure, the substrate may be a single-crystal substrate or a composite substrate.

[0077] For example, the substrate is a Si substrate or a sapphire substrate.

[0078] In this embodiment of the disclosure, the buffer layer may be a GaN layer.

[0079] In this embodiment of the disclosure, the buffer layer can be an AlN layer.

[0080] In this embodiment of the disclosure, the channel layer 101 may be a GaN layer.

[0081] In this embodiment of the disclosure, the barrier layer 102 can be an AlGaN layer.

[0082] In this embodiment of the disclosure, the source / drain metal layer 103 can be a metal stack, such as a Ti / Al / TiN stack.

[0083] In this embodiment of the disclosure, the passivation layer 104 can be a SiN or SiO2 layer.

[0084] In one example of this disclosure, the chip is a power semiconductor device, such as a high electron mobility transistor (HEMT).

[0085] In another example of this disclosure, the chip is a power semiconductor device, such as a power diode or other types of transistors.

[0086] Figure 10 This is a flowchart illustrating a method for fabricating a power semiconductor device according to an embodiment of this disclosure. See also... Figure 10 The method includes the following steps: 301. A wafer is provided, on which a plurality of chips are formed, each chip having a sealing ring around its periphery, and a dicing track being provided between two adjacent chips.

[0087] 302. A temporary connection structure is formed within the dicing channel, and the two ends of the temporary connection structure are electrically connected to the sealing rings of two adjacent chips, so that the sealing rings of the two adjacent chips maintain an equipotential state.

[0088] Steps 301 and 302 may not have a clear sequential relationship; for example, the temporary connection structure of step 302 may be prepared during the wafer fabrication process.

[0089] 303. Perform a wafer dicing process, dicing the wafer along the dicing track, and cutting the temporary connection structure during the dicing process, so that the sealing rings of each chip are electrically isolated from each other after dicing, and the temporary connection structure no longer exists in any of the chips.

[0090] In this embodiment, any two adjacent seal rings are electrically connected via a temporary connection structure, temporarily electrically connecting the seal rings of all dies on the wafer. This ensures that all seal rings form an equipotential whole during the dielectric etching process, completely eliminating the potential difference caused by charge accumulation and mitigating the risk of electrostatic breakdown at its source. This temporary connection structure is only a temporary process protection structure and will be completely severed during subsequent dicing. It does not affect the final electrical isolation and normal function of a single chip, leaves no residue in any chip, introduces no permanent structure, and has zero impact on the normal operation of the chip. The temporary connection structure of this embodiment is fully compatible with existing processes: Scheme 1 is formed simultaneously with the active region implantation process, and Scheme 2 is formed simultaneously with the metal interconnect process, both requiring no additional process steps.

[0091] Figure 11 This is a flowchart illustrating another method for fabricating a power semiconductor device according to an embodiment of this disclosure. See also... Figure 11 The flowchart of this method includes: 401. Provide a substrate.

[0092] In this embodiment of the disclosure, the substrate may be a single-crystal substrate or a composite substrate.

[0093] For example, the substrate is a Si substrate or a sapphire substrate.

[0094] Optionally, the method may further include: The substrate is placed in the metal-organic chemical vapor deposition (MOCVD) reaction chamber used for nitride epitaxy. Hydrogen gas is introduced as a carrier gas and the substrate temperature is raised to 1000℃~1100℃. The high temperature decomposes the oxide on the substrate surface to obtain a clean surface.

[0095] For example, a clean silicon surface is obtained by placing a silicon substrate in an MOCVD process, raising the substrate temperature to 1050°C, and treating it in an H2 atmosphere for 5-10 minutes.

[0096] 402. Fabricate a buffer layer on the substrate.

[0097] In one example, step 402 may include: An AlN buffer layer is deposited on the substrate.

[0098] 403. Construct a channel layer and a barrier layer sequentially on the buffer layer.

[0099] In this embodiment of the disclosure, the channel layer 101 may be a GaN layer.

[0100] In one example, the channel layer forms multiple chip active regions 111 arranged in an array by an ion implantation process, multiple sealing ring active regions 112 arranged around the multiple chip active regions 111 respectively, and a connection active region (temporary connection structure 400) that is an integral structure of two sealing ring active regions 112 corresponding to two adjacent sealing rings 200.

[0101] In another example, the channel layer is formed by an ion implantation process to form a plurality of chip active regions 111 arranged in an array, and a plurality of sealing ring active regions 112 arranged around the plurality of chip active regions 111 respectively.

[0102] During ion implantation, by blocking the corresponding region of the active region, other regions are implanted, forming an insulating layer in those other regions.

[0103] He, N, B, and other ions can be used for ion implantation.

[0104] In this embodiment of the disclosure, the barrier layer 102 can be an AlGaN layer.

[0105] 404. Fabricate source / drain metal layers on the barrier layer.

[0106] The source / drain metal layer is in contact with the barrier layer or passes through the barrier layer to contact the channel layer.

[0107] In this embodiment of the disclosure, the source / drain metal layer 103 can be a metal stack, such as a Ti / Al / TiN stack.

[0108] In one example, the source / drain metal layer 103 includes multiple sets of source / drain electrodes 131 that are respectively in contact with the multiple active regions 111 of the chips, and multiple sealing rings 200 that are respectively in contact with the multiple active regions 112 of the sealing rings.

[0109] In another example, the source / drain metal layer 103 includes multiple sets of source / drain electrodes 131 that are respectively in contact with the multiple active regions 111 of the chips, multiple sealing rings 200 that are respectively in contact with the multiple active regions 112 of the sealing rings, and a connection metal (temporary connection structure 400) that is integral with two adjacent sealing rings 200.

[0110] For example, step 404 may include: Step 1 (optional): Deposit an insulating layer on the barrier layer.

[0111] The second step is to create vias in the insulating layer that extend to the barrier layer or channel layer.

[0112] The aforementioned through holes are made at the positions of the source / drain electrodes and the sealing ring.

[0113] The third step is to create the source and drain metal layers.

[0114] In one example, the third step includes: Step 1: Form a mask layer on the insulating layer. The mask layer has grooves.

[0115] This groove corresponds to the location where the source / drain metal layer needs to form metal.

[0116] Step 2: Under the cover of the mask layer, evaporate the source leak metal.

[0117] Step 3: Remove the mask layer and the source / drain metal on the mask layer.

[0118] When the source / drain metal layer comprises multiple stacked metal layers, repeat steps 1 to 3 above.

[0119] In another example, the third step includes: Step 1: Deposit source and drain metal films by physical vapor deposition (PVD).

[0120] When the source / drain metal layer comprises multiple stacked metal layers, repeat step 1 above.

[0121] Step 2: The source / drain metal film is processed by photolithography and etching to form the source / drain metal layer.

[0122] In the two examples above, the photoresists used are different. In the first example, the mask layer uses negative photoresist, while in the second example, positive photoresist is used for photolithography.

[0123] The fourth step is to form ohmic contacts through annealing.

[0124] When the source / drain metal layer includes a connecting metal, the mask layer corresponding to the metal layer containing the connecting metal has more grooves than the mask layer corresponding to other metal layers, and the extra part corresponds to the location of the connecting metal.

[0125] Optionally, the method further includes forming a gate metal layer, the fabrication process of which is similar to that of the source / drain metal layers, and will not be described in detail here.

[0126] 405. Create a passivation layer.

[0127] The passivation layer is located on the barrier layer and covers the portion of the source / drain metal layer that is exposed above the barrier layer.

[0128] In this embodiment of the disclosure, the passivation layer 104 can be a SiN or SiO2 layer.

[0129] For example, step 405 may include: Deposited passivation layer film; The passivation layer is etched using ICP or CCP processes to form scribe lines.

[0130] 406. Perform a wafer dicing process, dicing the wafer along the dicing track, and cutting the temporary connection structure during the dicing process, so that the sealing rings of each chip are electrically isolated from each other after dicing, and the temporary connection structure no longer exists in any of the chips.

[0131] This dicing process separates multiple chips.

[0132] The solution provided in this disclosure, in addition to solving the electrostatic breakdown problem and significantly improving yield, also has the following advantages: Process compatible, no additional cost: Only the layout needs to be adjusted during the layout design stage. No new process steps such as photolithography, etching, or deposition are added. Existing equipment parameters and process sequence are not changed. There are no process development costs, and the manufacturing cost of a single chip will not increase. It is compatible with the existing GaN device manufacturing process.

[0133] It does not occupy the effective chip area: all temporary connection structures are arranged in the dicing area, without intruding into the active area and functional circuit area inside the chip, and do not affect the device size, integration and core electrical performance, and are compatible with the layout of various high voltage and RF GaN power devices.

[0134] Improving overall device reliability: The equipotential sealing ring network not only solves the problem of static electricity accumulation during the etching stage, but also effectively resists the electrostatic discharge (ESD) impact during subsequent cleaning, sputtering, and packaging processes, reducing electrostatic damage throughout the process and improving the long-term reliability and ESD resistance of the device.

[0135] Flexible design and strong adaptability: It provides two implementation paths, active region injection and metal strip bridging, which can be flexibly selected according to different GaN process platforms and product types. The two solutions can be used alone or in combination, with a wide range of applications and strong mass production capability.

[0136] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A wafer structure, characterized in that, The wafer structure includes: Multiple chips (100), each chip (100) has a sealing ring (200) around its periphery, and a dicing channel (300) is provided between two adjacent chips. At least one temporary connection structure (400) is disposed within the dicing channel (400), and the two ends of the temporary connection structure (400) are electrically connected to the sealing rings (200) of two adjacent chips (100). The temporary connection structure (400) maintains the equipotential state between the sealing rings (200) of two adjacent chips (100) before the wafer dicing process. The temporary connection structure (400) is configured to be cut off during the wafer dicing process, so that the sealing rings (200) of each chip (100) are electrically isolated from each other after dicing, and the temporary connection structure (400) no longer exists in any of the chips (100).

2. The wafer structure according to claim 1, characterized in that, The wafer structure includes a channel layer (101), a barrier layer (102), a source / drain metal layer (103), and a passivation layer (104). The channel layer (101) includes a plurality of chip active regions (111) arranged in an array, and a plurality of sealing ring active regions (112) arranged around the plurality of chip active regions (111). The source and drain metal layer (103) includes multiple sets of source and drain electrodes (131) that are in contact with the multiple active regions (111) of the chip respectively, and multiple sealing rings (200) that are in contact with the multiple active regions (112) of the sealing ring respectively. Any two adjacent sealing rings (200) are electrically connected by a temporary connection structure (400).

3. The wafer structure according to claim 2, characterized in that, The temporary connection structure (400) is the active connection area in the channel layer (101), and the active connection area and the two active sealing ring areas (112) corresponding to the two adjacent sealing rings (200) are an integral structure.

4. The wafer structure according to claim 2, characterized in that, The temporary connection structure (400) is the connecting metal in the source / drain metal layer (103), and the connecting metal and the two adjacent sealing rings (200) are an integral structure.

5. The wafer structure according to any one of claims 1 to 4, characterized in that, The temporary connection structure (400) is elongated, with a width of 200 nanometers to 500 micrometers and a length of 30 to 150 micrometers.

6. A method for fabricating a power semiconductor device, characterized in that, The method includes: A wafer is provided, on which a plurality of chips are formed, each chip having a sealing ring around its periphery and a dicing track being provided between two adjacent chips; A temporary connection structure is formed within the dicing channel, and the two ends of the temporary connection structure are electrically connected to the sealing rings of two adjacent chips, so that the sealing rings of the two adjacent chips maintain an equipotential state. The wafer dicing process is performed, cutting the wafer along the dicing track. During the dicing process, the temporary connection structure is cut off, so that the sealing rings of each chip are electrically isolated from each other after dicing, and the temporary connection structure no longer exists in any of the chips.

7. The method according to claim 6, characterized in that, The wafer structure includes a channel layer, a barrier layer, source / drain metal layers, and a passivation layer; The channel layer includes multiple chip active regions arranged in an array, and multiple sealing ring active regions arranged around the multiple chip active regions respectively. The source and drain metal layer includes multiple sets of source and drain electrodes that are in contact with the active regions of the multiple chips respectively, and multiple sealing rings that are in contact with the active regions of the multiple sealing rings respectively. Any two adjacent sealing rings are electrically connected through a temporary connection structure.

8. The method according to claim 7, characterized in that, The temporary connection structure is the active connection region in the channel layer, and the active connection region and the active regions of the two adjacent sealing rings are an integral structure.

9. The method according to claim 7, characterized in that, The temporary connection structure is the connecting metal in the source / drain metal layer, and the connecting metal and the two adjacent sealing rings are an integral structure.

10. The method according to any one of claims 6 to 9, characterized in that, The temporary connection structure is elongated, with a width of 200 nanometers to 500 micrometers and a length of 30 to 150 micrometers.

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