Alignment mark structure, method of manufacturing semiconductor structure, and semiconductor structure

Abstract

The application relates to an alignment mark structure, a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises the following steps: providing a substrate, a first dielectric layer is formed on the substrate, the upper surface of the first dielectric layer has a first upper surface part and a second upper surface part, the first upper surface part is higher than the second upper surface part; a conductive material layer is distributed on the upper surface of the first dielectric layer in a conformal mode; a patterning etching process is performed to remove the conductive material layer between the first upper surface part and the second upper surface part, thereby forming an alignment mark structure on the first upper surface part and a conductive circuit layer on the second upper surface part; a second dielectric layer is formed on the alignment mark structure, the conductive circuit layer and the exposed first dielectric layer; and a planarization process is performed, the alignment mark structure is taken as a polishing stop layer, and the second dielectric layer is thinned to expose at least part of the upper surface of the alignment mark structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an alignment mark structure, a method for preparing a semiconductor structure, and a semiconductor structure. Background Technology

[0002] Alignment marker structures can be used to provide a spatial positioning reference for semiconductor structures that can be identified by an optical alignment system during subsequent packaging processes. In a typical application scenario, alignment marker structures can be fabricated on the surface of a display driver chip to establish a relative positional reference between the chip and the glass substrate.

[0003] In the fabrication of a typical semiconductor structure, alignment mark structures can be formed simultaneously with the top conductive material layer in the top region of the semiconductor structure and covered by a dielectric material layer (such as a silicon oxide layer). Subsequently, by introducing a separate photomask layer and corresponding etching steps, the silicon oxide layer above the alignment mark structure is selectively removed, thereby exposing the alignment mark structure for optical identification during the packaging process.

[0004] In the aforementioned method of defining and etching alignment mark structures using independent photomasks, the surface of the conductive material layer exposed to the etching environment is prone to over-etching, resulting in corrosion defects. These corrosion defects are difficult to completely eliminate even in subsequent cleaning steps, potentially causing detectable changes in the morphology of the alignment mark structure and consequently affecting the stability of the optical alignment system in recognizing the mark edges.

[0005] Furthermore, after depositing the silicon nitride (SiN) layer and before introducing a separate photomask layer, chemical mechanical polishing (CMP) is typically performed to thin the SiN layer. Due to the significant thickness of the SiN layer and the lack of an effective polishing stop layer, the amount of material removed during polishing must be controlled by time (by-time). This can lead to substantial fluctuations in the surface flatness of the SiN layer across different semiconductor structures or manufacturing batches. These flatness variations can further affect the focus control in subsequent photolithography steps and interfere with the grayscale contrast between the package alignment markers and surrounding metal lines. Summary of the Invention

[0006] To address the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a method for preparing an alignment mark structure, a semiconductor structure, and a semiconductor structure. By utilizing the pre-formed stepped morphology of the dielectric layer surface structure combined with CMP process to fabricate the alignment mark structure, the corrosion defects caused by dry etching in the prior art can be solved, thereby improving the recognition stability of the optical alignment system.

[0007] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: a method for preparing an alignment mark structure, comprising the following steps: A substrate is provided, on which a first dielectric layer is formed, the upper surface of the first dielectric layer having a first upper surface portion and a second upper surface portion, the first upper surface portion being higher than the second upper surface portion; A conductive material layer is conformally distributed on the upper surface of the first dielectric layer; A patterning etching process is performed to remove the conductive material layer located between the first upper surface portion and the second upper surface portion, forming an alignment mark structure located on the first upper surface portion and a conductive circuit layer located on the second upper surface portion, wherein the conductive circuit layer and the alignment mark structure are separated from each other. A second dielectric layer is formed on the alignment mark structure, the conductive line layer, and the exposed first dielectric layer; A planarization process is performed, using the alignment mark structure as a grinding stop layer, to thin the second dielectric layer to expose at least a portion of the upper surface of the alignment mark structure.

[0008] Furthermore, it also includes the following steps: A passivation layer is formed on the thinned second dielectric layer and the exposed alignment mark structure.

[0009] Furthermore, before conformally distributing a conductive material layer on the upper surface of the first dielectric layer, the following steps are also included: A vertical via is formed on the first dielectric layer, and the vertical via extends from the second upper surface portion into the substrate direction through the first dielectric layer to expose the underlying conductive structure.

[0010] Furthermore, the step of forming a vertical via on the first dielectric layer includes the following sub-steps: A first patterned photoresist layer is distributed on the first dielectric layer, and the first patterned photoresist layer has a first opening that defines the location of a vertical via in the first dielectric layer. An etching process is performed to etch the first dielectric layer along the first opening and stop at the lower conductive structure to form the vertical via. Remove the first patterned photoresist layer and clean the surface residue.

[0011] Furthermore, there is a side face between the first upper surface portion and the second upper surface portion. In the step of performing the patterning etching process to remove the conductive material layer located between the first upper surface portion and the second upper surface portion, at least a portion of the conductive material layer distributed on the side face is removed, thereby separating the alignment mark structure and the conductive circuit layer from each other.

[0012] Furthermore, the conductive line layer is configured as a patterned conductive line layer; during the patterned etching process, the alignment mark structure and the patterned conductive line layer are formed simultaneously.

[0013] Furthermore, the step of simultaneously forming the alignment mark structure and the patterned conductive line layer includes the following sub-steps: A second patterned photoresist layer is distributed on the conductive material layer. The second patterned photoresist layer has a second opening that defines a separation region between the alignment mark structure and the conductive line layer, and a third opening that defines the wiring shape of the patterned conductive line layer. A patterned etching process is performed to simultaneously etch the conductive material layer along the second and third openings to form mutually separated alignment mark structures and patterned conductive circuit layers. Remove the second patterned photoresist layer and clean the surface residue.

[0014] Furthermore, both the first dielectric layer and the second dielectric layer are configured as silicon oxide material layers, and the passivation layer is configured as a silicon nitride material layer.

[0015] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a method for preparing a semiconductor structure, including the method for preparing an alignment mark structure as described in the claims.

[0016] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: providing a semiconductor structure, comprising: Substrate; A first dielectric layer is formed above the substrate, and the upper surface of the first dielectric layer has a first upper surface portion and a second upper surface portion, wherein the first upper surface portion is higher than the second upper surface portion; An alignment mark structure is formed on a portion of the first upper surface of the first dielectric layer; A conductive circuit layer covering at least a portion of the second upper surface portion, the conductive circuit layer being separated from the alignment mark structure and electrically connected to the underlying conductive structure; A second dielectric layer covers the conductive circuit layer and the exposed second upper surface portion of the first dielectric layer, with at least a portion of the upper surface of the alignment mark structure exposed in the second dielectric layer; and A passivation layer covers the second dielectric layer and the alignment mark structure.

[0017] In summary, the alignment mark structure, the method for preparing the semiconductor structure, and the semiconductor structure of the present invention have at least the following unexpected technical effects: (i) This invention forms a stepped morphology on a first dielectric layer and conformally distributes a conductive material layer on the stepped morphology. Then, using a patterned etching process, it simultaneously forms an alignment mark structure at a higher position and a conductive line layer at a lower position, eliminating the need for a separate photolithography step in traditional processes to selectively expose the alignment mark structure. Furthermore, the alignment mark structure formed by the stepped morphology in this invention avoids the etching step in traditional processes. In conventional methods, the etching step of the alignment mark structure causes the surface of the alignment mark structure to directly contact the etching gas, easily leading to over-etching and corrosion defects, thus affecting the stability of the optical alignment system in recognizing the mark edges. This invention, by changing the exposure method of the alignment mark structure from etching exposure to polishing exposure, isolates the corrosive gas environment introduced by the etching process in the original process, significantly improving the corrosion defects caused by dry etching during manufacturing.

[0018] (ii) This invention utilizes the natural height difference formed by the first upper surface portion being higher than the second upper surface portion, ensuring that the overall height of the alignment mark structure located on the first upper surface portion is higher than the surrounding conductive circuit layer. Thus, during planarization processes, the alignment mark structure can serve as a natural stop layer for chemical mechanical polishing. Compared to conventional techniques that rely solely on time control to polish the second dielectric layer above the alignment mark structure, the end-point control mechanism employed in this invention effectively improves the global flatness of the wafer surface and reduces the range of thickness fluctuations caused by differences in deposition or polishing rates between different substrates, thereby enhancing batch-to-batch consistency.

[0019] (iii) Since the alignment mark structure in this invention is located above the first upper surface portion, its vertical position is raised relative to the entire conductive circuit layer. In subsequent alignment processes, the height difference makes the mark image captured by the optical alignment system more clearly distinguishable from the dense metal circuit pattern inside the chip in terms of grayscale contrast, thereby reducing the pattern confusion problem that may be caused by the complexity of the metal line pattern and improving the signal recognition capability of the alignment system.

[0020] (iv) In the patterning etching process, a second opening for separation and a third opening for patterning the conductive circuit layer are defined simultaneously in the same photolithography step. The conductive material layer is then etched synchronously along these openings, thereby simultaneously completing the patterning of the conductive circuit layer and the separation of the alignment mark structure from the conductive circuit layer in the same etching process. This synchronous etching method reduces the number of photolithography and etching cycles, lowers process complexity and manufacturing costs, and avoids process drift or alignment errors that may occur between two consecutive etching operations. This ensures good consistency in the sidewall morphology, linewidth control, and residue distribution of the alignment mark structure and the conductive circuit layer, improving device reliability. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic cross-sectional view of the first ILD layer fabrication stage in the first alignment mark structure fabrication process of a conventional technique.

[0022] Figure 2 This is a schematic cross-sectional view of the first vertical through-hole fabrication stage in the fabrication process of the first alignment mark structure in a conventional technique.

[0023] Figure 3 This is a schematic cross-sectional view of the fabrication stage of the first conductive material layer in the preparation process of the first alignment mark structure in a conventional technique.

[0024] Figure 4 This is a schematic cross-sectional view of the first alignment mark structure and the first conductive line layer fabrication stage in the preparation process of the first alignment mark structure in a conventional technology.

[0025] Figure 5 This is a schematic cross-sectional view of the second ILD layer deposition stage in the preparation process of the first alignment mark structure in a conventional technique.

[0026] Figure 6 This is a schematic cross-sectional view of the planarization of the second ILD layer during the fabrication process of the first alignment mark structure in a conventional technique.

[0027] Figure 7 This is a schematic cross-sectional view of the etching stage in the fabrication process of the first alignment mark structure in a conventional technique.

[0028] Figure 8 This is a schematic cross-sectional view of the first passivation layer fabrication stage in the first alignment mark structure fabrication process of a conventional technique.

[0029] Figure 9 This is a process flow diagram of an embodiment of the preparation method of the second alignment mark structure of the present invention.

[0030] Figure 10 This is a schematic cross-sectional view of the second substrate during the fabrication process of the second alignment mark structure of the present invention.

[0031] Figure 11 This is a schematic cross-sectional view of the first dielectric layer fabrication stage in the preparation process of the second alignment mark structure of the present invention.

[0032] Figure 12 and Figure 13 This is a schematic cross-sectional view of the second vertical through-hole fabrication stage in the preparation process of the second alignment mark structure of the present invention.

[0033] Figure 14 This is a schematic cross-sectional view of the second conductive material layer fabrication stage in the preparation process of the second alignment mark structure of the present invention.

[0034] Figure 15 and Figure 16 This is a schematic cross-sectional view of the second alignment mark structure and the fabrication stage of the second conductive line layer in the preparation process of the second alignment mark structure of the present invention.

[0035] Figure 17 This is a schematic cross-sectional view of the second dielectric layer deposition stage in the preparation process of the second alignment mark structure of the present invention.

[0036] Figure 18 This is a schematic cross-sectional view of the second dielectric layer planarization stage in the preparation process of the second alignment mark structure of the present invention.

[0037] Figure 19 This is a schematic cross-sectional view of the second passivation layer fabrication stage in the preparation process of the second alignment mark structure of the present invention.

[0038] The diagrams in the instruction manual are labeled as follows: First substrate 200; lower conductive structure 201; first ILD layer 210; first vertical via 220; first conductive material layer 230; first conductive line layer 232; second ILD layer 240; first passivation layer 250; Second substrate 100; lower metal interconnect layer 101; first dielectric layer 110; first upper surface portion 111; second upper surface portion 112; second vertical via 120; first patterned photoresist layer 121; first opening 122; second conductive material layer 130; second alignment mark structure 13a; second conductive line layer 13b; fracture band 13c; second patterned photoresist layer 131; second opening 132; third opening 133; second dielectric layer 140; second passivation layer 150. Detailed Implementation

[0039] The following disclosure provides various embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where other components may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations.

[0040] Furthermore, spatial relation terms such as "below," "under," "below," "above," and "above" may be used herein to readily describe the relationship between one element or component and another element (or component) or component (or component) as shown in the figure. In addition to the orientations shown in the figure, spatial relation terms will encompass various different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations) and will be interpreted accordingly through the spatial relation descriptors used herein.

[0041] Although the numerical ranges and parameter settings presented in this invention are approximations, the numerical settings in specific instances are reported as precisely as possible. Any numerical value, however, inherently contains certain inevitable errors arising from the standard deviation found in the respective test measurements. Similarly, as used herein, the term "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable average standard error that can be conceived by one of ordinary skill in the art. Except in instances of operation / work, or unless expressly stated otherwise, all numerical ranges, totals, values, and percentages, such as those for material quantities, durations, temperatures, operating conditions, amounts, and other similarities disclosed herein, should be understood to be modified by the term "about" in all cases. Therefore, unless otherwise stated, the numerical parameter settings set forth in this invention and the appended claims are approximations that can be changed upon request. At a minimum, each numerical parameter should be interpreted based on the number of significant figures reported and the application of ordinary rounding techniques. A range herein may be expressed as from one endpoint to another or between two endpoints. All scopes disclosed herein include endpoints unless otherwise stated.

[0042] Furthermore, the technical parts described in this invention and the appended claims are primarily the improved technical parts of this invention, and do not limit the object protected by this invention to only having these technical parts. Other known essential components (structures and / or methods) and / or non-essential components of the object protected, besides the technical parts described in this invention and the appended claims, are not included in this invention and the appended claims because they do not fall within the scope of improvements of this invention; however, this does not mean that the object protected by this invention does not possess these known components.

[0043] Please see Figures 1 to 8 This illustration provides a schematic cross-sectional view of a typical existing alignment mark structure fabrication stage. The alignment mark structure is typically formed concurrently with the top conductive material layer (such as the top metal interconnect layer) of the device substrate in the top region of the semiconductor structure, and its fabrication process is roughly as follows: S210, Deposit the first ILD (Interlayer Dielectric) layer: The first ILD layer 210 can be formed on one side of the first substrate 200 by chemical vapor deposition processes such as PECVD (Plasma Enhanced Chemical Vapor Deposition), SACVD (Subnormal Pressure Chemical Vapor Deposition), APCVD (Ambient Pressure Chemical Vapor Deposition) or other suitable processes.

[0044] S220, Fabrication of the first vertical via 220: A photolithography process is introduced to define the location of the first vertical via 220 on the first ILD layer 210. The first vertical via 220 is etched using dry etching processes such as reactive ion etching (RIE), high-density plasma etching (HDP), deep reactive ion etching (DRIE), or other suitable processes. The first vertical via 220 exposes the underlying conductive structure 201. The underlying conductive structure 201 corresponds to different devices depending on the layer level of the current metal interconnect layer. Specifically, if the current layer is the first metal interconnect layer, the underlying conductive structure 201 can be configured as a source region, drain region, and / or gate structure. If the current layer is an upper metal interconnect layer (e.g., the top metal interconnect layer), the underlying conductive structure 201 can be configured as the first conductive line layer of the lower metal interconnect layer, such as a metal line composed of copper, aluminum, tungsten, or other metal materials.

[0045] S230, Deposit the first conductive material layer 230: The first conductive material layer 230 can be conformally distributed on the upper surface of the first ILD layer 210 and inside the first vertical via 220 using any known process. Conformal means that the outline of the first conductive material layer 230 is along the outline of the upper surface of the first ILD layer 210 or is located on the outline of the first ILD layer 210.

[0046] S240, Fabrication of the first alignment mark structure 231 and the first conductive line layer 232: A photolithography process is introduced. Through the exposure and development of the photolithography process, the areas on the first conductive material layer 230 designated for forming the first alignment mark structure 231 and the areas designated for forming the first conductive line layer 232 can be clearly distinguished from each other, thereby independently forming the first alignment mark structure 231 and the first conductive line layer 232. The first conductive line layer 232 is electrically connected to the lower conductive structure 201 through the first vertical via 220.

[0047] S250, Deposit and planarize the second ILD layer 240: On the exposed surfaces of the first alignment mark structure 231, the first conductive line layer 232 and the first ILD layer 210, the second ILD layer 240 is formed using chemical vapor deposition processes such as PECVD, SACVD, APCVD or other suitable processes, and then the second ILD layer 240 is planarized using a mechanical polishing process such as chemical mechanical planarization (CMP).

[0048] S260, Exposing the first alignment mark structure 231: The photolithography process is introduced again to selectively expose the area on the second ILD layer 240 corresponding to the first alignment mark structure 231 (i.e., the area to be etched on the second ILD layer 240 is defined by the patterned opening of the photoresist), and then dry etching or other suitable etching processes are applied to etch the second ILD layer 240 and stop at the first alignment mark structure 231, thereby exposing the first alignment mark structure 231.

[0049] S270, Deposit the first passivation layer 250: A first passivation layer 250 is formed on the surface of the first alignment mark structure 231 and the second ILD layer 240 to protect against external environmental corrosion or avoid damage from subsequent processes; the first passivation layer 250 can be selected from processes such as PECVD, SACVD, APCVD, atomic layer deposition (ALD) or any other process considered suitable for depositing dense dielectric thin films, and is uniformly and conformally deposited on the surface of all the above-mentioned exposed areas, thereby providing reliable physical and electrical protection for the underlying first alignment mark structure 231 and the second ILD layer 240.

[0050] During the fabrication of the first alignment mark structure 231, an independent photolithography process combined with a corresponding etching process is required to selectively remove the second ILD layer 240 of the first alignment mark structure 231, thereby ensuring that the first alignment mark structure 231 can be selectively exposed to the external environment. However, due to this selective removal process, the surface of the first conductive material layer 230 (the exposed surface of the first alignment mark structure 231) originally exposed to the etching environment is susceptible to over-etching, resulting in a certain degree of corrosion defects. These corrosion defects may cause changes in the surface morphology of the first alignment mark structure 231 that are recognizable by current detection methods, thereby having a significant negative impact on the stability and reliability of the subsequent optical alignment system when identifying the mark edge position.

[0051] To address the problem of corrosion defects on the surface of the first alignment mark structure 231 caused by selective etching, which reduces the recognition stability of the optical alignment system, it is necessary to find an alternative process that can effectively expose the first alignment mark structure 231 while minimizing etching damage to its exposed surface. Therefore, an improved method for fabricating the alignment mark structure is provided below to solve the technical problem of surface corrosion defects caused by the aforementioned photolithography and etching processes. To clearly distinguish the improved scheme from the first alignment mark structure 231 described above, the alignment mark structure involved in the improved scheme will be described in detail below using the term "second alignment mark structure."

[0052] Please see Figure 9 The present invention exemplarily illustrates the process flow of the preparation method of the alignment mark structure (second alignment mark structure). In the illustrated embodiment, the preparation method of the second alignment mark structure includes the following steps: S110, please refer to Figure 10 A second substrate 100 is provided.

[0053] The second substrate 100 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or a silicon wafer elemental or compound semiconductor substrate. It can also include a stacked structure composed of the aforementioned semiconductor materials, or a composite substrate such as silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator germanium, or germanium-on-insulator. Regarding the doping type, the second substrate 100 can be an undoped intrinsic silicon substrate, or a silicon substrate doped with a P-type dopant such as boron, and thus used as a P-type substrate. Alternatively, the second substrate 100 can comprise another suitable semiconductor material. For example, the second substrate 100 can be a silicon substrate doped with an N-type dopant such as phosphorus or arsenic, and thus used as an N-type substrate.

[0054] The second substrate 100 is a device substrate that has been fabricated using front-end-of-line processing (FEOL) and is undergoing back-end-of-line processing (BEOL). As those skilled in the art will understand, depending on the specific device type to be formed, the front-end process may include a series of fabrication steps matching that device type. For example, in one or more exemplary but non-limiting embodiments, the front-end process may include one or more of the following steps: forming a trench isolation structure, such as a shallow trench isolation (STI) structure, in the second substrate 100; forming a well region in the second substrate 100, the well region may include an N-type well region and / or a P-type well region; forming a source region and a drain region in the active region of the second substrate 100; and forming a gate structure on the second substrate 100, wherein the gate structure may further include a gate dielectric layer and a gate electrode layer, and optionally include a gate sidewall (spacer) structure. In some embodiments, the front-end process may also optionally include threshold voltage regulated implantation, lightly doped drain (LDD) implantation, and annealing activation steps. Through the aforementioned front-end processes, a basic structure of multiple active devices (e.g., metal-oxide-semiconductor field-effect transistors, MOSFETs) is formed on the second substrate 100, thereby providing a fully functional device substrate for subsequent processes. The term "currently undergoing subsequent processes" can refer to the fabrication of a metal interconnect structure, for example, the fabrication of at least one front metal interconnect layer (lower metal interconnect layer 101) of the metal interconnect structure on the device substrate.

[0055] S120, please refer to Figure 11A first dielectric layer 110 (e.g., a silicon oxide material layer) is formed on the second substrate 100. The first dielectric layer 110 is configured to have a first upper surface portion 111 and a second upper surface portion 112 on its upper surface. The first upper surface portion 111 is higher than the second upper surface portion 112 in the vertical direction, thereby forming a dielectric layer surface structure with a stepped morphology.

[0056] The first dielectric layer 110 can be made of any material deemed suitable (e.g., silicon oxide) and can be formed on the entire upper surface of the second substrate 100 by chemical vapor deposition such as PECVD, SACVD, APCVD, or any other suitable process capable of forming a uniform dielectric film on the substrate surface. The thickness of the first dielectric layer 110 can be adjusted according to the morphology of the underlying metal interconnect layer 101 and the requirements for subsequent planarization.

[0057] In one or more exemplary but non-limiting embodiments, the first dielectric layer 110 is configured as part of the top metal interconnect layer. The first dielectric layer 110 is further deposited on the upper surface of the already completed lower metal interconnect layer 101, thereby achieving interlayer electrical isolation while providing a basis for the subsequent second alignment mark structure 13a (see...). Figure 16 The fabrication of the second conductive layer provides a dielectric substrate with a predetermined stepped morphology.

[0058] In one or more exemplary but non-limiting embodiments, a stepped surface structure of the dielectric layer can be formed by photolithography and etching processes after depositing a first dielectric layer 110 of sufficient thickness. Alternatively, the stepped morphology can be achieved using a two-stage deposition method. Specifically, a first sub-dielectric layer of suitable thickness is first deposited to form a lower second upper surface portion 112. Then, a photolithography process is introduced to selectively expose specific locations where a higher region needs to be formed, and a second sub-dielectric layer is additionally formed over the exposed region by a second deposition process, thereby superimposing to form a relatively convex first upper surface portion 111. Regardless of the method used, the upper surface of the finally obtained first dielectric layer 110 is divided into a first upper surface portion 111 and a second upper surface portion 112 of different heights, thereby providing a topological basis for the subsequent fabrication of the second alignment mark structure 13a and the second conductive line layer.

[0059] S130, please refer to Figure 12 and Figure 13 A second vertical via 120 is formed on the first dielectric layer 110. The second vertical via 120 penetrates the first dielectric layer 110 from the second upper surface portion 112 toward the second substrate 100 to expose the underlying conductive structure.

[0060] A photolithography process is introduced to define the location of the second vertical via 120 in the first dielectric layer 110. The second vertical via 120 is then etched using dry etching processes such as RIE, HDP, DRIE, or other suitable processes until the underlying conductive structure is exposed. The underlying conductive structure corresponds to different devices depending on the layer hierarchy of the current metal interconnect layer. Specifically, if the current layer is the first metal interconnect layer, the underlying conductive structure can be configured as an active device structure formed in the previous process, such as a source region, drain region, and / or gate structure; if the current layer is the top metal interconnect layer, the underlying conductive structure can be configured as the second conductive line layer 13b of the underlying metal interconnect layer 101 (see...). Figure 16 Metal wires made of materials such as copper, aluminum, and tungsten.

[0061] In one or more exemplary but non-limiting embodiments, this step may include the following sub-steps: S131. A first patterned photoresist layer 121 is distributed on the first dielectric layer 110, the first patterned photoresist layer 121 having a first opening 122 defining the position of the second vertical via 120 located in the first dielectric layer 110.

[0062] In this step, a layer of photoresist material is uniformly coated on the second substrate 100 after the first dielectric layer 110 has been deposited, and a photoresist film with good adhesion and uniform thickness is formed through pretreatment processes such as spin coating and soft baking; then, the photoresist film is exposed using a photomask with a preset via pattern, and then developed to form a first patterned photoresist layer 121. At least one first opening 122 is formed in the first patterned photoresist layer 121, and the position and critical dimension (CD) of the first opening 122 are precisely set to correspond to the preset position and critical dimension of the second vertical via 120 to be formed on the first dielectric layer 110.

[0063] S132. Perform an etching process to etch the first dielectric layer 110 along the first opening 122 and stop at the lower conductive structure to form the second vertical via 120.

[0064] In this step, the first patterned photoresist layer 121 is used as an etching barrier mask. One or more etching gas systems with a high etching selectivity between the first dielectric layer 110 material (e.g., silicon oxide material) and the underlying conductive structure material are selected to anisotropically etch the first dielectric layer 110 along the first opening 122. The etching process automatically stops when the top surface of the underlying conductive structure is reached (or is interrupted in time by endpoint detection technology), thereby forming a second vertical through-hole 120 that penetrates vertically inside the first dielectric layer 110 and exposes the underlying conductive structure at the bottom.

[0065] S133. Remove the first patterned photoresist layer 121 and clean the surface residue.

[0066] In this step, wet stripping or plasma ashing processes can be used to completely remove the first patterned photoresist layer 121 remaining on the surface of the first dielectric layer 110, and the interior of the formed second vertical via 120 can be cleaned with a suitable cleaning medium to remove any remaining etching byproducts or polymer residues, thereby obtaining a clean and intact second vertical via 120 structure, which prepares the interface for subsequent filling of conductive materials.

[0067] S140, please refer to Figure 14 A second conductive material layer 130 is conformally distributed on the upper surface of the first dielectric layer 110. Conformal means that the outline of the second conductive material layer 130 is along the outline of the upper surface of the first dielectric layer 110 or is located on the outline of the first dielectric layer 110.

[0068] The second conductive material layer 130 can be made of any metal or conductor material deemed suitable. Examples include aluminum (Al), aluminum / silicon / copper alloys (Al / Si / Cu), copper (Cu), titanium (Ti), titanium nitride (TiN), tungsten (W), polycrystalline silicon (Poly-Si), metal silicides (such as tungsten silicide, cobalt silicide, nickel silicide), or any combination thereof. The second conductive material layer 130 can be formed by processes including PVD, chemical vapor deposition (CVD), or any known process.

[0069] S150, please refer to Figure 15 and Figure 16 A patterned etching process is performed to remove the areas of the second conductive material layer 130 located between the first upper surface portion 111 and the second upper surface portion 112 that are not covered by the photoresist mask, thereby forming the second alignment mark structure 13a located on the first upper surface portion 111 and the second conductive line layer 13b located on the second upper surface portion 112; so that the second conductive line layer 13b and the second alignment mark structure 13a are clearly separated from each other, and there is no direct conductive connection between them.

[0070] In one or more exemplary but non-limiting embodiments, this step may include the following sub-steps: S151, A second patterned photoresist layer 131 is distributed on the second conductive material layer 130.

[0071] The second patterned photoresist layer 131 has a second opening 132 that defines the separation region between the second alignment mark structure 13a and the second conductive line layer 13b, and may also have a third opening 133 for defining the desired shape (wiring shape) of the patterned second conductive line layer 13b, so as to ensure that the fabrication of the second alignment mark structure 13a and the patterned conductive line layer (patterned second conductive line layer 13b) can be completed simultaneously in the same etching operation in the subsequent patterning etching process.

[0072] In this step, a layer of photoresist is uniformly coated on the completed second conductive material layer 130, and a photoresist film with good adhesion and uniform thickness is formed through pretreatment processes such as spin coating and soft baking. Subsequently, the photoresist film is exposed using a photomask with a preset opening pattern, and then developed to form a second patterned photoresist layer 131. The second patterned photoresist layer 131 has a second opening 132 for defining the separation region between the second alignment mark structure 13a and the second conductive line layer 13b, so that the areas on the second conductive material layer 130 designated for forming the second alignment mark structure 13a and the areas designated for forming the second conductive line layer 13b can be clearly distinguished from each other, thereby independently forming the second alignment mark structure 13a and the second conductive line layer 13b. The second conductive line layer 13b is electrically connected to the lower conductive structure through the second vertical via 120. The second patterned photoresist layer 131 also has a third opening 133 for defining the specific wiring shape of the second conductive line layer 13b. The pattern of the third opening 133 determines the extension path and key dimensions of the second conductive line layer 13b in the horizontal direction, so that the final formed second conductive line layer 13b can present the desired patterned structure according to the pre-designed layout pattern.

[0073] In one or more exemplary but non-limiting embodiments, in order to achieve a better three-dimensional morphology of the second alignment mark structure 13a and the second conductive line layer 13b in the vertical stacking direction of the semiconductor device, and to ensure that the overall height of the second alignment mark structure 13a is higher than that of the second conductive line layer 13b (the height difference helps improve the accuracy and stability of the subsequent optical alignment system when identifying the mark edges), the second opening 132 is defined precisely on the side facade between the first upper surface portion 111 and the second upper surface portion 112. Specifically, the second opening 132 can be configured to be directly opposite to the second conductive material layer 130 covering the side facade. Directly opposite means that on the horizontal projection plane obtained by projection along the vertical direction, one side of the second opening 132 coincides with the horizontal projection line of the side facade (i.e., coplanar), and the other side of the second opening 132 coincides with the horizontal projection line of the outer side of the second conductive material layer 130 covering the side facade (i.e., also coplanar). By employing the aforementioned facing arrangement, it is possible to ensure that at least a portion of the second conductive material layer 130 covering the side facade (e.g., at least the upper portion, or the entire portion covering the side facade) is effectively etched off in the vertical direction, thereby creating complete electrical isolation and physical separation between the second alignment mark structure 13a and the second conductive line layer 13b. This allows the separated second alignment mark structure 13a to sit precisely on the relatively higher first upper surface portion 111, while the second conductive line layer 13b sits on the relatively lower second upper surface portion 112. This naturally raises the overall height of the second alignment mark structure 13a to a position higher than the second conductive line layer 13b by utilizing the stepped morphology inherent in the first dielectric layer 110 itself.

[0074] S152. Perform a patterned etching process to simultaneously etch the second conductive material layer 130 along the second opening 132 and the third opening 133 to form a mutually separated second alignment mark structure 13a and a patterned second conductive line layer 13b.

[0075] In this step, the second patterned photoresist layer 131 is used as an etching barrier mask. One or more etching gas systems with a high etching selectivity between the second conductive material layer 130 and the lower first dielectric layer 110 are selected to simultaneously and anisotropically etch the second conductive material layer 130 along the second opening 132 and the third opening 133.

[0076] It should be noted that, since the second conductive material layer 130 corresponding to the second opening 132 is a portion covering the side surface of the first dielectric layer 110, its vertical dimension (thickness) is usually greater than the thickness of the second conductive material layer 130 at the third opening 133 (located above the second upper surface portion 112). Therefore, the etching depth requirements for the two openings 132 and 133 in this step can be different. Specifically, for the third opening 133, etching needs to continue until the second conductive material layer 130 in this area is completely removed, thereby exposing the upper surface of the first dielectric layer 110 below it to form a patterned second conductive circuit layer 13b; while for the second opening 132, etching does not require penetrating all the second conductive material layer 130 covering the side surface and exposing the first dielectric layer 110, only that the etching depth is sufficient to completely cut off at least a segment of the second conductive material layer 130 in the vertical direction (e.g., at least the upper segment). In other words, as long as the continuity of the second conductive material layer 130 covering the side facade is disrupted at the location of the second opening 132, forming a fracture zone 13c, no conductive path exists between the second alignment mark structure 13a on the first upper surface portion 111 and the second conductive circuit layer 13b on the second upper surface portion 112, thus achieving separation. In actual process control, the etching time, etching rate, and endpoint detection strategy can be adjusted so that the etching depth at the second opening 132 is just greater than the local thickness of the second conductive material layer 130 at that location (usually the minimum thickness of the side facade coverage area), thereby achieving reliable electrical isolation without excessively damaging the underlying first dielectric layer 110. The differentiated etching results described above can be achieved through over-etching control within the same etching process. Since the second conductive material layer 130 to be removed at the second opening 132 is slightly thicker in the vertical direction, while the second conductive material layer 130 at the third opening 133 is relatively thinner, when the etching reaches the third opening 133 where the first dielectric layer 110 is exposed, a controlled over-etching process is required to ensure that the second conductive circuit layer 13b at the second opening 132 is completely severed. During this over-etching process, because the etching gas system used has a high etching selectivity ratio between the second conductive material layer 130 and the first dielectric layer 110 (the etching selectivity ratio can be configured to be greater than or equal to 20:1), it will not affect the electrical isolation function of the first dielectric layer 110 or the subsequent processes.

[0077] After etching is completed, based on the specific location of the second opening 132 (directly opposite the second conductive material layer 130 covering the side facade in the vertical direction), at least a portion of the side facade is exposed in both the horizontal and vertical directions. This exposure ensures that the second alignment mark structure 13a and the patterned second conductive line layer 13b are not only completely electrically disconnected, but also have a clear gap formed in the physical structure, thereby eliminating the possibility of short circuit due to metal residue.

[0078] S153, Remove the second patterned photoresist layer 131 and clean the surface residue.

[0079] In this step, wet stripping or plasma ashing processes can be used to thoroughly remove the second patterned photoresist layer 131 remaining on the exposed surface of the second conductive line layer 13b, the second alignment mark structure 13a, and the first dielectric layer 110. The resulting disconnected area is then cleaned with a suitable cleaning medium to remove any remaining etching byproducts or polymer residues, thereby obtaining a clean and intact surface, which prepares the interface for possible subsequent deposition or passivation treatments.

[0080] It should be noted that combining the etching of the second opening 132 and the third opening 133 into a single process eliminates the need for a separate photolithography-etching cycle, thereby reducing the number of photomasks and shortening the process time. Simultaneously, completing the etching of both regions within the same etching chamber avoids potential process drift or alignment deviations between etching operations, resulting in more consistent sidewall morphologies of the second alignment mark structure 13a and the second conductive circuit layer 13b, which is beneficial for subsequent optical alignment and interconnect reliability. However, this is not the only implementation method. In other embodiments, if the etching depth or selectivity requirements for the two openings differ significantly, they can be etched independently in sequence, for example, patterning the circuit layer first and then cutting the sidewall metal, or cutting the sidewall metal and then patterning the circuit layer. While sequential etching may require additional photolithography layers, it may provide a larger process window or more flexible morphology control for some materials or structures. Those skilled in the art can make reasonable choices between synchronous and sequential modes based on specific pattern density, material stack-up, and equipment capabilities, without departing from the technical concept disclosed in this invention.

[0081] S160, please refer to Figure 17 A second dielectric layer 140 (such as a silicon oxide material layer) is formed on the second alignment mark structure 13a, the second conductive line layer 13b and the exposed first dielectric layer 110.

[0082] The second dielectric layer 140 can be made of any material considered suitable (e.g., silicon oxide) and can be formed on the entire upper surface of the second substrate 100 by chemical vapor deposition such as PECVD, SACVD, APCVD or any other suitable process that can form a uniform dielectric film on the substrate surface, thereby achieving full coverage and protection of the underlying structural layers.

[0083] S170, please refer to Figure 18 A planarization process is performed, using the second alignment mark structure 13a as a grinding stop layer, to thin and planarize the second dielectric layer 140 until at least a portion of the upper surface of the second alignment mark structure 13a is selectively exposed.

[0084] In this step, mechanical polishing processes, such as chemical mechanical polishing (CMP), can be used to thin the second dielectric layer 140 and achieve global planarization, providing a smooth device surface for subsequent processes and ensuring that critical dimensions of subsequent processes are not affected. During the planarization process, based on the aforementioned three-dimensional surface structure, the higher second alignment mark structure 13a forms a natural CMP polishing stop layer. Using this end-point control mechanism based on the structure itself to planarize the surface of the second dielectric layer 140 effectively improves the surface flatness of the second substrate 100 and reduces the range of flatness fluctuations caused by differences in polishing time between different substrates, compared to the time-controlled mechanism used in conventional techniques.

[0085] S180, please refer to Figure 19 A second passivation layer 150 (such as a silicon nitride material layer) is formed on the thinned second dielectric layer 140 and the exposed second alignment mark structure 13a.

[0086] The second passivation layer 150 can be made of any material deemed suitable and can be uniformly and conformally deposited on the surface of all the above-mentioned exposed areas by processes such as PECVD, SACVD, APCVD, ALD or any other process deemed suitable for depositing dense dielectric films, thereby providing reliable physical and electrical protection for the underlying second alignment mark structure 13a and the second dielectric layer 140.

[0087] In summary, the method for preparing the second alignment mark structure of the present invention has the following unexpected technical effects: (i) This invention forms a stepped morphology (the first upper surface portion is higher than the second upper surface portion) on a first dielectric layer, and after conformally distributing a second conductive material layer on the stepped morphology, it simultaneously forms a second alignment mark structure at a higher position and a second conductive line layer at a lower position using a patterned etching process, eliminating the need for a separate photolithography step in traditional processes to selectively expose the second alignment mark structure. Furthermore, the second alignment mark structure formed by the stepped morphology in this invention avoids the etching step in traditional processes. In conventional solutions, the etching step of the second alignment mark structure causes the surface of the second alignment mark structure to directly contact the etching gas, easily leading to over-etching and corrosion defects, thus affecting the stability of the optical alignment system in recognizing the mark edges. This invention, by changing the exposure method of the second alignment mark structure from etching exposure to polishing exposure (exposed through an existing polishing process), isolates the corrosive gas environment introduced by the etching process in the original process, significantly improving the corrosion defects caused by dry etching during manufacturing.

[0088] (ii) This invention utilizes the natural height difference formed by the first upper surface portion being higher than the second upper surface portion, so that the overall height of the second alignment mark structure located above the first upper surface portion is higher than the surrounding second conductive circuit layer. Thus, during the planarization process, the second alignment mark structure can serve as a natural stop layer for chemical mechanical polishing. Compared to conventional techniques that rely solely on time control to polish the second dielectric layer above the second alignment mark structure, the endpoint control mechanism based on the structure itself employed in this invention can effectively improve the global flatness of the wafer surface and reduce the range of thickness fluctuations caused by differences in deposition or polishing rates between different substrates, thereby improving batch-to-batch consistency.

[0089] (iii) The second alignment mark structure in this invention is located above the first upper surface portion, and its vertical position is raised relative to the second conductive line layer as a whole. In the subsequent alignment process, the height difference makes the mark image captured by the optical alignment system more clearly distinguishable from the dense metal line pattern inside the chip in terms of grayscale contrast, thereby reducing the pattern confusion problem that may be caused by the complexity of the metal line pattern and improving the signal recognition capability of the alignment system.

[0090] (iv) In the patterning etching process, a second opening for separation and a third opening for patterning the second conductive line layer are defined simultaneously in the same photolithography step. The second conductive material layer is then etched synchronously along these openings, thereby simultaneously completing the patterning of the second conductive line layer and the separation between the second alignment mark structure and the second conductive line layer in the same etching process. This synchronous etching method reduces the number of photolithography and etching cycles, lowers process complexity and manufacturing costs, and avoids process drift or alignment errors that may occur between two consecutive etching operations. This ensures that the sidewall morphology, linewidth control, and residue distribution of the second alignment mark structure and the second conductive line layer maintain good consistency, improving device reliability.

[0091] Based on the fabrication method disclosed in the above embodiments, the present invention further discloses a method for fabricating a semiconductor structure, which includes at least all the fabrication steps of the second alignment mark structure 13a described above. Furthermore, it integrates other process operations related to the overall manufacturing of the semiconductor structure, such as semiconductor front-end processes, the formation of the lower metal interconnect layer 101, pad fabrication, and subsequent pre-packaging treatments. The semiconductor structure fabrication method proposed in this invention can be considered as a comprehensive process solution formed by embedding the aforementioned fabrication process of the second alignment mark structure 13a into conventional semiconductor back-end processes. The process steps it covers are not limited to the formation of the second alignment mark structure 13a, but also include operations such as patterning of the second conductive line layer 13b, planarization of the second dielectric layer 140, and deposition of the top passivation layer, which are performed in conjunction with it. Specific details can be found in the corresponding descriptions of the preceding steps.

[0092] Please continue reading Figure 19 Based on the above embodiments, the present invention further discloses a semiconductor structure, which can be any existing semiconductor structure that requires the above method to prepare the second alignment mark structure 13a. The formation of the second alignment mark structure 13a and the patterning of the top metal interconnect layer are integrated into the same process sequence.

[0093] The semiconductor structure includes at least the second substrate 100, a metal interconnect layer formed on the second substrate 100, a second alignment mark structure 13a, and a second passivation layer 150 covering at least a portion of the surface.

[0094] The second substrate 100 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or a silicon wafer elemental or compound semiconductor substrate. It can also include a stacked structure composed of the aforementioned semiconductor materials, or a composite substrate such as silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator germanium, or germanium-on-insulator. Regarding the doping type, the second substrate 100 can be an undoped intrinsic silicon substrate, or a silicon substrate doped with a P-type dopant such as boron, and thus used as a P-type substrate. Alternatively, the second substrate 100 can comprise another suitable semiconductor material. For example, the second substrate 100 can be a silicon substrate doped with an N-type dopant such as phosphorus or arsenic, and thus used as an N-type substrate.

[0095] The second substrate 100 is a device substrate that has been fabricated using front-end processes and is undergoing back-end processes. As those skilled in the art will understand, depending on the specific device type to be formed, the front-end processes may include a series of manufacturing steps matching that device type. Examples include well implantation, gate formation, source / drain doping, and shallow trench isolation. "Undergoing back-end processes" can, for example, mean undergoing the fabrication of a metal interconnect structure, where the device substrate has already completed the fabrication of at least one front-end metal interconnect layer.

[0096] The metal interconnect layer can be configured as the top metal interconnect layer, and can vary depending on the total number of metal interconnect layers required by different types of devices. For example, for a logic chip requiring four metal interconnect layers, the fourth metal layer is the top layer; for a memory requiring eight metal layers, the eighth metal layer is the top layer. The metal interconnect layer includes at least the aforementioned first dielectric layer 110, second conductive line layer 13b, and second dielectric layer 140.

[0097] The first dielectric layer 110 is configured such that its upper surface has a first upper surface portion 111 and a second upper surface portion 112 that are distinct from each other. The height of the first upper surface portion 111 in the vertical direction is set to be higher than that of the second upper surface portion 112, thereby forming a dielectric layer surface structure with a stepped morphology. This stepped morphology can be achieved through various processes, such as global deposition followed by selective etch-back, or by using two-step deposition plus selective region stacking. The specific methods have been described in detail in the previous step descriptions and will not be repeated here.

[0098] The first dielectric layer 110 can be made of any suitable insulating material (e.g., silicon oxide) and can be deposited on the entire upper surface of the second substrate 100 by chemical vapor deposition processes such as PECVD, SACVD, APCVD, or any other suitable process capable of forming a uniform dielectric film on the substrate surface. The thickness of the first dielectric layer 110 can be adjusted according to the morphology of the underlying metal interconnect layer 101 and the requirements of subsequent planarization.

[0099] According to one or more exemplary but non-limiting embodiments, the first dielectric layer 110 is further deposited on the upper surface of the already completed lower metal interconnect layer 101, thereby achieving interlayer electrical isolation while providing a dielectric substrate with a predetermined stepped morphology for the subsequent fabrication of the second alignment mark structure 13a and the second conductive line layer 13b. A second vertical via 120 is formed on the first dielectric layer 110. The second vertical via 120 is formed by photolithography and etching processes, vertically etching from the second upper surface portion 112 of the first dielectric layer 110 toward the second substrate 100, exposing the lower conductive structure in the lower metal interconnect layer 101 at its bottom, thereby providing an electrical connection path for the subsequent filling of conductive material.

[0100] The second conductive layer 13b includes horizontal and vertical connectors distributed on the first dielectric layer 110. The horizontal connectors are the second conductive layer 13b (conductive thin film) conformally distributed on the upper surface of the first dielectric layer 110, used to transmit electrical signals or provide interconnect wiring in the horizontal direction; the vertical connectors are the second conductive layer 13b filling the interior of the second vertical via 120, used to achieve electrical connection between different metal layers in the vertical direction. The vertical connectors are electrically connected to the lower conductive structure (e.g., metal wires made of copper, aluminum, or tungsten) in the lower metal interconnect layer 101 via the second vertical via 120, thereby transmitting signals from the top metal circuitry to the lower device structure. The second conductive layer 13b can be made of any metal or conductor material deemed suitable, such as aluminum (Al), aluminum / silicon / copper alloy (Al / Si / Cu), copper (Cu), titanium (Ti), titanium nitride (TiN), tungsten (W), polysilicon (Poly-Si), metal silicides (such as tungsten silicide, cobalt silicide, nickel silicide), or any combination thereof. The choice of different materials depends on factors such as specific resistivity requirements, adhesion to the dielectric layer, resistance to electromigration, and process compatibility.

[0101] The second conductive line layer 13b conformally covers the second vertical via 120 and at least a portion of the second upper surface portion 112. The second conductive line layer 13b is separated from the second alignment mark structure 13a and electrically connected to the underlying conductive structure.

[0102] The second conductive line layer 13b and the second alignment mark structure 13a are completed simultaneously through a patterning etching step. During fabrication, a second conductive material layer 130 is first conformally distributed on the entire upper surface of the first dielectric layer 110 (including the first upper surface portion 111, the second upper surface portion 112, the side facade between them, and the surface of the second vertical via 120). Subsequently, a second patterned photoresist layer 131 is covered on top of the second conductive material layer 130, in which a second opening 132 and a third opening 133 are pre-formed. The second opening 132 defines the separation region between the second alignment mark structure 13a and the second conductive line layer 13b, and is positioned near the side facade between the first upper surface portion 111 and the second upper surface portion 112. The third opening 133 defines the specific wiring shape of the second conductive line layer 13b, and the pattern of the third opening 133 determines the extension path and critical dimensions of the horizontal connector on the second upper surface portion 112. Finally, a suitable etching process (e.g., dry etching) is performed to simultaneously etch the second conductive material layer 130 towards the second substrate 100 along the second opening 132 and the third opening 133. The etching process continues until a fracture band 13c is formed in the second conductive material layer 130 at the second opening 132 and the third opening 133. Based on this simultaneous etching operation, the second alignment mark structure 13a located on the first upper surface portion 111 and the patterned second conductive line layer 13b located on the second upper surface portion 112 are simultaneously defined, and they are reliably electrically isolated from each other through the fracture band 13c at the second opening 132. This simultaneous fabrication method avoids additional photolithography layers, simplifies the process flow, and reduces alignment errors that may be introduced by two consecutive etching operations.

[0103] The second dielectric layer 140 covers the second conductive circuit layer 13b and the exposed second upper surface portion 112 of the first dielectric layer 110, with at least a portion of the upper surface of the second alignment mark structure 13a exposed in the second dielectric layer 140. The second dielectric layer 140 serves to protect the conductive circuit layer from potential damage from the external environment or subsequent process steps.

[0104] Based on the stepped morphology described above, when depositing the second dielectric layer 140, the lower second upper surface portion 112 (i.e., the location of the second conductive line layer 13b) naturally becomes the reference plane for the deposition thickness. This is because the second dielectric layer 140 only needs to completely cover the second conductive line layer 13b located on the lower plane, while the second alignment mark structure 13a located on the higher first upper surface portion 111 will be actively exposed in the subsequent planarization process, and it is not required to be completely covered during the deposition stage. Compared to the conventional technology that requires a dielectric layer of sufficient thickness to be deposited on a flat surface to cover all structures (including the originally higher second mark structure area), this invention utilizes the natural elevation of the first upper surface portion 111, so that the deposition thickness of the second dielectric layer 140 can be determined solely by referring to the lower second upper surface portion 112. Since the deposition reference plane is relatively lowered, the required dielectric layer thickness is reduced, thereby reducing material consumption and deposition process time costs to a certain extent. It also helps to reduce the volume of dielectric layer to be removed in the subsequent planarization process, thereby improving the overall process efficiency of chemical mechanical polishing.

[0105] The second passivation layer 150 can be configured as a highly dense dielectric material such as silicon nitride or silicon oxynitride to enhance its resistance to moisture penetration and scratches. The second passivation layer 150 covers the second dielectric layer 140 and the second alignment mark structure 13a, protecting them from moisture, mobile ions, or mechanical particles in the external environment, and preventing unnecessary damage to the underlying structure from subsequent processes (such as laser scribing, plasma cleaning, or bump reflow during packaging). The first passivation layer 250 can be prepared using processes such as PECVD, SACVD, APCVD, ALD, or any other process considered suitable for depositing dense dielectric films, and is uniformly and conformally deposited on the surface of all the exposed areas, thereby providing reliable physical and electrical protection for the underlying second alignment mark structure 13a and the second dielectric layer 140.

[0106] In summary, the semiconductor structure of the present invention has the following unexpected technical effects: (i) The second alignment mark structure and the second conductive line layer are located at different height levels of the first dielectric layer (the second alignment mark structure is located on the higher first upper surface portion, while the second conductive line layer is located on the lower second upper surface portion). This height difference, determined by the stepped morphology of the dielectric layer itself, causes the second alignment mark structure to naturally protrude from the surrounding line layer, which is beneficial for the optical alignment system in subsequent packaging or bonding equipment to obtain higher grayscale contrast and reduce misidentification caused by the complex background of the metal lines.

[0107] (ii) The second alignment mark structure is not exposed to the etching atmosphere throughout the entire downstream process, and its metal surface is free from morphological defects such as edge roughness, depressions, or corrosion pits caused by over-etching. Such a metal surface not only helps maintain the stability of the optical reflection signal, but also provides more reliable interface quality in subsequent processes that may involve direct metal-to-metal contact (such as hybrid bonding or under-bump metallization).

[0108] (iii) The second dielectric layer uses a lower second upper surface portion as the deposition reference plane. Compared with the traditional structure, which requires a thicker dielectric layer to be deposited on the same horizontal surface to cover all structures, the thickness of the second dielectric layer in this invention is reduced, which can reduce the raw material consumption and deposition time of chemical vapor deposition, help save costs, and improve the overall process efficiency of subsequent chemical mechanical polishing. The thinner dielectric layer accumulates less film internal stress, which is beneficial to improve the warping behavior of large-size wafers in subsequent heat treatment.

[0109] (iv) Since the second alignment mark structure is located above the higher first upper surface portion, its vertical height exceeds the surrounding second conductive line layer and most of the second dielectric layer, so it is exposed first in chemical mechanical polishing, forming a natural polishing stop layer, thereby obtaining more stable endpoint control and more uniform surface thickness.

[0110] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A method for preparing an alignment mark structure, characterized in that, Includes the following steps: A substrate is provided, on which a first dielectric layer is formed, the upper surface of the first dielectric layer having a first upper surface portion and a second upper surface portion, the first upper surface portion being higher than the second upper surface portion; A conductive material layer is conformally distributed on the upper surface of the first dielectric layer; A patterning etching process is performed to remove the conductive material layer located between the first upper surface portion and the second upper surface portion, forming an alignment mark structure located on the first upper surface portion and a conductive circuit layer located on the second upper surface portion, wherein the conductive circuit layer and the alignment mark structure are separated from each other. A second dielectric layer is formed on the alignment mark structure, the conductive line layer, and the exposed first dielectric layer; A planarization process is performed, using the alignment mark structure as a grinding stop layer, to thin the second dielectric layer to expose at least a portion of the upper surface of the alignment mark structure.

2. The method for preparing the alignment mark structure as described in claim 1, characterized in that, It also includes the following steps: A passivation layer is formed on the thinned second dielectric layer and the exposed alignment mark structure.

3. The method for preparing the alignment mark structure as described in claim 1, characterized in that, Before the conductive material layer is conformally distributed on the upper surface of the first dielectric layer, the following steps are also included: A vertical via is formed on the first dielectric layer, and the vertical via extends from the second upper surface portion into the substrate direction through the first dielectric layer to expose the underlying conductive structure.

4. The method for preparing the alignment mark structure as described in claim 2, characterized in that, The step of forming a vertical via on the first dielectric layer includes the following sub-steps: A first patterned photoresist layer is distributed on the first dielectric layer, and the first patterned photoresist layer has a first opening that defines the location of a vertical via in the first dielectric layer. An etching process is performed to etch the first dielectric layer along the first opening and stop at the lower conductive structure to form the vertical via. Remove the first patterned photoresist layer and clean the surface residue.

5. The method for preparing the alignment mark structure as described in claim 1, characterized in that: The first upper surface portion and the second upper surface portion have a side facade. In the step of performing a patterning etching process to remove the conductive material layer located between the first upper surface portion and the second upper surface portion, at least a portion of the conductive material layer distributed on the side facade is removed, thereby separating the alignment mark structure and the conductive circuit layer from each other.

6. The method for preparing the alignment mark structure as described in claim 1, characterized in that: The conductive line layer is configured as a patterned conductive line layer; during the patterning etching process, the alignment mark structure and the patterned conductive line layer are formed simultaneously.

7. The method for preparing the alignment mark structure as described in claim 6, characterized in that, The step of simultaneously forming the alignment mark structure and the patterned conductive line layer includes the following sub-steps: A second patterned photoresist layer is distributed on the conductive material layer. The second patterned photoresist layer has a second opening that defines a separation region between the alignment mark structure and the conductive line layer, and a third opening that defines the wiring shape of the patterned conductive line layer. A patterned etching process is performed to simultaneously etch the conductive material layer along the second and third openings to form mutually separated alignment mark structures and patterned conductive circuit layers. Remove the second patterned photoresist layer and clean the surface residue.

8. The method for preparing the alignment mark structure as described in claim 1, characterized in that, The first dielectric layer and / or the second dielectric layer are configured as silicon oxide material layers, and the passivation layer is configured as a silicon nitride material layer.

9. A method for fabricating a semiconductor structure, characterized in that: The method for preparing the alignment mark structure as described in any one of claims 1 to 8.

10. A semiconductor structure, characterized in that, include: Substrate; A first dielectric layer is formed above the substrate, and the upper surface of the first dielectric layer has a first upper surface portion and a second upper surface portion, wherein the first upper surface portion is higher than the second upper surface portion; An alignment mark structure is formed on a portion of the first upper surface of the first dielectric layer; A conductive circuit layer covering at least a portion of the second upper surface portion, the conductive circuit layer being separated from the alignment mark structure and electrically connected to the underlying conductive structure; as well as A second dielectric layer covers the conductive circuit layer and the exposed second upper surface portion of the first dielectric layer, with at least a portion of the upper surface of the alignment mark structure exposed in the second dielectric layer.

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