Soi wafer marking and method of forming the same
Patent Information
- Application Number
- CN202610955807.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-29
- Publication Date
- 2026-09-25
AI Technical Summary
[0005]本发明的目的在于提供一种SOI晶圆标记及其形成方法，以解决激光标记过程中产生氧化物残屑难以去除，造成在后续化学机械研磨等工艺中引发缺陷以及激光标记区域平整度严重恶化，后续光刻工艺中因标记码区域的平整度差导致机台过货异常的问题
[0021]在本发明提供的一种SOI晶圆标记的形成方法中，SOI晶圆包括自下而上依次堆叠的衬底硅、埋氧层及顶层硅，顶层硅远离衬底硅的一面形成有钝化层；先形成贯穿所述钝化层和所述顶层硅并延伸至所述埋氧层内的开口，位于埋氧层内的开口深度为第一深度；然后形成SOI 晶圆的标记码，标记码位于开口下方的衬底硅的顶表面。该方法通过刻蚀去除部分埋氧层，有效解决了厚埋氧层SOI晶圆激光标记区域平整度恶化的问题，避免了后续光刻工艺中因平整度不足导致的机台过货异常，同时消除了激光直接在薄顶层硅上标记时因导热差异引起的界面变形、爆裂及产生氧化物残屑等问题，从而显著降低了后续化学机械研磨工艺中的划伤缺陷和破片风险，提升了产品良率和工艺稳定性。
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Figure CN122825835A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an SOI wafer marker and a method for forming the same. Background Technology
[0002] Large-size wafers are extremely valuable in manufacturing processes. To ensure accurate traceability, each wafer must be distinguished to prevent operational confusion. Laser marking identification numbers are an effective means of achieving this. Typically, during the process of processing wafers into the required chips or integrated circuits, a laser mark is created on the outer periphery of the wafer. The laser mark consists of numbers or characters, representing a code, encoding, or serial number; by reading the laser mark, the wafer being processed can be identified, for example, its batch number. The conventional laser marking process is performed near the wafer notch. The laser mark is generally formed on the substrate layer of the silicon wafer, and can be read using observation tools to obtain the wafer's encoding or batch number information.
[0003] For conventional wafers, laser markings are typically printed directly on the front side. However, for silicon-on-insulator (SOI) wafers, the top silicon layer is too thin to be directly marked on the front. Attempting to mark the substrate silicon from the front of the SOI wafer is problematic because the laser marking process generates significant heat. The difference in thermal conductivity between the buried oxide layer and the top and substrate silicon can easily cause deformation or cracking at the interface, resulting in silicon and oxide residues. Even after wafer cleaning, these residues are difficult to remove, leading to scratches and defects in subsequent chemical mechanical polishing processes, resulting in low yields and wafer breakage.
[0004] For buried oxide layers with a thickness of less than 4000 Å, the marking code can be applied to the substrate silicon by etching away the top silicon layer and the buried oxide layer. However, for buried oxide layers with a thickness of more than 4000 Å, etching the top silicon layer and the buried oxide layer will create deep pits, which will severely degrade the flatness of the marking code area. In subsequent photolithography processes, the poor flatness of the marking code area will cause problems with the machine's feed rate. Summary of the Invention
[0005] The purpose of this invention is to provide an SOI wafer marking method and a method for forming the marking, in order to solve the problems of oxide residues generated during laser marking being difficult to remove, causing defects in subsequent chemical mechanical polishing and other processes, and the serious deterioration of the flatness of the laser marking area, leading to abnormal machine feeds in subsequent photolithography processes due to the poor flatness of the marking code area.
[0006] To address the above problems, this invention provides a method for forming SOI wafer markers, comprising:
[0007] An SOI wafer is provided, the SOI wafer comprising a substrate silicon, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top, wherein a passivation layer is formed on the side of the top silicon layer away from the substrate silicon.
[0008] An opening is formed, which penetrates the passivation layer and the top silicon layer and extends into the buried oxide layer, wherein the depth of the opening located in the buried oxide layer is a first depth;
[0009] A marking code is formed on the SOI wafer, the marking code being located on the top surface of the substrate silicon below the opening.
[0010] Optionally, the number of openings is one, and the width of one opening is at least greater than the length of the mark code.
[0011] Optionally, the number of openings is multiple, and the sum of the widths of the multiple openings is at least greater than the length of the mark code.
[0012] Optionally, the plurality of openings may include grid-type structural openings.
[0013] Optionally, the thickness of the buried oxide layer is greater than 4500 Å, and the first depth is 4000 Å.
[0014] Optionally, an anti-corrosion coating is also formed on the passivation layer, and the step of forming the opening includes:
[0015] An edge adhesive removal process is performed, firstly forming a first opening on the resist coating to define a marking area, and then performing a first etching process to etch the passivation layer and the top silicon along the first opening;
[0016] A second etching process is performed to etch the buried oxide layer of the marked area along the first opening to form a second opening, the depth of which is the first depth.
[0017] Optionally, the marking area is located at the edge of the SOI wafer.
[0018] Optionally, prior to the step of forming the marking code on the SOI wafer, the process further includes: removing the resist coating from the non-marked areas using a wet resist removal process.
[0019] Optionally, the passivation layer is made of silicon oxide, and the thickness of the passivation layer is 100 Å to 700 Å.
[0020] Based on the same inventive concept, the present invention also provides an SOI wafer marker, which is prepared by the SOI wafer marker formation method described above.
[0021] In a method for forming SOI wafer marking provided by this invention, the SOI wafer includes a substrate silicon, a buried oxide layer, and a top silicon layer stacked sequentially from bottom to top. A passivation layer is formed on the side of the top silicon layer away from the substrate silicon. An opening is first formed, penetrating the passivation layer and the top silicon layer and extending into the buried oxide layer, with the opening depth within the buried oxide layer being a first depth. Then, a marking code for the SOI wafer is formed, located on the top surface of the substrate silicon below the opening. This method effectively solves the problem of deteriorated flatness in the laser marking area of a thick buried oxide layer SOI wafer by etching away part of the buried oxide layer. This avoids machine overruns caused by insufficient flatness in subsequent photolithography processes. It also eliminates problems such as interface deformation, cracking, and oxide residue generation caused by thermal conductivity differences when lasers directly mark on thin top silicon layers. This significantly reduces scratches and breakage risks in subsequent chemical mechanical polishing processes, improving product yield and process stability. Attached Figure Description
[0022] Figure 1 This is a flowchart of the method for forming SOI wafer markers in Embodiment 1 of the present invention.
[0023] Figure 2 This is a schematic diagram of the SOI wafer structure in Embodiment 1 of the present invention.
[0024] Figure 3 This is a schematic diagram of the structure of the passivation layer formed on the top silicon layer of the SOI wafer in Embodiment 1 of the present invention.
[0025] Figure 4 This is a schematic diagram of the structure of forming an anti-corrosion coating on the passivation layer of the SOI wafer in Embodiment 1 of the present invention.
[0026] Figure 5 This is a schematic diagram of the structure in which a first opening is formed on the resist coating of an SOI wafer in Embodiment 1 of the present invention.
[0027] Figure 6 This is a schematic diagram of the structure of the SOI wafer with the passivation layer removed along the first opening in Embodiment 1 of the present invention.
[0028] Figure 7 This is a schematic diagram of the SOI wafer structure in Embodiment 1 of the present invention, showing the removal of the top layer silicon along the first opening.
[0029] Figure 8 This is a schematic diagram of the structure for forming a second opening on an SOI wafer in Embodiment 1 of the present invention.
[0030] Figure 9 This is a schematic diagram of the structure of the resist coating on the SOI wafer after removing the unmarked areas in Embodiment 1 of the present invention.
[0031] Figure 10This is a schematic diagram of the SOI wafer forming marking code in Embodiment 1 of the present invention.
[0032] Figure 11 This is a schematic diagram of the structure in Embodiment 2 of the present invention, showing the formation of a first opening on the resist coating of an SOI wafer.
[0033] Figure 12 This is a top view of the formation of the first opening on the resist coating of the SOI wafer in Example 2.
[0034] Figure 13 This is a schematic diagram of the structure of the SOI wafer with the passivation layer removed along the first opening in Embodiment 2 of the present invention.
[0035] Figure 14 This is a schematic diagram of the SOI wafer structure in Embodiment 2 of the present invention, showing the removal of the top layer silicon along the first opening.
[0036] Figure 15 This is a schematic diagram of the structure for forming a second opening on an SOI wafer in Embodiment 2 of the present invention.
[0037] Figure 16 This is a schematic diagram of the structure of the resist coating on the SOI wafer after removing the unmarked areas in Embodiment 2 of the present invention.
[0038] Figure 17 This is a schematic diagram of the SOI wafer forming marking code in Embodiment 2 of the present invention.
[0039] The reference numerals in the attached figures are explained as follows:
[0040] 101-Substrate silicon; 102-Buried oxide layer; 103-Top silicon layer; 104-Passivation layer; 105-Resist coating; 106-Marking area; 106a-First opening; 107a-First opening; 106b-Second opening; 107b-Second opening; 108-Marking code. Detailed Implementation
[0041] The SOI wafer marker and its formation method provided by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly illustrating the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures need to show different emphases and sometimes use different scales. It should be understood that relative terms such as "above," "below," "top," and "bottom" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between the various components, elements, steps, etc.
[0042] Example 1
[0043] Figure 1 This is a flowchart of the method for forming SOI wafer markers in Embodiment 1 of the present invention. Figure 1 As shown, this embodiment provides a method for forming SOI wafer markers, including:
[0044] Step S1: Provide an SOI wafer, the SOI wafer comprising a substrate silicon, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top, wherein a passivation layer is formed on the side of the top silicon layer away from the substrate silicon.
[0045] Step S2, forming an opening that penetrates the passivation layer and the top silicon layer and extends into the buried oxide layer, wherein the depth of the opening within the buried oxide layer is a first depth;
[0046] Step S3: Form a marking code for the SOI wafer, the marking code being located on the top surface of the substrate silicon below the opening.
[0047] Figures 2 to 10 This is a schematic diagram of the structure corresponding to the steps of the SOI wafer marker formation method provided in Embodiment 1 of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following is in conjunction with... Figures 2 to 10 The method for forming SOI wafer markers provided in this embodiment will be described in detail.
[0048] In step S1, as Figure 2As shown, an SOI wafer is provided, the SOI wafer comprising a substrate silicon 101, a buried oxide layer 102 and a top silicon layer 103 stacked sequentially from bottom to top.
[0049] Please continue to refer to this. Figure 2 The thickness of the substrate silicon 101 is, for example, 600 μm to 800 μm, the thickness of the buried oxide layer 102 is, for example, greater than 4500 Å, and the thickness of the top silicon layer 103 is, for example, 200 Å to 2000 Å. Before the step of forming a passivation layer on the front side of the SOI wafer, the SOI wafer is cleaned to remove surface contaminants.
[0050] like Figure 3 As shown, a passivation layer 104 is formed on the side of the top silicon 103 of the SOI wafer away from the substrate silicon 101. The material of the passivation layer 104 is, for example, silicon oxide, and it is formed using a thermal oxidation process or a chemical vapor deposition (CVD) process. The thickness of the passivation layer 104 is, for example, 100 Å to 900 Å. In this embodiment, for example, a layer of silicon oxide is grown on the surface of the top silicon 103 of the SOI wafer as a passivation layer using a chemical vapor deposition process. The chemical vapor deposition process parameters are: deposition temperature, for example, 300°C to 450°C; reactant gases, for example, SiH4 and O2; radio frequency power, for example, 100W to 450W; and deposition rate, for example, 100 Å / min to 450 Å / min. In this embodiment, the thickness of the passivation layer 104 is, for example, 350 Å. The passivation layer 104 serves to protect the top silicon 103 from damage during subsequent etching and chemical mechanical polishing processes, and to provide a suitable substrate for the coating of the resist coating, thereby forming a more uniform and continuous resist coating.
[0051] like Figure 4 As shown, a resist coating 105 is also formed on the passivation layer 104 formed on the SOI wafer. The material forming the resist coating 105 is, for example, photoresist, and the photoresist layer is formed as the resist coating 105 using a spin-coating process. The thickness of the resist coating 105 is, for example, 100 nm to 550 nm. The spin-coating speed is, for example, 1500 rpm to 4000 rpm, and the soft-baking temperature after spin-coating is, for example, 90°C to 110°C, and the soft-baking time is, for example, 60 s to 110 s, to ensure a uniform thickness of the resist coating 105.
[0052] In step S2, the opening is formed, penetrating the passivation layer 104 and the top silicon layer 103 and extending into the buried oxide layer 102. The etching depth of the opening within the buried oxide layer 102 is a first depth. In this embodiment, there is one opening, the width of which is at least greater than the length of the marking code. The width of the opening is, for example, 1.5 cm to 2.0 cm. The thickness of the buried oxide layer 102 is, for example, greater than 4500 Å, and the first depth is, for example, 4000 Å.
[0053] like Figures 5 to 8 As shown, the steps for forming the opening include:
[0054] Step S21: Perform an edge adhesive removal process. First, form a first opening 106a on the resist coating 105 to define the marking area 106. Then, perform a first etching process to etch the passivation layer 104 and the top silicon layer 103 along the first opening 106a.
[0055] Step S22: Perform a second etching process to etch the buried oxide layer 102 of the marked region 106 along the first opening 106a to form a second opening 106b. The etching depth of the second opening 106b located in the buried oxide layer 102 is the first depth.
[0056] In step S21, please continue to refer to Figure 5The edge resist removal process, which includes wafer edge exposure (WEE), is performed. The marking region 106 is located at the edge of the SOI wafer to avoid the central device region. In this embodiment, for example, the wafer edge exposure process is used to form the first opening 106a in the edge region of the SOI wafer, for example, near the SOI wafer notch. The first opening 106a is used to define the marking region 106. The wafer edge exposure process, for example, involves placing the SOI wafer, after the resist coating 105 has been applied, in a WEE device, which includes an annular exposure light source located above the edge of the SOI wafer. The position of the SOI wafer is adjusted so that the SOI wafer notch is aligned with a predetermined exposure area of the annular exposure light source. The exposure width of the annular exposure light source is set to extend 2mm to 4mm from the edge of the SOI wafer towards the center, for example, the exposure wavelength is 365nm, and the exposure dose is 200mJ / cm² to 450mJ / cm². During the wafer edge exposure process, the annular exposure light source selectively exposes the edge region of the resist coating 105, with the exposed region covering the area near the notch of the SOI wafer. After exposure, the exposed resist coating 105 is developed, for example, using tetramethylammonium hydroxide (TMAH) developer, with development parameters such as a development time of 30 to 50 seconds and a development temperature of 25°C. After development, a first opening 106a is formed in the edge region of the SOI wafer near the notch, penetrating the resist coating and exposing the top surface of the passivation layer, thereby exposing the passivation layer 104 below the marked area 106.
[0057] The first etching process is performed to remove the passivation layer 104 and the top silicon layer 103 of the marked region 106. In this embodiment, the first etching process includes a first etching step and a second etching step, wherein the first etching step is used to remove the passivation layer 104 and the second etching step is used to remove the top silicon layer 103.
[0058] Please continue to refer to this. Figure 6Along the first opening 106a, the first step of etching is performed to remove the passivation layer 104. The etching gas for the first step of etching is, for example, a mixture of CF4, CHF3 and Ar, or a mixture of C4F8 and O2. The etching parameters are, for example, a chamber pressure of 10 mTorr to 65 mTorr, an RF power of 200 W to 650 W, and an etching rate of approximately 500 Å / min to 1850 Å / min. The first dry etching is stopped when the etching endpoint is detected, for example, by monitoring the SiF or CO signal using optical emission spectroscopy. In this embodiment, the thickness of the passivation layer 104 is, for example, 350 Å, and the etching time is 15 s to 55 s. After the first dry etching is completed, the passivation layer 104 in the marked region 106 is completely removed, exposing the top silicon 103.
[0059] Please continue to refer to this. Figure 7 Along the first opening 106a, the second etching step is performed to remove the top silicon 103. The etching gas used in the second etching step is, for example, a mixture of SF6 and O2, or a mixture of Cl2 and HBr. The etching parameters are, for example, a chamber pressure of 5 mTorr to 40 mTorr, an RF power of 300 W to 550 W, and an etching rate of 1000 Å / min to 4500 Å / min. The second dry etching is stopped when the buried oxide layer 102 is reached, determined by endpoint detection. In this embodiment, the thickness of the top silicon 103 is, for example, 450 Å, and the etching time is 15 s to 40 s. After etching is completed, the top silicon 103 in the marked region 106 is completely removed, exposing the buried oxide layer 102.
[0060] In step S22, please continue to refer to Figure 8The second etching process is performed to etch the buried oxide layer 102 of the marked region 106 along the first opening 106a to form a second opening 106b. The etching depth of the second opening 106b within the buried oxide layer 102 is the first depth, which is, for example, 4000 Å. The etching gas for the second etching process is, for example, a mixture of CF4, CHF3, and Ar, or a mixture of C4F8, CO, and Ar. The etching parameters for the second etching process are, for example, a chamber pressure of 20 mTorr to 70 mTorr, an RF power of 400 W to 950 W, and an etching rate of 1000 Å / min to 3500 Å / min. The etching is stopped when the substrate silicon 101 is reached, determined by endpoint detection. In this embodiment, the thickness of the buried oxide layer 102 is, for example, 4500 Å, and the etching time is, for example, 60 s to 150 s. After the second etching process is completed, the second opening 106b stops within the buried oxide layer 102. The etching depth of the second opening 106b within the buried oxide layer 102 is, for example, 4000 Å, without exposing the top surface of the substrate silicon 101.
[0061] like Figure 9 As shown, before the step of forming the marking code on the SOI wafer, the process further includes: removing the resist coating 105 from the non-marked areas using a wet stripping process. The non-marked areas are the areas on the SOI wafer other than the marking areas 106. In this embodiment, for example, the wet stripping process is used to remove the resist coating 105 from the non-marked areas. The wet stripping process is, for example, immersing the SOI wafer in a stripping solution, which is an organic solvent-based stripping solution, such as N-methylpyrrolidone (NMP), dimethyl sulfoxide (DMSO), or a mixture of alkaline monoethanolamine (MEA) and dimethyl sulfoxide. The stripping temperature is, for example, 60°C to 95°C, and the immersion time is, for example, 10 min to 45 min, during which gentle stirring or ultrasonic oscillation can be used to enhance the stripping effect. After the wet stripping process is completed, the SOI wafer is rinsed sequentially with, for example, isopropanol (IPA) and deionized water, and then spun dry. Alternatively, a sulfuric acid-hydrogen peroxide (SPM) solution (H2SO4:H2O2 = 3:1~5:1), at a temperature of 100℃~115℃, and a treatment time of 5min~20min can be used to treat the SOI wafer to further remove residual organic contaminants. In this case, the passivation layer 104, the top silicon layer 103, and the buried oxide layer 102 in the unmarked area remain intact and are not affected by any etching.
[0062] In step S3, as Figure 10As shown, the marking code 108 forming the SOI wafer is located on the top surface of the substrate silicon 101 below the opening. In this embodiment, for example, a laser marking device is used to form the marking code 108 on the top surface of the substrate silicon 101 below the second opening 106b. The parameters of the laser marking are, for example, an infrared nanosecond laser with a wavelength of 1064nm or an ultraviolet picosecond laser with a wavelength of 355nm, a laser power of 2W~15W, and a scanning speed of 100mm / s~550mm / s, to form a clear marking code 108. Since the passivation layer 104, the top silicon layer 103, and part of the buried oxide layer 102 in the marked region 106 are removed, the laser passes through the remaining part of the buried oxide layer 102 and acts on the substrate silicon 101. The small amount of oxide residue generated is located in the second opening 106b. In subsequent device manufacturing processes, including chemical mechanical polishing, photolithography, etching, etc., scratch defects will not be caused, which significantly improves the yield of SOI wafer products.
[0063] Please continue to refer to this. Figure 10 This embodiment also provides an SOI wafer marker, which is prepared using the aforementioned SOI wafer marker formation method. The SOI wafer marker is the marking code 108. After the marking code 108 is formed, it can be read using, for example, an optical microscope or an automated optical inspection (AOI) device to confirm its clarity and legibility. In this embodiment, the length of the marking code 108 is, for example, 0.5cm to 1.4cm, and the width of one of the openings is greater than the length of the marking code 108. The marking code 108 consists of numbers or characters, representing the batch number information of the SOI wafer, thus meeting the requirements for accurate identification and traceability management of large-size SOI wafers in complex manufacturing processes.
[0064]
Example 2
[0065] The difference between this embodiment and Embodiment 1 is that the number of openings in step S2 is multiple, and the sum of the widths of the multiple openings is at least greater than the length of the marking code 108. In this embodiment, the sum of the widths of the multiple openings is, for example, 1.5cm to 2.0cm, and the multiple openings are, for example, grid-type structure openings.
[0066] Figures 11 to 17 This is a schematic diagram of the structure corresponding to the steps of the SOI wafer marker formation method provided in Embodiment 2 of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following is in conjunction with... Figures 11 to 17 The method for forming SOI wafer markers provided in this embodiment will be described in detail.
[0067] like Figures 11 to 15As shown, the steps for forming the opening include:
[0068] Step S21: Perform an edge adhesive removal process. First, form a first opening 107a on the resist coating 105 to define the marking area 106. Then, perform a first etching process to etch the passivation layer 104 and the top silicon layer 103 along the first opening 107a.
[0069] Step S22: Perform a second etching process to etch the buried oxide layer 102 of the marking region 106 along the first opening 107a to form a second opening 107b. The etching depth of the second opening 107b located in the buried oxide layer 102 is the first depth.
[0070] In step S21, please continue to refer to Figure 11 The difference from the edge adhesive removal process in Embodiment 1 is that a grid-type mask (not shown in the figure) is added, and an exposure and development process is performed to form the first opening 107a. The steps for forming the first opening 107a are, for example, as follows: First, a grid-type mask is placed on the resist coating 105, and exposure is performed, for example, using ultraviolet light (UV), with an exposure dose of, for example, 50 mJ / cm². 2 ~150mJ / cm 2 The exposure time is, for example, 5s to 15s; followed by development, the developer is, for example, a tetramethylammonium hydroxide (TMAH) aqueous solution, the concentration of the developer is, for example, 2wt% to 3.5wt%, the development temperature is, for example, 20℃ to 25℃, and the development time is, for example, 30s to 90s. Figure 12 This is a top view showing the formation of a first opening in the resist coating of the SOI wafer in Example 2. Figure 11 and Figure 12 As shown, the difference between the first opening 107a in this embodiment and the first opening 107a in Embodiment 1 is that the first opening 107a is, for example, a grid-type structure opening, and the grid-type structure opening consists of multiple openings.
[0071] Please continue to refer to this. Figure 13 Along the first opening 107a, the same first step of etching to remove the passivation layer 104 as in Embodiment 1 is performed.
[0072] Please continue to refer to this. Figure 14 Along the first opening 107a, the second step of etching to remove the top silicon 103 is performed, the same as in Example 1.
[0073] In step S22, please continue to refer to Figure 15The same second etching process as in Embodiment 1 is performed to etch the buried oxide layer 102 of the marked region 106 along the first opening 107a to form the second opening 107b. The etching depth of the second opening 107b within the buried oxide layer 102 is the first depth. In this embodiment, the thickness of the buried oxide layer 102 is, for example, 4500 Å, and the first depth is, for example, 4000 Å.
[0074] like Figure 16 As shown, prior to the step of forming the marking code on the SOI wafer, the process further includes, for example, removing the resist coating 105 from the non-marked area using the same wet resist removal process as in Example 1.
[0075] In step S3, as Figure 17 As shown, the marking code 108 that forms the SOI wafer is located on the top surface of the substrate silicon 101 below the second opening 107b.
[0076] Please continue to refer to this. Figure 17 This embodiment also provides an SOI wafer marker, which is the marker code 108. In this embodiment, the length of the marker code 108 is, for example, 0.5cm to 1.4cm, and the sum of the widths of the plurality of openings is greater than the length of the marker code 108.
[0077] In summary, the SOI wafer marking method provided in this embodiment of the invention includes a substrate silicon, a buried oxide layer, and a top silicon layer stacked sequentially from bottom to top. A passivation layer is formed on the side of the top silicon layer away from the substrate silicon. An opening is first formed that penetrates the passivation layer and the top silicon layer and extends into the buried oxide layer, with the opening depth within the buried oxide layer being a first depth. Then, a marking code for the SOI wafer is formed, located on the top surface of the substrate silicon layer below the opening. This method effectively solves the problem of flatness deterioration in the laser marking area of a thick buried oxide layer SOI wafer by etching away part of the buried oxide layer. This avoids machine overruns caused by insufficient flatness in subsequent photolithography processes. It also eliminates problems such as interface deformation, cracking, and oxide residue caused by thermal conductivity differences when the laser directly marks on the thin top silicon layer. This significantly reduces scratches and breakage risks in subsequent chemical mechanical polishing processes, improving product yield and process stability.
[0078] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0079] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for forming SOI wafer markers, characterized in that, include: An SOI wafer is provided, the SOI wafer comprising a substrate silicon, a buried oxide layer and a top silicon layer stacked sequentially from bottom to top, wherein a passivation layer is formed on the side of the top silicon layer away from the substrate silicon. An opening is formed, which penetrates the passivation layer and the top silicon layer and extends into the buried oxide layer, wherein the depth of the opening located in the buried oxide layer is a first depth; A marking code is formed on the SOI wafer, the marking code being located on the top surface of the substrate silicon below the opening.
2. The method for forming SOI wafer markers as described in claim 1, characterized in that, The number of openings is one, and the width of one opening is at least greater than the length of the mark code.
3. The method for forming SOI wafer markers as described in claim 1, characterized in that, The number of openings is multiple, and the sum of the widths of the multiple openings is at least greater than the length of the mark code.
4. The method for forming SOI wafer markers as described in claim 3, characterized in that, The plurality of openings include grid-type structural openings.
5. The method for forming SOI wafer markers as described in claim 1, characterized in that, The thickness of the buried oxide layer is greater than 4500 Å, and the first depth is 4000 Å.
6. The method for forming SOI wafer markers as described in claim 1, characterized in that, An anti-corrosion coating is also formed on the passivation layer, and the step of forming the opening includes: An edge adhesive removal process is performed, firstly forming a first opening on the resist coating to define a marking area, and then performing a first etching process to etch the passivation layer and the top silicon along the first opening; A second etching process is performed to etch the buried oxide layer of the marked area along the first opening to form a second opening, the depth of which is the first depth.
7. The method for forming SOI wafer markers as described in claim 6, characterized in that, The marked area is located at the edge of the SOI wafer.
8. The method for forming SOI wafer markers as described in claim 6, characterized in that, Prior to the step of forming the marking code on the SOI wafer, the process further includes: removing the resist coating from the non-marked areas using a wet resist removal process.
9. The method for forming SOI wafer markers as described in claim 1, characterized in that, The passivation layer is made of silicon oxide and has a thickness of 100 Å to 700 Å.
10. An SOI wafer marker, characterized in that, It is prepared using the SOI wafer marker formation method as described in any one of claims 1 to 9.