Method for manufacturing a rewiring layer, rewiring layer and chip packaging structure

Abstract

The application provides a preparation method of a rewiring layer, the rewiring layer and a chip packaging structure. The method first forms a conductive layer on a first insulating layer, the conductive layer including at least a conductive trace filled in an insulating layer via hole, and the thickness of the conductive trace at the insulating layer via hole is greater than the hole depth of the insulating layer via hole. Then, based on the thickness of the conductive layer at different position regions on the first insulating layer, a spraying matrix composed of multiple nozzles is used to perform zoned etching on the conductive layer at different position regions to obtain a trace layer formed by a trace and a conductive column. The above scheme significantly improves the plating flatness of the conductive layer at the insulating layer via hole of the first insulating layer by first increasing the plating thickness of the conductive layer on the first insulating layer (i.e., the front insulating layer) at the overlapping insulating layer via hole, and then performing overall thinning and flattening treatment, thereby reducing the adverse effect on the opening morphology of the insulating layer via hole of the second insulating layer (i.e., the rear insulating layer), and ensuring the preparation yield of the rewiring layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more specifically, to a method for preparing a redistribution layer, the redistribution layer, and a chip packaging structure. Background Technology

[0002] In the redistribution layer (RDL) fabrication process, due to limitations in chip packaging space and signal transmission requirements, stacked vias are commonly used in the product stack-up structure. However, in the two overlapping redistribution sublayers at the stacked vias of the redistribution layer, the limited flatness of the electroplating filling at the insulating layer vias of the first redistribution sublayer directly leads to poor opening morphology of the insulating layer vias of the second redistribution sublayer, thus affecting the overall fabrication yield of the redistribution layer. Therefore, how to improve the opening yield of the second redistribution sublayer at the stacked vias in the redistribution layer structure has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] To overcome the technical problems mentioned in the above background, this application provides a method for fabricating a redistribution layer. The redistribution layer includes stacked insulating layers and a routing layer located between adjacent insulating layers. The adjacent insulating layers include a first insulating layer and a second insulating layer located on the first insulating layer. The vias of the first insulating layer overlap with the vias of the second insulating layer. The method includes: A conductive layer is formed on the first insulating layer, wherein the conductive layer includes conductive traces that fill at least the insulating layer vias of the first insulating layer, and the thickness of the conductive traces at the insulating layer vias is greater than the depth of the insulating layer vias in a direction perpendicular to the plane of the first insulating layer. Based on the thickness of the conductive layer at different locations on the first insulating layer, a spray matrix composed of multiple nozzles is used to etch the conductive layer at different locations in sections, resulting in a trace layer formed by traces and conductive pillars, wherein the side of the traces and conductive pillars away from the first insulating layer is a flat plane.

[0004] In one possible implementation, the step of fabricating a conductive layer on the first insulating layer includes: A seed layer is formed on one side of the first insulating layer; A conductive material layer is fabricated based on the seed layer; The conductive layer is obtained by patterning the conductive material layer.

[0005] In one possible implementation, the step of using a spray matrix composed of multiple nozzles to etch the conductive layer in different locations on the first insulating layer, based on the thickness of the conductive layer at different locations, to obtain a trace layer formed by traces and conductive pillars, includes: The thickness of the conductive layer at different locations on the first insulating layer is obtained; The etching solution spray intensity for different locations is determined based on the thickness of those locations. The nozzle performs etching on the corresponding location area based on the etching liquid spray intensity, to obtain a trace layer formed by the traces and conductive pillars.

[0006] Another objective of this application is to provide a redistribution layer, the redistribution layer comprising stacked insulating layers and routing layers located between adjacent insulating layers; The insulating layer further includes insulating layer vias, and the wiring layer includes conductive pillars that fill at least the insulating layer vias and wiring distributed on one side of the insulating layer; The adjacent insulating layers include a first insulating layer and a second insulating layer located on the first insulating layer. The insulating through-holes of the first insulating layer overlap with the insulating through-holes of the second insulating layer. At the first insulating layer, the conductive post and the trace on the side away from the first insulating layer are a flat plane. In the direction perpendicular to the plane of the first insulating layer, the thickness of the conductive post at the insulating through-hole is greater than or equal to the depth of the insulating through-hole.

[0007] In one possible implementation, at the first insulating layer, the side of the trace away from the first insulating layer is flush with the side of the conductive post away from the first insulating layer.

[0008] In one possible implementation, at the first insulating layer, the conductive post includes a conductive post body filling the through-hole of the insulating layer and a conductive post trace located on the side of the conductive post body away from the first insulating layer, the orthographic projection of the conductive post trace on the first insulating layer covering the through-hole of the insulating layer.

[0009] In one possible implementation, the insulating through-hole of the second insulating layer includes a first through-hole sidewall and a second through-hole sidewall. The angle formed between the first through-hole sidewall and the conductive post surface at the insulating through-hole of the first insulating layer is a first angle, and the angle formed between the second through-hole sidewall and the conductive post surface at the insulating through-hole of the first insulating layer is a second angle. The first angle and the second angle are the same.

[0010] In one possible implementation, the first angle is in the range of 90° to 115°.

[0011] In one possible implementation, the redistribution layer further includes a seed layer located between the insulating layer and the routing layer.

[0012] Another objective of this application is to provide a chip packaging structure, which includes the aforementioned multiple redistribution layers provided in this application.

[0013] Based on any of the above aspects, embodiments of this application provide a method for fabricating a redistribution layer, a redistribution layer, and a chip packaging structure. The method first fabricates a conductive layer on a first insulating layer. This conductive layer includes conductive traces that at least fill the vias in the insulating layer, and the thickness of the conductive traces at the vias is greater than the depth of the vias. Then, based on the thickness of the conductive layer at different locations on the first insulating layer, a spray matrix composed of multiple nozzles is used to perform partitioned etching of the conductive layer at different locations, resulting in a redistribution layer formed by traces and conductive pillars. This solution, by first increasing the plating thickness of the conductive layer on the first insulating layer (i.e., the front insulating layer) at the overlapping vias, and then performing overall thinning and leveling treatment, significantly improves the plating flatness of the conductive layer at the vias in the first insulating layer, thereby reducing the adverse effects on the via morphology of the second insulating layer (i.e., the rear insulating layer), effectively ensuring the yield of the redistribution layer. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a process diagram illustrating the fabrication of a portion of the film layer in a redistribution layer in the prior art. Figure 2 This is a schematic flowchart of a method for fabricating a redistribution layer provided in this embodiment; Figure 3 for Figure 2 Corresponding process flow chart; Figure 4 This is a schematic diagram of the structure after the conductive layer is prepared in step S12 of this embodiment; Figure 5 A schematic diagram of the zone etching of the spray matrix provided in this embodiment; Figure 6 Provided for this embodiment Figure 2 Process diagram for step S12; Figure 7 This is a schematic diagram of the nozzle action area in the spray matrix provided in this embodiment; Figure 8 for Figure 2 A flowchart illustrating the sub-steps of step S11; Figure 9 for Figure 8 Corresponding process flow chart; Figure 10 This is a schematic diagram of a redistribution layer provided in this embodiment; Figure 11 This is a schematic diagram of a chip packaging structure provided in this embodiment.

[0016] Icons: Insulating layer-11; First insulating layer-110; Insulating layer via-111; Conductive layer-12; Tracing layer-13; Conductive layer-131; Tracing-130; Conductive pillar-14; Seed layer-15; Second insulating layer-112; First via sidewall-1101; Second via sidewall-1102; Conductive trace-120; First conductive trace-1201; Second conductive trace-1202; Conductive pillar body-1310; Conductive pillar trace-1311; Redirecting layer-1; Nozzle-170; Substrate-18; Chip-19; Encapsulation layer-20; Nozzle channel-171; Pressure gauge-172; Pressure regulating valve-174; Etching solution delivery pump-173. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0022] The inventors discovered through research that, in the redistribution layer 1 (RDL) process, due to limitations in chip packaging space and signal transmission requirements, stacked vias are commonly used in the product stack-up structure. However, in the two overlapping redistribution sublayers at the stacked vias of the redistribution layer 1, the limited flatness of the plating filling at the insulating layer via 111 of the front redistribution sublayer A directly leads to poor opening morphology of the insulating layer via 111 of the rear redistribution sublayer B. For example, please refer to... Figure 1 , Figure 1 The existing fabrication process diagram for a portion of the redistribution layer 1 shows that during the fabrication of the preceding redistribution sublayer A, the plating thickness of this layer is fixed and cannot be changed according to process requirements, resulting in limited via-filling capability. After plating, the wiring layer 13 easily forms depressions at the vias 111 in the insulating layer. This directly affects the opening morphology and process performance of the vias 111 in the subsequent redistribution sublayer B, thereby affecting the overall fabrication yield of the redistribution layer 1. Therefore, how to improve the opening yield of the subsequent redistribution sublayer B at the stacked vias in the redistribution layer 1 has become a technical problem urgently needing to be solved by those skilled in the art.

[0023] In order to solve the aforementioned technical problems, the inventors have innovatively designed the following technical solutions, and the specific implementation scheme of this application will be described in detail below with reference to the accompanying drawings.

[0024] Please see Figure 2 and Figure 3 , Figure 1 This is a schematic flowchart illustrating the steps of a method for fabricating redistribution layer 1 provided in this embodiment. Figure 3 for Figure 2The corresponding process diagram is shown. The redistribution layer includes stacked insulating layers 11 and a routing layer 13 located between adjacent insulating layers 11. Each adjacent insulating layer 11 includes a first insulating layer 110 and a second insulating layer 112 located on the first insulating layer 110. The insulating vias 111 of the first insulating layer 110 and the insulating vias 111 of the second insulating layer 112 overlap. In this embodiment, the plating smoothness at the insulating vias 111 of the first insulating layer 110 directly affects the opening morphology of the insulating vias 111 of the second insulating layer 112. That is, if the conductive pillars 131 at the insulating vias 111 of the first insulating layer 110 are recessed, it directly increases the difficulty of opening the insulating vias 111 of the second insulating layer 112 on the conductive pillars 131, resulting in poor opening morphology of the insulating vias 111 of the second insulating layer 112, thereby affecting the fabrication yield of the redistribution layer 1. This embodiment provides a method for fabricating a redistribution layer 1 for stacked vias, which is described below in conjunction with... Figure 2 and Figure 3 The fabrication method of the redistribution layer 1 is described in detail.

[0025] Step S11: A conductive layer 12 is formed on the first insulating layer 110. The conductive layer 12 includes conductive traces 120 that fill at least the insulating through-holes 111 of the first insulating layer 110. In a direction perpendicular to the plane of the first insulating layer 110, the thickness of the conductive traces 120 at the insulating through-holes 111 is greater than the depth of the insulating through-holes 111.

[0026] In this step, the first insulating layer 110 can be a first film layer formed directly on a temporary carrier plate (not shown in the figure), or it can be another film layer in the redistribution layer 1. When the first insulating layer 110 is formed on the temporary carrier plate, the temporary carrier plate can serve as a mechanical support substrate in subsequent processes. For example, the temporary carrier plate can be a glass carrier plate. The first insulating layer 110 has a uniform thickness and a smooth surface. The thickness of the first insulating layer 110 is not specifically limited here. The conductive layer 12 can be obtained by electroplating based on the seed layer 15 and then performing patterning processing.

[0027] In this embodiment, an insulating layer through-hole 111 is obtained by opening a hole in the first insulating layer 110, and the depth of the insulating layer through-hole 111 is the thickness of the first insulating layer 11. Furthermore, the position of the insulating layer through-hole 111 corresponds to the position of the insulating layer through-hole 111 in the subsequent insulating layer 11 (i.e., the second insulating layer 112). That is, the insulating layer through-hole 111 of the second insulating layer 112 is opened based on the insulating layer through-hole 111 of the first insulating layer 110.

[0028] In this embodiment, please refer to Figure 4 , Figure 4This is a schematic diagram of the structure after the conductive layer 12 is prepared in step S11 of this embodiment. The conductive layer 12 includes conductive traces 120 located at the insulating layer via 111 and conductive layers 12 located on one side of the first insulating layer 110. The conductive layer 12 located at the insulating layer via 111 is used to form conductive pillars 131 of the wiring layer 13, and the conductive layer 12 located on the first insulating layer 11 is used to form traces 130 of the wiring layer 13. The conductive traces 120 at the insulating layer via 111 at least fill the insulating layer via 111, that is, the conductive traces 120 at the insulating layer via 111 include a first conductive trace 1201 filled within the insulating layer via 111 and a second conductive trace 1202 located on the first conductive trace 1201.

[0029] In this embodiment, please refer to Figure 4 The thickness D1 of the conductive trace 120 at the insulating layer via 111 is greater than the hole depth D2 of the insulating layer via 111. That is, the lowest point of the recess of the conductive trace 120 at the insulating layer via 111 of the first insulating layer 110 is greater than the hole depth of the insulating layer via 111 of the first insulating layer 110. In this way, the overall thickness of the conductive trace 120 on the first insulating layer 110 is increased, which prepares for the subsequent etching and thinning process. After the etching and thinning process, the thickness of the conductive pillar 131 at the insulating layer via 111 should be greater than or equal to the hole depth of the insulating layer via 111. That is, the conductive trace 120 at least fills the insulating layer via 111, and its thickness is greater than the hole depth of the insulating layer via 111. In addition, the thickness of the conductive trace 120 at the insulating layer via 111 of the first insulating layer 110 can be the same as the thickness of the conductive layer 12 located on one side of the first insulating layer.

[0030] Step S12: Based on the thickness of the conductive layer 12 at different locations on the first insulating layer 11, a spray matrix composed of multiple nozzles 170 is used to perform partition etching on the conductive layer 12 at different locations to obtain a wiring layer 13 formed by wiring 130 and conductive pillars 131, wherein the side of the wiring 130 and conductive pillars 131 away from the insulating layer 11 is a flat plane.

[0031] In this step, the first insulating layer 110 can be divided into multiple location regions, each with a nozzle 170. The etching solution spray intensity of the nozzles 170 in different locations is adjusted according to the thickness distribution within each region to balance the etching uniformity, resulting in a smooth wiring layer 13. This provides a foundation for subsequent via opening. The etching solution spray intensity includes both the flow rate and pressure of the etching solution. Please refer to... Figure 5 , Figure 5This is a schematic diagram of the zoned etching process using the spray matrix provided in this embodiment. In this embodiment, the first insulating layer 110 can be divided into six location regions: region A, region B, region C, region E, region F, and region G. Each location region is controlled by a separate nozzle pipe 171, and the spray intensity of the etching solution from the nozzles 170 on each nozzle pipe 171 is controlled by a pressure regulating valve 174, an etching solution delivery pump 173, and a pressure gauge 172. Please refer to... Figure 6 and Figure 7 , Figure 6 Provided for this embodiment Figure 2 The process diagram for step 12 is shown below. Figure 7 This is a schematic diagram of the nozzle action area in the spray matrix provided in this embodiment. Since the area where the etching liquid is sprayed by the nozzle pipe 171 in the spray matrix is ​​a fan-shaped area AA, the etching impact force and flow rate at the edge of this fan-shaped area AA will be reduced. In this embodiment, the etching liquid sprayed by the nozzle 170 in the adjacent nozzle pipe 171 overlaps at the edge of the fan-shaped area AA. In this way, the etching intensity is consistent throughout the entire position area, further ensuring the uniformity of etching.

[0032] In the above scheme, a conductive layer 12 with a relatively large thickness is first fabricated on the first insulating layer 110 to at least fill the insulating layer via 111 of the first insulating layer 110. Then, the conductive layer 12 is thinned and etched using a partition etching process to achieve a smooth surface. This ensures that the surface of the conductive pillar 131 at the insulating layer via 111 of the first insulating layer 110 is smooth, which is beneficial to the opening morphology and process performance of the subsequent via (i.e., the insulating layer via 111 of the second insulating layer 112), thereby ensuring the preparation yield of the redistribution layer 1.

[0033] It is worth noting that when preparing the redistribution layer 1, the above-described scheme can be used to prepare the routing layer 13 on the first insulating layer 110, and then prepare the second insulating layer 112 on the routing layer 13 to form two overlapping insulating layer vias 111. Furthermore, the above-described scheme can be repeated layer by layer on the second insulating layer 112 and subsequent sequentially stacked insulating layers 11 to prepare corresponding routing layers 13, thereby forming multiple overlapping insulating layer vias 111.

[0034] Further, please refer to Figure 8 and Figure 9 , Figure 8 for Figure 1 A flowchart illustrating the sub-steps of step S11. Figure 9 for Figure 8 The corresponding process diagram, step S11 can be implemented in the following way.

[0035] Step S110: Create a seed layer 15 on one side of the first insulating layer 110.

[0036] In this step, a seed layer 15 is formed on one side of the first insulating layer 110, including the inner wall of the insulating layer through hole 111, by means of physical vapor deposition or chemical vapor deposition. The seed layer 15 is usually a composite layer of titanium layer and copper layer, wherein the titanium layer serves as an adhesion barrier layer and the copper layer serves as the electroplating substrate of conductive layer 12.

[0037] Step S111: Fabricate a conductive material layer 16 based on the seed layer 15.

[0038] In this embodiment, by adjusting parameters such as electroplating time and current density, the thickness of the conductive material layer 16 at the insulating layer via 111 is made greater than the depth of the insulating layer via 111. In subsequent via fabrication, the electroplating thickness of the conductive material layer 16 is increased accordingly based on the depth, aperture size, via density selectivity, and number of stacked insulating layer vias 111 of the first insulating layer 110. For example, when the depth or aperture size of the insulating layer via 111 of the first insulating layer 110 is large, depressions are easily formed during electroplating, so it is necessary to adaptively increase the electroplating thickness of the conductive material layer.

[0039] Step S112: The conductive material layer 16 is patterned to obtain the conductive layer 12.

[0040] In this embodiment, after the conductive material layer 16 is patterned, part of the seed layer 15 is exposed, and the exposed seed layer 15 can be removed by partition etching.

[0041] Furthermore, step S12 can be implemented in the following way.

[0042] First, the thickness of the conductive layer 12 at different locations on the first insulating layer 11 is obtained.

[0043] In this step, the thickness of the entire wiring layer 13 can be measured using a thickness measuring device.

[0044] Next, the etching solution spray intensity corresponding to different location regions is determined based on the thickness of different location regions.

[0045] Finally, the nozzle 170 performs etching on the corresponding location area based on the etching liquid spray intensity to obtain the wiring layer 13 formed by the wiring 130 and the conductive pillar 131.

[0046] Based on the same inventive concept, please refer to Figure 10 , Figure 10This is a partial schematic diagram of a redistribution layer 1 provided in this embodiment. This application also provides a redistribution layer 1, which includes an insulating layer 11 and a wiring layer 13 alternately stacked. The insulating layer 11 includes an insulating layer via 111 penetrating the insulating layer 11. The wiring layer 13 is located on one side of the insulating layer 11 and includes conductive pillars 131 at least filled within the insulating layer via 111 and wirings 130 distributed on one side of the insulating layer 11.

[0047] The adjacent insulating layer 11 includes a first insulating layer 110 and a second insulating layer 112 located on the first insulating layer 110. The insulating through-hole 111 of the first insulating layer 110 overlaps with the insulating through-hole 111 of the second insulating layer 112. At the first insulating layer 110, the side of the conductive post 131 and the trace 130 away from the insulating layer 11 is a flat plane. In the direction perpendicular to the plane of the first insulating layer 110, the thickness D3 of the conductive post 131 at the insulating through-hole 111 is greater than or equal to the hole depth D2 of the insulating through-hole 111.

[0048] In the above scheme, after the first insulating layer 110 and the wiring layer 13 on the first insulating layer 110 are prepared, the conductive pillar 131 and the wiring 130 of the wiring layer 13 in the first insulating layer 110 are a flat plane on the side away from the insulating layer 11. In this way, the next insulating layer 11 (i.e., the second insulating layer 112) is then prepared on the basis of the wiring layer 13 of the first insulating layer 110. Since the conductive pillar 131 at the insulating layer via 111 of the first insulating layer 110 is a flat plane, it is beneficial to ensure the opening morphology and process performance of the insulating layer via 111 of the second insulating layer 112, thereby ensuring the preparation yield of the redistribution layer 1.

[0049] In this embodiment, when the conductive post D3 at the insulating layer through-hole 111 of the first insulating layer 110 is greater than the hole depth D2 of the insulating layer through-hole 111, the conductive post 131 includes a conductive post body 1310 filled in the insulating layer through-hole 111 and a conductive post trace 1311 on the side of the conductive post body 1310 away from the first insulating layer 110. When the thickness D3 of the conductive post 131 at the insulating layer through-hole 111 is equal to the hole depth D3 of the insulating layer through-hole 111, the conductive post 131 completely fills the insulating layer through-hole 111.

[0050] Furthermore, please refer to again Figure 10At the first insulating layer 110, the side of the trace 130 away from the first insulating layer 110 is flush with the side of the conductive post 131 away from the first insulating layer 110. In this embodiment, the conductive post 131 includes a conductive post body 1310 filled in the through hole 111 of the insulating layer and a conductive post trace 1311 located on the side of the conductive post body 1310 away from the first insulating layer 110. The side of the conductive post trace 1311 away from the first insulating layer 110 is flush with the side of the trace 130 away from the first insulating layer 110.

[0051] Furthermore, please refer to again Figure 10 At the first insulating layer 110, the conductive pillar 131 includes a conductive pillar body 1310 filled within the insulating layer via 111 and a conductive pillar trace 1311 located on the side of the conductive pillar body 1310 away from the first insulating layer 110. The orthogonal projection of the conductive pillar trace 1311 onto the first insulating layer 110 covers the insulating layer via 111. During the fabrication of the redistribution layer 1, the conductive pillar 131 is formed by the conductive trace 120 located at the insulating layer via 111. In this embodiment, the plating thickness is adaptively increased during the fabrication of the wiring layer 13 of the first insulating layer 110, that is, ensuring that the conductive layer 12 includes the conductive trace 120 filled within the insulating layer via 111, and that the thickness of the conductive trace 120 is greater than the depth of the insulating layer via 111. Therefore, the conductive pillar 131 at the insulating layer via 111 also includes the conductive pillar trace 1311 extending to the first side 11a of the insulating layer 11. This preparation method is more conducive to achieving a smooth surface of the conductive post 131, which is beneficial to the opening morphology and process performance of the insulating layer through hole 111 of the second insulating layer 112. It also ensures that the contact area between the conductive post 131 at the insulating layer through hole 111 of the first insulating layer 110 and the conductive post 131 of the second insulating layer 112 is increased, further ensuring the preparation yield of the redistribution layer 1.

[0052] Furthermore, please refer to again Figure 10 The insulating layer through-hole 111 of the second insulating layer 112 includes a first through-hole sidewall 1110 and a second through-hole sidewall 1111. The angle formed between the first through-hole sidewall 1110 and the surface of the conductive post 131 at the insulating layer through-hole 111 of the first insulating layer 110 is a first angle α1, and the angle formed between the second through-hole sidewall 1111 and the surface of the conductive post 131 at the insulating layer through-hole 111 of the first insulating layer 110 is a second angle α2. The first angle α1 and the second angle α2 are the same. In this embodiment, the opening morphology of the insulating layer through-hole 111 is consistent on the flat wiring layer 13 of the first insulating layer 110.

[0053] Furthermore, the first angle α1 ranges from 90° to 115°. For example, the first angle α1 can be 90°, 95°, 100°, 105°, 110°, or 115°. Thus, in the fabrication of the redistribution layer 1 with the stacked via structure, this embodiment first fabricates a relatively thick conductive layer 12 on the first insulating layer 110 to at least fill the insulating via 111. Then, a partition etching process is used to thin and etch the conductive layer 12 to achieve a smooth surface. This ensures that the surfaces of the wiring layers 13 on the first insulating layer 110 are all smooth surfaces, which is beneficial to the opening morphology and process performance of the insulating via 111 in the second insulating layer 112, and ensures the fabrication yield of the redistribution layer 1.

[0054] It is worth noting that the size of the first angle α1 is not specifically limited here, and can be selected from the above range.

[0055] Furthermore, please refer to again Figure 10 The redistribution layer 1 also includes a seed layer 15, which is located between the insulating layer 11 and the trace layer 13. In this embodiment, part of the seed layer 15 is located between the inner wall of the insulating layer via 111 and the conductive post 131, and part of the seed layer 15 is located between adjacent insulating layers 11. The seed layer 15 is typically a composite layer of titanium and copper.

[0056] Based on the same inventive concept, this application also provides a chip packaging structure, which includes the redistribution layer 1 provided in the aforementioned embodiments of this application. In this embodiment, please refer to... Figure 11 , Figure 11 This is a schematic diagram of a chip packaging structure provided in this embodiment. The chip packaging structure also includes a substrate 18, a chip 19, and a molding compound 20. A redistribution layer 1 is disposed on one side of the substrate 18. The chip 19 is located on the side of the redistribution layer 1 away from the substrate 18 and is connected to the wiring layer 13 of the redistribution layer 1. The molding compound 20 is disposed around the chip 19. In this embodiment, the chip packaging structure can be fabricated by first fabricating the chip 19 on the substrate 18, and then fabricating the redistribution layer 1 on the side of the chip 19 away from the substrate.

[0057] In this embodiment, during the fabrication of the redistribution layer 1 with stacked vias, a thick conductive layer 12 is first fabricated on the first insulating layer 110 (i.e., the front insulating layer) to at least fill the insulating vias 111. Then, a partition etching process is used to thin and etch the conductive layer 12 to achieve a smooth surface of the conductive pillars 130 at the insulating vias 111 of the first insulating layer 110. This is beneficial to the opening morphology and process performance of the insulating vias 111 of the second insulating layer 112 (i.e., the back insulating layer), ensuring the fabrication yield of the redistribution layer 1, and thus ensuring the fabrication yield of the chip packaging structure.

[0058] In summary, this application provides a method for fabricating a redistribution layer, the redistribution layer itself, and a chip packaging structure. The method first fabricates a conductive layer on a first insulating layer. This conductive layer includes conductive traces that at least fill the vias in the insulating layer, with the thickness of the conductive traces at the vias being greater than the depth of the vias. Then, based on the thickness of the conductive layer at different locations on the first insulating layer, a spray matrix composed of multiple nozzles is used to etch the conductive layer in different areas, resulting in a redistribution layer formed by traces and conductive pillars. This approach, by first increasing the plating thickness of the conductive layer on the first insulating layer (i.e., the front insulating layer) at the overlapping vias, and then performing overall thinning and leveling, significantly improves the plating flatness of the conductive layer at the vias in the first insulating layer. This reduces the adverse effects on the via morphology of the second insulating layer (i.e., the rear insulating layer), thereby effectively ensuring the yield of the redistribution layer.

[0059] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a redistribution layer, characterized in that, The redistribution layer includes stacked insulating layers and routing layers located between adjacent insulating layers, wherein adjacent insulating layers include a first insulating layer and a second insulating layer located on the first insulating layer, and the insulating vias of the first insulating layer overlap with the insulating vias of the second insulating layer. The method includes: A conductive layer is formed on the first insulating layer, wherein the conductive layer includes conductive traces that fill at least the insulating layer vias of the first insulating layer, and the thickness of the conductive traces at the insulating layer vias is greater than the depth of the insulating layer vias in a direction perpendicular to the plane of the first insulating layer. Based on the thickness of the conductive layer at different locations on the first insulating layer, a spray matrix composed of multiple nozzles is used to etch the conductive layer at different locations in sections, resulting in a trace layer formed by traces and conductive pillars, wherein the side of the traces and conductive pillars away from the first insulating layer is a flat plane.

2. The method for fabricating a redistribution layer as described in claim 1, characterized in that, The step of fabricating a conductive layer on the first insulating layer includes: A seed layer is formed on one side of the first insulating layer; A conductive material layer is fabricated based on the seed layer; The conductive layer is obtained by patterning the conductive material layer.

3. The method for fabricating a redistribution layer as described in claim 1, characterized in that, The step of using a spray matrix composed of multiple nozzles to etch the conductive layer in different locations on the first insulating layer, based on the thickness of the conductive layer at different locations, to obtain a trace layer formed by traces and conductive pillars, includes: The thickness of the conductive layer at different locations on the first insulating layer is obtained; The etching solution spray intensity for different locations is determined based on the thickness of those locations. The nozzle performs etching on the corresponding location area based on the etching liquid spray intensity, to obtain a trace layer formed by the traces and conductive pillars.

4. A redistribution layer, characterized in that, The rewiring layer includes stacked insulating layers and wiring layers located between adjacent insulating layers; The insulating layer further includes insulating layer vias, and the wiring layer includes conductive pillars that fill at least the insulating layer vias and wiring distributed on one side of the insulating layer; The adjacent insulating layers include a first insulating layer and a second insulating layer located on the first insulating layer. The insulating through-holes of the first insulating layer overlap with the insulating through-holes of the second insulating layer. At the first insulating layer, the conductive post and the trace on the side away from the first insulating layer are a flat plane. In the direction perpendicular to the plane of the first insulating layer, the thickness of the conductive post at the insulating through-hole is greater than or equal to the depth of the insulating through-hole.

5. The redistribution layer as described in claim 4, characterized in that, At the first insulating layer, the side of the trace away from the first insulating layer is flush with the side of the conductive post away from the first insulating layer.

6. The redistribution layer as described in claim 5, characterized in that, At the first insulating layer, the conductive post includes a conductive post body filling the through hole of the insulating layer and a conductive post trace located on the side of the conductive post body away from the first insulating layer, and the orthographic projection of the conductive post trace on the first insulating layer covers the through hole of the insulating layer.

7. The redistribution layer as described in claim 6, characterized in that, The insulating layer through-hole of the second insulating layer includes a first through-hole sidewall and a second through-hole sidewall. The angle formed between the first through-hole sidewall and the conductive post surface at the insulating layer through-hole of the first insulating layer is a first angle, and the angle formed between the second through-hole sidewall and the conductive post surface at the insulating layer through-hole of the first insulating layer is a second angle. The first angle and the second angle are the same.

8. The redistribution layer as described in claim 7, characterized in that, The first angle ranges from 90° to 115°.

9. The redistribution layer as described in claim 4, characterized in that, The redistribution layer further includes a seed layer located between the insulating layer and the routing layer.

10. A chip packaging structure, characterized in that, The chip packaging structure includes the redistribution layer as described in any one of claims 4-9.

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