A method for manufacturing a ceramic substrate multilayer metal circuit and a ceramic substrate

Abstract

The application discloses a preparation method of a ceramic substrate multilayer metal circuit and a ceramic substrate, and aims to solve the problems of low yield, poor reliability and complicated process under a small aperture in the prior art. The preparation method comprises the following steps: firstly, forming a first metal circuit layer through electroplating; secondly, covering a PI insulating layer and opening a through window; thirdly, activating the bottom of the through window, and then growing a solid interconnection column for filling the through window from bottom to top through a chemical plating process, so that the problems of cavity in the hole and plating leakage can be solved; and finally, sputtering a second seed layer, and forming a second metal circuit layer through electroplating, so that reliable vertical interconnection is realized. The manufacturing method simplifies the process, the prepared ceramic substrate has a complete structure, high strength, good interlayer conduction insulation effect and strong metal structure push-pull force.

Description

Technical Field

[0001] This application belongs to the field of internal interconnection technology of electronic components, and specifically relates to a method for preparing multilayer metal circuits on a ceramic substrate. Background Technology

[0002] Ceramic substrates are widely used in power semiconductors, radio frequency devices, and high-density system-in-package (SiP) applications due to their excellent insulation, thermal conductivity, and thermal expansion coefficient that matches the chip. As electronic systems evolve towards miniaturization, higher frequencies, and higher power densities, the core requirements for vertical interconnects of multilayer metal circuits on ceramic substrates—namely, small apertures, high reliability, and low loss—have emerged.

[0003] Currently, the mainstream process solutions for achieving interlayer interconnection of multilayer metal circuits on ceramic substrates are mainly divided into two categories, but both have technical bottlenecks determined by the process mechanism.

[0004] The first type is a laser drilling combined with electroplating for filling. This method uses a laser to form through-holes on a ceramic substrate, followed by sputtering a seed layer and electroplating to fill the holes and form solid interconnect pillars. The core problem lies in the hard and brittle nature of ceramic materials, which makes laser drilling of extremely small holes extremely difficult. Microcracks easily form on the hole walls, resulting in low yields for small-diameter holes. Simultaneously, mass transfer of the electroplating solution within high aspect ratio through-holes is difficult, easily leading to void defects during the filling process, affecting the long-term reliability of the interconnects. Furthermore, this process involves multiple steps, including laser processing, vacuum coating, electroplating, and planarization, making it complex and costly to produce.

[0005] The second type is the photolithography-electroplating combined process. This method involves sputtering a seed layer across the entire surface, defining the circuit pattern using photoresist, and then thickening the layer with electroplating to form the circuitry and interconnecting vias. This method has the following inherent drawbacks: First, the inner walls of the vias rely on electroplating for coverage. Due to differences in wettability and uneven current density distribution within the vias, localized incomplete plating or plating voids can easily occur, leading to discontinuous interlayer conductivity and a risk of open circuits. Second, the entire conductive seed layer results in uneven current distribution between sparse and dense areas of the pattern during electroplating, making it difficult to control the plating thickness on the inner walls of the vias and resulting in poor plating uniformity. Third, a full-surface sputtering seed layer must be applied to the ceramic substrate before via electroplating, which is cumbersome and results in high material loss, hindering economic efficiency for mass production.

[0006] In summary, existing interlayer interconnection schemes for multilayer metal circuits on ceramic substrates present irreconcilable contradictions regarding the feasibility of fabricating small apertures, the integrity and electrical continuity of the interconnect structure, and the complexity and cost of the process. There is an urgent need for an interconnect structure and fabrication method that can balance small size, high reliability, and process economy. Summary of the Invention

[0007] The purpose of this application is to overcome the shortcomings of the prior art and provide a method for preparing multilayer metal circuits on a ceramic substrate and a ceramic substrate.

[0008] Firstly, to achieve the above objectives, the technical solution adopted in this application is: a method for preparing multilayer metal circuits on a ceramic substrate, comprising the following steps:

[0009] S1) A ceramic substrate is provided, and a first seed layer is formed on the surface of the ceramic substrate;

[0010] S2) Coating photoresist on the first seed layer and performing photolithography and development on the photoresist to form a first opening that exposes a predetermined line area, and forming a first metal line layer in the first opening by electroplating.

[0011] S3) Remove the photoresist and the first seed layer located thereunder;

[0012] S4) An insulating layer is formed on the first metal circuit layer, and a conductive window is formed in the insulating layer to expose part of the upper surface of the first metal circuit layer;

[0013] S5) Activate the exposed metal surface at the bottom of the conductive window, and form interconnect pillars that grow upward from the exposed metal surface and fill the conductive window through a chemical plating process.

[0014] S6) A second seed layer is formed on the insulating layer, the second seed layer covering the upper surface of the interconnect post;

[0015] S7) Photoresist is coated on the second seed layer, and the photoresist is photolithographically etched and developed to form a second opening that exposes a predetermined circuit area. A second metal circuit layer is formed in the second opening by electroplating. The second metal circuit layer is vertically interconnected with the first metal circuit layer through the interconnect pillars.

[0016] In a feasible embodiment, in step S5), the interconnect pillar formed by the chemical plating process is a multi-layer metal structure, which includes a barrier layer, an anti-oxidation layer and a protective layer from bottom to top.

[0017] In one feasible embodiment, the barrier layer is a Ni layer; the anti-oxidation layer is a Pd layer; and the protective layer is an Au layer.

[0018] In one feasible embodiment, the Ni layer has a thickness of 6-8 μm, the Pd layer has a thickness of 0.08-0.12 μm, and the Au layer has a thickness of 0.04-0.06 μm.

[0019] In one feasible embodiment, the diameter of the conductive window is 30-50 μm, the thickness of the insulating layer is 14-16 μm, and the thickness of the first metal circuit layer is 14-16 μm.

[0020] In one feasible embodiment, the insulating layer is a polyimide film, and the step of forming a conductive window in the insulating layer includes:

[0021] A polyimide film is laminated onto the first metal circuit layer;

[0022] The polyimide film is subjected to photolithography, development, and etching to form the conductive window;

[0023] In one feasible embodiment, the ceramic substrate with the conductive window is subjected to high-temperature curing treatment.

[0024] In one feasible embodiment, the high-temperature curing treatment is performed at a temperature of 180-220°C for 10-12 hours.

[0025] In one feasible embodiment, the materials of the first seed layer and the second seed layer are Ti-Cu composite layers.

[0026] In one feasible embodiment, prior to step 1), the ceramic substrate is further subjected to CMP polishing to achieve a surface roughness of 100-200 nm and a total thickness deviation of 1-3 μm.

[0027] Secondly, the purpose of this application is to provide a ceramic substrate prepared by the aforementioned method for preparing multilayer metal circuits.

[0028] Thirdly, the purpose of this application is also to provide a multilayer metal circuit structure for a ceramic substrate, comprising:

[0029] Ceramic substrate;

[0030] A first metal circuit layer is formed above the ceramic substrate;

[0031] An insulating layer covers the first metal circuit layer, and the insulating layer has a conductive window;

[0032] Interconnect pillars are filled within the conductive window, and the interconnect pillars are metal pillars formed by chemical plating growing upward from the upper surface of the first metal circuit layer.

[0033] The second seed layer covers the upper surface of the insulating layer and the upper surface of the interconnect pillars;

[0034] A second metal circuit layer is formed on the second seed layer and is vertically interconnected with the first metal circuit layer through the interconnect pillars.

[0035] Compared with the prior art, this application has the following advantages: This invention provides a method for preparing multilayer metal interconnects on a ceramic substrate by combining chemical plating and electroplating, which can solve the problems of uneven plating, poor bonding force, and complex process in traditional electroplating interlayer connections. The ceramic substrate of the final product has the advantages of complete structure, high strength, good interlayer conductivity and insulation effect, and strong push-pull force of metal structure, which can improve the conductivity stability, bonding force and long-term reliability of multilayer metal circuits on ceramic substrates. Attached Figure Description

[0036] Figure 1 A schematic diagram of the internal structure of one embodiment of this application is provided. Specific Implementation

[0037] To illustrate the technical content, structural features, achieved objectives, and effects of the invention in detail, the technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. In the following description, for illustrative purposes, numerous specific details are set forth to provide a detailed description of various exemplary embodiments or implementations of the invention. However, various exemplary embodiments may also be implemented independently without these specific details or in one or more equivalent arrangements. Furthermore, the various exemplary embodiments may differ, but are not necessarily exclusive. For example, the specific shape, construction, and characteristics of the exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0038] See Figure 1 As shown, this application discloses a method for fabricating multilayer metal circuits on a ceramic substrate, comprising the following steps:

[0039] S1) A ceramic substrate 1 is provided, which can be made of materials such as alumina, silicon nitride, or aluminum nitride. The ceramic substrate 1 is subjected to chemical mechanical polishing (CMP) to achieve a surface roughness Ra of 100-200 nm and a total thickness deviation (TTV) controlled within 2 μm. After cleaning and drying, titanium and copper are sequentially deposited on the surface of the ceramic substrate using magnetron sputtering to form a first seed layer on the surface of the ceramic substrate 1, such as a Ti-Cu coating (not shown in the figure).

[0040] The purpose of CMP (Ceramic Metallurgical Processing) is to reduce the surface roughness and total thickness deviation of the ceramic substrate, providing a flat working plane for subsequent photolithography processes. When photoresist is spin-coated on a rough surface, thickness uniformity deteriorates significantly, affecting linewidth accuracy. Excessive total thickness deviation (TTV) can lead to inconsistent depth of focus during exposure, resulting in localized defocusing. Thorough cleaning after CMP treatment removes residual abrasive particles and metal ions from the surface, preventing contamination from spreading.

[0041] Ceramic itself is an insulator and cannot be directly electroplated. Sputtering a Ti-Cu composite seed layer serves two purposes: firstly, the Ti layer acts as an adhesion layer, forming good bonds with both the ceramic substrate and the Cu layer, preventing subsequent film detachment; secondly, the Cu layer acts as a conductive layer, providing a low-resistivity conductive path for the next electroplating process, ensuring uniform distribution of the electroplating current.

[0042] S2) Photoresist is coated on the first seed layer, and the photoresist is photolithographically etched and developed to form a first opening that exposes a predetermined circuit area. A first metal circuit layer 2 is then formed in the first opening by electroplating. Common materials for the first metal circuit layer 2 include copper, copper alloys, gold, silver, and nickel.

[0043] Furthermore, a layer of photoresist is spin-coated onto the seed layer, and after soft baking, it is exposed using a photomask with the first layer of metal circuit pattern. After development, a first opening is formed in the photoresist, exposing the underlying Ti-Cu seed layer. Then, the substrate is immersed in an electroplating solution such as copper sulfate, and DC electroplating is performed using the first seed layer as the cathode. During electroplating, the metal material fills the first opening and thickens. By controlling parameters such as electroplating time and current, the thickness of the plating layer can be adjusted to form the first metal circuit layer 2. Electroplating is used in this step instead of sputtering because electroplating can efficiently deposit thick metal materials, especially copper, which can provide low resistance current carrying capacity, while sputtering deposition of thick films is inefficient and stress-prone.

[0044] S3) After electroplating, the photoresist is dissolved and removed using an organic resist remover. Resin removal must be thorough to avoid organic residues affecting the adhesion of subsequent insulating layers. Then, using the first metal circuit layer 2 itself as a mask, a wet etching process is employed to sequentially etch away the exposed copper seed layer and titanium seed layer.

[0045] S4) An insulating layer 3 is formed on the first metal circuit layer 2, and a conductive window is formed in the insulating layer 3 to expose part of the upper surface of the first metal circuit layer 2.

[0046] In some embodiments, a photosensitive polyimide film (PI) can be used as the insulating film. It is uniformly pressed onto the first metal circuit layer using a vacuum laminator. During the lamination process, air bubbles in the circuit gaps are thoroughly removed to prevent voids from forming and affecting reliability. The insulating layer 3 serves as the interlayer dielectric between the upper and lower metal circuit layers, providing electrical isolation and physical support. Polyimide materials possess excellent thermal stability and a low dielectric constant, making them particularly suitable for high-frequency applications.

[0047] Then, the substrate is exposed using a photomask with a conductive window pattern, followed by development, precisely forming conductive windows of predetermined size on the PI insulating layer 3, exposing the clean upper surface of the first metal circuit layer 2. Finally, the ceramic substrate 1 is placed in an oven for high-temperature curing. High-temperature curing must be carried out in an oxygen-free atmosphere to prevent oxidation of the exposed first metal surface at high temperatures, which would lead to failure of subsequent chemical plating or poor adhesion.

[0048] In some embodiments, the diameter of the conductive window is 30-50 μm, the thickness of the insulating layer is 14-16 μm, and the thickness of the first metal circuit layer is 14-16 μm.

[0049] S5) The exposed metal surface at the bottom of the conductive window is activated by chemical plating to form interconnect pillars that grow upward from the exposed metal surface and fill the conductive window.

[0050] The activation process involves immersing the ceramic substrate in an ion-activating solution, causing a catalytically active substance to deposit on the exposed surface at the bottom of the conductive window through a displacement reaction. After cleaning, the ceramic substrate is immersed in a chemical plating solution to grow interconnect pillars 4 that are connected to the first metal circuit layer.

[0051] The purpose of chemical plating is to form vertical interconnections between layers. Compared with electroplating for filling holes, chemical plating does not rely on an electric field, has excellent plating uniformity, and can form dense, void-free solid pillars within small windows. Therefore, it can solve the problems of incomplete plating and uneven plating thickness in electroplating solutions.

[0052] S6) A second seed layer is formed on the insulating layer 3, so that the second seed layer covers the upper surface of the interconnect post 4.

[0053] The second seed layer can be deposited by magnetron sputtering on the insulating layer, the sidewall of the conductive window, and the upper surface of the interconnect pillar. The second seed layer can be a Ti-Cu composite seed layer.

[0054] S7) Photoresist is coated on the second seed layer, and the photoresist is photolithographically etched and developed to form a second opening that exposes a predetermined line area. A second metal line layer 5 is formed in the second opening by electroplating. The second metal line layer 5 is vertically interconnected with the first metal line layer 2 through the interconnect pillar 4.

[0055] Specifically, the same process as in step S2 can be used to spin-coat photoresist onto the second seed layer, followed by photolithography and development to form a second opening, exposing the area where the second layer of wiring needs to be formed. The design of the second opening must ensure complete coverage of the interconnect pillars 4. Electroplating is then performed to form a second metal wiring layer 5 that meets the required thickness. Finally, the process of step S3 is repeated to remove the photoresist and etch away the underlying seed layer.

[0056] In some feasible embodiments, the interconnect pillars formed by the chemical plating process in step S5) have a multilayer metal structure, wherein the interconnect pillars, from bottom to top, include a barrier layer, an anti-oxidation layer, and a protective layer. For example, the barrier layer can be a Ni layer; the anti-oxidation layer can be a Pd layer; and the protective layer can be an Au layer, wherein the thickness of the Ni layer is 6-8 μm, the thickness of the Pd layer is 0.08-0.12 μm, and the thickness of the Au layer is 0.04-0.06 μm. The functions of the multilayer metal structure are as follows: the Ni layer serves as both the host and the barrier layer, preventing the first metal from diffusing into the protective layer; the Pd layer serves as the anti-oxidation layer, densely covering the Ni layer to prevent its oxidation from affecting welding or connection performance; and the Au layer serves as the protective layer, preventing the Pd layer from being contaminated during storage and providing excellent surface contact performance.

[0057] A ceramic substrate prepared by the above method has the following properties: Figure 1 The multilayer metal circuit structure shown includes:

[0058] Ceramic substrate 1;

[0059] A first metal circuit layer 2 is formed above the ceramic substrate 1;

[0060] An insulating layer 3 covers the first metal circuit layer 2, and the insulating layer 3 is provided with multiple conductive windows;

[0061] At least one interconnect post 4 is filled in the conductive window, and the interconnect post 4 is a metal post formed by chemical plating growing upward from the upper surface of the first metal circuit layer 2.

[0062] The second seed layer covers the upper surface of the insulating layer 3 and the upper surface of the interconnecting post 4;

[0063] The second metal circuit layer 5 is formed on the second seed layer and is vertically interconnected with the first metal circuit layer 2 through the interconnect post 4.

[0064] The interconnecting pillar 4 comprises a multilayer material, such as a Ni-Pd-Au composite material.

[0065] The second seed layer 4 is made of Ti-Cu material, and the first metal circuit layer 2 and the second metal circuit layer 5 are made of Cu material.

[0066] To more clearly illustrate the method for fabricating multilayer metal circuits on ceramic substrates provided in this application, specific embodiments are described below.

[0067] Example 1

[0068] S1) Select a ceramic substrate and perform CMP polishing on it to control the surface roughness to be 100-200nm and the TTV to be about 2μm.

[0069] S2) The first seed layer Ti-Cu is prepared on the ceramic surface by sputtering deposition.

[0070] S3) A layer of photoresist is spin-coated onto the surface of the ceramic substrate. After photolithography and development, the first layer of metal circuit pattern, i.e., the first opening, is formed.

[0071] S4) Electroplating the first layer of metal Cu, with a thickness controlled at around 15μm, to form the first metal circuit layer.

[0072] S5) Resin Removal Etching: Clean the excess photoresist from the surface of the ceramic substrate and etch the first seed layer cleanly.

[0073] S6) Press-film photolithography: a layer of polyimide (PI) film is pressed onto the first metal circuit layer, and then photolithography and development are performed to etch out a circular conductive window with a diameter of 40μm, uniformly exposing the copper surface below the conductive window. The total thickness of the PI insulating layer is 15μm.

[0074] S7) Place the ceramic substrate in an oven for high-temperature curing at 180°C for 12 hours.

[0075] S8) Activate the area of ​​the conductive window, immerse the activated ceramic substrate in a chemical plating solution, and perform chemical plating of Ni-Pd-Au interconnect pillars. Ni is a barrier layer to prevent Cu diffusion; the Pd layer is to prevent Ni oxidation, but if it is too thin, pinholes will appear; the Au layer is a protective layer. The Ni layer is 6μm, the Pd layer is 0.1μm, and the Au layer is 0.05μm.

[0076] S9) A second seed layer Ti-Cu is sputtered onto the surface of the polyimide insulating layer, then photolithography and development are performed to form a second opening. A second metal layer is then electroplated, and then the resist is removed and etched to form a second metal circuit layer, enabling it to be tightly connected to the interconnect pillars.

[0077] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope. The scope of protection of the present invention is defined by the appended claims, specification, and their equivalents.

Claims

1. A method for fabricating multilayer metal circuits on a ceramic substrate, characterized in that, Includes the following steps: S1) A ceramic substrate is provided, and a first seed layer is formed on the surface of the ceramic substrate; S2) Coating photoresist on the first seed layer and performing photolithography and development on the photoresist to form a first opening that exposes a predetermined line area, and forming a first metal line layer in the first opening by electroplating. S3) Remove the photoresist and the first seed layer located thereunder; S4) An insulating layer is formed on the first metal circuit layer, and a conductive window is formed in the insulating layer to expose part of the upper surface of the first metal circuit layer; S5) Activate the exposed metal surface at the bottom of the conductive window, and form interconnect pillars that grow upward from the exposed metal surface and fill the conductive window through a chemical plating process. S6) A second seed layer is formed on the insulating layer, the second seed layer covering the upper surface of the interconnect post; S7) Photoresist is coated on the second seed layer, and the photoresist is photolithographically etched and developed to form a second opening that exposes a predetermined circuit area. A second metal circuit layer is formed in the second opening by electroplating. The second metal circuit layer is vertically interconnected with the first metal circuit layer through the interconnect pillars.

2. The preparation method according to claim 1, characterized in that: In step S5), the interconnect pillars formed by the chemical plating process are multi-layer metal structures, which include a barrier layer, an anti-oxidation layer and a protective layer from bottom to top.

3. The preparation method according to claim 2, characterized in that: The barrier layer is a Ni layer; the anti-oxidation layer is a Pd layer; and the protective layer is an Au layer.

4. The preparation method according to claim 3, characterized in that: The thickness of the Ni layer is 6-8 μm, the thickness of the Pd layer is 0.08-0.12 μm, and the thickness of the Au layer is 0.04-0.06 μm. According to the preparation method of claim 1, the diameter of the conductive window is 30-50 μm, the thickness of the insulating layer is 14-16 μm, and the thickness of the first metal circuit layer is 14-16 μm.

5. The preparation method according to claim 1, characterized in that: The insulating layer is a polyimide film, and the step of forming a conductive window in the insulating layer includes: A polyimide film is laminated onto the first metal circuit layer; The polyimide film is subjected to photolithography, development, and etching to form the conductive window; The ceramic substrate with conductive windows is subjected to high-temperature curing treatment.

6. The preparation method according to claim 6, characterized in that: The high-temperature curing treatment is performed at a temperature of 180-220℃ for 10-12 hours.

7. The preparation method according to claim 1, characterized in that: The first seed layer and the second seed layer are made of Ti-Cu composite layer.

8. The preparation method according to claim 1, characterized in that: Before step 1), the ceramic substrate is also subjected to CMP polishing to make its surface roughness Ra 100-200nm and total thickness deviation 1-3μm.

9. A ceramic substrate, characterized in that, It is prepared by the method according to any one of claims 1 to 9.

10. A multilayer metal circuit structure on a ceramic substrate, characterized in that, include: Ceramic substrate; A first metal circuit layer is formed above the ceramic substrate; An insulating layer covers the first metal circuit layer, and the insulating layer has a conductive window; Interconnect pillars are filled within the conductive window, and the interconnect pillars are metal pillars formed by chemical plating growing upward from the upper surface of the first metal circuit layer. The second seed layer covers the upper surface of the insulating layer and the upper surface of the interconnect pillars; A second metal circuit layer is formed on the second seed layer and is vertically interconnected with the first metal circuit layer through the interconnect pillars.

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