A method for wafer-level co-planar fabrication of a silicon core embedded through a glass matrix

Abstract

The embodiment of the application relates to a kind of silicon core particle through embedded glass matrix plate-level coplanar preparation method, comprising: forming the core particle embedding window along the thickness direction of glass matrix on the panel type glass matrix with oppositely arranged first surface and second surface;Provide preform silicon core particle, preform silicon core particle includes silicon body and the plurality of copper column arranged at the first surface of silicon body;The second surface of glass matrix is fixed to temporary carrier plate, and preform silicon core particle is embedded in core particle embedding window, the first surface of silicon body is between the first surface and the second surface of glass matrix, the end of each copper column protrudes from the first surface of glass matrix, and the assembly gap is formed between the circumferential side of preform silicon core particle and the inner wall of core particle embedding window;Insulating filling material is filled in assembly gap and solidified;From the first surface side of glass matrix, copper column and solidified insulating filling material are flattened.

Description

Technical Field

[0001] This application relates to the field of advanced semiconductor packaging technology, and in particular to a method for preparing a plate-level coplanar substrate with silicon core particles embedded in a glass substrate. Background Technology

[0002] With the development of heterogeneous chip integration and high-density packaging technologies, glass substrates, due to their excellent insulation properties, low dielectric loss, good dimensional stability, and suitability for large-size processing, are increasingly being used in interposers and multi-chip packaging structures. In the related fabrication process, a through-hole embedding window can be formed on the glass substrate along its thickness direction. Silicon chips pre-formed with functional circuits, through-silicon vias (TSVs), or interconnect structures are then embedded into this window, allowing the silicon chips and the glass substrate to jointly form the supporting structure for subsequent redistribution, bump fabrication, and chip bonding.

[0003] After silicon chips are embedded in a glass substrate, their two sides need to be coplanar with the corresponding surfaces of the glass substrate to meet wiring and bonding requirements. However, due to factors such as glass substrate thickness deviation, silicon chip thickness deviation, chip embedding height, and curing shrinkage of the filler material, the surface of the silicon chip can easily protrude or sink relative to the glass substrate surface. If the height difference is directly eliminated by grinding the silicon body, the grinding pressure, grinding fluid, and local over-grinding may damage the functional circuits, through-silicon vias, capacitor structures, or surface wiring inside the silicon chip. If effective leveling is not performed, the height difference between the silicon chip and the glass substrate will affect the continuous formation of subsequent redistribution layers and cause inconsistent microbump heights or insufficient chip bonding contact.

[0004] Therefore, the relevant technologies have at least the following technical problems: how to make the two sides of the pre-made silicon core form a stable coplanar relationship with the corresponding surfaces of the glass substrate after embedding the pre-made silicon core through the glass substrate, without directly grinding and damaging the silicon body and its functional structure, so as to provide a flat process base surface for subsequent wiring and chip bonding. Summary of the Invention

[0005] One objective of this application is to provide a method for preparing a plate-level coplanar structure of silicon core particles embedded in a glass substrate, which at least addresses the aforementioned problems.

[0006] To achieve the above objectives, some embodiments of this application provide a method for fabricating a plate-level coplanar structure of a silicon core embedded in a glass substrate, comprising:

[0007] A core-embedded window is formed on a glass substrate having a first surface and a second surface arranged opposite to each other, extending through the thickness direction of the panel-type glass substrate;

[0008] A pre-fabricated silicon core is provided, the pre-fabricated silicon core comprising a silicon body and a plurality of copper pillars disposed on a first surface of the silicon body;

[0009] The second surface of the glass substrate is attached and fixed to a temporary carrier plate, and the pre-made silicon core is embedded in the core embedding window, such that the side surface of the pre-made silicon core away from the copper pillar is coplanar with the second surface of the glass substrate. The first surface of the silicon body is located between the first surface and the second surface of the glass substrate. The ends of each copper pillar away from the silicon body protrude from the first surface of the glass substrate, and an assembly gap is formed between the periphery of the pre-made silicon core and the inner wall of the core embedding window.

[0010] Fill the assembly gap with insulating filler material and allow the insulating filler material to cure;

[0011] The copper pillars and the cured insulating filler material are leveled from the first surface side of the glass substrate, removing the portions of each copper pillar that protrude from the first surface of the glass substrate and the portions of the cured insulating filler material that are higher than the first surface of the glass substrate, so that the leveled end faces of each copper pillar and the leveled surface of the insulating filler material are coplanar with the first surface of the glass substrate.

[0012] Optionally, there are multiple core embedding windows arranged in an array on the glass substrate, and there are multiple pre-made silicon cores. Each pre-made silicon core is embedded in a corresponding core embedding window, and the insulating filling material is filled, cured, and leveled using the temporary carrier plate as a support reference.

[0013] Optionally, the chip embedding window is a rectangular window, and the minimum opening size of the chip embedding window in the length direction and the width direction is larger than the outer dimensions of the pre-made silicon chip in the corresponding directions, and the size difference is 5-10μm;

[0014] The core-embedded window is micro-conical, and the size of one end of the core-embedded window located on the second surface of the glass substrate is larger than the size of one end located on the first surface of the glass substrate, and the size difference between the two ends of the core-embedded window in the corresponding direction is less than or equal to 2 μm.

[0015] Optionally, the assembly gap is an annular gap provided around the periphery of the pre-fabricated silicon core.

[0016] The insulating filler material is an epoxy material modified with nano-silica and boron nitride composite filler. The median particle size D50 of the composite filler is less than or equal to 0.2 μm. The thermal expansion coefficient of the insulating filler material is 6-10 ppm / ℃, the elastic modulus is 2-4 GPa, and the curing shrinkage rate is less than or equal to 0.2%.

[0017] Optionally, the leveling treatment is a flexible chemical mechanical polishing treatment, and the polishing pressure of the flexible chemical mechanical polishing treatment is 0.2 MPa;

[0018] After the leveling process is completed, the leveled end face of each copper pillar, the leveled surface of the insulating filler material, and the first surface of the glass substrate together form a level plane. The global coplanarity of the level plane is less than or equal to 0.5 μm, and the coplanarity of the area used for chip bonding in the level plane is less than or equal to 0.3 μm.

[0019] Optionally, during the formation of the core embedding window, a plurality of glass through holes extending along the thickness direction of the glass substrate are also formed on the glass substrate. The core embedding window and the glass through holes are formed simultaneously by a combination of laser-induced modification and partitioned wet etching.

[0020] Optionally, before embedding the pre-fabricated silicon die into the die embedding window, the method further includes:

[0021] A patterned photoresist layer is formed on the glass substrate, such that the patterned photoresist layer covers the chip mounting window and the inner wall of the chip mounting window, and exposes the glass via.

[0022] A composite seed layer comprising a titanium layer and a copper layer is deposited on the glass substrate, and copper is filled into the glass vias by electroplating.

[0023] Remove the patterned photoresist layer covering the chip mounting window and the metal layer attached to the surface of the patterned photoresist layer, so that the glass via filled with copper forms a vertical conductive path, and keep the inner wall of the chip mounting window insulated.

[0024] Optionally, the plurality of said prefabricated silicon chips include at least one active silicon-based power chip and at least one passive silicon-based decoupling chip;

[0025] The active silicon-based power chip integrates a voltage regulator unit and a first silicon via array that penetrates the silicon body of the active silicon-based power chip. The first silicon via array is electrically connected to wiring structures disposed on both sides of the silicon body of the active silicon-based power chip.

[0026] The passive silicon-based decoupling core integrates a deep trench capacitor array and / or a metal-insulator-metal capacitor array, as well as a second silicon via array penetrating the silicon body of the passive silicon-based decoupling core. The second silicon via array is electrically connected to a capacitor bus wiring located on the side of the passive silicon-based decoupling core where the copper pillar is located. The surface of the passive silicon-based decoupling core facing away from the copper pillar is an insulating passivated surface without a metal pattern.

[0027] Optionally, after the leveling process is completed, a first redistribution layer electrically connected to each of the copper pillars is formed on the first surface of the glass substrate, and microbumps are formed on the pads of the first redistribution layer.

[0028] The first wiring layer includes a high-speed signal wiring area, an active chip power wiring area, a ground shield wiring area, and a passive chip capacitor bus wiring area. The copper layer thickness of the high-speed signal wiring area is 2μm, the copper layer thickness of the active chip power wiring area and the ground shield wiring area is 2.5μm, and the copper layer thickness of the passive chip capacitor bus wiring area is 1.0μm.

[0029] Optionally, the method for fabricating coplanar silicon core particles embedded in a glass substrate at the plate level further includes:

[0030] At least one upper-layer functional bare core is bonded to the first rewiring layer via the microbumps;

[0031] Fill the interconnection gap between the upper functional bare core and the glass substrate with underfill material, and allow the underfill material to cure.

[0032] The upper functional bare core, the microbumps, and the first redistribution layer are coated with epoxy molding compound, and the cured epoxy molding compound is leveled so that the surface of the upper functional bare core that is away from the glass substrate is exposed.

[0033] Optionally, after the epoxy molding compound is leveled, the glass substrate is separated from the temporary carrier plate, and the side with the upper functional bare core particle and the epoxy molding compound is attached to the second temporary carrier plate, so that the second surface of the glass substrate is exposed.

[0034] A second redistribution layer is formed on the second surface of the glass substrate, and flip-chip bumps for connection with the packaging substrate are formed on the pads of the second redistribution layer.

[0035] Compared with related technologies, the solution provided in this application involves forming a through-hole core embedding window on a glass substrate and attaching and fixing the second surface of the glass substrate to a temporary carrier plate. This allows the surface of the pre-fabricated silicon core away from the copper pillar to abut against the temporary carrier plate along with the second surface of the glass substrate, thus establishing a coplanar reference for that side using the temporary carrier plate. Simultaneously, by positioning the first surface of the silicon body between the first and second surfaces of the glass substrate and making the copper pillar located on the first surface of the silicon body protrude beyond it, the height allowance to be removed later is concentrated on the copper pillar. Therefore, while achieving a coplanar relationship on one side of the pre-fabricated silicon core, the silicon body and its internal functional structures remain below the first surface of the glass substrate, avoiding the silicon body being directly ground.

[0036] After the pre-fabricated silicon die is embedded, an assembly gap is formed between its periphery and the inner wall of the die embedding window. An insulating filler material is then filled and cured within this gap, enabling circumferential positioning and fixation of the pre-fabricated silicon die. This prevents lateral displacement during subsequent leveling and creates a continuous electrically insulating interface between the silicon die and the glass substrate. Subsequently, the portions of each copper pillar protruding from the first surface of the glass substrate, as well as the portions of the insulating filler material protruding above the first surface, are removed from the first surface side of the glass substrate. This ensures that the leveled end faces of the copper pillars and the leveled surfaces of the insulating filler material are coplanar with the first surface of the glass substrate. This fabrication method utilizes a temporary carrier and copper pillars for coplanar positioning on the second surface side and leveling compensation on the first surface side, respectively. It achieves coplanar fit between the pre-fabricated silicon die and both sides of the glass substrate without directly grinding the silicon body and its internal circuitry, vias, or capacitor structures. This provides a flat process surface for the continuous formation of redistribution layers across the glass substrate, insulating filler material, and copper pillars, as well as for subsequent microbump fabrication and chip bonding. Attached Figure Description

[0037] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0038] Figure 1 This is a schematic diagram of the structure of the glass substrate after forming the core embedding window and glass through-hole according to an embodiment of the present disclosure;

[0039] Figure 2 This is a schematic diagram of the structure after a patterned photoresist layer is formed on a glass substrate, as provided in an embodiment of this disclosure;

[0040] Figure 3 This is a schematic diagram of the structure after metallization of the glass through-hole provided in an embodiment of this disclosure;

[0041] Figure 4 This is a schematic diagram of the structure after removing the patterned photoresist layer and keeping the chip mounting window insulated, provided in an embodiment of this disclosure;

[0042] Figure 5 This is a schematic diagram of the structure after pre-fabricated silicon chips are embedded in the chip embedding window, provided in an embodiment of this disclosure;

[0043] Figure 6 This is a schematic diagram of the structure provided in this embodiment where the copper pillar protrudes from the first surface of the glass substrate after the pre-fabricated silicon core is embedded;

[0044] Figure 7This is a schematic diagram of the structure after leveling the copper pillar and insulating filler material according to an embodiment of the present disclosure;

[0045] Figure 8 This is a schematic diagram of the structure after a first redistribution layer is formed on the first surface of a glass substrate, provided in an embodiment of this disclosure;

[0046] Figure 9 This is a schematic diagram of the structure after forming microbumps on the first wiring layer according to an embodiment of the present disclosure;

[0047] Figure 10 This is a schematic diagram of the structure after bonding the upper functional bare core to the first redistribution layer according to an embodiment of this disclosure;

[0048] Figure 11 This is a schematic diagram of the structure provided in this embodiment of the invention after filling the bottom with adhesive and covering the upper functional bare core particle with epoxy molding compound;

[0049] Figure 12 This is a schematic diagram of the structure provided in this embodiment, showing the side with the upper functional bare core particle attached to the second temporary carrier plate;

[0050] Figure 13 This is a schematic diagram of the structure after forming a second redistribution layer and flip-chip bumps on the second surface of a glass substrate, as provided in an embodiment of this disclosure;

[0051] Figure 14 This is a schematic diagram of the packaging structure after the second surface process is completed, provided in an embodiment of this disclosure;

[0052] Figure 15 This is a schematic diagram of the planar layout of a single intermediary layer unit provided in an embodiment of this disclosure;

[0053] Figure 16 This is a schematic diagram of the structure of multiple intermediary layer units arranged in an array on a panel-type glass substrate according to an embodiment of this disclosure;

[0054] Figure 17 This is a schematic flowchart of a plate-level coplanar fabrication method for silicon core particles embedded in a glass substrate, as provided in an embodiment of this disclosure.

[0055] Figure label:

[0056] 1: Glass substrate; 103: Chip embedding window; 104: Glass via; 202: Copper pillar; 204: Active silicon-based power chip; 205: Passive silicon-based decoupling chip; 3: Temporary carrier; 6: Patterned photoresist layer; 7: Composite seed layer; 8: First redistribution layer; 9: Microbump; 10: Upper functional bare chip; 11: Interconnect gap; 12: Underfill; 14: Second temporary carrier; 15: Second redistribution layer; 16: Flip-chip bump. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0059] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0060] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0061] Unless otherwise stated, the term "multiple" means two or more.

[0062] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0063] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0064] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0065] Combination Figures 1 to 17 As shown in the embodiments of this disclosure, a board-level coplanar fabrication method for silicon core particles embedded in a glass substrate is provided. The glass substrate 1 has a first surface and a second surface disposed opposite to each other. The prefabricated silicon core particle includes a silicon body and a plurality of copper pillars 202 disposed on the first surface of the silicon body. For ease of description, the side of the glass substrate 1 subsequently used to form the first redistribution layer 8 and microbumps 9 is referred to as the first surface, and the side of the glass substrate 1 subsequently used to form the second redistribution layer 15 and flip-chip bumps 16 is referred to as the second surface. The side of the prefabricated silicon core particle with copper pillars 202 corresponds to the first surface of the glass substrate 1, and the side of the prefabricated silicon core particle opposite to the copper pillars 202 corresponds to the second surface of the glass substrate 1.

[0066] In some embodiments, the glass substrate 1 is made of alkali-free aluminosilicate glass, and the thickness of the glass substrate 1 can be 50-300 μm. The glass substrate 1 can be a rectangular glass panel with dimensions of 310 mm × 310 mm, 515 mm × 510 mm, 600 mm × 600 mm, or 620 mm × 620 mm. Other panel specifications can also be used depending on the size and layout of the intermediate layer units to be prepared.

[0067] Before forming the core embedding window 103, the glass substrate 1 can be sequentially cleaned with organic solvents, cleaned with deionized water, purified by plasma, and stress-annealed to remove organic contaminants and particulate impurities from the surface of the glass substrate 1 and release residual stress inside the glass substrate 1. The overall warpage of the pretreated glass substrate 1 can be controlled within 5 μm, and the total thickness deviation can be controlled within 1 μm. By establishing a relatively stable panel flatness foundation before opening and embedding, the degree to which the subsequent array opening position, core embedding height, and photolithographic focal plane change with the panel position can be reduced.

[0068] A core-particle embedding window 103 is formed on the glass substrate 1, extending through the thickness direction of the glass substrate 1. The core-particle embedding window 103 is used to accommodate the pre-fabricated silicon core, so that the pre-fabricated silicon core is not simply attached to the surface of the glass substrate 1, but embedded inside the glass substrate 1 along the thickness direction of the glass substrate 1. The through-hole embedding can shorten the distance between the two sides of the pre-fabricated silicon core and the two sides of the interconnection structure of the glass substrate 1, and provide a spatial basis for the formation of coplanar structures on both sides of the pre-fabricated silicon core.

[0069] In some embodiments, the die-mounting window 103 is a rectangular window, the shape of which is adapted to the planar shape of the pre-fabricated silicon die. The minimum opening size of the die-mounting window 103 in both the length and width directions is larger than the outer dimensions of the pre-fabricated silicon die in the corresponding directions, with a size difference of 5-10 μm. This size difference can be a bilateral size difference between the window size and the overall size of the die; for example, the length of the die-mounting window 103 is 8 μm larger than the length of the pre-fabricated silicon die, and the width of the die-mounting window 103 is 8 μm larger than the width of the pre-fabricated silicon die. Therefore, the pre-fabricated silicon die can enter the die-mounting window 103 without forming an excessively large lateral movement space within the window.

[0070] The core-embedding window 103 can be micro-conical, with one end on the second surface of the glass substrate 1 having a larger dimension than the end on the first surface of the glass substrate 1. The dimensional difference between the two ends of the core-embedding window 103 in the corresponding direction is less than or equal to 2 μm. The micro-conical inner wall can gradually guide and limit the core during the core embedding process, reducing the possibility of rigid interference between the corners of the rectangular silicon core and the edge of the glass window. At the same time, the small taper difference will not cause significant differences in the assembly gap at both ends of the window, which is beneficial for the uniform distribution of the subsequent insulating filler material along the periphery of the core.

[0071] In some embodiments, the sidewall perpendicularity of the core embedding window 103 is not less than 85°, the sidewall surface roughness Ra is not greater than 0.5 μm, and the opening position accuracy is controlled within ±2 to ±3 μm. Controlling the sidewall perpendicularity and roughness can reduce the obstruction of the insulating filler material flow by local sharp corners and pits, and reduce the possibility of forming local stress concentration points at the interface after curing. Controlling the opening position accuracy helps maintain the designed positional relationship between the embedded copper pillar 202, the glass via 104, and the subsequent redistribution pads.

[0072] The pre-fabricated silicon core can be pre-fabricated by an external wafer front-end process. The internal functional circuits, through-silicon vias, capacitor structures, and surface wiring of the pre-fabricated silicon core can be completed before the core is embedded in the glass substrate 1, so as to avoid performing high-temperature or high-precision front-end processes suitable for silicon wafers on the glass panel after the core is embedded.

[0073] The pre-fabricated silicon core includes a silicon body and a plurality of copper pillars 202 disposed on the first surface of the silicon body. The thickness of the silicon body is less than the thickness of the glass substrate 1, while the overall height of the pre-fabricated silicon core, including the copper pillars 202, is greater than the thickness of the glass substrate 1. The initial height of the copper pillars 202 is set according to the thickness difference between the silicon body and the glass substrate 1 and a predetermined grinding allowance, so that after the pre-fabricated silicon core is embedded, the first surface of the silicon body is located inside the glass substrate 1, while the ends of the copper pillars 202 away from the silicon body can protrude from the first surface of the glass substrate 1.

[0074] For example, the thickness of the glass substrate 1 can be 280 μm, the thickness of the silicon body can be 220 μm, and the overall height of the pre-fabricated silicon core, including the copper pillar 202, can be approximately 300 μm. In this case, the silicon body has a thickness difference of approximately 60 μm relative to the glass substrate 1. The copper pillar 202 can both bridge this thickness difference and retain a grinding allowance above the first surface of the glass substrate 1. By pre-setting the grinding allowance on the copper pillar 202, the subsequent leveling target can be transferred from the silicon body to the copper pillar 202, avoiding the need to rely on thinning the silicon body to obtain a coplanar structure.

[0075] The second surface of the glass substrate 1 is attached and fixed to the temporary carrier plate 3. The temporary carrier plate 3 can be a glass carrier plate with high rigidity and flatness, and a peelable layer is provided on the side of the temporary carrier plate 3 facing the glass substrate 1. The peelable layer can be a heat-release, ultraviolet-release, or laser-release polymer layer, as long as it can separate the glass substrate 1 from the temporary carrier plate 3 in subsequent processes.

[0076] After the glass substrate 1 is bonded to the temporary carrier plate 3, the pre-fabricated silicon core particles are embedded from one side of the first surface of the glass substrate 1 into the core particle embedding window 103 until the side of the pre-fabricated silicon core particle facing away from the copper pillar 202 abuts against the reference surface of the temporary carrier plate 3. Thus, the side of the pre-fabricated silicon core particle facing away from the copper pillar 202 and the second surface of the glass substrate 1 are on the same reference plane. The temporary carrier plate 3 simultaneously supports both the glass substrate 1 and the pre-fabricated silicon core particles; therefore, the coplanar relationship of the second side of the pre-fabricated silicon core particles does not depend on individual height measurement or individual adjustment of the mounting height.

[0077] In the completed embedding state, the first surface of the silicon substrate is located between the first and second surfaces of the glass substrate 1, and the ends of each copper pillar 202 away from the silicon substrate protrude from the first surface of the glass substrate 1. An assembly gap is formed between the periphery of the pre-fabricated silicon core and the inner wall of the core embedding window 103. This structure sets a coplanar reference on one side and a grinding allowance on the other side on the temporary carrier 3 and the copper pillar 202, respectively, so that the coplanarity of the two sides is achieved through different but complementary processes: the second surface of the glass substrate 1 is coplanar by jointly abutting against the temporary carrier 3, and the first surface of the glass substrate 1 is coplanar by removing the protruding parts of the copper pillar 202. Thus, without directly grinding the silicon substrate and its internal functional structure, a coplanar structure suitable for subsequent double-sided wiring and bonding can be formed.

[0078] In some embodiments, there are multiple core-particle mounting windows 103 arranged in an array on the glass substrate 1, and there are also multiple pre-fabricated silicon core particles, each of which is mounted in its corresponding core-particle mounting window 103. The multiple pre-fabricated silicon core particles are mounted with the same temporary carrier plate 3 as the height reference, and the filling, curing and leveling of the insulating filler material are completed on the same panel.

[0079] Since different core particles do not rely on independent fixtures to establish height references, but instead share the same temporary carrier plate 3 as the second surface reference, height dispersion caused by repeated positioning of mounting equipment, adhesive layer thickness, and differences in the flatness of individual carriers can be reduced. Subsequent leveling processing uses the same first surface of the glass substrate 1 as the termination reference, thus enabling simultaneous control of the first surface height of multiple mounting units within the same panel. The technical benefits of the array process are not only reflected in the simultaneous processing of multiple units, but also in the fact that each unit shares the same set of panel references, which helps improve coplanar consistency across the entire panel.

[0080] After the pre-fabricated silicon core is installed, insulating filler material is filled into the assembly gap between the periphery of the pre-fabricated silicon core and the inner wall of the core installation window 103. The assembly gap is set around the periphery of the pre-fabricated silicon core, forming an annular gap. Here, "annular" is not limited to a circular ring, but also includes a rectangular frame-like gap that extends continuously around the rectangular pre-fabricated silicon core.

[0081] The insulating filler material can be filled under vacuum or reduced pressure conditions. During the filling process, the glass substrate 1 and the pre-fabricated silicon core particles can be preheated, and then the insulating filler material can be injected from one or more locations in the assembly gap, allowing the insulating filler material to flow along the periphery of the pre-fabricated silicon core particles and fill the assembly gap. Vacuum filling can reduce the possibility of residual gas forming closed bubbles in narrow gaps and avoid local delamination of the interface caused by bubble expansion during subsequent heat treatment.

[0082] In some embodiments, the insulating filler material is an epoxy material modified with a composite filler of nano-silica and boron nitride, wherein the median particle size D50 of the composite filler is less than or equal to 0.2 μm. The insulating filler material has a coefficient of thermal expansion of 6-10 ppm / ℃, an elastic modulus of 2-4 GPa, and a curing shrinkage rate of less than or equal to 0.2%.

[0083] Nano-silica is used to reduce the curing shrinkage and coefficient of thermal expansion of epoxy materials, while boron nitride is used to improve the thermal conductivity of the filler layer. Controlling the filler particle size to within 0.2 μm allows the filler to enter the assembly gaps with widths on the micrometer scale with the resin, reducing the possibility of filler accumulation at the inlet causing filling interruptions. Controlling the elastic modulus to 2-4 GPa ensures that the cured insulating filler material provides circumferential support to the pre-fabricated silicon core particles while also exhibiting elastic deformation when the silicon body and glass substrate 1 undergo varying degrees of thermal deformation. Controlling the curing shrinkage rate to within 0.2% reduces the shrinkage tension applied to the periphery of the pre-fabricated silicon core particles during curing, thus reducing core particle misalignment and panel warping.

[0084] Therefore, the annular gap and low-stress insulating filler material are not merely used to fill the void, but rather to form a continuous electrically insulating and stress-buffering interface between the silicon core and the glass window. This interface can simultaneously restrict the lateral movement of the core, isolate the periphery of the core from the conductive structures on the glass substrate 1, and buffer the thermal expansion mismatch between silicon and glass.

[0085] After the insulating filler material is cured, it is leveled from the first surface side of the glass substrate 1. The leveling process mainly applies to the copper pillar 202 portion that is higher than the first surface of the glass substrate 1 and the insulating filler material that is higher than the first surface of the glass substrate 1, but does not grind the silicon body that is lower than the first surface of the glass substrate 1.

[0086] In some embodiments, the leveling process employs a flexible chemical mechanical polishing (CMP) process with a polishing pressure of 0.2 MPa. During polishing, a low downpressure, a low feed rate, and a polishing slurry suitable for the simultaneous removal of copper and epoxy materials can be used to gradually lower the copper pillar 202 and the cured insulating filler material to the height of the first surface of the glass substrate 1. Polishing is stopped when the leveled end face of the copper pillar 202, the leveled surface of the insulating filler material, and the first surface of the glass substrate 1 together form a continuous leveled plane.

[0087] After leveling, the global coplanarity of the entire plane is less than or equal to 0.5 μm, and the coplanarity of the region used for chip bonding within the plane is less than or equal to 0.3 μm. Global coplanarity is used to control the depth of focus and film thickness uniformity during subsequent whole-plane photolithography, seed layer deposition, and redistribution formation. Local coplanarity of the chip bonding region is used to control the degree of synchronous contact of the microbumps 9 during thermo-press bonding.

[0088] Since the leveling allowance is pre-set on the copper pillar 202, and the leveling endpoint is determined by the first surface of the glass substrate 1, the silicon substrate itself does not need to be thinned. Compared to directly grinding the silicon substrate containing voltage regulator circuits, deep trench capacitors, or through-silicon vias, this process reduces the risk of damage to precision functional structures due to grinding pressure, slurry penetration, or localized over-grinding. Simultaneously, the copper pillar 202 retains its metal end face, which connects to the internal wiring of the silicon substrate, after grinding, and can be directly used as the electrical connection location for the subsequent first wiring layer 8.

[0089] In some embodiments, during the formation of the core-embedded window 103, a plurality of glass through-holes 104 extending along the thickness direction of the glass substrate 1 are also formed on the glass substrate 1. The core-embedded window 103 and the glass through-holes 104 can be formed simultaneously by combining laser-induced modification with partitioned wet etching.

[0090] Specifically, nanosecond ultraviolet lasers can be used to selectively modify the glass substrate 1 according to the pattern of the core-embedded window 103 and the array pattern of the glass vias 104, so that the areas where the core-embedded window 103 and the glass vias 104 are to be formed have different corrosion rates than the unmodified glass areas. Subsequently, based on the size and aspect ratio of the rectangular window area and the circular via area, a partitioned wet etching process is used to form the core-embedded window 103 and the glass vias 104 on the same glass panel.

[0091] The core embedding window 103 is used to accommodate the pre-fabricated silicon core, and the glass via 104 is used to form a vertical conductive and thermally conductive path between the two sides of the glass substrate 1. The two types of through structures are formed using the same set of laser positioning coordinates, which can reduce the cumulative positional deviation caused by coordinate reference transformation when processing the two types of through structures separately, and maintain the predetermined positional relationship between the glass via 104, the embedded core, and the subsequent redistribution pattern.

[0092] After the glass via 104 is formed, a patterned photoresist layer 6 is formed on the glass substrate 1. The patterned photoresist layer 6 covers the opening area of ​​the die-mounting window 103 and the inner wall of the die-mounting window 103, while the glass via 104 remains exposed. The thickness of the patterned photoresist layer 6 can be 10-20 μm. After exposure and development, the photoresist layer can be baked and cured at 120-150℃ to maintain continuous coverage during subsequent seed layer deposition and electroplating processes.

[0093] Subsequently, a composite seed layer 7, comprising a titanium layer and a copper layer, is formed on the glass substrate 1 by physical vapor deposition. The titanium layer is used to improve the adhesion between the copper layer and the glass surface, while the copper layer is used to provide conductive seeds for subsequent electroplating. After the composite seed layer 7 is deposited, copper is electroplated to fill the glass vias 104.

[0094] In some embodiments, the electroplating solution includes inhibitors, accelerators, and leveling agents, and a pulse electroplating method is used to regulate the copper deposition rate at different depths inside the glass via 104. By controlling the concentration distribution of the accelerator and inhibitor within the via, copper grows gradually from the inside of the glass via 104 towards the opening, reducing the possibility of voids remaining inside the via after premature sealing of the opening. After the copper filling is completed within the glass via 104, the glass via 104 forms a metallic conductive pillar penetrating the glass substrate 1.

[0095] After the copper filling of the glass via 104 is completed, the patterned photoresist layer 6 covering the die-mounted window 103 is removed, and the metal layer attached to the surface of the patterned photoresist layer 6 is also removed. The photoresist layer can be removed by first swelling with an organic solvent and then by oxygen plasma ashing. Since the inner wall of the die-mounted window 103 is shielded by the photoresist layer during the deposition and electroplating of the composite seed layer 7, after the photoresist layer is stripped, there is no continuous metal layer on the inner wall of the die-mounted window 103, while the copper filling remains in the glass via 104.

[0096] The aforementioned selective shielding and combined stripping processes create vertical conductive paths for the glass vias 104 on the same glass substrate 1, while the larger core embedding windows 103 remain insulated. This process avoids the formation of peripheral leakage or metal bridging between different power domains due to copper layers simultaneously covering the inner wall of the core embedding windows 103 during the overall metallization of the glass vias 104.

[0097] In some embodiments, the plurality of prefabricated silicon dies include at least one active silicon-based power die 204 and at least one passive silicon-based decoupling die 205. The active silicon-based power die 204 may be arranged in the middle of an interposer cell or near the main computing die, and the passive silicon-based decoupling die 205 may be distributed around the active silicon-based power die 204 or near the power supply terminals of different load chips.

[0098] The active silicon-based power chip 204 integrates a voltage regulator unit and a first through-silicon via array penetrating its silicon body. The voltage regulator unit can be an integrated voltage regulator. The first through-silicon via array is electrically connected to the wiring structures on both sides of the active silicon-based power chip 204, enabling the active silicon-based power chip 204 to receive power from the second surface side of the glass substrate 1 and supply power to the upper functional bare chip 10 from the first surface side of the glass substrate 1.

[0099] The active silicon-based power chip 204 can have power wiring, ground wiring, and pad structures on both sides, respectively. One side with copper pillars 202 forms a metal end for connection to the first rewiring layer 8, while the side facing away from the copper pillars 202 forms an electrical pad for connection to the second rewiring layer 15. A first through-silicon via array connects the wiring structures on both sides, allowing the power supply current to pass through the active silicon-based power chip 204 along the thickness direction of the glass substrate 1, shortening the vertical power supply path from the packaging substrate to the upper load chip.

[0100] The passive silicon-based decoupling chip 205 integrates a deep trench capacitor array and / or a metal-insulator-metal capacitor array, as well as a second through-silicon via array penetrating the silicon body. The deep trench capacitor array can utilize the trench sidewalls inside the silicon body to form a large capacitor area, while the metal-insulator-metal capacitor array can be formed on the surface of the silicon body or within the interlayer dielectric. The second through-silicon via array is electrically connected to the capacitor bus wiring located on the side of the passive silicon-based decoupling chip 205 where the copper pillars 202 are provided, enabling multiple capacitor units to be connected to the first rewiring layer 8 through the copper pillars 202.

[0101] The passive silicon-based decoupling core 205 has an insulating passivated surface on the side facing away from the copper pillar 202, without any metallic pattern. This surface does not form an electrical connection with the second rewiring layer 15, thus preventing the passive silicon-based decoupling core 205 from generating additional current loops on its back side or from unintended coupling with adjacent power domains. The passive silicon-based decoupling core 205 primarily connects to the power and ground networks near the load from the first surface side, which can shorten the decoupling current loop and reduce the equivalent series inductance of the decoupling path.

[0102] The active silicon-based power chip 204 and the passive silicon-based decoupling chip 205 can undergo continuity testing, insulation testing, voltage regulation function testing, and capacitance parameter testing respectively before embedding. The qualified chips are then embedded into the glass substrate 1. Pre-inspection can avoid discovering embedded chip failures only after panel-level filling, leveling, and rewiring are completed, reducing the impact of failed chips on other units on the same panel.

[0103] By embedding an active silicon-based power supply chip 204 and a passive silicon-based decoupling chip 205 within the same glass substrate 1, the near-load voltage regulation function and the near-load intermediate frequency decoupling function can be implemented by silicon chips suitable for undertaking the corresponding functions. The active silicon-based power supply chip 204 shortens the high-current path between the voltage regulator unit and the load, while the passive silicon-based decoupling chip 205 shortens the transient current path between the capacitor and the load power supply terminal. The two types of chips avoid forming unwanted back-side conductive structures through different silicon via connection methods.

[0104] After the copper pillars 202 and the insulating filler material are leveled, a first super-wiring layer 8, electrically connected to each copper pillar 202, is formed on the first surface of the glass substrate 1. The first super-wiring layer 8 can be formed sequentially by plasma activation, seed layer sputtering, photolithography patterning, electroplating thickening, and wet etching. The first super-wiring layer 8 spans the first surface of the glass substrate 1, the leveled end face of the copper pillars 202, and the leveled surface of the insulating filler material, connecting the copper pillars 202 of the pre-fabricated silicon core to the glass vias 104 and external pads on the glass substrate 1 according to the designed circuit.

[0105] The first wiring layer 8 includes a high-speed signal wiring area, an active chip power wiring area, a ground shield wiring area, and a passive chip capacitor bus wiring area. The copper layer thickness of the high-speed signal wiring area can be 2μm, the copper layer thickness of the active chip power wiring area and the ground shield wiring area can both be 2.5μm, and the copper layer thickness of the passive chip capacitor bus wiring area can be 1.0μm.

[0106] The high-speed signal wiring area uses a 2μm copper layer, which allows for control of the cross-sectional dimensions and impedance of the high-speed signal lines while ensuring line continuity and manufacturing stability. The power supply wiring area and the ground shield wiring area use a thicker 2.5μm copper layer, which increases the conductive cross-sectional area of ​​the high-current power supply path and reduces the DC voltage drop of the power and ground paths. The passive core capacitor bus wiring area uses a 1.0μm copper layer, which reduces the volume of the metal loop and the current loop area connected to the decoupling capacitor, thus reducing the parasitic inductance of the capacitor connection path.

[0107] Instead of uniformly increasing or decreasing the copper thickness across the entire board, different wiring areas have their copper thicknesses set according to the different requirements of high-speed signals, high-current power supply, and low parasitic decoupling. This avoids the increase in parasitic parameters in fine decoupling interconnects when using uniformly thick copper, and also avoids the increased voltage drop in high-current power supply lines when using uniformly thin copper. This partitioned copper thickness structure allows signal integrity, power transmission capability, and parasitic parameters of decoupling loops to be controlled separately within the same rewiring layer.

[0108] In some embodiments, the first redistribution layer 8 further forms a grounding shielding structure surrounding different power domains and is connected to grounding glass vias 104 in different regions of the glass substrate 1. The insulating region of the glass substrate 1 itself physically separates different external power domains, and the grounding shielding structure electrically shields the sub-power domains near the core, thereby reducing crosstalk between adjacent power domains generated by the redistribution layer and the core interconnection.

[0109] Microbumps 9 are formed on the pads of the first multi-layer wiring layer 8. The microbumps 9 can be copper-tin composite microbumps 9, including copper pillars 202 and tin-based solder portions located at the ends of the copper pillars 202. The microbumps 9 are used to connect the first multi-layer wiring layer 8 to the upper functional bare die 10.

[0110] At least one upper-layer functional bare chip 10 is bonded to the first rerouting layer 8 via microbumps 9. The upper-layer functional bare chip 10 may include at least one of computing bare chips, high-bandwidth storage bare chips, and input / output interface bare chips. For example, the upper-layer functional bare chip 10 may include a graphics computing bare chip, four high-bandwidth storage bare chips, and at least one input / output interface bare chip.

[0111] The upper functional bare core 10 can be connected to the microbumps 9 by thermocompression bonding. During the bonding process, the upper functional bare core 10 is aligned with the first redistribution layer 8, so that the pads of the upper functional bare core 10 contact the corresponding microbumps 9, and metallurgical interconnects are formed under predetermined temperature and pressure.

[0112] After bonding is completed, a filler 12 is filled into the interconnect gap 11 between the upper functional bare core 10 and the glass substrate 1. The filler 12 can enter between adjacent microbumps 9 through capillary flow and is cured under isothermal conditions. After curing, the filler 12 forms a continuous support between the upper functional bare core 10, the microbumps 9 and the first redistribution layer 8, sharing the shear stress on the microbumps 9 caused by the difference in thermal expansion coefficients between the upper functional bare core 10 and the glass substrate 1.

[0113] Subsequently, an epoxy molding compound is used to coat the upper functional bare core granules 10, microbumps 9, and the first redistribution layer 8. Vacuum transfer molding can be used during the molding process to reduce the possibility of residual air bubbles around the upper functional bare core granules 10 and between multiple bare core granules. After the epoxy molding compound cures, it is leveled to remove the molding material above the surface of the upper functional bare core granules 10 facing away from the glass substrate 1, thus exposing the surface of the upper functional bare core granules 10 facing away from the glass substrate 1.

[0114] The underfill 12 primarily fills the local interconnection gaps 11 where the microbumps 9 are located, while the epoxy molding compound comprehensively covers the upper functional bare core particles 10, microbumps 9, and the first redistribution layer 8 on the entire board. Together, these two components ensure that the microbumps 9 are supported by the nearby underfill 12 and constrained by the external molding structure. The composite structure formed after molding and leveling can be transported as a whole during subsequent board disassembly and flipping processes, reducing the possibility of local displacement or warping of the upper functional bare core particles 10 relative to the glass substrate 1.

[0115] After leveling the epoxy molding compound, the glass substrate 1 is separated from the original temporary carrier plate 3. Since the original temporary carrier plate 3 has a peelable layer, the adhesive force of the peelable layer can be reduced by heating, ultraviolet irradiation, laser irradiation or mechanical peeling, so that the glass substrate 1 and the pre-fabricated silicon core particles, the upper functional bare core particles 10 and the epoxy molding compound are separated from the original temporary carrier plate 3 as a whole.

[0116] The side with the upper functional bare core granules 10 and epoxy molding compound formed is attached to the second temporary carrier plate 14, with the upper functional bare core granules 10 and the molded structure facing the second temporary carrier plate 14, exposing the second surface of the glass substrate 1. The second temporary carrier plate 14 may also be provided with a peelable layer so that it can be disassembled again after the second surface processing is completed.

[0117] Plasma activation, seed layer deposition, photolithography patterning, electroplating thickening, and etching are sequentially performed on the second surface of the glass substrate 1 to form a second redistribution layer 15. The second redistribution layer 15 is connected to the fill copper in the glass via 104 and the electrical pads on the back side of the active silicon-based power chip 204. Flip-chip bumps 16, which can be C4 bumps, are formed on the pads of the second redistribution layer 15 to connect the glass substrate 1 to the lower packaging substrate.

[0118] First, the bonding, underfilling, overall molding, and molding leveling of the upper functional bare core 10 on the first surface are completed. Then, the board is disassembled, flipped, and the redistribution fabrication on the second surface is performed, so that the micro-bumps 9 and fine redistribution lines on the first surface are covered by underfill adhesive 12 and epoxy molding compound before back-side processing. As a result, during flipping, cleaning, photolithography, sputtering, and electroplating processes, the precision interconnect structure on the first surface is not directly subjected to clamping and fluid impact, reducing the impact of back-side processes on the already formed bonding structure.

[0119] After the second rewiring layer 15 and flip-chip bumps 16 are formed, the glass substrate 1 is separated from the second temporary carrier 14, and a passivation protective layer is formed on the exposed insulating areas of the first and second surfaces of the glass substrate 1. The passivation protective layer avoids the bonding areas of the microbumps 9 and flip-chip bumps 16 and is used to cover the metal lines in the first rewiring layer 8 and the second rewiring layer 15 that do not need to be exposed.

[0120] Subsequently, the entire board can be subjected to electrical continuity testing, insulation withstand voltage testing, PDN impedance scanning, microbump bonding strength testing, and thermal cycling reliability testing in sequence. Electrical continuity testing is used to detect the continuity of the interconnect links formed by the glass via 104, silicon vias, the first rewiring layer 8, and the second rewiring layer 15; insulation withstand voltage testing is used to detect whether there is leakage between the inner wall of the chip embedding window 103, the insulating filler material, and different power domains; PDN impedance scanning is used to detect the impedance changes of the power supply network formed by the active silicon-based power chip 204, the passive silicon-based decoupling chip 205, and the glass substrate 1 wiring at different frequencies; thermal cycling reliability testing is used to detect whether delamination or cracking occurs between the silicon substrate, glass substrate 1, insulating filler material, and copper interconnect structure.

[0121] After completing the overall panel inspection, the glass panel is cut according to the boundaries of each interposer unit, and the cut edges are trimmed to obtain an independent silicon core embedded glass substrate 1. Since the inspection is completed before panel cutting, non-compliant interposer units can be identified first, and then marked and cut according to the inspection results.

[0122] This embodiment uses a glass substrate 1 as an example to illustrate a co-package of one computing die, four high-bandwidth storage dies, and input / output interface dies. The target packaging unit has a planar size of approximately 55mm × 90mm and is fabricated using an array of 310mm × 310mm alkali-free aluminosilicate glass panels, with multiple interposer units arranged on one glass panel.

[0123] A 280μm thick alkali-free aluminosilicate glass panel was selected and subjected to organic solvent cleaning, plasma impurity removal and stress annealing in sequence to ensure that the overall warpage of the glass panel was no more than 5μm and the total thickness deviation was no more than 1μm.

[0124] A process combining nanosecond ultraviolet laser-induced modification and partitioned wet etching is used to simultaneously form rectangular core-embedded windows 103 and glass through-holes 104 on a glass panel. Each core-embedded window 103 has a dimensional difference of 8 μm relative to the corresponding pre-fabricated silicon core in both the length and width directions. The dimension of the end of the core-embedded window 103 located on the second surface of the glass substrate 1 is slightly larger than the dimension of the end located on the first surface, with the dimensional difference between the two ends controlled within 2 μm; the perpendicularity of the window sidewall is not less than 85°, the sidewall roughness Ra is not greater than 0.5 μm, and the opening position accuracy is controlled within ±2 μm.

[0125] A 20 μm thick photoresist is coated onto the glass panel surface. After exposure and development, the photoresist covers the opening and inner wall of the chip mounting window 103, leaving the glass via 104 exposed. The photoresist is then baked and cured at 150°C. A titanium / copper composite seed layer 7 is formed by physical vapor deposition, and copper is filled into the glass via 104 using pulse electroplating. After copper filling, the photoresist and its surface metal layer are removed using a combination of organic solvent swelling and oxygen plasma ashing, leaving the copper filling inside the glass via 104 while the inner wall of the chip mounting window 103 remains in a glass insulating state.

[0126] The prefabricated silicon chips include an active silicon-based power chip 204 and a passive silicon-based decoupling chip 205. The active silicon-based power chip 204 has a silicon body thickness of 220 μm and integrates a voltage regulator unit and a first through-silicon via array for electrical connections on both sides. The passive silicon-based decoupling chip 205 has a silicon body thickness of 220 μm and integrates a deep trench capacitor array, a metal-insulator-metal capacitor array, and a second through-silicon via array; its side facing away from the copper pillar 202 is an insulating passivation surface. The overall height of both types of prefabricated silicon chips, including the copper pillar 202, is approximately 300 μm.

[0127] The second surface of the glass panel is attached to a temporary glass carrier 3 with a peelable layer. In a vacuum environment, active silicon-based power chips 204 are embedded in the middle of each interposer unit, and multiple passive silicon-based decoupling chips 205 are embedded around the active silicon-based power chips 204, so that the side surface of each prefabricated silicon chip facing away from the copper pillar 202 is coplanar with the second surface of the glass substrate 1.

[0128] An epoxy material modified with a composite filler of nano-silica and boron nitride is filled into the assembly gaps around the pre-fabricated silicon core particles. The median particle size D50 of the composite filler is no greater than 0.2 μm, the coefficient of thermal expansion of the insulating filler is 8 ppm / ℃, the elastic modulus is 3 GPa, and the curing shrinkage rate is no greater than 0.2%. After filling, low-temperature curing is performed to form a continuous interface layer of insulating filler surrounding the pre-fabricated silicon core particles.

[0129] A flexible chemical mechanical polishing (CMP) process with a polishing pressure of 0.2 MPa was used to level the copper pillars 202 and the cured insulating filler material that protruded above the first surface of the glass substrate 1. After polishing, the leveled end faces of each copper pillar 202, the leveled surface of the insulating filler material, and the first surface of the glass substrate 1 formed a continuous flat plane. The overall coplanarity of the flat plane was no greater than 0.5 μm, and the coplanarity of the area used for subsequent chip bonding was no greater than 0.3 μm.

[0130] The entire plane is plasma activated, followed by seed layer sputtering, photolithography patterning, electroplating thickening, and wet etching to form the first wiring layer 8. In the first wiring layer 8, the copper layer thickness in the high-speed signal wiring region is 2 μm, the copper layer thickness in the active chip power wiring region and the ground shield wiring region is 2.5 μm, and the copper layer thickness in the passive chip capacitor bus wiring region is 1.0 μm. Copper-tin composite microbumps 9 are formed on the pads of the first wiring layer 8.

[0131] The computing bare core, four high-bandwidth storage bare cores, and input / output interface bare cores are aligned with their corresponding microbumps 9 and bonded using low-temperature thermocompression. After bonding, a filler 12 is filled between the bare cores and the glass substrate 1 via capillary flow and cured. Subsequently, a vacuum transfer molding process is used to encapsulate all the upper functional bare cores 10, microbumps 9, and the first redistribution layer 8 with epoxy molding compound. The cured epoxy molding compound is then leveled until the surface of the upper functional bare cores 10 facing away from the glass substrate 1 is exposed.

[0132] The glass substrate 1, after front-side bonding and molding, is separated from the original temporary carrier 3, and the molded surface is attached to the second temporary carrier 14, exposing the second surface of the glass substrate 1. A second rewiring layer 15 is formed on the second surface of the glass substrate 1, and C4 flip-chip bumps 16 are formed on the pads of the second rewiring layer 15. The second rewiring layer 15 connects the back-side electrical pads of the active silicon-based power chip 204 and the glass via 104 to the C4 flip-chip bumps 16 to form a vertical interconnect path for power supply from the package substrate to the upper functional bare chip 10.

[0133] After completing the second surface treatment, final disassembly and passivation protection are performed, followed by sequential testing of electrical conductivity, insulation withstand voltage, PDN impedance, bonding strength, and thermal cycling. After testing, the substrate is laser-cut according to the boundaries of the interposer units to obtain multiple independent glass-based interposer units.

[0134] In this embodiment, one side of the pre-fabricated silicon chip is established with a coplanar reference through a temporary carrier plate 3, and the other side is obtained with a coplanar structure through sacrificial grinding of copper pillars 202; the active silicon-based power chip 204 and the passive silicon-based decoupling chip 205 respectively undertake near-load voltage regulation and near-load decoupling functions within the same glass substrate 1; the glass via 104 forms a vertical conductive path while maintaining the insulation of the chip embedding window 103; the chip bonding and molding protection of the first surface are completed before the redistribution process of the second surface. The above processes have a sequential dependency relationship, enabling the functional structure protection of the pre-fabricated silicon chip, the buffering of the silicon-glass heterogeneous interface, the formation of double-sided interconnects, and the panel-level array processing to be realized in the same process.

[0135] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims, and the foregoing embodiments should be considered exemplary and non-limiting.

Claims

1. A method for fabricating a plate-level coplanar structure of silicon core particles embedded in a glass substrate, characterized in that, include: A core-embedded window is formed on a glass substrate having a first surface and a second surface arranged opposite to each other, extending through the thickness direction of the panel-type glass substrate; A pre-fabricated silicon core is provided, the pre-fabricated silicon core comprising a silicon body and a plurality of copper pillars disposed on a first surface of the silicon body; The second surface of the glass substrate is attached and fixed to a temporary carrier plate, and the pre-made silicon core is embedded in the core embedding window, such that the side surface of the pre-made silicon core away from the copper pillar is coplanar with the second surface of the glass substrate. The first surface of the silicon body is located between the first surface and the second surface of the glass substrate. The ends of each copper pillar away from the silicon body protrude from the first surface of the glass substrate, and an assembly gap is formed between the periphery of the pre-made silicon core and the inner wall of the core embedding window. Fill the assembly gap with insulating filler material and allow the insulating filler material to cure; The copper pillars and the cured insulating filler material are leveled from the first surface side of the glass substrate, removing the portions of each copper pillar that protrude from the first surface of the glass substrate and the portions of the cured insulating filler material that are higher than the first surface of the glass substrate, so that the leveled end faces of each copper pillar and the leveled surface of the insulating filler material are coplanar with the first surface of the glass substrate.

2. The method according to claim 1, characterized in that, The core particle embedding windows are multiple and arranged in an array on the glass substrate. There are multiple pre-made silicon core particles, each of which is embedded in the corresponding core particle embedding window. The insulating filling material is filled, cured, and leveled using the temporary carrier plate as a support reference.

3. The method according to claim 1, characterized in that, The core embedding window is a rectangular window, and the minimum opening size of the core embedding window in the length direction and the width direction is larger than the outer dimensions of the pre-made silicon core in the corresponding directions, and the size difference is 5-10μm; The core-embedded window is micro-conical, and the size of one end of the core-embedded window located on the second surface of the glass substrate is larger than the size of one end located on the first surface of the glass substrate, and the size difference between the two ends of the core-embedded window in the corresponding direction is less than or equal to 2 μm.

4. The method according to claim 1, characterized in that, The leveling process is a flexible chemical mechanical polishing process; After the leveling process is completed, the leveled end face of each copper pillar, the leveled surface of the insulating filler material, and the first surface of the glass substrate together form a level plane. The coplanarity of the level plane is less than or equal to 0.5 μm, and the coplanarity of the area used for chip bonding in the level plane is less than or equal to 0.3 μm.

5. The method according to claim 1, characterized in that, During the formation of the core embedding window, multiple glass through holes extending along the thickness direction of the glass substrate are also formed on the glass substrate. The core embedding window and the glass through holes are formed simultaneously by a combination of laser-induced modification and partitioned wet etching.

6. The method according to claim 5, characterized in that, Before embedding the pre-fabricated silicon die into the die embedding window, the method further includes: A patterned photoresist layer is formed on the glass substrate, such that the patterned photoresist layer covers the chip mounting window and the inner wall of the chip mounting window, and exposes the glass via. A composite seed layer comprising a titanium layer and a copper layer is deposited on the glass substrate, and copper is filled into the glass vias by electroplating. Remove the patterned photoresist layer covering the chip mounting window and the metal layer attached to the surface of the patterned photoresist layer, so that the glass via filled with copper forms a vertical conductive path, and keep the inner wall of the chip mounting window insulated.

7. The method according to claim 2, characterized in that, The plurality of the prefabricated silicon chips include at least one active silicon-based power chip and at least one passive silicon-based decoupling chip; The active silicon-based power chip integrates a voltage regulator unit and a first silicon via array that penetrates the silicon body of the active silicon-based power chip. The first silicon via array is electrically connected to wiring structures disposed on both sides of the silicon body of the active silicon-based power chip. The passive silicon-based decoupling core integrates a deep trench capacitor array and / or a metal-insulator-metal capacitor array, as well as a second silicon via array penetrating the silicon body of the passive silicon-based decoupling core. The second silicon via array is electrically connected to a capacitor bus wiring located on the side of the passive silicon-based decoupling core where the copper pillar is disposed.

8. The method according to claim 7, characterized in that, After the leveling process is completed, a first redistribution layer electrically connected to each of the copper pillars is formed on the first surface of the glass substrate, and microbumps are formed on the pads of the first redistribution layer. The first wiring layer includes a high-speed signal wiring area, an active chip power wiring area, a ground shield wiring area, and a passive chip capacitor bus wiring area.

9. The method according to claim 8, characterized in that, Also includes: At least one upper-layer functional bare core is bonded to the first rewiring layer via the microbumps; Fill the interconnection gap between the upper functional bare core and the glass substrate with underfill material, and allow the underfill material to cure. The upper functional bare core, the microbumps, and the first redistribution layer are coated with epoxy molding compound, and the cured epoxy molding compound is leveled so that the surface of the upper functional bare core that is away from the glass substrate is exposed.

10. The method according to claim 9, characterized in that, After the epoxy molding compound is leveled, the glass substrate is separated from the temporary carrier plate, and the side with the upper functional bare core particle and the epoxy molding compound is attached to the second temporary carrier plate, so that the second surface of the glass substrate is exposed. A second redistribution layer is formed on the second surface of the glass substrate, and flip-chip bumps for connection with the packaging substrate are formed on the pads of the second redistribution layer.

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