Multi-layer re-wired panel level package structure and its packaging method and packaging device

Abstract

The application relates to the technical field of semiconductor packaging, solves the problem that different functional chips and passive elements cannot be high-density interconnected in limited packaging size in the prior art, and provides a panel-level packaging structure with multiple re-routed conductor layers, a packaging method and a packaging device, wherein a vertical conductive interconnection structure is arranged around a chip to be packaged, multiple re-routed conductor layers are respectively constructed on two side surfaces of the chip to be packaged, a double-sided three-dimensional interconnection network is formed, multiple different types of chips to be packaged and passive elements can be integrated in a compact packaging module, double-sided high-density three-dimensional interconnection of the chip to be packaged is realized, and the packaging volume is significantly reduced. Moreover, due to panel-level batch processing, the final packaging space is greatly saved, the alignment accuracy and packaging yield are improved, and the manufacturing cost is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a multi-layer rewiring panel-level packaging structure, packaging method, and packaging device thereof. Background Technology

[0002] Packaging is the process of placing the bare integrated circuit dies produced by the wafer fab onto a substrate that serves as a support, connecting the integrated circuits and pins on the die with leads, bringing the pins out, and then fixing and packaging them into a whole.

[0003] As electronic products continue to evolve towards miniaturization and multifunctionality, chip sizes are shrinking and the variety of chips is increasing, making advanced packaging technology one of the best options for continuing Moore's Law. Panel-level packaging, as one of the advanced packaging forms, has attracted widespread market attention due to its potential cost-effectiveness and higher manufacturing efficiency. Existing panel-level embedded packaging solutions can already achieve the embedded packaging of multiple chips and other components. For example, Chinese patent CN109686669A discloses an integrated circuit packaging method and packaging structure. This solution first pre-fabricates an organic polymer frame with cavities using a coreless copper pillar method, then embeds multiple components into the cavity of the polymer frame at once, performs single-sided fan-out after packaging, and subsequently performs double-sided layering.

[0004] However, this patented solution requires the prefabrication of a polymer frame with cavities before embedding and packaging components, resulting in a long processing flow and high costs. Secondly, the multiple embedded and packaged components need to be placed on the same layer, making it impossible to simultaneously package components with large thickness differences. Furthermore, after embedding and packaging multiple components, only single-sided fan-out can be achieved, making wiring difficult and unable to achieve high-density interconnection of multiple chips and passive components within a limited package size. Summary of the Invention

[0005] In view of this, the multi-layer rewiring panel-level packaging structure, packaging method, and packaging device provided in the embodiments of the present invention are used to solve the problem that the prior art cannot achieve high-density interconnection between different functional chips and passive components within a limited packaging size.

[0006] In a first aspect, embodiments of the present invention provide a panel-level packaging method for multi-layer rewiring, the method comprising: At least one chip to be packaged is placed on a preset reference carrier, and a vertical conductive interconnect structure is set at a preset position on the reference carrier to form an embedded component assembly. The first surface of the embedded component assembly is wired in a first direction, including the sequential repeated execution of lamination, photolithography and redistribution processes, to construct at least two first-direction redistribution conductor layers on the first surface to obtain a single-sided wiring structure. The second surface of the single-sided wiring structure is wired in a second direction, including the sequential repeated execution of lamination, photolithography and redistribution processes, to construct at least two second-direction redistribution conductor layers on the second surface to obtain a double-sided wiring structure. Among them, a portion of the first-direction redistributed conductor layer and the second-direction redistributed conductor layer are electrically interconnected between layers through the vertical conductive interconnection structure; Pads are formed on the conductor layer in the first direction and / or the conductor layer in the second direction, and at least one passive component is soldered on the pads to obtain the target package panel.

[0007] By setting a vertical conductive interconnect structure on a reference carrier and repeatedly performing lamination, photolithography, and redistribution processes on both sides of the chip, at least two first-direction redistribution conductor layers and at least two second-direction redistribution conductor layers are constructed, achieving high-density three-dimensional interconnection on both sides of the chip. This allows for the integration of multiple chips and passive components within a limited package size, significantly reducing the package volume. Furthermore, based on panel-level batch processing, the lengthy process of pre-fabricating cavity frames required in traditional solutions is avoided, simplifying the process flow, improving production efficiency, and reducing manufacturing costs.

[0008] As an optional implementation, after obtaining the target packaged panel, the method further includes: The target packaging panel is encapsulated as a whole, and then divided into multiple independent packaging modules based on preset cutting parameters.

[0009] By first completing the electrical integration of all chips and passive components and then performing unified overall molding and cutting, the molding process can be centralized, reducing material waste and process deviations caused by multiple molding processes. At the same time, the panel-level batch cutting method increases the output of a unit panel, further improving packaging efficiency and yield.

[0010] As an optional implementation, the wiring in the first direction on the first surface of the embedded component assembly specifically includes: The first surface of the embedded component assembly is subjected to repeated lamination, photolithography and redistribution processes three times to prepare the single-sided wiring structure with three layers of redistributed conductors in the first direction. The second-direction wiring of the second surface of the single-sided wiring structure specifically includes: The second surface of the single-sided wiring structure is subjected to repeated lamination, photolithography and redistribution processes three times to prepare the double-sided wiring structure, which has three layers of redistributed conductors in the first direction and three layers of redistributed conductors in the second direction.

[0011] The six-layer redistribution conductor architecture provides ample wiring space and flexible interconnect paths, which can meet the high-density interconnection requirements of various functional chips and multiple passive components, thus improving functional density. At the same time, the symmetrical three-layer redistribution structure helps to balance the double-sided wiring stress and reduce the risk of package warpage.

[0012] As an optional implementation, the vertical conductive interconnect structure includes pre-embedded metal pillars or a metal frame; the reference carrier is a biodegradable adhesive film.

[0013] Using pre-embedded metal pillars or metal frames as vertical interconnect structures results in lower contact resistance and higher structural strength compared to filling conductive materials after laser etching, effectively improving interconnect reliability. The reference carrier uses a biodegradable adhesive film, which can be removed by degradation or peeling after wiring is completed, avoiding complex carrier removal procedures, simplifying process steps, and reducing the risk of mechanical damage to the packaging structure.

[0014] As an optional implementation, the process of performing lamination, photolithography, and redistribution of the conductor layer includes: Perform a lamination process to form an insulating dielectric layer; A photolithography process is performed to form a through-hole pattern in the insulating dielectric layer; A redistribution process is performed to form a redistributed conductor layer in the via pattern, the redistributed conductor layer including a first-direction redistributed conductor layer and a second-direction redistributed conductor layer; both the first-direction redistributed conductor layer and the second-direction redistributed conductor layer include redistributed wires and vertical conductive posts.

[0015] By sequentially repeating the lamination, photolithography, and redistribution processes, the construction steps of each redistributed conductor layer are standardized and modularized, facilitating independent control and optimization of process parameters and improving process consistency and repeatability. Redistributed conductors and vertical conductive pillars are formed simultaneously in the same process, reducing process interfaces and enhancing interconnect reliability.

[0016] As an optional implementation, after performing the rewiring process, the method further includes: After each layer of the re-laid conductor is formed, a molding process is performed on the re-laid conductor to fill the gaps around the re-laid conductor and provide mechanical protection.

[0017] Layer-by-layer molding can promptly fill the gaps around each layer of redistributed conductors and vertical conductive pillars, providing a flattened surface for subsequent lamination between film layers and significantly improving the interlayer bonding quality during multilayer stacking. At the same time, layer-by-layer molding releases stress layer by layer, effectively controlling the cumulative warpage of large-size panels during multiple thermal process cycles, ensuring the accuracy of via alignment between redistributed conductor layers, and improving the process yield of multilayer wiring.

[0018] As an optional implementation, each type of chip to be packaged includes at least one, and the different types of chips to be packaged correspond to different functions; the types of chips to be packaged include controller type and power type; the passive components include resistors, capacitors or diodes.

[0019] As an optional implementation, the packaging module is a DC / DC power supply module.

[0020] By integrating the controller chip, power chip, and passive components such as resistors, capacitors, and diodes within the same package module, a complete circuit function of the power module is achieved through integrated packaging. This reduces the interconnection distance between the packaged chip and the passive components, lowers parasitic inductance and resistance, and helps improve the electrical performance, conversion efficiency, and dynamic response speed of the power module.

[0021] In a second aspect, embodiments of the present invention provide a multilayer rewiring panel-level packaging device, the device comprising: A positioning and arrangement module is used to place at least one chip to be packaged on a preset reference carrier and to set a vertical conductive interconnect structure at a preset position on the reference carrier to form an embedded component assembly. The first redistribution module is used to perform first-direction wiring on the first surface of the embedded component assembly, including sequentially performing lamination, photolithography and redistribution processes to construct at least two first-direction redistribution conductor layers on the first surface of the embedded component assembly to obtain a single-sided wiring structure. The second rewiring module is used to perform second-direction wiring on the second surface of the single-sided wiring structure, including sequentially repeating the processes of lamination, photolithography and redistribution of conductor layers to construct at least two second-direction redistribution conductor layers on the second surface of the single-sided wiring structure to obtain a double-sided wiring structure. Among them, a portion of the first-direction redistributed conductor layer and the second-direction redistributed conductor layer are electrically interconnected between layers through the vertical conductive interconnection structure; A soldering module is used to form pads on a conductor layer redistributed in the first direction and / or a conductor layer redistributed in the second direction, and to solder at least one passive component on the pads to obtain a target package panel.

[0022] By mapping each process step to an independent functional module, a modular design for the packaging device is achieved. Each module can be independently debugged, maintained, and upgraded, reducing the complexity of the packaging device and improving the flexibility and scalability of the production line. At the same time, the clear division of labor and sequential collaboration between modules facilitates the automation and standardization of the panel-level packaging process, improving production efficiency and packaging consistency.

[0023] Thirdly, embodiments of the present invention provide a multi-layer rewiring panel-level packaging structure, including: At least one chip to be packaged, and a vertical conductive interconnect structure disposed at a predetermined position around the chip to be packaged; A first-direction redistributed conductor layer is disposed on the first surface of the chip to be packaged, and the first-direction redistributed conductor layer includes at least two layers. A second-direction redistributed conductor layer is disposed on the second surface of the chip to be packaged, and the second-direction redistributed conductor layer includes at least two layers. Among them, a portion of the first-direction redistributed conductor layer and the second-direction redistributed conductor layer are electrically interconnected between layers through the vertical conductive interconnection structure; The pads are disposed on the outermost first-direction redistributed conductor layer and / or the second-direction redistributed conductor layer; And at least one passive component, soldered onto the pad.

[0024] This packaging structure uses a vertical conductive interconnect structure as an electrical bridge to achieve three-dimensional interconnection of double-sided conductor layers on the chip. It completes high-density integration of multiple chips and passive components in a limited three-dimensional space, resulting in a compact structure. The symmetrical double-sided wiring architecture makes the electrical signal path shorter and the heat dissipation path more diverse, which helps to improve the electrical performance and thermal management capabilities of the package module. It is suitable for power management applications with stringent requirements for both size and performance.

[0025] In summary, the beneficial effects of the present invention are as follows: The multi-layer redistribution panel-level packaging structure, packaging method, and packaging device provided in this invention form a double-sided three-dimensional interconnect network by setting a vertical conductive interconnect structure around the chip to be packaged and constructing multiple redistribution conductor layers on both sides of the chip to be packaged. This enables multiple different types of chips to be packaged and passive components to be integrated into a compact packaging module. Based on panel-level batch processing, it significantly saves packaging space, improves alignment accuracy and packaging yield, and reduces manufacturing costs.

[0026] For example, in one embodiment, a complete dual-channel DC / DC power module can be built on a micro-module with dimensions of only 5.0mm × 3.8mm × 1.9mm. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, and these are all within the protection scope of the present invention.

[0028] Figure 1 This is a flowchart of a panel-level packaging method for multi-layer rewiring according to an embodiment of the present invention; Figure 2 This is an exploded view of the structure of the chip to be packaged in one embodiment of the present invention; Figure 3 This is a schematic diagram of the cross-sectional structure of the chip to be packaged in one embodiment of the present invention; Figure 4a This is a top view of the finished packaging module in one embodiment of the present invention; Figure 4b This is a side view of the finished packaging module in one embodiment of the present invention; Figure 4c This is a bottom view of the finished packaging module in one embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the panel-level packaging device for multi-layer rewiring according to an embodiment of the present invention; Figure 6 This is a cross-sectional schematic diagram of the multi-layer rewiring panel-level packaging structure of the present invention in one embodiment; The attached figures are labeled as follows: 301 - Chip to be packaged, 3011 - First molding layer, 3012 - Chip body, 3013 - Contact, 3014 - Second molding layer, 3015 - Wiring layer, 3016 - Pin, 3017 - Third molding layer, 302 - Vertical conductive interconnect structure, 303 - First direction redistributed conductor layer, 304 - Second direction redistributed conductor layer, 305 - Pad, 306 - Passive component, 400 - Packaged module finished product. Detailed Implementation

[0029] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the invention.

[0030] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0031] In simple terms, packaging involves placing the bare integrated circuit (i.e., chip) die produced by a wafer foundry onto a substrate that serves as a support, interconnecting the integrated circuit on the die with leads and pins, then leading the pins out from the substrate, and finally securing and packaging it into a whole. Packaging protects the chip, essentially providing a protective shell for it. It not only secures and seals the chip but also enhances its electrical and thermal performance.

[0032] The semiconductor chip manufacturing process consists of wafer fabrication, wafer testing, chip packaging, and post-packaging testing. After molding, a series of operations are performed, such as post-mold curing (PMC), trimming and forming, plating, and printing. However, as electronic products continue to move towards miniaturization and multifunctionality, chip sizes are becoming smaller and the types are increasing. This has made advanced packaging technologies such as 3D packaging, fan-out wafer-level packaging (FOWLP), micro-pitch wire bonding technology, and system-in-package (SIP) among the best choices for continuing Moore's Law.

[0033] Panel-level packaging (PLP) is one of the advanced packaging methods. Its advantages over wafer-level packaging mainly lie in its higher utilization of the panel, resulting in lower costs and faster processing speed. Based on this, the multi-layer redistribution method of this invention is based on panel-level packaging, aiming to minimize the overall package size while ensuring a sufficient number of bottom solder balls, thereby improving the overall chip alignment process and increasing the overall package yield.

[0034] Firstly, please refer to the following: Figure 1As shown, this application provides a panel-level packaging method with a multi-layer redistribution layer, which can be used to manufacture dual-channel 5A step-down DC / DC power modules. The final package size of each power module can be controlled within 5.0mm × 3.8mm × 1.9mm. This panel-level packaging method with a multi-layer redistribution layer includes the following steps S101 to S104: Step S101: Place at least one chip to be packaged on a preset reference carrier, and set a vertical conductive interconnect structure at a preset position on the reference carrier to form an embedded component assembly.

[0035] Each type of chip to be packaged includes at least one chip. Different types of chips to be packaged have different functions, that is, the functions, thickness, size and quantity of different types of chips to be packaged can be different. In an optional embodiment, the types of chips to be packaged include controller type and power type. Specifically, it can be a controller chip and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) chip with a rated value of 40V / 40A. The number of controller chips can be one and the number of power MOSFET chips can be four.

[0036] The reference carrier can hold two or four types of chips to be packaged; for the sake of brevity, these will not be listed here. Before placing the chips to be packaged, the wafer is pre-processed. Specifically, adhesive is first applied to the front surface of the wafer to form a protective or adhesive layer; then, ball bearings are placed on the front surface of the wafer to pre-form bumps for electrical connection on the chip pads; after the ball bearings are placed, adhesive is applied again to reinforce or protect the ball bearing area; then, the back surface of the wafer is ground and thinned to meet the packaging thickness requirements; finally, the thinned wafer is cut and separated to form individual chips to be packaged.

[0037] like Figures 2-3 As shown, the chip to be packaged 301 consists of the following layers stacked sequentially: a first molding compound 3011, a chip body 3012, a contact 3013, a second molding compound 3014, a wiring layer 3015, a pin 3016, and a third molding compound 3017. The first molding compound 3011, the second molding compound 3014, and the third molding compound 3017 can be made of epoxy resin, the contact 3013 can be a solder ball, and the wiring layer 3015 and the pin 3016 can be made of copper or silver.

[0038] On the upper surface of a pre-defined reference carrier, at least one chip to be packaged is placed using a mounting device. Simultaneously, vertical conductive interconnect structures are set at pre-planned interconnect coordinates on the reference carrier, located around the chips or between the chips. The vertical conductive interconnect structures are set independently of the chips to be packaged and extend along the package thickness direction to connect the redistributed conductor layers that will be subsequently built on different layers. Thus, the reference carrier, the chips to be packaged, and the vertical conductive interconnect structures together constitute an embedded component assembly.

[0039] Specifically, the vertical conductive interconnect structure includes pre-embedded metal pillars or metal frames; the reference carrier can be a temporarily provided large-size biodegradable film.

[0040] Step S102: Perform first-direction wiring on the first surface of the embedded component assembly, including sequentially performing lamination, photolithography and redistribution processes to build at least two first-direction redistribution conductor layers on the first surface to obtain a single-sided wiring structure.

[0041] A first-direction wiring is performed on the first surface of the embedded component assembly, which may be the surface facing the front of the chip. The first-direction wiring is an iterative process, specifically including sequentially repeating the processes of lamination, photolithography, and redistribution to construct at least two first-direction redistributed conductor layers. Each cycle specifically includes steps A1 to A3: Step A1: Perform a lamination process to apply an insulating dielectric layer, such as a photosensitive dielectric material, to the first surface of the embedded component assembly; Step A2: Perform photolithography to form through-hole patterns on the insulating dielectric layer using exposure and development techniques; if necessary, drilling can be performed to assist in forming vertical through-holes.

[0042] Step A3: Perform the redistribution process. First, chemical copper plating is performed to form a seed layer in the via pattern. Then, metal is deposited and patterned using an electroplating process to form redistributed conductors on the insulating dielectric layer. Metal is then filled into the vias to form vertical conductive pillars. The redistributed conductors and vertical conductive pillars together constitute a redistributed conductor layer, namely the first-direction redistributed conductor layer.

[0043] By repeating the above cycle multiple times, a multilayer first-direction redistributed conductor layer, i.e., a single-sided wiring structure, is fabricated on the first surface of the chip to be packaged. In an optional embodiment, the first-direction wiring can be repeated three times to sequentially construct a single-sided wiring structure containing three first-direction redistributed conductor layers.

[0044] As an optional implementation, after each layer of the fabricated conductor is prepared, a molding process is performed on the fabricated conductor layer to fill the gaps around the layer with epoxy molding compound and provide mechanical protection. Subsequent grinding can be performed to planarize the surface in preparation for the next cycle of lamination.

[0045] Step S103: Perform second-direction wiring on the second surface of the single-sided wiring structure, including sequentially repeating the processes of lamination, photolithography and redistribution, to construct at least two second-direction redistribution conductor layers on the second surface, thereby obtaining a double-sided wiring structure.

[0046] Before performing step S103, in order to reduce the movement of the rewiring device, the single-sided wiring structure obtained in step S102 can be flipped so that its second surface faces upward, that is, the surface facing the back of the chip to be packaged faces the rewiring device.

[0047] On the second surface of the chip to be packaged, second-direction wiring is performed on the second surface of the single-sided wiring structure. Similarly, the processes of lamination, photolithography, and redistribution are repeated sequentially to construct at least two second-direction redistributed conductor layers. The specific process of each cycle in the second-direction wiring is exactly the same as described in step S102, and will not be repeated here.

[0048] By repeating the above cycle multiple times, a multilayer second-direction redistributed conductor layer, i.e., a double-sided wiring structure, is fabricated on the second surface of the chip to be packaged. In an optional embodiment, the second-direction wiring can be repeated three times to sequentially construct a double-sided wiring structure containing three layers of second-direction redistributed conductor layers.

[0049] Similarly, after each layer of the fabricated conductor is prepared, a molding process is performed on it. Epoxy molding compound is used to fill the gaps around the fabricated conductor layer and provide mechanical protection. Subsequent grinding can be performed to planarize the surface, preparing it for the next cycle of lamination.

[0050] In one optional embodiment, three first-direction redistributed conductor layers can be fabricated on the front side of the chip to be packaged by repeating the first-direction wiring three times, and then three second-direction redistributed conductor layers can be fabricated on the back side of the chip to be packaged by repeating the second-direction wiring three times. Thus, a total of six redistributed conductor layers are formed on the top and bottom vertical surfaces of the chip to be packaged, constituting a double-sided three-dimensional interconnect network.

[0051] In the process of constructing the first direction redistribution conductor layer and the second direction redistribution conductor layer, some of the first direction redistribution conductor layers and the second direction redistribution conductor layers are electrically interconnected between the layers through a vertical conductive interconnection structure. That is, the first direction redistribution conductor layer and the second direction redistribution conductor layer are directly electrically connected through the vertical conductive interconnection structure, without occupying the pins of the chip to be packaged, thus paving the way for the subsequent pin lead-out of passive components.

[0052] Step S104: Form pads on the first direction redistribution conductor layer and / or the second direction redistribution conductor layer, and solder at least one passive component on the pads to obtain the target package panel.

[0053] After completing the double-sided multilayer redistributed conductor layer, specific pad areas are patterned on the outermost first-direction redistributed conductor layer and / or second-direction redistributed conductor layer of the double-sided wiring structure obtained in step S103 by photolithography and etching processes to form pads for surface mounting.

[0054] Then, using high-precision surface mount technology, multiple passive components, including resistors, capacitors, and diodes, are mounted and soldered onto their corresponding pads. Utilizing a vertical conductive interconnect structure, some passive components requiring external electrical connections (such as those needing separate grounding or input / output) can directly establish electrical connections without passing through the chip to be packaged. At this point, all the chips to be packaged are electrically integrated with the passive components, resulting in the target packaged panel.

[0055] After completing step S104, the target package panel obtained in step S104 can be molded as a whole. Specifically, epoxy molding compound can be used to wrap all the chips to be packaged, redistribute the conductor layer, solder pads and passive components to form the final protective shell.

[0056] Subsequently, the molded target package panel is ground to expose the leads, and the surface of the leads is treated with chemical tin plating to improve solderability. After laser marking the molded target package panel, based on preset cutting parameters, the molded target package panel is cut and separated along the boundary using mechanical cutting or laser cutting technology to obtain multiple independent package modules.

[0057] Preset cutting parameters may include cutting width, cutting depth, feed speed, and boundary coordinates of each packaging module. A high-precision vision recognition system is used to automatically identify and locate alignment marks or laser markings on the target packaging panel to compensate for potential positional offsets introduced by molding and previous processes, ensuring precise alignment of the cutting path and boundary coordinates. In one optional implementation, such as... Figures 4a-4c As shown, multiple finished packaging modules with dimensions of 5.0mm × 3.8mm × 1.9mm were obtained by dividing the product using preset cutting parameters.

[0058] After cutting, the edges of the packaging modules can be cleaned or trimmed if necessary to remove cutting debris and burrs. Finally, the target packaging panel is divided into multiple physically independent, fully functional packaging modules. Each individual packaging module undergoes electrical testing and visual inspection to select qualified finished products, which are then packaged.

[0059] The panel-level packaging method with multi-layer redistribution provided in this application integrates multiple chips to be packaged and several passive components within a compact package through double-sided multi-layer redistribution conductor layers, forming a complete functional circuit module, which greatly saves space. At the same time, based on panel-level batch processing and pre-embedded interconnect structure, alignment accuracy and packaging yield are improved, and costs are reduced.

[0060] Secondly, embodiments of this application also provide a panel-level packaging device with a multi-layer redistribution layer, such as... Figure 5 As shown, the device includes: The positioning and arrangement module 201 is used to place at least one chip to be packaged on a preset reference carrier and to set a vertical conductive interconnect structure at a preset position on the reference carrier to form an embedded component assembly. The first redistribution module 202 is used to perform first-direction wiring on the first surface of the embedded component assembly, including sequentially performing lamination, photolithography and redistribution processes to construct at least two first-direction redistribution conductor layers on the first surface of the embedded component assembly to obtain a single-sided wiring structure. The second rewiring module 203 is used to perform second-direction wiring on the second surface of the single-sided wiring structure, including sequentially repeating the processes of lamination, photolithography and redistribution of conductor layers, so as to construct at least two second-direction redistribution conductor layers on the second surface of the single-sided wiring structure to obtain a double-sided wiring structure. Among them, some of the first-direction redistributed conductor layers and the second-direction redistributed conductor layers achieve interlayer electrical interconnection through a vertical conductive interconnection structure; The welding module 204 is used to form pads on the conductor layer in the first direction and / or the conductor layer in the second direction, and to weld at least one passive component on the pads to obtain the target package panel.

[0061] Since the multi-layer redistribution panel-level packaging device described in this embodiment is an electronic device used to implement the multi-layer redistribution panel-level packaging method in this embodiment of the invention, those skilled in the art can understand the specific implementation methods and various variations of the electronic device in this embodiment based on the multi-layer redistribution panel-level packaging method described in this embodiment of the invention. Therefore, how the electronic device implements the method in this embodiment of the invention will not be described in detail here. Any electronic device used by those skilled in the art to implement the multi-layer redistribution panel-level packaging method in this embodiment of the invention falls within the scope of protection of this invention.

[0062] Thirdly, embodiments of this application also provide a panel-level packaging structure with multiple redistribution layers, such as... Figure 6 As shown, the structure includes: At least one chip to be packaged 301, and a vertical conductive interconnect structure 302 disposed at a predetermined position around the chip to be packaged 301; A first-direction redistribution conductor layer 303 is disposed on the first surface of the chip to be packaged 301, and the first-direction redistribution conductor layer 303 includes at least two layers. A second-direction redistributed conductor layer 304 is disposed on the second surface of the chip to be packaged 301, and the second-direction redistributed conductor layer 304 includes at least two layers. Among them, some of the first direction redistributed conductor layers and the second direction redistributed conductor layers are electrically interconnected between layers through a vertical conductive interconnection structure 302; Pad 305 is disposed on the outermost first direction redistributed conductor layer 303 and / or second direction redistributed conductor layer 304; And at least one passive component 306, soldered onto pad 305.

[0063] The panel-level packaging structure of the multi-layer redistribution layer is made by any of the embodiments of the first aspect described above.

[0064] In summary, the multi-layer redistribution panel-level packaging structure, packaging method, and packaging apparatus provided by the embodiments of the present invention, by setting a vertical conductive interconnect structure and constructing multiple redistribution conductor layers on both sides of the chip, form a double-sided three-dimensional interconnect network. This allows multiple functional chips and passive components to be integrated into a compact packaging module. Based on panel-level batch processing, it significantly saves packaging space, improves alignment accuracy and packaging yield, and reduces manufacturing costs. For example, in one embodiment, a complete dual-channel DC / DC power supply module can be constructed on a micro-module with dimensions of only 5.0mm × 3.8mm × 1.9mm.

[0065] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0066] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0067] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0069] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0070] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0071] The above are merely specific embodiments of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A panel-level packaging method for multi-layer rewiring, characterized in that, The method includes: At least one chip to be packaged is placed on a preset reference carrier, and a vertical conductive interconnect structure is set at a preset position on the reference carrier to form an embedded component assembly. The first surface of the embedded component assembly is wired in a first direction, including the sequential repeated execution of lamination, photolithography and redistribution processes, to construct at least two first-direction redistribution conductor layers on the first surface to obtain a single-sided wiring structure. The second surface of the single-sided wiring structure is wired in a second direction, including the sequential repeated execution of lamination, photolithography and redistribution processes, to construct at least two second-direction redistribution conductor layers on the second surface to obtain a double-sided wiring structure. Among them, a portion of the first-direction redistributed conductor layer and the second-direction redistributed conductor layer are electrically interconnected between layers through the vertical conductive interconnection structure; Pads are formed on the conductor layer in the first direction and / or the conductor layer in the second direction, and at least one passive component is soldered on the pads to obtain the target package panel.

2. The panel-level packaging method for multi-layer rewiring according to claim 1, characterized in that, After obtaining the target packaged panel, the process further includes: The target packaging panel is encapsulated as a whole, and then divided into multiple independent packaging modules based on preset cutting parameters.

3. The panel-level packaging method for multi-layer rewiring according to claim 2, characterized in that, The first direction wiring of the first surface of the embedded component assembly specifically includes: The first surface of the embedded component assembly is subjected to repeated lamination, photolithography and redistribution processes three times to prepare the single-sided wiring structure with three layers of redistributed conductors in the first direction. The second-direction wiring of the second surface of the single-sided wiring structure specifically includes: The second surface of the single-sided wiring structure is subjected to repeated lamination, photolithography and redistribution processes three times to prepare the double-sided wiring structure, which has three layers of redistributed conductors in the first direction and three layers of redistributed conductors in the second direction.

4. The panel-level packaging method for multi-layer rewiring according to claim 3, characterized in that, The vertical conductive interconnect structure includes pre-embedded metal pillars or a metal frame; the reference carrier is a biodegradable adhesive film.

5. The panel-level packaging method for multi-layer rewiring according to claim 4, characterized in that, The processes of lamination, photolithography, and re-laying the conductor layer include: Perform a lamination process to form an insulating dielectric layer; A photolithography process is performed to form a through-hole pattern in the insulating dielectric layer; A redistribution process is performed to form a redistributed conductor layer in the via pattern, the redistributed conductor layer including a first-direction redistributed conductor layer and a second-direction redistributed conductor layer; both the first-direction redistributed conductor layer and the second-direction redistributed conductor layer include redistributed wires and vertical conductive posts.

6. The panel-level packaging method for multi-layer rewiring according to claim 5, characterized in that, After performing the rewiring process, the process also includes: After each layer of the re-laid conductor is formed, a molding process is performed on the re-laid conductor to fill the gaps around the re-laid conductor and provide mechanical protection.

7. The panel-level packaging method for multi-layer rewiring according to claim 6, characterized in that, Each type of chip to be packaged includes at least one, and different types of chips to be packaged have different functions; the types of chips to be packaged include controller type and power type; the passive components include resistors, capacitors or diodes.

8. The panel-level packaging method for multi-layer rewiring according to claim 7, characterized in that, The packaged module is a DC / DC power supply module.

9. A multi-layer rewiring panel-level packaging device, characterized in that, The device includes: A positioning and arrangement module is used to place at least one chip to be packaged on a preset reference carrier and to set a vertical conductive interconnect structure at a preset position on the reference carrier to form an embedded component assembly. The first redistribution module is used to perform first-direction wiring on the first surface of the embedded component assembly, including sequentially performing lamination, photolithography and redistribution processes to construct at least two first-direction redistribution conductor layers on the first surface of the embedded component assembly to obtain a single-sided wiring structure. The second rewiring module is used to perform second-direction wiring on the second surface of the single-sided wiring structure, including sequentially repeating the processes of lamination, photolithography and redistribution of conductor layers to construct at least two second-direction redistribution conductor layers on the second surface of the single-sided wiring structure to obtain a double-sided wiring structure. Among them, a portion of the first-direction redistributed conductor layer and the second-direction redistributed conductor layer are electrically interconnected between layers through the vertical conductive interconnection structure; A soldering module is used to form pads on a conductor layer redistributed in the first direction and / or a conductor layer redistributed in the second direction, and to solder at least one passive component on the pads to obtain a target package panel.

10. A multi-layer rewiring panel-level packaging structure, characterized in that, include: At least one chip to be packaged, and a vertical conductive interconnect structure disposed at a predetermined position around the chip to be packaged; A first-direction redistributed conductor layer is disposed on the first surface of the chip to be packaged, and the first-direction redistributed conductor layer includes at least two layers. A second-direction redistributed conductor layer is disposed on the second surface of the chip to be packaged, and the second-direction redistributed conductor layer includes at least two layers. Among them, a portion of the first-direction redistributed conductor layer and the second-direction redistributed conductor layer are electrically interconnected between layers through the vertical conductive interconnection structure; The pads are disposed on the outermost first-direction redistributed conductor layer and / or the second-direction redistributed conductor layer; And at least one passive component, soldered onto the pad.

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