3D packaging structure for HBM and GPU and packaging process thereof

Abstract

The application belongs to the field of integrated circuit packaging, and discloses a 3D packaging structure for HBM and GPU and a packaging process thereof, wherein the 3D packaging structure comprises a glass substrate, a plurality of silicon carbide small substrates are packaged on the glass substrate, longitudinal through holes are formed in the silicon carbide small substrates, GPU chips and HBM chips are packaged on the silicon carbide small substrates, single silicon carbide small substrate metal pads are respectively welded with part of Bump bumps of the GPU chips and the HBM chips, the GPU chips and the HBM chips are transversely connected through the silicon carbide small substrates, and part of the Bump bumps of the GPU chips and the HBM chips are welded with metal pads of the glass substrate to realize longitudinal connection; the application effectively improves heat dissipation and avoids the warping problem of the substrate caused by large-area thermal stress by using the ultra-thin silicon carbide small substrate and the large-size glass substrate as an interlayer.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit packaging technology, specifically relating to a 3D packaging structure and packaging process for HBM and GPU. Background Technology

[0002] As the semiconductor industry enters the post-Moore era, advanced packaging technologies centered on heterogeneous integration and 3D packaging have become key drivers for the continued improvement of chip performance. Among them, 3D packaging technology, with its advantages of enabling high-density integration of multiple chips, shortening interconnection paths, and improving signal transmission efficiency, has been widely used in high-performance computing, artificial intelligence, data centers, and other fields. In particular, in the integrated packaging of GPUs and HBMs, it is a core technology path to solve the bandwidth bottleneck of high-performance computing.

[0003] In the 3D packaging structure of GPUs and HBMs, the interposer, as a core component connecting multi-chip GPUs, multi-chip HBMs, and the underlying polymer substrate, plays a crucial role in lateral and vertical signal interconnection and heat conduction. Its performance directly determines the computing efficiency, heat dissipation, and structural reliability of the entire packaging system. Currently, the mainstream interposer solution in the industry uses silicon-based materials and relies on the mature through-silicon via (TSV) processing technology to achieve interconnection and integration between chips. This solution has a certain degree of technical maturity in small and medium-sized interposer applications. However, with the continuous increase in the demand for chip integration and bandwidth in high-performance computing, it is necessary to expand the interposer size to 2000-10000μm. 2 At this point, the inherent defects of silicon-based interposers gradually become apparent, becoming a core bottleneck restricting technological development.

[0004] On the one hand, silicon-based materials have low thermal conductivity, only 150~160 W / m·k, which is insufficient to meet the heat dissipation requirements of high-power GPU chips. As GPU power consumption continues to rise, the heat dissipation bottleneck of silicon-based interposers will lead to increased chip operating temperature and reduced performance, seriously affecting the long-term reliability of the packaging system. On the other hand, during the large-area fabrication process, silicon-based interposers are prone to substrate warping and deformation due to thermal stress, which can lead to chip interconnect failure. Therefore, their size is strictly limited to below 2000 mm², which cannot meet the application requirements of large-size interposers and is difficult to adapt to GPU and HBM multi-chip packaging scenarios with higher integration.

[0005] To address the heat dissipation and size limitations of silicon-based interposers, the industry has begun exploring the use of silicon carbide (SiC) materials to replace silicon-based materials in interposer fabrication. SiC boasts a thermal conductivity more than twice that of silicon (some SiC materials even reach 490 W / m·K, more than three times that of silicon), exhibiting excellent heat dissipation performance. Furthermore, its coefficient of thermal expansion closely matches that of the chip material, effectively mitigating warping caused by thermal stress, making it an ideal interposer material choice. However, the processing technology for through-hole (TSV) vias on SiC substrates is extremely challenging. Limited by current dry etching equipment, when the TSV size is controlled at around 5-8 micrometers, the thickness of the SiC substrate can only be 8-10 times the TSV size; otherwise, the precision requirements for TSV processing cannot be met. Simultaneously, large-size SiC substrates are highly susceptible to breakage during thinning and polishing, hindering large-scale production and application, thus limiting the use of SiC materials in large-size interposers. Summary of the Invention

[0006] To address the shortcomings mentioned in the background art, the present invention aims to provide a 3D packaging structure and packaging process for HBM and GPU. By combining an ultra-thin silicon carbide small substrate with a large-size glass substrate as an interlayer, heat dissipation is effectively improved and substrate warping caused by large-area thermal stress is avoided. At the same time, it breaks through the bottleneck of SiC processing technology, improves process feasibility and scalability, realizes the expansion of large-size interlayer, and meets the high integration packaging requirements.

[0007] The objective of this invention can be achieved through the following technical solutions: A 3D packaging structure for HBM and GPU includes a glass substrate, on which multiple silicon carbide (SiC) micro-substrates are packaged. Vertically penetrating vias are formed within the SiC micro-substrates. A GPU chip and an HBM chip are packaged on the SiC micro-substrates. Metal pads on individual SiC micro-substrates are soldered to portions of the bumps of the GPU chip and the HBM chip, respectively. The GPU chip and the HBM chip are laterally connected via the SiC micro-substrates, while simultaneously, portions of the bumps of the GPU chip and the HBM chip are soldered to the metal pads on the glass substrate, achieving a vertical connection.

[0008] More preferably, an organic substrate is mounted on the bottom of the glass substrate, and the organic substrate is connected to an external circuit.

[0009] More preferably, the glass substrate is a borosilicate glass substrate, and the size of the glass substrate is 2000~10000 mm. 2 .

[0010] More preferably, the thickness of the silicon carbide substrate is 50~80μm.

[0011] More preferably, the through-hole diameter of the silicon carbide small substrate is 5~8μm.

[0012] A packaging process for a 3D packaging structure of HBM and GPU includes the following steps: S1. A bridging metal line connecting the GPU and HBM chips is fabricated on the front side of the silicon carbide substrate. 3 to 6 layers of metal interconnects can be fabricated to form a metal pad connecting the HBM and GPU chips. A dry etching process is used to form blind vias with a diameter of 5 to 8 μm and a depth of 30 to 50 μm. S2. A temporary bonding process is used to bond the front side of the silicon carbide substrate to the glass substrate, and the back side is ground to the thickness of the blind via depth to open the blind via and to create back bumps. S3. The back side of the silicon carbide substrate is attached to the cutting mold frame, then laser debonding is used to detach it from the glass carrier, and the bonding adhesive is cleaned off. The silicon carbide substrate is then cut into multiple small silicon carbide substrates using a diamond dicing wheel or laser dicing process. S4. Bond the bumps on the back of the silicon carbide small substrate to a large glass substrate with pre-placed multilayer metal interconnects and metal pads. Flip and bond the bumps on the front of the pre-fabricated GPU and HBM chips to the pads on the front of the SiC chip. At the same time, bond the remaining bumps to the top metal pads of the glass substrate. Then heat the substrate to connect and fix some areas of the GPU and HBM to the silicon carbide small substrate and some areas to the large glass substrate, thus completing the multilayer 3D packaging structure.

[0013] The beneficial effects of this invention are: This architecture uses silicon carbide chiplets as the lateral connection components between the GPU and HBM, making full use of the excellent heat dissipation performance of SiC material, which has a thermal conductivity more than twice that of silicon-based materials. This efficiently conducts the heat generated during the operation of high-power GPUs, avoiding problems such as performance throttling and accelerated aging caused by excessively high chip temperatures. At the same time, the thermal expansion coefficient of SiC material is highly compatible with that of the chip material, which can effectively alleviate thermal stress, reduce the risk of substrate warping and deformation, further improve the long-term reliability of the packaging system, and meet the heat dissipation requirements of kilowatt-level high-power GPUs.

[0014] This invention breaks through the bottleneck of SiC processing technology, improves process feasibility and scalability, and uses small SiC chips to replace large-size SiC substrates. The thickness of the small chips is controlled at 30-50 micrometers, which avoids the problem of easy breakage during the thinning and grinding of large-size SiC substrates and greatly reduces the processing difficulty of SiC through-hole (TSV). It is compatible with the current dry etching equipment process requirements, does not require major modification to existing processing equipment, reduces production investment, and realizes the large-scale application of SiC materials.

[0015] This invention enables the expansion of large-size interposers to meet the requirements of high-integration packaging. It uses a mature large-size borosilicate glass substrate as the second interposer substrate, and its size can stably cover 2000-10000μm. 2 This range, exceeding the traditional silicon-based interposer size limitation of 2000μm, breaks through this limitation. 2 The following bottlenecks; at the same time, borosilicate glass substrates have excellent electrical insulation and thermomechanical properties, which can effectively solve the warping problem of large-size substrates, adapt to the high-density integration requirements of multi-chip GPUs and multi-chip HBMs, and provide hardware support for improving high-performance computing bandwidth.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the 3D packaging structure used for HBM and GPU in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the packaging process step S1 of the 3D packaging structure for HBM and GPU in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the packaging process step S2 of the 3D packaging structure for HBM and GPU in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the packaging process step S3 of the 3D packaging structure for HBM and GPU in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of step S4 in the 3D packaging process of HBM and GPU in Embodiment 1 of the present invention.

[0019] In the figure: 1-Silicon carbide substrate, 2-Silicon carbide substrate metal pad, 3-Silicon carbide substrate through hole, 4-Glass carrier, 5-Silicon carbide substrate bump, 6-Cutting mold frame, 7-Silicon carbide small substrate, 8-Glass substrate, 9-GPU chip, 10-HBM chip, 11-Organic substrate. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be understood that the terms "opening", "upper", "lower", "thickness", "top", "middle", "length", "inner", "around", etc., which indicate orientation or positional relationship, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this invention.

[0022] like Figure 1 As shown, a 3D packaging structure for HBM and GPU includes a large-size glass substrate 8, which is a borosilicate glass substrate. An organic substrate 11 is mounted on the bottom of the glass substrate 8. Multiple small-size silicon carbide substrates 7 are packaged on the glass substrate 8. The silicon carbide substrates 7 have longitudinally penetrating through holes with a diameter of 5~8μm. A GPU chip 9 and an HBM chip 10 are packaged on the silicon carbide substrates 7. The metal pads of each silicon carbide substrate 7 are respectively soldered to a portion of the bumps of the GPU chip 9 and the HBM chip 10. The GPU chip 9 and the HBM chip 10 are laterally connected through the silicon carbide substrates 7. At the same time, the bumps of the GPU chip 9 and the HBM chip 10 are soldered to the metal pads of the silicon substrate 8 to achieve a longitudinal connection. like Figures 2-5 As shown, the packaging process for the 3D packaging structure used in HBM and GPU includes the following steps: S1. A bridging metal line connecting the GPU and HBM chips is fabricated on the front side of the silicon carbide substrate. 3 to 6 layers of metal interconnects can be fabricated to form a metal pad connecting the HBM and GPU chips. A dry etching process is used to form blind vias with a diameter of 5 to 8 μm and a depth of 30 to 50 μm. S2. A temporary bonding process is used to bond the front side of the silicon carbide substrate to the glass substrate, and the back side is ground to the thickness of the blind via depth to open the blind via and to create back bumps. S3. The back side of the silicon carbide substrate is attached to the cutting mold frame, then laser debonding is used to detach it from the glass carrier, and the bonding adhesive is cleaned off. The silicon carbide substrate is then cut into multiple small silicon carbide substrates using a diamond dicing wheel or laser dicing process. S4. Bond the bumps on the back of the silicon carbide small substrate to a large glass substrate with pre-placed multilayer metal interconnects and metal pads. Flip and bond the bumps on the front of the pre-fabricated GPU and HBM chips to the pads on the front of the SiC chip. At the same time, bond the remaining bumps to the top metal pads of the glass substrate. Then heat the substrate to connect and fix some areas of the GPU and HBM to the silicon carbide small substrate and some areas to the large glass substrate, thus completing the multilayer 3D packaging structure.

[0023] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0024] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A 3D packaging structure for HBM and GPU, characterized in that, The device includes a glass substrate on which multiple silicon carbide sub-substrates are encapsulated. Each silicon carbide sub-substrates has a longitudinally penetrating through-hole. A GPU chip and an HBM chip are encapsulated on the silicon carbide sub-substrates. A metal pad on each silicon carbide sub-substrates is soldered to a portion of the bump on the GPU chip and the HBM chip, respectively. The GPU chip and the HBM chip are laterally connected through the silicon carbide sub-substrates, while simultaneously, a portion of the bump on the GPU chip and the HBM chip is soldered to the metal pad on the glass substrate, achieving a longitudinal connection.

2. The 3D packaging structure for HBM and GPU according to claim 1, characterized in that, An organic substrate is mounted on the bottom of the glass substrate, and the organic substrate is connected to an external circuit.

3. The 3D packaging structure for HBM and GPU according to claim 1, characterized in that, The glass substrate is a borosilicate glass substrate, and the size of the glass substrate is 2000~10000 mm. 2 .

4. The 3D packaging structure for HBM and GPU according to claim 1, characterized in that, The thickness of the silicon carbide substrate is 50~80μm.

5. The 3D packaging structure for HBM and GPU according to claim 1, characterized in that, The through-hole diameter of the silicon carbide small substrate is 5~8μm.

6. The packaging process for the 3D packaging structure of HBM and GPU according to any one of claims 1 to 6, characterized in that, Includes the following steps: S1. A bridging metal line connecting the GPU and HBM chips is fabricated on the front side of the silicon carbide substrate. 3 to 6 layers of metal interconnects can be fabricated to form a metal pad connecting the HBM and GPU chips. A dry etching process is used to form blind vias with a diameter of 5 to 8 μm and a depth of 30 to 50 μm. S2. A temporary bonding process is used to bond the front side of the silicon carbide substrate to the glass substrate, and the back side is ground to the thickness of the blind via depth to open the blind via and to create back bumps. S3. The back side of the silicon carbide substrate is attached to the cutting mold frame, then laser debonding is used to detach it from the glass carrier, and the bonding adhesive is cleaned off. The silicon carbide substrate is then cut into multiple small silicon carbide substrates using a diamond dicing wheel or laser dicing process. S4. Bond the bumps on the back of the silicon carbide small substrate to a large glass substrate with pre-placed multilayer metal interconnects and metal pads. Flip and bond the bumps on the front of the pre-fabricated GPU and HBM chips to the pads on the front of the SiC chip. At the same time, bond the remaining bumps to the top metal pads of the glass substrate. Then heat the substrate to connect and fix some areas of the GPU and HBM to the silicon carbide small substrate and some areas to the large glass substrate, thus completing the multilayer 3D packaging structure.

7. The 3D packaging structure process of HBM and GPU according to claim 6, characterized in that, In step S1, the silicon carbide substrate is dry-etched with blind holes. The blind holes have a diameter of 5~8μm and a depth of 30~50μm.

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