Semiconductor device package

Abstract

A semiconductor device package includes a first substrate, a second substrate disposed over the first substrate, and a surface mount device (SMD) component disposed between the first substrate and the second substrate. The SMD component includes a plurality of connection electrodes that electrically connect the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from one another.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the invention patent application filed on September 6, 2019, with application number "201910843218.6" and title "Semiconductor Device Packaging". Technical Field

[0003] This disclosure relates to semiconductor device packaging, and to semiconductor device packages comprising one or more surface mount device (SMD) components, said components being configured as support components between two substrates and as interconnect components electrically connecting the substrates. Background Technology

[0004] Stacked semiconductor device packages, such as package-on-package (POP) or package-in-package (PIP), may include two substrates stacked on top of each other, and electronic components, such as ICs, that can be mounted on the substrates. For example, a molding material encapsulation layer is disposed between the substrates to encapsulate the electronic components, and silicon interposers are disposed between the substrates to electrically connect the electronic components mounted on the substrates. However, the silicon interposers will impede the molding flow of the molding material, thus reducing the yield and reliability of the semiconductor device package. Summary of the Invention

[0005] In some embodiments, a semiconductor device package includes a first substrate, a second substrate disposed above the first substrate, and a surface mount device (SMD) assembly disposed between the first substrate and the second substrate. The SMD assembly includes a plurality of connection electrodes that electrically connect the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other.

[0006] In some embodiments, a semiconductor device package includes a first substrate, a second substrate disposed above the first substrate, a first conductive pad disposed on the first substrate, a second conductive pad disposed on the second substrate, and a surface mount device (SMD) assembly disposed between the first substrate and the second substrate. The SMD assembly includes at least one connection electrode that electrically connects the first conductive pad to the second conductive pad. An outer edge of the first conductive pad protrudes beyond a corresponding outer edge of the connection electrode, and an outer edge of the second conductive pad is substantially aligned with or recessed from the corresponding outer edge of the connection electrode.

[0007] In some embodiments, a semiconductor device package includes a first substrate, a second substrate disposed above the first substrate, a first conductive pad disposed on the first substrate, a second conductive pad disposed on the second substrate, and a surface mount device (SMD) assembly disposed between the first substrate and the second substrate and electrically connecting the first conductive pad to the second conductive pad. The SMD assembly includes an insulating substrate and at least one connection electrode. The insulating substrate includes a first outer surface facing the first substrate, a second outer surface facing the second substrate, and an outer edge connected to the first and second outer surfaces. The connection electrode is disposed on the insulating substrate. The connection electrode includes a main portion disposed on the outer edge of the insulating substrate, a first extension extending to the first outer surface of the insulating substrate, and a second extension extending to the second outer surface of the insulating substrate. The length of the first extension of the connection electrode is different from the length of the second extension of the connection electrode. Attached Figure Description

[0008] When read in conjunction with the accompanying drawings, aspects of some embodiments of this disclosure will be readily understood from the following detailed description. Various structures may not be drawn to scale, and the dimensions of various structures may be arbitrarily increased or decreased for clarity of explanation.

[0009] Figure 1 This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0010] Figure 1A yes Figure 1 An enlarged cross-sectional view of region A of the semiconductor device package.

[0011] Figure 1B yes Figure 1 An enlarged top view of region A of the semiconductor device package.

[0012] Figure 2A This is a top view of a semiconductor device package according to some embodiments of the present disclosure.

[0013] Figure 2B This is a top view of a semiconductor device package according to some embodiments of the present disclosure.

[0014] Figure 3A This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0015] Figure 3B This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0016] Figure 3CThis is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0017] Figure 4A This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure.

[0018] Figure 4B This is a cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed or arranged in direct contact, and may also include embodiments in which additional features are formed or arranged between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for the purpose of simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0020] As used herein, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” and “right” are used to describe, for ease of description, the relationship of one element or feature to another element or feature illustrated in the figures. Apart from the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatially related descriptive terms used herein can be interpreted in the same way. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to said other element, or there may be an intermediate element present.

[0021] This disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes two stacked substrates and a surface mount device (SMD) assembly disposed therebetween. The SMD assembly is configured as a support assembly for maintaining a gap between the two stacked substrates and also as an interconnect assembly for electrically connecting the two stacked substrates to electronic components disposed on the two stacked substrates. The SMD assembly may include a plurality of connection electrodes that electrically connect one substrate to the other. Each of the connection electrodes allows a corresponding electrical terminal of a first substrate to be electrically connected in a vertical direction to a corresponding electrical terminal of a second substrate, and the connection electrodes are horizontally disconnected from each other. The SMD assembly may include a plurality of discretely arranged components that do not obstruct the flow of molding material. The SMD assembly may include dummy passive components in which the functionality of passive components is disabled.

[0022] Figure 1 This is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. Figure 1A yes Figure 1 An enlarged cross-sectional view of region A of semiconductor device package 1, and Figure 1B yes Figure 1 An enlarged top view of region A of the semiconductor device package 1. This view is intended to highlight the features of the semiconductor device package 1. Figure 1B Some components are omitted. For example... Figure 1 , Figure 1A and Figure 1BAs shown, the semiconductor device package 1 includes a first substrate 10, a second substrate 20, and at least one surface mount device (SMD) assembly 30. The second substrate 20 is disposed above and spaced apart from the first substrate 10. The first substrate 10 includes a first surface 101, and the second substrate 20 includes a second surface 201 facing the first surface 101 and spaced apart from it. The first substrate 10 may include, for example, a packaging substrate of a circuit board. By way of example, the first substrate 10 may include one or more dielectric layers and one or more circuit layers stacked on top of each other. The material of the dielectric layer may include, but is not limited to, resins such as epoxy resin, bismaleimide-triazine (BT), glass fiber such as FR-4, semiconductor, ceramic, glass, plastic, or other suitable materials. The circuit layer may include redistribution layers (RDL), vias, conductive traces, conductive lines, etc. The circuit layer may be disposed in, on, or between adjacent dielectric layers. The material of the circuit layer may include, but is not limited to, metals such as copper (Cu). In some embodiments, the circuit layer in the first substrate 10 may comprise a substrate-level circuit layer, which is a low-density circuit layer with a wide linewidth / spacing (L / S). For example, the L / S of the circuit layer may be equal to or greater than about 10 μm / about 10 μm. In some other embodiments, the circuit layer in the first substrate 10 may comprise a substrate-level circuit layer, which may include a raised substrate, and the substrate-level circuit layer is a high-density circuit layer with a narrower L / S. For example, the L / S of the circuit layer may be less than about 10 μm / about 10 μm.

[0023] In some embodiments, the first substrate 10 may additionally include a plurality of first conductive pads 12 disposed on a dielectric layer. The first conductive pads 12 may be disposed near, adjacent to, or embedded in and exposed by the dielectric layer, and configured to receive electronic components 16 and / or SMD components 30. The first conductive pads 12 may be electrically connected to circuit layers of the first substrate 10. The material of the first conductive pads 12 may include, for example, but is not limited to, metals such as copper (Cu). In some embodiments, the first conductive pads 12 may include an under-bump metallurgy (UBM) layer. In some embodiments, a passivation layer may be disposed on the first substrate 10, and the passivation layer may at least partially expose the first conductive pads 12.

[0024] The second substrate 20 may comprise, for example, a packaging substrate for a circuit board. By way of example, the second substrate 20 may comprise one or more dielectric layers and one or more circuit layers. In some embodiments, the circuit layers in the second substrate 20 may comprise substrate-level circuit layers (e.g., low-density circuit layers) or bump-level circuit layers (e.g., high-density circuit layers). In some embodiments, the second substrate 20 may additionally comprise a plurality of second conductive pads 22 disposed on the dielectric layers. The second conductive pads 22 may be disposed near, adjacent to, or embedded in and exposed by the dielectric layers, and configured to receive electronic components 26 and / or SMD components 30. The second conductive pads 22 may be electrically connected to the circuit layers of the second substrate 20. The materials of the dielectric layers, circuit layers, and second conductive pads 22 of the second substrate 20 may be similar to the materials of the dielectric layers, circuit layers, and first conductive pads 12 of the first substrate 10. In some embodiments, the second conductive pads 22 may comprise UBM. In some embodiments, a passivation layer may be disposed on the second substrate 20, and the passivation layer may at least partially expose the second conductive pads 22.

[0025] The semiconductor device package 1 may further include one or more first electronic components 16 disposed on a first substrate 10, and one or more second electronic components 26 disposed on a second substrate 20. The first electronic components 16 may be disposed on a first surface 101 and / or a third surface 102 opposite to the first surface 101 of the first substrate 10. The second electronic components 26 may be disposed on a second surface 201 and / or a fourth surface 202 opposite to the second surface 201 of the second substrate 20. In some embodiments, the first electronic components 16 may include active electronic components 16A, such as a system-on-a-chip (SOC) component, a memory component, etc., and / or passive electronic components 16B, such as a resistor, capacitor, or inductor. The first electronic components 16 may be electrically connected to a first conductive pad 12 via conductive structures 16X, such as solder bumps or solder paste. The first electronic components 16 may be electrically connected to each other via the first substrate 10. In some embodiments, the second electronic component 26 may include an active electronic component 26A, such as a SOC component, a memory component, etc., and / or a passive electronic component 26B, such as a resistor, capacitor, or inductor. The second electronic component 26 may be electrically connected to the second conductive pad 22 via conductive structures 26X, such as solder bumps or solder paste. The second electronic component 26 may be electrically connected to each other via the second substrate 20. The first electronic component 16 and the second electronic component 26 may be electrically connected to each other via the first substrate 10, the SMD component 30, and the second substrate 20.

[0026] An SMD assembly 30 is disposed between a first substrate 10 and a second substrate 20. The SMD assembly 30 includes a plurality of connection electrodes 34 that electrically connect the first substrate 10 to the second substrate 20, and the plurality of connection electrodes 34 are electrically disconnected from each other. Each of the connection electrodes 34 is used to provide an independent electrical connection path between the first substrate 10 and the second substrate 20 in a vertical direction, while no electrical connection is formed between the connection electrodes 34 in a horizontal direction. In some embodiments, the SMD assembly 30 may additionally include an insulating substrate 32 having an outer surface 32S covered by the plurality of connection electrodes 34. The outer surface 32S of the insulating substrate 32 defines an internal volume 32V, and the connection electrodes 34 are electrically disconnected from each other inside and outside the internal volume 32V. In some embodiments, when an AC voltage is applied to the connection electrodes 34, the connection electrodes 34 are electrically disconnected from each other inside the internal volume 32V. In some embodiments, adjacent connection electrodes 34 may be parasiticly coupled outside the internal volume 32V of the insulating substrate 32. The SMD component 30 is configured as a support component for maintaining a gap between the first substrate 10 and the second substrate 20. The SMD component 30 is also configured as an interconnect component for interconnecting the first substrate 10 and the second substrate 20. In some embodiments, the SMD component 30 includes, for example... Figure 1A and Figure 1B The two connection electrodes 34 shown are disposed on opposite sides of the insulating substrate 32, and the SMD assembly 30 can be configured as a two-terminal interconnect assembly. The number of connection electrodes 34 can be modified to implement multi-terminal interconnect requirements. Different SMD assemblies 30 can have different numbers of connection electrodes 34 to meet interconnection requirements in different locations of the semiconductor device package 1. Figure 1 For example, two SMD components 30 can be drawn, but the number of SMD components 30 can be modified based on the I / O connection between the first substrate 10 and the second substrate 20.

[0027] In some embodiments, the outer surface 32S of the insulating substrate 32 may include a first outer surface 32S1 facing the first substrate 10, a second outer surface 32S2 facing the second substrate 20, and an outer edge 32S3 connected to the first outer surface 32S1 and the second outer surface 32S2. Each connecting electrode 34 may include a main portion 340 disposed on the outer edge 32S3 of the insulating substrate 32, a first extension portion 341 extending to the first outer surface 32S1 of the insulating substrate 32, and a second extension portion 342 extending to the second outer surface 32S2 of the insulating substrate 32.

[0028] The semiconductor device package 1 may additionally include a plurality of first solder materials 42 disposed on a first substrate 10 and a plurality of second solder materials 44 disposed on a second substrate 20. Each first solder material 42 may partially cover a corresponding connection electrode 34, such as a portion of the main portion 340 and a portion of the first extension portion 341 of the corresponding connection electrode 34, and facilitates bonding the corresponding connection electrode 34 to a corresponding first conductive pad 12. Each second solder material 44 may partially cover a corresponding connection electrode 34, such as a portion of the main portion 340 and a portion of the second extension portion 342 of the corresponding connection electrode 34, and facilitates bonding the corresponding connection electrode 34 to a corresponding second conductive pad 22. In some embodiments, the outer edge 12E of each first conductive pad 12 protrudes beyond the corresponding outer edge 34E of the connection electrode 34, and the outer edge 22E of each second conductive pad 22 protrudes beyond the corresponding outer edge 34E of the connection electrode 34. In some embodiments, the first solder materials 42 and the second solder materials 44 are spaced apart from each other such that the first solder materials 42 and the second solder materials 44 do not fuse. Therefore, the amounts of the first solder material 42 and the second solder material 44 can be precisely controlled, thereby minimizing the risk of open circuits and short circuits, increasing tolerance to warpage, and improving yield and reliability. The materials of the first solder material 42 and the second solder material 44 may include, for example, but not limited to, tin (Sn), lead (Pb), silver (Ag), copper (Cu), or alloys thereof. In some embodiments, the materials of the first solder material 42 and the second solder material 44 may contain the same material or different materials.

[0029] The SMD component 30 may be a pre-formed component, formed prior to bonding to the first substrate 10 and / or the second substrate 20. In some embodiments, the SMD component 30 may include discrete components and be disposed between first electronic components 16, between second electronic components 26, or between first electronic components 16 and second electronic components 26. The SMD component 30 may include dummy passive components in which the function of passive components is disabled. By way of example, the SMD component 30 may include dummy resistors with no or negligible resistor function. The dummy resistor may have two or more connection electrodes 34 that are electrically disconnected from each other and disposed on an insulating substrate 32, and no resistive wires, such as resistive films, are disposed in the insulating substrate 32. In some embodiments, the SMD component 30 may include dummy capacitors with no or negligible capacitor function. The dummy capacitor may have two or more connection electrodes 34 that are electrically disconnected from each other and disposed on an insulating substrate 32, and the dielectric constant of the insulating substrate 32, the overlap area of ​​the connection electrodes 34, and the distance between the connection electrodes 34 are selected in a manner that allows for negligible capacitance. In some embodiments, the SMD component 30 may include a dummy inductor with no inductor function or negligible inductor function. The dummy inductor may have two or more connection electrodes 34 that are electrically disconnected from each other and disposed on an insulating substrate 32, and no coil is disposed in the insulating substrate 32.

[0030] The semiconductor device package 1 may further include an encapsulation layer 50 disposed between the first substrate 10 and the second substrate 20 and encapsulating the SMD component 30, the first electronic component 16, and the second electronic component 26. The SMD component 30 may include discrete components and be individually disposed between the first electronic components 16, between the second electronic components 26, or between the first electronic components 16 and the second electronic components 26. Therefore, the SMD component 30 does not obstruct the molding flow of the molding material of the encapsulation layer 50, and the molding material can flow smoothly into the space between the first substrate 10 and the second substrate 20 from any direction parallel to the first surface 101 and the second surface 201, such as the first direction D1 and the second direction D2.

[0031] In some embodiments, a portion of the first electronic component 16 and the second electronic component 26 are further disposed on the third surface 102 of the first substrate 10 and / or the fourth surface 202 of the second substrate 20, and encapsulation layers 52 and / or 54 may be disposed on the third surface 102 of the first substrate 10 and the fourth surface 202 of the second substrate 20. The materials of the encapsulation layers 50, 52, and 54 may comprise organic molding materials, such as epoxy resin. The materials of the encapsulation layers 50, 52, and 54 may be the same or different. In some embodiments, fillers such as silicon oxide fillers may be added to the encapsulation layers 50, 52, and 54 respectively. In some embodiments, the SMD component 30 is a discrete component and the SMD component 30 may be arranged individually. Therefore, the SMD component 30 does not obstruct the mold flow during the formation of the encapsulation layer 50, and the utilization rate of the substrate area can be increased.

[0032] In some embodiments, the semiconductor device package 1 may additionally include an electrical conductor 18, such as a solder ball, disposed on a third surface 102 of the first substrate 10 and configured to electrically connect the first substrate 10 to another electronic device, such as a printed circuit board (PCB).

[0033] The SMD component 30 is configured as both a support component for maintaining the gap between the first substrate 10 and the second substrate 20, and a multi-terminal interconnect component for interconnecting the first substrate 10 and the second substrate 20. Therefore, the size of the semiconductor device package 1 can be reduced. Compared to semiconductor interconnect interposers, the manufacturing cost and package size of the SMD component 30 can be reduced. Furthermore, the SMD component 30 can be formed using, for example, a surface mount technique (SMT) with a gripping operation. Additionally, the SMD component 30 may include discrete components and be individually disposed between the first electronic components 16, between the second electronic components 26, or between the first electronic components 16 and the second electronic components 26. Therefore, the SMD component 30 does not obstruct the molding flow of the molding material of the encapsulation layer 50, and the molding material can flow smoothly into the space between the first substrate 10 and the second substrate 20 from any direction parallel to the first surface 101 and the second surface 201, such as the first direction D1 and the second direction D2.

[0034] The semiconductor device package disclosed herein is not limited to the embodiments described above, and may be implemented according to other embodiments. For the sake of simplicity of this specification and for ease of comparison between various embodiments of this disclosure, similar components in the following embodiments are labeled with the same reference numerals and may not be described further.

[0035] Figure 2A This is a top view of a semiconductor device package 2A according to some embodiments of the present disclosure. Figure 2AAs shown, the SMD assembly 30 of the semiconductor device package 2A includes a plurality of connection electrodes 34 disposed on two opposite sides of an insulating substrate 32. For example, each of the two opposite sides of the insulating substrate 32 is covered by two or more connection electrodes 34. The SMD assembly 30 of the semiconductor device package 2A provides additional I / O connections between the first substrate 10 and the second substrate 20.

[0036] Figure 2B This is a top view of a semiconductor device package 2B according to some embodiments of the present disclosure. Figure 2B As shown, the SMD assembly 30 of the semiconductor device package 2B includes a plurality of connection electrodes 34 disposed on more than two sides of an insulating substrate 32. For example, each of the four sides of the insulating substrate 32 is covered by one or more connection electrodes 34. The SMD assembly 30 of the semiconductor device package 2B provides additional I / O connections between the first substrate 10 and the second substrate 20.

[0037] Figure 3A This is a cross-sectional view of a semiconductor device package 3A according to some embodiments of the present disclosure. Figure 3A As shown, the SMD assembly 30 may include a connection electrode 34. The connection electrode 34 may be disposed on at least one side of the insulating substrate 32. For example, the connection electrode 34 may be disposed on two or four opposite sides of the insulating substrate 32. The number of first conductive pads 12 and second conductive pads 22 may be the same as or different from the number of connection electrodes 34. The outer edge 12E of the first conductive pad 12 is not aligned with the corresponding outer edge 22E of the second conductive pad 22. By way of example, the outer edge 12E of each first conductive pad 12 protrudes beyond the corresponding outer edge 34E of the connection electrode 34, while the outer edge 22E of the second conductive pad 22 is substantially aligned with or recessed from the corresponding outer edge 34E of the connection electrode 34. The asymmetrical design of the first conductive pads 12 and second conductive pads 22 helps to accurately control the position of the first solder material 42 and the second solder material 44 and prevents the first solder material 42 and the second solder material 44 from fusing together. Therefore, the amount of the first welding material 42 and the amount of the second welding material 44 can be accurately controlled, and the risk of open circuit and short circuit can be reduced.

[0038] Figure 3B This is a cross-sectional view of a semiconductor device package 3B according to some embodiments of the present disclosure. Figure 3BAs shown, the outer edge 12E of each first conductive pad 12 is not aligned with the corresponding outer edge 22E of the second conductive pad 22. By way of example, the outer edge 12E of each first conductive pad 12 protrudes beyond the corresponding outer edge 34E of the connecting electrode 34, while the outer edge 22E of the second conductive pad 22 is substantially aligned with or recessed from the corresponding outer edge 34E of the connecting electrode 34. This asymmetrical design of the first conductive pad 12 and the second conductive pad 22 helps to accurately control the position of the first solder material 42 and the second solder material 44, and prevents the first solder material 42 from fusing with the second solder material 44. Therefore, the amount of the first solder material 42 and the amount of the second solder material 44 can be accurately controlled, and the risk of open circuits and short circuits can be reduced.

[0039] Figure 3C This is a cross-sectional view of a semiconductor device package 3C according to some embodiments of the present disclosure. For example... Figure 3C As shown, the outer edge 12E of each first conductive pad 12 is not aligned with the corresponding outer edge 22E of the second conductive pad 22. By way of example, the outer edge 12E of each first conductive pad 12 is substantially aligned with or recessed from the corresponding outer edge 34E of the connecting electrode 34, while the outer edge 22E of the second conductive pad 22 protrudes beyond the corresponding outer edge 34E of the connecting electrode 34. This asymmetrical design of the first conductive pad 12 and the second conductive pad 22 helps to accurately control the position of the first solder material 42 and the second solder material 44, and prevents the first solder material 42 from fusing with the second solder material 44. Therefore, the amount of the first solder material 42 and the amount of the second solder material 44 can be accurately controlled, and the risk of open circuits and short circuits can be reduced.

[0040] Figure 4A This is a cross-sectional view of a semiconductor device package 4A according to some embodiments of the present disclosure. Figure 4A As shown, the length L1 of the first extension 341 is different from the length L2 of the second extension 342. For example, the length L1 of the first extension 341 is less than the length L2 of the second extension 342. The asymmetrical design of the first extension 341 and the second extension 342 helps to accurately control the positions of the first welding material 42 and the second welding material 44, and prevents the first welding material 42 from fusing with the second welding material 44. Therefore, the amount of the first welding material 42 and the amount of the second welding material 44 can be accurately controlled, and the risk of short circuits can be reduced.

[0041] Figure 4B This is a cross-sectional view of a semiconductor device package 4B according to some embodiments of the present disclosure. Figure 4BAs shown, the outer edge 12E of each first conductive pad 12 is not aligned with the corresponding outer edge 22E of the second conductive pad 22. By way of example, the outer edge 12E of each first conductive pad 12 is substantially aligned with or recessed from the corresponding outer edge 34E of the connecting electrode 34, while the outer edge 22E of the second conductive pad 22 protrudes beyond the corresponding outer edge 34E of the connecting electrode 34. Furthermore, the length L1 of the first extension 341 is different from the length L2 of the second extension 342. By way of example, the length L1 of the first extension 341 is less than the length L2 of the second extension 342. The asymmetrical design of the first extension 341 and the second extension 342, combined with the asymmetrical design of the first conductive pad 12 and the second conductive pad 22, helps to accurately control the position of the first welding material 42 and the second welding material 44, and prevents the first welding material 42 from fusing with the second welding material 44. Therefore, the amount of the first welding material 42 and the amount of the second welding material 44 can be accurately controlled, and the risk of open circuits and short circuits can be reduced.

[0042] In some embodiments of this disclosure, a semiconductor device package includes two stacked substrates and an SMD component disposed therebetween. The SMD component is configured as a support component to maintain a gap between the two stacked substrates and also as an interconnect component to electrically connect the two stacked substrates to electronic components disposed on the two stacked substrates. Therefore, the size of the semiconductor device package can be reduced. The SMD component can be readily formed using, for example, a surface mount technology with a gripping operation. The SMD component includes a plurality of connection electrodes that electrically connect one substrate to the other. Each of the connection electrodes allows a corresponding electrical terminal of the first substrate to be electrically connected in a vertical direction to a corresponding electrical terminal of the second substrate, and the connection electrodes are horizontally disconnected from each other. The SMD component may include a plurality of discretely arranged components that do not obstruct the flow of molding material. Therefore, the electronic components and the SMD component can be arranged to maximize substrate area utilization without obstructing the flow of molding material. The SMD component may include dummy passive components in which the function of passive components is disabled. Therefore, the manufacturing cost of the semiconductor device package can be reduced.

[0043] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple references.

[0044] As used herein, the terms “substantially,” “basically,” “approximately,” and “about” are used to indicate and explain small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. For example, when used in conjunction with numerical values, the terms can cover a range of variation less than or equal to ±10% of the value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two values ​​can be considered “substantially” or “about” the same. For example, "essentially parallel" can refer to an angle range of less than or equal to ±10° relative to 0°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°. Similarly, "essentially perpendicular" can refer to an angle range of less than or equal to ±10° relative to 90°, such as ±5°, ±4°, ±3°, ±2°, ±1°, ±0.5°, ±0.1°, or ±0.05°.

[0045] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0046] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the technical representations in this disclosure and actual apparatuses. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, the order and grouping of operations are not limited by this disclosure unless specifically indicated herein.

Claims

1. A semiconductor device package comprising: A first substrate, which includes a first conductive pad; A second substrate is disposed above the first substrate and includes a second conductive pad; and A surface mount device (SMD) assembly is disposed between a first substrate and a second substrate, wherein the SMD assembly includes an insulating substrate and at least one connection electrode for electrically connecting the first conductive pad to the second conductive pad, and the outer edges of the first conductive pad and the second conductive pad are not aligned. The insulating substrate includes a first outer surface facing the first substrate, a second outer surface facing the second substrate, and an outer edge connected to the first outer surface and the second outer surface, and the connecting electrode is disposed on the first outer surface, the outer edge, and the second outer surface of the insulating substrate.

2. The semiconductor device package of claim 1, wherein the outer edge of the first conductive pad protrudes beyond the corresponding outer edge of the connection electrode, and the outer edge of the second conductive pad is not aligned with the corresponding outer edge of the connection electrode, and the connection electrode includes a main portion disposed on the outer edge of the insulating substrate, a first extension extending to the first outer surface, and a second extension extending to the second outer surface.

3. The semiconductor device package of claim 1, further comprising a first solder material disposed between the first conductive pad and the insulating substrate, and a second solder material disposed between the second conductive pad and the insulating substrate.

4. The semiconductor device package of claim 3, wherein the first solder material contacts the first conductive pad, the connecting electrode, and the insulating substrate.

5. The semiconductor device package of claim 4, wherein the first solder material surrounds the first extension portion of the connecting electrode.

6. The semiconductor device package of claim 1, wherein the endpoint edge of the first extension of the connecting electrode is not aligned with the endpoint edge of the second extension of the connecting electrode.

7. The semiconductor device package of claim 1, further comprising an encapsulation layer disposed between the first substrate and the second substrate and encapsulating the SMD component.

8. The semiconductor device package of claim 1, wherein the size of the second conductive pad is larger than the size of the first conductive pad.

9. The semiconductor device package of claim 1, wherein the connection electrode of the SMD component provides an independent electrical connection path between the first substrate and the second substrate in a vertical direction, such that the SMD component is configured as an interconnect component for interconnecting the first substrate and the second substrate.

10. A semiconductor device package comprising: A first substrate, which includes a first conductive pad; A second substrate is disposed above the first substrate and includes a second conductive pad; and A surface mount device (SMD) assembly disposed between a first substrate and a second substrate and electrically connecting the first conductive pad to the second conductive pad, wherein the SMD assembly includes: An insulating substrate includes a first outer surface facing the first substrate, a second outer surface facing the second substrate, and a first outer edge connected to the first outer surface and the second outer surface; and A first connecting electrode is disposed on the first outer surface, the first outer edge, and the second outer surface of the insulating substrate, wherein the length of a first extension of the first connecting electrode extending to the first outer surface is different from the length of a second extension of the first connecting electrode extending to the second outer surface.

11. The semiconductor device package of claim 10, wherein the insulating substrate includes a second outer edge connected to the first outer surface and the second outer surface and relative to the first outer edge, and the SMD assembly includes a second connection electrode disposed on the insulating substrate relative to the first connection electrode, the second connection electrode including a main portion disposed on the second outer edge, a third extension extending to the first outer surface, and a fourth extension extending to the second outer surface, the first connection electrode and the second connection electrode being electrically isolated from each other and thus substantially symmetrically arranged.

12. The semiconductor device package of claim 11, wherein the distance between the second extension of the first connecting electrode and the fourth extension of the second connecting electrode is less than the distance between the first extension of the first connecting electrode and the third extension of the second connecting electrode.

13. The semiconductor device package of claim 11, wherein when an alternating current voltage is applied to the first connection electrode or the second connection electrode, the first connection electrode and the second connection electrode are electrically disconnected from each other within the internal volume of the SMD assembly.

14. The semiconductor device package of claim 10, further comprising a first solder material disposed between the first conductive pad and the insulating substrate, and a second solder material disposed between the second conductive pad and the second extension, wherein the first solder material is spaced apart from the second solder material.

15. The semiconductor device package of claim 14, wherein the first solder material covers the first extension portion of the first connecting electrode and contacts the first outer surface of the insulating substrate.

16. The semiconductor device package of claim 14, wherein the volume of the first solder material is greater than the volume of the second solder material.

17. The semiconductor device package of claim 11, wherein the first substrate further includes a third conductive pad and the second substrate further includes a fourth conductive pad, and the second connection electrode electrically connects the third conductive pad of the first substrate to the fourth conductive pad of the second substrate.

18. The semiconductor device package of claim 17, wherein the first connection electrode and the second connection electrode of the SMD component respectively provide two different independent electrical connection paths between the first substrate and the second substrate in the vertical direction.

19. The semiconductor device package of claim 18, further comprising: An encapsulation layer is disposed between the first substrate and the second substrate and encapsulates the SMD component; At least one first electronic component is disposed on the first substrate; and At least one second electronic component disposed on the second substrate, wherein the at least one first electronic component and the at least one second electronic component are electrically connected through different independent electrical connection paths provided by the first connection electrode or the second connection electrode of the SMD component.

20. A semiconductor device package comprising: A first substrate, which includes a first conductive pad; A second substrate is disposed above the first substrate and includes a second conductive pad; and A surface mount device (SMD) assembly disposed between a first substrate and a second substrate, wherein the SMD assembly includes an insulating substrate having an outer surface and a plurality of connection electrodes for electrically connecting the first substrate to the second substrate. The outer surface of the insulating substrate defines an internal volume, and the plurality of connecting electrodes are disconnected from each other and parasiticly coupled outside the internal volume of the insulating substrate.

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