Chip package module and method of manufacturing the same

Abstract

The application relates to the chip packaging technical field and provides a chip packaging module and a manufacturing method thereof.The chip packaging module comprises a substrate, a power supply surface and a ground surface; a power supply adapter plate is vertically arranged on the substrate; the power supply adapter plate is internally provided with a first power supply wall and a first ground wall which penetrate in the height direction; the first power supply wall is connected with the power supply surface; the first ground wall is connected with the ground surface; a first chip is arranged on the substrate; the first chip comprises a first power supply pad and a first ground pad; the first power supply pad is bonded with the first power supply wall through a first bonding wire; and the first ground pad is bonded with the first ground wall through a second bonding wire.The chip packaging module provided by the application can lift the power supply plane and the ground plane of the first chip from the surface of the substrate to the surface of the power supply adapter plate, shorten the length of the power supply bonding wire and the ground bonding wire, reduce the parasitic inductance and voltage drop of the bonding wire, improve the stability of the power supply voltage and reduce the power supply noise.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging module and its manufacturing method. Background Technology

[0002] In chip packaging, the chip is typically bonded to pads on the substrate via bonding wires, and the power supply path inside the substrate supplies power to the chip through the bonding wires.

[0003] However, in this power supply method, the bonding wires are typically quite long (on the order of several hundred micrometers), resulting in large parasitic inductance and a large power supply signal voltage drop. High parasitic inductance degrades PDN performance and leads to high power supply noise. A large power supply signal voltage drop causes a decrease in the chip's supply voltage, resulting in unstable supply voltage. Summary of the Invention

[0004] This application provides a chip packaging module and its manufacturing method, which can shorten the length of the power supply bonding wire and the ground return bonding wire of the chip, thereby reducing the parasitic inductance and voltage drop of the bonding wire, improving the stability of the power supply voltage and reducing power supply noise.

[0005] In a first aspect, embodiments of this application provide a chip packaging module, including: A substrate, the substrate including a power plane and a ground plane; A power adapter board is vertically disposed on the substrate. The power adapter board has a first power wall and a first ground wall that extend through the height direction. The first power wall is connected to the power surface, and the first ground wall is connected to the ground plane. A first chip is disposed on the substrate. The first chip includes a first power pad and a first ground pad. The first power pad is bonded to the first power wall via a first bonding wire, and the first ground pad is bonded to the first ground wall via a second bonding wire.

[0006] In some embodiments, the power adapter board includes a first end facing the substrate, the first end being provided with a first micro-bump and a second micro-bump, the first micro-bump being connected to the first power wall, and the second micro-bump being connected to the first ground wall. The substrate includes a first surface facing the power adapter board, the first surface being provided with a second power pad and a second ground pad, the second power pad being connected to the power surface, and the second ground pad being connected to the ground plane; The first microbump is connected to the second power pad via thermo-bonding, and the second microbump is connected to the second ground pad via thermo-bonding.

[0007] In some embodiments, the power adapter board further includes a second end opposite to the first end, the second end being provided with a third power pad and a third ground pad, the third power pad being connected to the first power wall, and the third ground pad being connected to the first ground wall; The first power pad is bonded to the third power pad via a first bonding wire, and the first ground pad is bonded to the third ground pad via a second bonding wire.

[0008] In some embodiments, the substrate is provided with a second power wall and a second ground wall that extend through the height direction. The second power wall is connected to the second power pad, and the second ground wall is connected to the second ground pad. The second power wall forms the power plane, and the second ground wall forms the ground plane.

[0009] In some embodiments, the substrate further includes a second surface opposite to the first surface, the second surface being provided with a power ball and a ground ball, the power ball being connected to the second power wall, the ground ball being connected to the second ground wall, the power ball being used to transmit power signals, and the ground ball being used to transmit return-to-ground signals.

[0010] In some embodiments, the first chip further includes a first signal pad, and the first surface of the substrate is provided with a second signal pad, wherein the first signal pad is bonded to the second signal pad via a third bonding line.

[0011] In some embodiments, the first power wall includes a plurality of spaced-apart first metallized vias, the plurality of first metallized vias being electrically connected through a first metal trace layer; The first grounding wall includes a plurality of spaced second metallized vias, which are electrically connected through a second metal trace layer; An insulating medium is provided between the first power supply wall and the first grounding wall.

[0012] In some embodiments, the chip packaging module further includes one or more second chips, which are stacked between the substrate and the first chip along the height direction of the substrate.

[0013] In some embodiments, the total height of the one or more second chips and the first chip is equal to the height of the power adapter board.

[0014] Secondly, embodiments of this application provide a method for manufacturing a chip packaging module, including: A substrate is provided, the substrate including a power plane and a ground plane; A power adapter board is provided, wherein a first power wall and a first grounding wall are provided inside the power adapter board, which extend through the height direction; The power adapter board is thermo-bonded to the substrate to connect the first power wall to the power surface and the first ground wall to the ground plane. A first chip is disposed on the substrate, the first chip including a first power pad and a first ground pad; The first power pad and the first power wall are bonded together using the first bonding wire; The first grounding pad and the first grounding wall are bonded together using a second bonding wire.

[0015] The chip packaging module of this application embodiment, by setting a power adapter board, can raise the power supply plane and ground plane of the first chip from the surface of the substrate to the surface of the power adapter board, that is, raise the power supply plane from the power plane to the first power wall, and raise the ground plane from the ground plane to the first ground wall. Compared with supplying power to the first chip and returning to ground from the surface of the substrate through bonding wires, the length of the power supply bonding wires and the return ground bonding wires can be shortened, thereby reducing the parasitic inductance and voltage drop of the bonding wires, improving the stability of the power supply voltage and reducing power supply noise. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the chip packaging module according to an embodiment of this application.

[0018] Figure 2 This is a top view of the power adapter board according to an embodiment of this application.

[0019] Figure 3 for Figure 2 The power adapter board shown is a cross-sectional view along the AA direction.

[0020] Figure 4 for Figure 2 The power adapter board shown is a cross-sectional view along the BB direction.

[0021] Figure 5 for Figure 2 The power adapter board shown is a cross-sectional view along the CC direction.

[0022] Figure 6 This is a schematic diagram of the substrate structure according to an embodiment of this application.

[0023] Figure 7 This is a schematic flowchart illustrating the manufacturing method of a chip packaging module according to an embodiment of this application.

[0024] Explanation of reference numerals in the attached figures: 10-Substrate, 20-Power adapter board, 31-First chip, 32-Second chip, 41-First bonding wire, 42-Second bonding wire, 43-Third bonding wire, P1-First power pad, P2-First ground pad, P3-First signal pad; 10a-First surface, 10b-Second surface, 11-Power plane, 12-Ground plane, 13-Second power pad, 14-Second ground pad, 15-Second power wall, 16-Second ground wall, 17-Power ball, 18-Ground, 19-Second signal pad; 20a-First terminal, 20b-Second terminal, 21-First power supply wall, 22-First grounding wall, 23-Insulating medium, 24-First micro-bump, 25-Second micro-bump, 26-Third power supply pad, 27-Third grounding pad; 211-First metallized via, 212-First metal trace layer, 221-Second metallized via, 222-Second metal trace layer; AA - First sectioning direction, BB - Second sectioning direction, CC - Third sectioning direction, Z - Height direction. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0026] This application provides a chip packaging module. (See reference...) Figure 1 , Figure 1 This is a schematic diagram of the chip packaging module according to an embodiment of this application. The chip packaging module includes a substrate 10, a power adapter board 20, and a first chip 31.

[0027] The substrate 10 includes a power plane 11 and a ground plane 12. The power plane 11 serves as the power supply for the chip packaging module, used to power the first chip 31. The ground plane 12 serves as the ground plane for the chip packaging module, used to transmit return-to-ground signals.

[0028] A power adapter board 20 is vertically disposed on the substrate 10. Structurally, the power adapter board 20 is vertically disposed on the substrate 10 and electrically connected to the substrate 10. The power adapter board 20 contains a first power wall 21 and a first ground wall 22 extending along its height direction. The first power wall 21 is connected to the power surface 11 to form a power supply plane. The first ground wall 22 is connected to the ground plane 12 to form a ground plane. The height direction can also be understood as the thickness direction.

[0029] Understandably, in practical applications, the power adapter board 20 can be a customized substrate, in which the first power wall 21 and the first ground wall 22 are formed through manufacturing processes (such as layering, drilling, and metallization of holes) inside the substrate, without the need to form other circuit patterns.

[0030] The first chip 31 can be a bare die (also called a bare chip, bare die, or wafer). The first chip 31 is disposed on the substrate 10. For example, the first chip 31 can be mounted on the substrate 10. The first chip 31 includes a first power pad P1 and a first ground pad P2. The first power pad P1 is bonded to a first power wall 21 via a first bonding wire 41, so that the first power wall 21 supplies power to the first chip 31 through the first bonding wire 41. The first bonding wire 41 can be understood as a power supply bonding wire. The first ground pad P2 is bonded to a first ground wall 22 via a second bonding wire 42, so that the first ground wall 22 and the second bonding wire 42 transmit the ground return signal of the first chip 31. The second bonding wire 42 can be understood as a ground return bonding wire.

[0031] The chip packaging module of this application embodiment, by setting a power adapter board 20, can raise the power supply plane and ground plane of the first chip 31 from the surface of the substrate 10 to the surface of the power adapter board 20. That is, the power supply plane is raised from the power plane 11 to the first power wall 21, and the ground plane is raised from the ground plane 12 to the first ground wall 22. Compared with supplying power to the first chip 31 and returning it to ground from the surface of the substrate 10 through bonding wires, the length of the power supply bonding wires and the return ground bonding wires can be shortened, thereby reducing the parasitic inductance and voltage drop of the bonding wires, improving the stability of the power supply voltage and reducing power supply noise.

[0032] In some embodiments, reference Figure 2 , Figure 3 and Figure 6 , Figure 2 This is a top view of the power adapter board 20 according to an embodiment of this application. Figure 3 for Figure 2 The power adapter board 20 shown is a cross-sectional view along the AA direction. Figure 6 This is a schematic diagram of the structure of the substrate 10 according to an embodiment of this application. The direction Z represents the height direction of the power adapter board 20, or can be understood as the thickness direction.

[0033] like Figure 3 As shown, the power adapter board 20 includes a first end 20a and a second end 20b opposite to each other. The first end 20a faces the substrate 10, and the second end 20b faces away from the substrate 10.

[0034] The first end 20a is provided with a first micro-bump 24 and a second micro-bump 25. The first micro-bump 24 is connected to a first power supply wall 21, and the second micro-bump 25 is connected to a first grounding wall 22. In one example, there are multiple first micro-bumps 24 and multiple second micro-bumps 25.

[0035] In one example, the first microbump 24 and the second microbump 25 may include a copper pillar (Cu) with a base (the base being one side connected to the first power wall 21 or the first ground wall 22), a diffusion barrier layer of nickel (Ni) covering the copper pillar, and a tin-silver (SnAg) solder covering the top of the nickel layer, thus forming a Cu / Ni / SnAg structure microbump. In one example, the diameter of the first microbump 24 and the second microbump 25 may be 25μm to 60μm, and the height may be 8μm to 20μm.

[0036] The second end 20b is provided with a third power pad 26 and a third ground pad 27. The third power pad 26 is connected to the first power wall 21, and the third ground pad 27 is connected to the first ground wall 22. The first power wall 21 and the first ground wall 22 penetrate the power adapter plate 20 along the height direction Z.

[0037] Specifically, the first power pad P1 of the first chip 31 is bonded to the third power pad 26 via the first bonding wire 41. The first ground pad P2 of the first chip 31 is bonded to the third ground pad 27 via the second bonding wire 42. Therefore, the first power pad P1 can be connected to the first power wall 21 via the first bonding wire 41, and the first ground pad P2 can be connected to the first ground wall 22 via the second bonding wire 42.

[0038] like Figure 6 As shown, the substrate 10 includes a first surface 10a and a second surface 10b facing each other. The first surface 10a faces the power adapter plate 20, and the second surface 10b faces away from the power adapter plate 20. A first chip 31 is disposed on the first surface 10a.

[0039] A second power pad 13 and a second ground pad 14 are provided on the first surface 10a. The second power pad 13 is connected to the power surface 11, and the second ground pad 14 is connected to the ground plane 12. In one example, a second power wall 15 and a second ground wall 16 extending through the height direction Z are provided inside the substrate 10. The second power wall 15 is connected to the second power pad 13, and the second ground wall 16 is connected to the second ground pad 14. The second power wall 15 forms the power surface 11, and the second ground wall 16 forms the ground plane 12.

[0040] In this configuration, the first microbump 24 of the power adapter board 20 is connected to the second power pad 13 via thermoforming. The second microbump 25 of the power adapter board 20 is connected to the second ground pad 14 via thermoforming. This forms a power supply path from power surface 11 to second power pad 13 to first microbump 24 to first power wall 21 to third power pad 26 to first bonding line 41 to first power pad P1, and a current return path from first ground pad P2 to ground plane 12 via second bonding line 42 to third ground pad 27 to first ground wall 22 to second microbump 25 to second ground pad 14.

[0041] In some embodiments, continue to refer to Figure 6 The second surface 10b of the substrate 10 is provided with a power ball 17 and a ground ball 18. The power ball 17 is connected to a second power wall 15, and the ground ball 18 is connected to a second ground wall 16. The power ball 17 is used to transmit power signals; for example, it can be connected to a power source to supply power to the first chip 31 through the aforementioned power supply path. The ground ball 18 is used to transmit ground return signals; for example, it can be connected to system ground to allow the current from the aforementioned current return path to flow back to system ground.

[0042] In one example, the power ball 17 and the ground ball 18 can be tin-based solder balls or solder balls formed of alloys such as tin, silver, and copper.

[0043] In some embodiments, reference is also made to Figure 1 and Figure 6 The first chip 31 also includes a first signal pad P3. A second signal pad 19 is provided on the first surface 10a of the substrate 10. The first signal pad P3 is bonded to the second signal pad 19 through a third bonding line 43 to realize signal transmission between the substrate 10 and the first chip 31.

[0044] In some embodiments, reference is also made to Figure 2 , Figure 4 and Figure 5 , Figure 4 for Figure 2 The power adapter board 20 shown is a cross-sectional view along the BB direction. Figure 5 for Figure 2The power adapter board 20 shown is a cross-sectional view along the CC direction.

[0045] The first power wall 21 of the power adapter board 20 includes a plurality of spaced-apart first metallized vias 211, which are electrically connected through a first metal trace layer 212. The first grounding wall 22 includes a plurality of spaced-apart second metallized vias 221, which are electrically connected through a second metal trace layer 222. An insulating medium 23 is provided between the first power wall 21 and the first grounding wall 22 to achieve electrical insulation between them. Both the first metal trace layer 212 and the second metal trace layer 222 can be multilayered.

[0046] In one example, the power adapter board 20 can be formed by progressively adding layers using a layer-adding process. The overall thickness of the power adapter board 20 can be between 300μm and 800μm. During the layer-adding process, metal layers (e.g., copper layers) and dielectric layers are stacked sequentially. Metal is removed from predetermined locations (i.e., the locations where the insulating dielectric 23 needs to be formed) of each metal layer using an etching process. Dielectric layers are then filled into the removed locations, ultimately forming the overall insulating dielectric 23. After layer-adding, multiple vias can be formed along the thickness direction using mechanical drilling or laser drilling. These vias are then metallized using processes such as metal sputtering and electroplating to form multiple metallized vias. Among the multiple metallized vias, the one located on one side of the insulating dielectric 23 is the first metallized via 211, and each metal layer connected to the multiple first metallized vias 211 is a first metal trace layer 212. The one located on the other side of the insulating dielectric 23 is the second metallized via 221, and each metal layer connected to the multiple second metallized vias 221 is a second metal trace layer 222. Thus, a structure like... Figure 2 , Figure 4 and Figure 5 The first power supply wall 21 and the first grounding wall 22 are shown.

[0047] In some embodiments, continue to refer to Figure 1 The chip packaging module also includes one or more second chips 32. The one or more second chips 32 are stacked and disposed between the substrate 10 and the first chip 31 along the height direction of the substrate 10.

[0048] In one example, such as Figure 1 As shown, there can be one second chip 32. The second chip 32 is disposed on the first surface 10a of the substrate 10. For example, the second chip 32 can be connected to the first surface 10a by flip-chip bonding. The first chip 31 is disposed on the side of the second chip 32 facing away from the substrate 10.

[0049] In another example, there may be multiple second chips 32, which are stacked sequentially on the first surface 10a of the substrate 10 along the height direction of the substrate 10. The first chip 31 is disposed on the side away from the substrate 10 after the multiple second chips 32 are stacked.

[0050] Understandably, the more second chips 32 there are, the higher the total height of the stacked second chips 32 will be, and the greater the distance between the first chip 31 and the substrate 10 will be. Without a power adapter board 20, the first chip 31 would need to connect to the power and ground planes of the substrate 10 via very long bonding wires (on the order of several hundred micrometers), introducing significant power noise and power signal voltage drop. In this embodiment, by providing a power adapter board 20, the power and ground planes of the substrate 10 can be raised onto the power adapter board 20, thereby shortening the length of the bonding wires required for the first chip 31 to supply power and return to ground, reducing the parasitic inductance and voltage drop of the bonding wires, and thus reducing power noise and power signal voltage drop.

[0051] In some embodiments, such as Figure 1 As shown, the total height of one or more second chips 32 and the first chip 31 is equal to the height of the power adapter board 20.

[0052] It is understandable that setting the total height of one or more second chips 32 and the first chip 31 to be equal to the height of the power adapter board 20 can raise the power plane and ground plane of the substrate 10 to the same height as the pads (first power pad P1 and first ground pad P2) of the first chip 31. Therefore, the length of the bonding wire can be minimized to achieve the best effect in reducing power noise and power signal voltage drop.

[0053] This application also provides a method for manufacturing a chip packaging module, used to manufacture the chip packaging module of any of the above embodiments. (See also...) Figure 7 , Figure 7 This is a schematic flowchart illustrating a method for manufacturing a chip packaging module according to an embodiment of this application. The manufacturing method includes the following steps 51-56: 51. A substrate is provided, the substrate including a power plane and a ground plane; 52. Provide a power adapter board, wherein the power adapter board is provided with a first power wall and a first grounding wall that run through the height direction; 53. The power adapter board and the substrate are thermo-bonded to connect the first power wall to the power surface and the first ground wall to the ground plane. 54. A first chip is disposed on the substrate, the first chip including a first power pad and a first ground pad; 55. Bond the first power pad and the first power wall together using the first bonding wire; 56. Bond the first grounding pad and the first grounding wall together using the second bonding wire.

[0054] First, a substrate 10 is provided. In practical applications, the substrate 10 can be manufactured through processes such as core board layering, pattern transfer, drilling, and electroplating. The substrate 10 includes the required circuit pattern. In one example, the substrate 10 can be a multilayer board.

[0055] The power adapter board 20 can also be manufactured through processes such as core board layering, pattern transfer, drilling, and electroplating. Understandably, the overall manufacturing process of the power adapter board 20 and the substrate 10 can be the same. The difference between the two lies in the internal circuit pattern and the arrangement of the external pads, as well as the different parameters such as size and thickness.

[0056] After the substrate 10 and the power adapter board 20 are manufactured, the power adapter board 20 and the substrate 10 are thermo-bonded to connect the first power wall of the power adapter board 20 to the power surface of the substrate 10 and the first ground wall of the power adapter board 20 to the ground plane of the substrate 10, thus completing the mechanical and electrical connection between the power adapter board 20 and the substrate 10.

[0057] Subsequently, a first chip 31 is disposed on the substrate 10, for example, by mounting the first chip 31 onto the substrate 10. It is understood that, in another example, the step of disposing of the first chip 31 on the substrate 10 may also be performed before the power adapter board 20 and the substrate 10 are thermo-bonded.

[0058] Finally, the first power pad of the first chip 31 and the first power wall of the power adapter board 20 are bonded together using the first bonding wire, and the first ground pad of the first chip 31 and the first ground wall of the power adapter board 20 are bonded together using the second bonding wire.

[0059] It should be noted that the specific structure and implementation of the substrate 10, the power adapter board 20 and the first chip 31 can be referred to the descriptions in the above embodiments, and will not be repeated here.

[0060] The manufacturing method of this application embodiment involves thermo-bonding the power adapter board 20 to the substrate 10, and then bonding the first chip 31 to the power adapter board 20 via bonding wires. Therefore, the power supply plane and ground plane of the first chip 31 can be raised from the surface of the substrate 10 to the surface of the power adapter board 20, which can shorten the length of the power supply bonding wire and the return-to-ground bonding wire of the first chip 31, thereby reducing the parasitic inductance and voltage drop of the bonding wires, improving the stability of the power supply voltage, and reducing power supply noise.

[0061] In the description of this application, it should be understood that terms such as “first” and “second” are used only to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0062] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0063] The chip packaging module and its manufacturing method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A chip packaging module, characterized in that, include: A substrate, the substrate including a power plane and a ground plane; A power adapter board is vertically disposed on the substrate. The power adapter board has a first power wall and a first ground wall that extend through the height direction. The first power wall is connected to the power surface, and the first ground wall is connected to the ground plane. A first chip is disposed on the substrate. The first chip includes a first power pad and a first ground pad. The first power pad is bonded to the first power wall via a first bonding wire, and the first ground pad is bonded to the first ground wall via a second bonding wire.

2. The chip packaging module according to claim 1, characterized in that, The power adapter board includes a first end facing the substrate, the first end being provided with a first micro-bump and a second micro-bump, the first micro-bump being connected to the first power wall, and the second micro-bump being connected to the first ground wall. The substrate includes a first surface facing the power adapter board, the first surface being provided with a second power pad and a second ground pad, the second power pad being connected to the power surface, and the second ground pad being connected to the ground plane; The first microbump is connected to the second power pad via thermo-bonding, and the second microbump is connected to the second ground pad via thermo-bonding.

3. The chip packaging module according to claim 2, characterized in that, The power adapter board also includes a second end opposite to the first end. The second end is provided with a third power pad and a third ground pad. The third power pad is connected to the first power wall, and the third ground pad is connected to the first ground wall. The first power pad is bonded to the third power pad via a first bonding wire, and the first ground pad is bonded to the third ground pad via a second bonding wire.

4. The chip packaging module according to claim 2, characterized in that, The substrate has a second power wall and a second ground wall that extend through the height direction. The second power wall is connected to the second power pad, and the second ground wall is connected to the second ground pad. The second power wall forms the power plane, and the second ground wall forms the ground plane.

5. The chip packaging module according to claim 4, characterized in that, The substrate further includes a second surface opposite to the first surface. The second surface is provided with a power ball and a ground ball. The power ball is connected to the second power wall, and the ground ball is connected to the second ground wall. The power ball is used to transmit power signals, and the ground ball is used to transmit return-to-ground signals.

6. The chip packaging module according to claim 2, characterized in that, The first chip further includes a first signal pad, and the first surface of the substrate is provided with a second signal pad. The first signal pad is bonded to the second signal pad through a third bonding line.

7. The chip packaging module according to any one of claims 1 to 6, characterized in that: The first power wall includes a plurality of spaced first metallized vias, and the plurality of first metallized vias are electrically connected through a first metal trace layer; The first grounding wall includes a plurality of spaced second metallized vias, which are electrically connected through a second metal trace layer; An insulating medium is provided between the first power supply wall and the first grounding wall.

8. The chip packaging module according to any one of claims 1 to 6, characterized in that, The chip packaging module further includes one or more second chips, which are stacked between the substrate and the first chip along the height direction of the substrate.

9. The chip packaging module according to claim 8, characterized in that, The total height of the one or more second chips and the first chip is equal to the height of the power adapter board.

10. A method for manufacturing a chip packaging module, characterized in that, include: A substrate is provided, the substrate including a power plane and a ground plane; A power adapter board is provided, wherein a first power wall and a first grounding wall are provided inside the power adapter board, which extend through the height direction; The power adapter board is thermo-bonded to the substrate to connect the first power wall to the power surface and the first ground wall to the ground plane. A first chip is disposed on the substrate, the first chip including a first power pad and a first ground pad; The first power pad and the first power wall are bonded together using the first bonding wire; The first grounding pad and the first grounding wall are bonded together using a second bonding wire.

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