Power module and method of manufacturing the same

Abstract

Embodiments of the present application provide a power module and a manufacturing method thereof. The power module includes, for example, a first substrate, a chip assembly, and an insulating member. The first substrate includes an insulating substrate and a conductive layer disposed on the insulating substrate, and the first substrate is provided with a through hole penetrating the conductive layer and the insulating substrate. The chip assembly includes a chip and an insulating layer, the chip is disposed on the conductive layer and has a bottom surface facing the conductive layer, and the insulating layer is disposed on the bottom surface of the chip and covers a part of the bottom surface of the chip, and the insulating layer at least partially extends into the through hole. The insulating member is disposed in the through hole and seals the insulating layer and the insulating substrate, a lower surface of the insulating layer away from the chip is at least partially uncovered by the insulating member, and the uncovered part of the lower surface of the insulating layer is configured as a cooling area. Embodiments of the present application can improve the heat dissipation effect of the power module.

Description

Technical Field

[0001] This invention relates to the field of power electronic device technology, and in particular to a power module and a method for manufacturing the power module. Background Technology

[0002] For power modules, such as automotive power modules, the power chip is typically fixed to the front surface of a high-performance multilayer ceramic substrate via conductive paste, and a heat sink is soldered to the back surface of the high-performance multilayer ceramic substrate to dissipate heat from the power chip. However, the metal layer and ceramic insulating layer on the high-performance multilayer ceramic substrate, and the heat sink, have different properties in terms of material density, specific heat capacity, and thermal conductivity. Furthermore, there are many thermal resistance elements along the heat dissipation path from the power chip to the surface of the heat sink away from the power chip, resulting in a large thermal resistance throughout the heat dissipation path, thus requiring further improvement in heat dissipation performance. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a power module and a method for manufacturing a power module to improve the heat dissipation effect of the power module.

[0004] Specifically, an embodiment of the present invention provides a power module, for example including: a first substrate, a chip assembly, and an insulating member; the first substrate includes an insulating substrate and a conductive layer disposed on the insulating substrate, and the first substrate has a through hole penetrating the conductive layer and the insulating substrate; the chip assembly includes a chip and an insulating layer, the chip is disposed on the conductive layer and has a bottom surface facing the conductive layer, the insulating layer is disposed on the bottom surface of the chip and covers a portion of the bottom surface of the chip, and the insulating layer at least partially extends into the through hole; and the insulating member is disposed in the through hole and sealably connects the insulating layer and the insulating substrate, wherein at least a portion of the lower surface of the insulating layer facing away from the chip is not covered by the insulating member, and the portion of the lower surface of the insulating layer not covered by the insulating member is configured as a cooling zone.

[0005] On the other hand, an embodiment of the present invention provides a method for manufacturing a power module, which includes, for example: (i) providing a first substrate, the first substrate including an insulating substrate and a conductive layer disposed on the insulating substrate, the first substrate having a through hole penetrating the conductive layer and the insulating substrate; (ii) providing a chip assembly and disposing the chip assembly on the first substrate, wherein the chip assembly includes a chip and an insulating layer, the chip being disposed on the conductive layer and having a bottom surface facing the conductive layer, the insulating layer being disposed on the bottom surface of the chip and covering a portion of the bottom surface of the chip, the insulating layer extending at least partially into the through hole; and (iii) disposing an insulating member in the through hole and sealingly connecting the insulating layer and the insulating substrate, wherein at least a portion of the lower surface of the insulating layer facing away from the chip is not covered by the insulating member, and the portion of the lower surface of the insulating layer not covered by the insulating member is configured as a cooling zone.

[0006] The above embodiments of the present invention can have the following beneficial effects: The power module and its manufacturing method in this embodiment, by providing the through hole on the first substrate, extending at least a portion of the insulating layer disposed on the bottom surface of the chip into the through hole, and using the insulating element to seal and connect the insulating layer to the insulating substrate of the first substrate and exposing at least a portion of the insulating layer away from the bottom surface of the chip, allows the chip to be cooled directly by cooling fluid through the insulating layer. This reduces the thermal resistance elements on the heat dissipation path of the chip, improving the heat dissipation effect. Moreover, thanks to the improved heat dissipation effect, the chip size can be designed to be smaller. Furthermore, the use of the insulating layer can reduce the performance requirements of the first substrate, which can only be used for mechanical support and electrical connection, thereby achieving cost reduction of the power module. In addition, compared with the prior art, the power module of the present invention does not require soldering a heat sink to the entire back surface of the first substrate, thus shortening the assembly time. Attached Figure Description

[0007] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0008] Figure 1A This is a structural cross-sectional schematic diagram of a power module provided in an embodiment of the present invention.

[0009] Figure 1B This is a structural cross-sectional schematic diagram of a power module provided for other embodiments of the present invention.

[0010] Figure 2A This is a cross-sectional view of another power module provided in an embodiment of the present invention.

[0011] Figure 2B This is a cross-sectional view of another power module provided in an embodiment of the present invention.

[0012] Figure 3 This is a cross-sectional view of another power module provided in an embodiment of the present invention.

[0013] Figure 4A This is a schematic cross-sectional view of the first substrate in a method for manufacturing a power module according to an embodiment of the present invention.

[0014] Figure 4B This is a top view of the chip structure of a chip component in a method for manufacturing a power module according to an embodiment of the present invention.

[0015] Figure 4C This is a top view of the chip structure of a chip component in a method for manufacturing a power module according to an embodiment of the present invention.

[0016] Figure 4D This is a cross-sectional schematic diagram of the combined structure of the chip assembly and the first substrate in a method for manufacturing a power module according to an embodiment of the present invention.

[0017] Figure 4E for Figure 4D Top view of the structure shown.

[0018] Figure 4F for Figure 4D The diagram shows a top view of the structure after the chip has been removed.

[0019] Figure 4G for Figure 4D The bottom view of the structure shown.

[0020] Figure 4H This is a cross-sectional schematic diagram of the combined structure of the chip assembly, the first substrate, the mask, and the insulating component in a method for manufacturing a power module according to an embodiment of the present invention.

[0021] Figure 4I for Figure 4H The diagram shows a working state of the power module obtained after removing the mask from the structure shown.

[0022] Figure 5 This is a schematic cross-sectional view of a process structure in another method for manufacturing a power module provided in an embodiment of the present invention, in which a heat sink is used as a mask.

[0023] Figures 6A to 6D This is a schematic cross-sectional view of a method for providing a chip assembly according to an embodiment of the present invention.

[0024] Figures 7A to 7E This is a schematic cross-sectional view of a method for providing a chip assembly according to another embodiment of the present invention.

[0025] Figure 8A This is a structural cross-sectional schematic diagram of a power module provided for other embodiments of the present invention.

[0026] Figure 8B This is a cross-sectional view of another power module provided for other embodiments of the present invention.

[0027] Figure 9A This is a cross-sectional view of another power module provided for other embodiments of the present invention.

[0028] Figure 9B This is a cross-sectional view of another power module provided for other embodiments of the present invention.

[0029] Figure 9C This is a cross-sectional view of another power module provided for other embodiments of the present invention.

[0030] Figure 9D This is a cross-sectional view of yet another power module provided for other embodiments of the present invention.

[0031] Figures 10A to 10C This is a cross-sectional schematic diagram of multiple process structures in a method for manufacturing a power module provided in other embodiments of the present invention.

[0032] Figure 10D In order to be in Figure 10C A schematic cross-sectional view of the structure after a nickel plating layer is formed on the basis shown.

[0033] Figure 10E In order to be in Figure 10D A schematic cross-sectional view of the structure after the encapsulation is formed based on the structure shown.

[0034] [Explanation of Key Figure Markings] 10. Power module; 11. First substrate; 111. Insulating substrate; 111T, 111B. Surface of insulating substrate; 113. Conductive layer; 113T, 113B. Surface of conductive layer; 115. Heat dissipation layer; 115T, 115B. Surface of heat dissipation layer; TH. Through hole; TH1. First through hole; HS1. Hole wall of first through hole; TH2. Second through hole; HS2. Hole wall of second through hole; 13. Chip assembly; 131. Chip; 131B. Bottom surface of chip; 131T. Top surface of chip; S. First power electrode pad; G. Control electrode pad; D. Second power electrode pad; 132. Connecting layer; 1320. Sintered material layer; 133. Insulating layer; 133T. Upper surface of insulating layer; 133B. 133E, Lower surface of the insulating layer; CA, Cooling zone; 15, Insulator; 15B, End face of the insulating component; 17, Connecting ring; 17S, Inner ring sidewall of the connecting ring; 18a, First metal layer; 18b, Second metal layer; 19, Heat sink; 19T, 19B, Surface of the heat sink; 190, Heat dissipation channel; A1, First direction; M1, Mask; CL, Cooling fluid; 1310, Semiconductor wafer; 1330, Insulating material layer; 130, Initial chip assembly; M2, Mask layer; 21, Connecting material; 23, Nickel plating layer; 25, Solder layer; 27, Sintered layer; 31, Second substrate; 311, Insulating substrate; 313, 315, Metal layer; 3150, Protrusion; 40, Package. Detailed Implementation

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0038] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0039] See Figure 1A The present invention provides a power module 10, which includes, for example, a first substrate 11, a chip assembly 13 and an insulating member 15.

[0040] The first substrate 11 includes an insulating substrate 111 and a conductive layer 113 disposed on the insulating substrate 111. The first substrate 11 has a through-hole TH penetrating the conductive layer 113 and the insulating substrate 111. For example, the insulating substrate 111 may be a ceramic material such as silicon nitride, and the conductive layer 113 may be a metal material such as copper, but the embodiments of the present invention are not limited thereto.

[0041] The chip assembly 13 includes a chip 131 and an insulating layer 133. The chip 131 is disposed on the conductive layer 113 and has a bottom surface 131B facing the conductive layer 113. The insulating layer 133 is disposed on the bottom surface 131B of the chip 131 and covers a portion of the bottom surface 131B of the chip 131. The insulating layer 133 extends at least partially into the via TH. For example, the chip 131 may be an insulated gate bipolar transistor (IGBT) or a SiC metal-oxide-semiconductor field-effect transistor (MOSFET), and the insulating layer 133 may be an insulating material with high thermal conductivity, such as aluminum nitride, silicon nitride, or aluminum oxide. However, the embodiments of the present invention are not limited thereto. In some embodiments, the insulating layer 133 is specifically disposed on the bottom surface 131B of the chip 131 by means of welding or sintering. Of course, in other embodiments, the insulating layer 133 can also be fixed to the bottom surface 131B of the chip 131 by other connection methods. The insulating layer 133 may cover the middle portion of the bottom surface 131B of the chip 131 but not the edge. Alternatively, the insulating layer 133 may cover a portion of the middle portion and a portion of the edge of the bottom surface 131B of the chip 131, or it may cover only a portion of the bottom surface 131B of the chip 131. This embodiment of the invention does not limit the scope of the invention. It is worth mentioning that in some embodiments, for example... Figure 1B As shown, the insulating layer 133 can also be made of other insulating materials such as diamond (e.g., single-crystal diamond) to achieve ultra-high thermal conductivity. Simultaneously, diamond's electrical insulation properties provide excellent insulation. In other words, in some embodiments, the insulating layer 133 is made of diamond (e.g., single-crystal diamond). When the insulating layer 133 is made of diamond, it can also be referred to as a diamond layer (e.g., a single-crystal diamond layer). In some embodiments, for example... Figure 1BAs shown, the chip assembly 13 may include the chip 131, the insulating layer 133, and the interconnect layer 132. The insulating layer 133 (e.g., a diamond layer, an aluminum nitride layer, a silicon nitride layer, or an aluminum oxide layer) is fixed to the bottom surface 131B of the chip 131 via the interconnect layer 132. The interconnect layer 132 also connects the surface 113T of the conductive layer 113 facing away from the insulating substrate 111 and the end face of the insulating member 15 facing the chip 131. For example, the interconnect layer 132 may be a sintered layer. In other words, the insulating layer 133 (e.g., a diamond layer, an aluminum nitride layer, a silicon nitride layer, or an aluminum oxide layer) may be sintered and fixed to the bottom surface 131B of the chip 131 via a preform sintering material layer, a sintering paste layer, or a pre-sintering foil. Furthermore, it is understood that in some embodiments, without damaging the chip 131 (e.g., <400°C), a reactive metal interlayer (such as Ti, Cr, Ni, etc.) can be used to form a robust interface between the insulating layer 133 (e.g., diamond layer, aluminum nitride layer, silicon nitride layer, or aluminum oxide layer) and the chip 131 as the connection layer 132.

[0042] The insulating element 15 is disposed within the through-hole TH and seals the insulating layer 133 and the insulating substrate 111. At least a portion of the lower surface 133B of the insulating layer 133, facing away from the chip 131, is not covered by the insulating element 15. This uncovered portion of the lower surface 133B of the insulating layer 133 is configured as a cooling zone CA. The sealing connection of the insulating layer 133 and the insulating substrate 111 by the insulating element 15 can be understood as: the insulating element 15 is sealed to the insulating layer 133 and also sealed to the insulating substrate 111. Figure 1A and Figure 1B In the illustrated embodiment, since the insulating element 15 seals the insulating layer 133 and the insulating substrate 111, the conductive layer 113 and the chip 131 are electrically insulated from the cooling zone CA through the insulating element 15. For example, the insulating element 15 can be made of insulating materials such as epoxy resin, molded compound, high-density polyethylene (HDPE), or magnesium oxide, but the embodiments of the present invention are not limited thereto.

[0043] As can be seen from the above, the power module 10 in this embodiment, by providing a through-hole TH on the first substrate 11, extending at least part of the insulating layer 133 disposed on the bottom surface 131B of the chip 131 into the through-hole TH, and using an insulating member 15 to seal and connect the insulating layer 133 to the insulating substrate 111 of the first substrate 11, exposing at least part of the lower surface 133B of the insulating layer 133 facing away from the chip 131, allows the chip 131 to be cooled directly by cooling fluid through the insulating layer 133. This reduces the thermal resistance elements on the heat dissipation path of the chip 131, improving the heat dissipation effect. Moreover, thanks to the improved heat dissipation effect, the size of the chip 131 can be designed to be smaller. Furthermore, the use of the insulating layer 133 can reduce the performance requirements of the first substrate, which can be used only for mechanical support and electrical connection, thereby achieving cost reduction of the power module 10. In addition, compared with the prior art, the power module 10 of this embodiment does not need to weld the heat sink to the entire back surface of the first substrate 11, thus shortening the assembly time.

[0044] In some embodiments, see Figure 1A and Figure 1B The via TH includes, for example, a first via TH1 penetrating the conductive layer 113 and a second via TH2 penetrating the insulating substrate 111 and communicating with the first via TH1. The insulating member 15 is sealed to the hole wall HS1 of the first via TH1, thereby achieving electrical insulation between the conductive layer 113 and the cooling zone CA, or between the conductive layer 113 and the cooling fluid flowing through the cooling zone CA. Exemplarily, in the first direction A1 from the conductive layer 113 to the insulating substrate 111, the end face of the insulating member 15 facing the chip 131 is flush with the surface 113T of the conductive layer 113 facing away from the insulating substrate 111, which further improves the sealing effect and thus achieves better electrical insulation.

[0045] In some embodiments, see Figure 1A To further improve the electrical insulation effect, the insulating member 15 can also be sealed to the periphery 133E of the lower surface 133B of the insulating layer 133. Here, the periphery of the lower surface 133B can be understood as the peripheral edge of the lower surface 133B. For example, when the lower surface 133B is circular or square, the periphery of the lower surface 133B can refer to the circumferential edge of the lower surface 133B. It is understood that in other embodiments, the insulating member 15 can also only seal the side surface of the insulating layer 133, exposing the entire lower surface 133B of the insulating layer 133 (e.g., Figure 1B (As shown).

[0046] In some embodiments, see Figure 1A The insulating element 15 can also be connected to the hole wall HS2 of the second through hole TH2 (e.g., Figure 1A The portion of the hole wall HS2 shown, or Figure 2A and Figure 2B The entire hole wall HS2 shown is sealed to further ensure the electrical insulation effect between the conductive layer 113 and the cooling zone CA.

[0047] In some embodiments, see Figure 1A The through-hole TH is a stepped hole, and the opening size of the first through-hole TH1 is larger than the opening size of the second through-hole TH2. The opening size of the first through-hole TH1 can also be understood as the diameter of the first through-hole TH1, and the opening size of the second through-hole TH2 can also be understood as the diameter of the second through-hole TH2. In this way, the adhesion of the insulating component 15 in the through-hole TH can be improved.

[0048] In some embodiments, see Figure 1A The power module 10, for example, further includes a connecting ring 17, which surrounds the insulating layer 133 and connects the area of ​​the bottom surface 131B of the chip 131 not covered by the insulating layer 133 to the conductive layer 113. The connecting ring 17 surrounding the insulating layer 133 can be understood as the connecting ring 17 being sleeved on the insulating layer 133, or it can be understood as the connecting ring 17 being arranged around the insulating layer 133. Figure 4B and Figure 4C As shown, when the chip 131 is a vertical chip, the chip 131 has a top surface 131T facing away from the first substrate 11 and a bottom surface 131B facing the conductive layer 113. The top surface 131T of the chip 131 is provided with a first power electrode pad S and a control electrode pad G. The bottom surface 131B of the chip 131 is provided with a second power electrode pad D. The second power electrode pad D is at least partially not covered by the insulating layer 133. The portion of the second power electrode pad D not covered by the insulating layer 133 is connected to the connecting ring 17 to be electrically connected to the conductive layer 113 of the first substrate 11. That is, the connecting ring 17 simultaneously realizes the mechanical connection and electrical connection between the chip 131 and the conductive layer 113. Furthermore, it is understood that in other embodiments, the chip 131 may also be a lateral chip, with the second power electrode pad D disposed on the top surface 131T of the chip 131 accordingly; in this case, the connecting ring 17 mainly realizes the mechanical connection between the chip 131 and the conductive layer 113, rather than the electrical connection, and the conductive layer 113 and the chip 131 can be electrically connected by wire bonding. It is also worth mentioning that, as Figure 1BIn some embodiments shown, the peripheral portion of the connection layer 132 (corresponding to the portion of the bottom surface 131B of the chip 131 not covered by the insulating layer 133) can function as the connection ring 17, that is, as Figure 1B In some embodiments shown, the connecting layer 132 not only connects the insulating layer 133 and the bottom surface 131B of the chip 131 to fix the insulating layer 133 to the bottom surface 131B of the chip, but also connects the surface 113T of the conductive layer 113 facing away from the insulating substrate 111 and the area of ​​the bottom surface 131B of the chip 131 that is not covered by the insulating layer 133, so as to realize the mechanical connection between the chip 131 and the conductive layer 113, or simultaneously realize the mechanical connection and electrical connection between the chip 131 and the conductive layer 113.

[0049] In some embodiments, see Figure 1A and Figure 2A-2B The via TH includes a first via TH1 penetrating the conductive layer 113 and a second via TH2 penetrating the insulating substrate 111 and communicating with the first via TH1; the surface portion of the connecting ring 17 facing the first substrate 11 is exposed to the first via TH1, and the insulating member 15 is sealed to the portion of the connecting ring 17 facing the first substrate 11 exposed to the first via TH1, the hole wall HS1 of the first via TH1, the hole wall HS2 of the second via TH2, and the periphery 133E of the lower surface 133B of the insulating layer 133; thereby better achieving electrical insulation between the conductive layer 113 and the connecting ring 17 and the cooling zone CA.

[0050] As described above, in the first direction A1 from the conductive layer 113 to the insulating substrate 111, the end face 15B of the insulating member 15 facing away from the chip 131 is located between the surface 111T of the insulating substrate 111 facing the conductive layer 113 and the surface 111B of the insulating substrate 111 facing away from the conductive layer 113 (e.g., Figure 1A and Figure 1B (as shown), or the end face 15B of the insulating member 15 facing away from the chip 131 is flush with the surface 111B of the insulating substrate 111 facing away from the conductive layer 113 (as shown). Figure 2A and Figure 2B (As shown). Furthermore, for example, Figure 1A , Figure 2A and Figure 2B As shown, the lower surface 133B of the insulating layer 133 is located in the first direction A1 between the surface 113T of the conductive layer 113 facing away from the insulating substrate 111 and the surface 113B of the conductive layer 113 facing the insulating substrate 111. Furthermore, for example... Figure 1A , Figure 2Aand Figure 2B As shown, the periphery of the bottom surface 131B of the chip 131 is not covered by the insulating layer 133. The connecting ring 17 is connected between the periphery of the bottom surface 131B of the chip 131 and the conductive layer 113. The inner ring sidewall 17S of the connecting ring 17 is attached to the insulating layer 133.

[0051] In some embodiments, see Figures 2A-3 and Figures 8A-9D The power module 10 further includes, for example, a heat sink 19 connected to the portion of the lower surface 133B of the insulating layer 133 not covered by the insulating member 15. For example, such as... Figures 2A to 3 As shown, the heat sink 19 is partially or entirely disposed within the through hole TH, or, as... Figures 8A to 9D As shown, the heat sink 19 is located outside the through hole TH. In this embodiment, the heat sink 19 is provided to further improve the heat dissipation effect of the power module 10. As an example, the heat sink 19 can be a heat sink fin, a heat sink column, a heat sink pin, or a nickel-copper tube, etc., but the embodiments of the present invention are not limited thereto.

[0052] In some embodiments, see Figure 2A and Figure 2B The surface 19B of the heat sink 19 facing away from the insulating layer 133 is located on the side of the insulating substrate 111 facing away from the conductive layer 113 in a first direction A1 from the conductive layer 113 to the insulating substrate 111. In this way, the heat sink 19 can be exposed to a higher cooling fluid flow rate, thereby further improving the heat dissipation effect.

[0053] In some embodiments, see Figure 2A The heat sink 19 has a heat dissipation channel 190 that extends from the surface 19T of the heat sink 19 near the insulating layer 133 to the surface 19B of the heat sink 19 away from the insulating layer 133, and is, for example, a nickel-copper tube. In this way, cooling fluid can directly contact the insulating layer 133 through the heat dissipation channel 190 to cool the chip 131, thereby improving the cooling effect. Furthermore, to improve the connection strength of the heat sink 19, in some embodiments, such as... Figure 2BAs shown, the end of the heat dissipation channel 190 near the insulating layer 133 is a closed end, and the end of the heat dissipation channel 190 away from the insulating layer 133 is an open end. Alternatively, the heat sink 19 has a metal base at the closed end of the heat dissipation channel 190. In this way, cooling fluid can form thermal contact with the insulating layer 133 through the heat dissipation channel 190 to cool the chip 131. The aforementioned closed end near the insulating layer 133 and open end of the heat dissipation channel 190 can be exemplarily understood as follows: the heat dissipation channel 190 penetrates the surface 19B of the heat sink 19 away from the insulating layer 133, but does not penetrate the surface 19T of the heat sink 19 near the insulating layer 133.

[0054] In some embodiments, see Figure 2A and 2B The insulating member 15 surrounds the heat sink 19 and is in contact with the outer side wall 19S of the heat sink 19. In this way, the stability of the heat sink 19 within the through hole TH can be improved.

[0055] In some embodiments, see Figure 3The first substrate 11 further includes, for example, a heat dissipation layer 115, which is located on the side of the insulating substrate 111 facing away from the conductive layer 113, and the via TH also penetrates the heat dissipation layer 115; in this way, the heat dissipation effect of the power module can be further improved. Furthermore, in the first direction A1 from the conductive layer 113 to the insulating substrate 111, the end face 15B of the insulating member 15 facing away from the chip 131 is located between the surface 111T of the insulating substrate 111 facing the conductive layer 113 and the surface 115B of the heat dissipation layer 115 facing away from the insulating substrate 111; in this way, the electrical insulation effect between the conductive layer 113 and the cooling zone CA can be improved. In addition, the lower surface 133B of the insulating layer 133 is located in the first direction A1 between the surface 113T of the conductive layer 113 facing away from the insulating substrate 111 and the surface 113B of the conductive layer 113 facing the insulating substrate 111. In addition, the power module also includes a heat sink 19, which is disposed within the through hole TH and connected to the portion of the lower surface 133B of the insulating layer 133 that is not covered by the insulating member 15. The surface 19B of the heat sink 19 facing away from the insulating layer 133 is located in the first direction A1 between the surface 115T of the heat sink 115 facing the insulating substrate 111 and the surface 115B of the heat sink 115 facing away from the insulating substrate 111. The provision of the heat sink 19 is beneficial to improving the heat dissipation effect of the power module. As an example, the heat sink 19 can be a heat sink fin, a heat sink column, a heat sink pin, or a Ni-Cu tube, but the present invention is not limited thereto.

[0056] In some embodiments, the thermal resistivity of the insulating layer 133 is lower than that of the insulating element 15. By employing an insulating layer 133 with lower thermal resistivity, the overall thermal resistance along the heat dissipation path of the chip 131 can be reduced, thereby improving heat dissipation performance.

[0057] To better understand the embodiments of the present invention, the following will be combined with Figures 4A to 4I For example, the above Figure 1A The power module 10 shown is manufactured in one of the following steps: a, b and c.

[0058] See Figure 4AStep a: Provide a first substrate 11. The first substrate 11 includes, for example, an insulating substrate 111 and a conductive layer 113 disposed on the insulating substrate 111. The first substrate 11 has a through-hole TH penetrating the conductive layer 113 and the insulating substrate 111. The through-hole TH includes, for example, a first through-hole TH1 penetrating the conductive layer 113 and a second through-hole TH2 penetrating the insulating substrate 111 and communicating with the first through-hole TH1.

[0059] See Figure 4B , Figure 4C and Figure 4D Step b: Provide a chip assembly 13 and dispose of the chip assembly 13 on the first substrate 11. The chip assembly 13 includes a chip 131 and an insulating layer 133. The chip 131 is disposed on the conductive layer 113 and has a bottom surface 131B facing the conductive layer 113. The insulating layer 133 is disposed on the bottom surface 131B of the chip 131 and covers a portion of the bottom surface 131B of the chip 131. The insulating layer 133 at least partially extends into the via TH. Furthermore, from... Figure 4B and Figure 4C It can be understood that the chip 131 is, for example, a vertical chip, with a first power electrode pad S and a control electrode pad G disposed on its top surface 131T, and a second power electrode pad D disposed on its bottom surface 131B. The second power electrode pad D is at least partially not covered by the insulating layer 133; the portion of the second power electrode pad D not covered by the insulating layer 133 is connected to the conductive layer 113 of the first substrate 11, for example, through a connecting ring 17. Furthermore, Figure 4E , Figure 4F and Figure 4G The relative positions of the insulating substrate 111 and conductive layer 113, the connecting ring 17, the chip 131 and the insulating layer 133 of the first substrate 11 are illustrated from different perspectives.

[0060] See Figure 4HStep c: An insulating element 15 is disposed within the via TH and the insulating layer 133 and the insulating substrate 111 are sealed together. The lower surface 133B of the insulating layer 133, facing away from the chip 131, is at least partially not covered by the insulating element 15, and the portion of the lower surface 133B of the insulating layer 133 not covered by the insulating element 15 is configured as a cooling zone CA. For example, disposing the insulating element 15 within the via TH and sealing the insulating layer 133 and the insulating substrate 111 may specifically include: (a) forming a mask M1 on the lower surface 133B of the insulating layer 133 within the via TH to define the cooling zone CA of the lower surface 133B of the insulating layer 133; and (b) after forming the mask M1, injecting an insulating filler material into the via TH and sealing the insulating layer 133 and the insulating substrate 111 to obtain the insulating element 15. The insulating filler material here may be, for example, epoxy resin, molding compound, high-density polyethylene, or magnesium oxide, but the embodiments of the present invention are not limited thereto.

[0061] After forming the insulating element 15 within the through-hole TH, the mask M1 is removed to obtain the power module 10, as shown below. Figure 4I As shown, the manufactured power module can be cooled by the cooling fluid CL during operation.

[0062] It is worth mentioning that, in some embodiments, see Figure 5 The heat sink 19 can be directly used as the mask M1, thus eliminating the need for the mask removal step. As an illustrative embodiment, such as... Figure 5 As shown, the heat sink 19 is connected to the portion of the lower surface 133B of the insulating layer 133 that is not covered by the insulating member 15, and has a heat dissipation channel 190. The heat dissipation channel 190 passes through the surface 19T of the heat sink 19 near the insulating layer 133 and the surface 19B of the heat sink 19 away from the insulating layer 133. The heat sink 19 is, for example, a nickel-copper tube; or as... Figure 2B As shown, the end of the heat dissipation channel 190 near the insulating layer 133 is a closed end, and the end of the heat dissipation channel 190 away from the insulating layer 133 is an open end. Furthermore, it is worth mentioning that in other embodiments, the heat sink 19 may be attached to the insulating layer 133 during the step of providing the chip assembly 13, in order to achieve better thermal contact between the heat sink 19 and the insulating layer 133.

[0063] In some embodiments, please refer to Figure 4DThe aforementioned manufacturing method further includes, for example, the step of: setting a connecting ring 17, wherein the connecting ring 17 surrounds the insulating layer 133 and connects the area of ​​the bottom surface 131B of the chip 131 not covered by the insulating layer 133 and the conductive layer 113. As an example, the step of setting the connecting ring may specifically include: (1) forming an annular pre-formed sintering material layer between the area of ​​the bottom surface 131B of the chip 131 not covered by the insulating layer 133 and the conductive layer 113; and (2) sintering the annular pre-formed sintering material layer together with the first substrate 11 and the chip assembly 13 to obtain, as shown in the figure. Figure 4D The connecting ring 17 is shown. The annular preformed sintered material layer here can be made of conductive paste, such as silver paste.

[0064] In addition, the following will combine Figures 6A to 6D and Figures 7A to 7E Two specific implementations of the steps of providing chip component 13 are illustrated by example.

Detailed Implementation Method 1

[0066] See Figure 6B An insulating material layer 1330 is formed on the first side of the semiconductor wafer 1310 to obtain a wafer assembly. The insulating material layer 1330 can be an insulating material with high thermal conductivity, such as aluminum nitride, silicon nitride, or aluminum oxide. Taking a vertical chip 131 as an example, the first side of the semiconductor wafer 1310 can be the side where the second power electrode pad D is located.

[0067] See Figure 6C The wafer assembly is then divided into multiple initial chip assemblies 130. The dicing method may include sawing, laser cutting, or plasma dicing.

[0068] See Figure 6D A portion of the insulating material layer 1330 of a single initial chip assembly 130 is etched away to obtain the chip assembly 13, wherein the remaining portion of the insulating material layer 1330 of the single initial chip assembly 13 serves as the insulating layer 133. This etching can be performed using wet etching or dry etching.

Detailed Implementation Method Two

[0070] See Figure 7B A mask layer M2 is disposed on the first side of the semiconductor wafer 1310. Taking the chip 131 as a vertical chip as an example, the first side of the semiconductor wafer 1310 may be the side where the second power electrode pad D is located. The material of the mask layer M2 may be different from that of the semiconductor wafer 1310, such as silicon.

[0071] See Figure 7C An insulating material layer is deposited as the insulating layer 133 on the first side of the semiconductor wafer 1310 on which the mask layer M2 is disposed. The insulating material layer 1330 here can be an insulating material with a high thermal conductivity, such as aluminum nitride, silicon nitride, or aluminum oxide.

[0072] See Figure 7D The mask layer M2 is then removed to obtain the wafer assembly. This removal can be done using either wet etching or dry etching.

[0073] See Figure 7E The wafer assembly is divided into multiple chip assemblies 13.

[0074] Additionally, in some embodiments, see Figure 8AThe first substrate 11 further includes a heat dissipation layer 115, and the power module further includes a heat sink 19. The heat dissipation layer 115 is located on the side of the insulating substrate 111 opposite to the conductive layer 113, and the via TH also penetrates the heat dissipation layer 115. A first metal layer 18a, such as a copper layer, is provided on the lower surface 133B of the insulating layer 133 opposite to the chip 131. The end face of the heat sink 19 facing the insulating layer 133 is connected to the insulating layer 133 through the first metal layer 18a, and the edge of the end face of the heat sink 19 facing the insulating layer 133 overlaps with the surface 115T of the heat dissipation layer 115 opposite to the insulating substrate 111. The heat sink 19 can be laser-welded or ultrasonically welded to the first metal layer 18a, thereby improving the connection stability of the heat sink 19. Furthermore, the insulating layer 133 is a material with high thermal conductivity, and its thermal conductivity is, for example, higher than that of the insulating substrate 111. Furthermore, the heat sink 19 can be a heat sink fin, heat sink column, heat sink pin, or nickel-copper tube, etc., but the embodiments of the present invention are not limited thereto. For example, when the heat sink 19 is a nickel-copper tube, it has a heat dissipation channel 190, the end of the heat dissipation channel 190 near the insulating layer 133 is a closed end, and the end of the heat dissipation channel 190 away from the insulating layer is an open end, or in other words, the heat sink 19 has a metal base, such as a copper base, at the closed end of the heat dissipation channel 190. Furthermore, in Figure 8A In the specific embodiment shown, in the first direction A1 from the conductive layer 113 to the insulating substrate 111, the end face of the insulating member 15 facing away from the chip 131 is, for example, flush with the surface 115B of the heat dissipation layer 115 facing away from the insulating substrate 111, thereby abutting the end face of the heat dissipation member 19 facing the insulating layer 133; the surface of the first metal layer 18a facing away from the insulating layer 133 is located at the surface 115T of the heat dissipation layer 115 facing the insulating substrate 111 and the surface of the heat dissipation layer 115 facing away from the insulating substrate 111. Between 115B, even in the first direction A1, the surface 115B of the heat dissipation layer 115 facing away from the insulating substrate 111 is flush with the surface 113T of the conductive layer 113 facing away from the insulating substrate 111; and the insulating element 15 is sealed to the conductive layer 113, the insulating substrate 111, the heat dissipation layer 115, the insulating layer 133 and the first metal layer 18a respectively, and the periphery of the bottom surface 131B of the chip 131 is not covered by the insulating layer 133.

[0075] In some embodiments, see Figure 8BThe insulating layer 133 has a second metal layer 18b, such as a copper layer, on its upper surface 133T facing the chip 131. The power module also includes a connecting ring 17, which surrounds the second metal layer 18b and connects the area of ​​the bottom surface 131B of the chip 131 not covered by the second metal layer 18b to the conductive layer 113. By providing the second metal layer 18b, the connection stability of the insulating layer 133 is improved.

[0076] In some embodiments, see Figure 9A and Figure 9B The power module includes, for example, a second substrate 31. The second substrate 31 is electrically connected to electrode pads disposed on the top surface 131T of the chip 131 away from the insulating layer 133 via a connecting material 21. The second substrate 31 improves mechanical stability and electrically connects the electrode pads, such as source pads and / or gate pads, disposed on the top surface 131T of the chip 31 to the leadframe. More specifically, the connecting material 21 is, for example, a conductive paste such as silver paste, and the second substrate 31 is, for example, a multilayer substrate, including, for example, an insulating substrate 311 and metal layers 313 and 315, such as copper layers, disposed on opposite sides of the insulating substrate 311. Thus, the second substrate 31 can be electrically connected to the electrode pads disposed on the top surface 131T of the chip 131 away from the insulating layer 133 via protrusions 3150 disposed facing the metal layer 315 of the first substrate 11 and the connecting material 21. It is understood that in other embodiments, the second substrate 31 may also be replaced with a copper clip structure.

[0077] In some embodiments, see Figure 9C The first substrate 11 further includes a heat dissipation layer 115, and the power module, in addition to the heat dissipation element 19, also includes a soldering layer 25; the heat dissipation layer 115 is located on the side of the insulating substrate 111 opposite to the conductive layer 113, and the via TH (reference) Figure 9AThe insulating layer 133, on its lower surface 133B facing away from the chip 131, is provided with a first metal layer 18a, such as a copper layer. The end face of the heat sink 19 facing the insulating layer 133 is connected to the insulating layer 133 via the first metal layer 18a. Specifically, the end face of the heat sink 19 facing the insulating layer 133 is fixed to the first metal layer 18a via the solder layer 25 to connect with the insulating layer 133, and the solder layer 25 overlaps the surface of the heat sink 115 facing away from the insulating substrate 111. Furthermore, the surface of the heat sink 115 facing away from the insulating substrate 111, the side surface of the solder layer 25, and the exposed surface of the heat sink 19 are further plated with a nickel layer 23, for example, by a nickel plating process, thereby effectively protecting the heat sink 115, the solder layer 25, etc., from damage.

[0078] In some embodiments, see Figure 9D The first substrate 11 further includes a heat dissipation layer 115, and the power module, in addition to the heat dissipation element 19, also includes a sintered layer 27, such as a silver sintered layer; the heat dissipation layer 115 is located on the side of the insulating substrate 111 opposite to the conductive layer 113, and the via TH (reference) Figure 9A The heat sink 19 also extends through the heat dissipation layer 115; the end face of the heat sink 19 facing the insulating layer 133 is fixed to the lower surface 133B of the insulating layer 133 away from the chip 131 via the sintering layer 27, and the sintering layer 27 overlaps the surface of the heat dissipation layer 115 away from the insulating substrate 111. Furthermore, the surface of the heat dissipation layer 115 away from the insulating substrate 111, the side surface of the portion of the sintering layer 27 outside the via TH, and the exposed surface of the heat sink 19 are further plated with a nickel layer 23, for example, by a nickel plating process, thereby effectively protecting the heat dissipation layer 115, the sintering layer 27, etc., from damage.

[0079] See Figures 10A-10C This invention also provides an exemplary description of a method for fabricating a power module using a diamond layer (e.g., a single-crystal diamond layer) as an insulating layer 133. Specifically, the fabrication method of this embodiment is related to the foregoing. Figure 1A The manufacturing method of the power module 10 shown is basically the same, including: step a, providing a first substrate 11; step b, providing a chip assembly 13 and placing the chip assembly 13 on the first substrate 11; and step c, placing an insulating member 15 in the through hole TH and sealingly connecting the insulating layer 133 and the insulating substrate 111. The main difference is in the specific details of step b, for example, step b may include the following sub-steps b1, b2 and b3.

[0080] Sub-step b1: The chip 131 is fixed to the second substrate 31 using the connecting material 21. Taking a vertical chip as an example, its top surface 131T is provided with a first power electrode pad S and a control electrode pad G, and its bottom surface 131B is provided with a second power electrode pad D (see reference). Figure 4B and Figure 4C The metal layer 315 of the second substrate 31, for example, a thick copper layer, has multiple electrode pad connection areas for connecting the first power electrode pad S and the control electrode pad G of the chip 131. By coating these electrode pad connection areas with conductive paste as the sintering material and then performing a sintering process, the coated conductive paste can be converted into the connection material 21, thereby fixing the chip 131 to the second substrate 31. Figure 10A As shown.

[0081] Sub-step b2: The insulating layer 133 (i.e., the diamond layer) is disposed on the side of the chip 131 opposite to the second substrate 31 by sintering the material layer 1320 (see again). Figure 10A As shown, the sintering material layer 1320 can be a pre-formed sintering material layer. It is worth noting that, to ensure the diamond layer does not shift before sintering, an adhesive can be used to temporarily fix the diamond layer onto the sintering material layer 1320. It is understood that in other embodiments, the sintering material layer 1320 can also be a sintering paste layer, such as a conductive silver paste layer; or, the sintering material layer 1320 can be a pre-sintered foil, which can directly integrate the diamond layer, and in this case, the pick-up and place-down operations of the foil will be simpler.

[0082] Sub-step b3: After the insulating layer 133 extends at least partially into the through-hole TH of the first substrate 11, sintering is performed, for example, pressure sintering or pressureless sintering, to transform the sintered material layer 1320 into a connection layer 132 that fixes the chip 131 to the conductive layer 113 and the insulating layer 133, such as... Figure 10B As shown.

[0083] As for step c: placing the insulating element 15 inside the through hole TH and sealing the insulating layer 133 and the insulating substrate 111, the process structure can be referred to Figure 10C As shown, for details of the process, please refer to the aforementioned... Figure 4H The relevant descriptions will not be repeated here.

[0084] As stated above, see also Figure 10DAfter the insulating element 15 is formed within the via TH, the mask M1 is removed to obtain the power module. Furthermore, to prevent the heat dissipation layer 115 from being damaged by cooling fluid during subsequent operation of the power module, the power module is further provided with a nickel plating layer 23. This nickel plating layer 23 at least covers the surface of the heat dissipation layer 115 facing away from the insulating substrate 111 and exposes at least a portion of the lower surface of the insulating layer 133 facing away from the chip 131. For example, in... Figure 10D In this embodiment, nickel plating 23 covers the surface of the heat dissipation layer 115 away from the insulating substrate 111, the hole wall of the through hole TH not covered by the insulating member 15, and the end face of the insulating member 15 away from the chip 131, but the embodiments of the present invention are not limited thereto.

[0085] In some embodiments, see Figure 10E The power module in this embodiment of the invention also includes a package 40. The package 40 is used, for example, to encapsulate the chip assembly 13, the first substrate 11, and the second substrate 31, and exposes at least a portion of the nickel plating layer 23 and the lower surface of the insulating layer 133, and at least a portion of the surface of the metal layer 313 of the second substrate 31 facing away from the insulating substrate 311. During operation, the packaged power module can be cooled by a cooling fluid CL.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A power module, characterized in that, include: A first substrate includes an insulating substrate and a conductive layer disposed on the insulating substrate, wherein the first substrate has a through-hole penetrating the conductive layer and the insulating substrate; A chip assembly includes a chip and an insulating layer, the chip being disposed on the conductive layer and having a bottom surface facing the conductive layer, the insulating layer being disposed on the bottom surface of the chip and covering a portion of the bottom surface of the chip, the insulating layer extending at least partially into the via; as well as An insulating element is disposed within the through-hole and sealably connects the insulating layer and the insulating substrate, wherein at least a portion of the lower surface of the insulating layer facing away from the chip is not covered by the insulating element, and the portion of the lower surface of the insulating layer not covered by the insulating element is configured as a cooling zone.

2. The power module according to claim 1, characterized in that, The via includes a first via penetrating the conductive layer and a second via penetrating the insulating substrate and connected to the first via; The insulating element is sealed to the wall of the second through hole, and / or the insulating element is sealed to the wall of the first through hole, and / or the insulating element is sealed to the periphery of the lower surface of the insulating layer.

3. The power module according to claim 2, characterized in that, The through hole is a stepped hole, and the opening size of the first through hole is larger than the opening size of the second through hole.

4. The power module according to claim 1, characterized in that, It also includes a connecting ring, which surrounds the insulating layer and connects the area on the bottom surface of the chip that is not covered by the insulating layer to the conductive layer.

5. The power module according to claim 4, characterized in that, The via includes a first via penetrating the conductive layer and a second via penetrating the insulating substrate and communicating with the first via; the surface portion of the connecting ring facing the first substrate is exposed to the first via, and the insulating member is sealed to the exposed portion of the surface portion of the connecting ring facing the first substrate, the wall of the first via, the wall of the second via, and the periphery of the lower surface of the insulating layer. In a first direction from the conductive layer to the insulating substrate, the end face of the insulating element facing away from the chip is located between the surface of the insulating substrate facing the conductive layer and the surface of the insulating substrate facing away from the conductive layer, or the end face of the insulating element facing away from the chip is flush with the surface of the insulating substrate facing away from the conductive layer. The lower surface of the insulating layer is located in the first direction between the surface of the conductive layer facing away from the insulating substrate and the surface of the conductive layer facing the insulating substrate; The periphery of the bottom surface of the chip is not covered by the insulating layer. The connecting ring is connected between the periphery of the bottom surface of the chip and the conductive layer. The inner ring sidewall of the connecting ring is attached to the insulating layer.

6. The power module according to claim 1, characterized in that, It also includes a heat sink, which is connected to the portion of the lower surface of the insulating layer that is not covered by the insulating layer.

7. The power module according to claim 6, characterized in that, The surface of the heat sink that faces away from the insulating layer is located on the side of the insulating substrate facing away from the conductive layer in a first direction from the conductive layer to the insulating substrate; and / or, The heat sink has a heat dissipation channel that extends through the surface of the heat sink near the insulating layer and the surface of the heat sink away from the insulating layer; or, one end of the heat dissipation channel near the insulating layer is a closed end, and the other end of the heat dissipation channel away from the insulating layer is an open end; and / or, The insulating element surrounds the heat sink and is attached to the outer side wall of the heat sink.

8. The power module according to claim 6, characterized in that, The first substrate further includes a heat dissipation layer, which is located on the side of the insulating substrate opposite to the conductive layer, and the via also penetrates the heat dissipation layer; In a first direction from the conductive layer to the insulating substrate, the end face of the insulating element facing away from the chip is located between the surface of the insulating substrate facing the conductive layer and the surface of the heat dissipation layer facing away from the insulating substrate. The lower surface of the insulating layer is located in the first direction between the surface of the conductive layer facing away from the insulating substrate and the surface of the conductive layer facing the insulating substrate; The heat sink is located within the through hole, and the surface of the heat sink away from the insulating layer is located in the first direction between the surface of the heat sink facing the insulating substrate and the surface of the heat sink away from the insulating substrate.

9. The power module according to claim 4, characterized in that, The chip has a top surface facing away from the first substrate. The top surface of the chip is provided with a first power electrode pad and a control electrode pad. The bottom surface of the chip is provided with a second power electrode pad. The second power electrode pad is at least partially not covered by the insulating layer. The portion of the second power electrode pad not covered by the insulating layer is connected to the connecting ring to be electrically connected to the conductive layer of the first substrate.

10. The power module according to claim 1, characterized in that, The thermal resistivity of the insulating layer is less than that of the insulating component.

11. The power module according to claim 6, characterized in that, The first substrate further includes a heat dissipation layer, which is located on the side of the insulating substrate opposite to the conductive layer, and the via also penetrates the heat dissipation layer; The end face of the heat sink facing the insulating layer is connected to the insulating layer, and the edge of the end face of the heat sink facing the insulating layer overlaps the surface of the heat sink layer away from the insulating substrate.

12. The power module according to claim 11, characterized in that, The insulating layer has a first metal layer on its lower surface away from the chip, and the end face of the heat sink facing the insulating layer is connected to the insulating layer through the first metal layer.

13. The power module according to claim 12, characterized in that, In a first direction from the conductive layer to the insulating substrate, the surface of the first metal layer facing away from the insulating layer and the end face of the insulating member facing away from the chip are both flush with the surface of the heat dissipation layer facing away from the insulating substrate, and the end face of the insulating member facing the chip is flush with the surface of the conductive layer facing away from the insulating substrate; the insulating member is sealed to the conductive layer, the insulating substrate, the heat dissipation layer, the insulating layer and the first metal layer respectively, and the periphery of the bottom surface of the chip is not covered by the insulating layer.

14. The power module according to claim 12, characterized in that, The insulating layer has a second metal layer on its upper surface facing the chip. The power module also includes a connecting ring, which surrounds the second metal layer and connects the area on the bottom surface of the chip that is not covered by the second metal layer to the conductive layer.

15. The power module according to claim 1, characterized in that, The first substrate further includes a heat dissipation layer, which is located on the side of the insulating substrate opposite to the conductive layer, and the via also penetrates the heat dissipation layer; The power module further includes a nickel plating layer that at least covers the surface of the heat dissipation layer opposite to the insulating substrate and exposes at least a portion of the lower surface of the insulating layer opposite to the chip.

16. The power module according to claim 1, characterized in that, It also includes a second substrate, on the side of the second substrate facing the first substrate, a metal layer with protrusions is provided, and the second substrate is electrically connected to an electrode pad disposed on the top surface of the chip away from the insulating layer through the protrusions and a connecting material.

17. The power module according to claim 1, characterized in that, The insulating layer is made of diamond.

18. The power module according to any one of claims 1-3, 6-8, 10-13 and 15-17, wherein the chip assembly further comprises a connection layer, the insulating layer being fixed to the bottom surface of the chip via the connection layer, and the connection layer also connecting the surface of the conductive layer away from the insulating substrate and the end face of the insulating member facing the chip.

19. A method for manufacturing a power module, characterized in that, include: A first substrate is provided, the first substrate including an insulating substrate and a conductive layer disposed on the insulating substrate, and the first substrate having a through hole penetrating the conductive layer and the insulating substrate; A chip assembly is provided and disposed on a first substrate, wherein the chip assembly includes a chip and an insulating layer, the chip is disposed on the conductive layer and has a bottom surface facing the conductive layer, the insulating layer is disposed on the bottom surface of the chip and covers a portion of the bottom surface of the chip, and the insulating layer extends at least partially into the via. as well as An insulating element is disposed within the through-hole and seals the insulating layer and the insulating substrate, wherein at least a portion of the lower surface of the insulating layer facing away from the chip is not covered by the insulating element, and the portion of the lower surface of the insulating layer not covered by the insulating element is configured as a cooling zone.

20. The manufacturing method according to claim 19, characterized in that, The provision of the chip assembly includes: providing a semiconductor wafer; forming an insulating material layer on a first side of the semiconductor wafer to obtain a wafer assembly; dividing the wafer assembly into a plurality of initial chip assemblies; and etching away a portion of the insulating material layer of a single initial chip assembly to obtain the chip assembly, wherein the remaining portion of the insulating material layer of the single initial chip assembly serves as the insulating layer; Alternatively, the provision of the chip assembly may include: providing a semiconductor wafer; disposing of a mask layer on a first side of the semiconductor wafer; depositing an insulating material layer as the insulating layer on the first side of the semiconductor wafer on which the mask layer is disposed; removing the mask layer to obtain a wafer assembly; and dividing the wafer assembly into a plurality of the chip assemblies.

21. The manufacturing method according to claim 19, characterized in that, The step of providing a chip assembly and disposing the chip assembly on the first substrate includes: The chip is fixed to the second substrate using a connecting material; The insulating layer is disposed on the side of the chip opposite to the second substrate by means of a sintering material layer, wherein the sintering material layer is a pre-formed sintering material layer, a sintering paste layer, or a pre-sintered foil; and After the insulating layer extends at least partially into the through-hole of the first substrate, it is sintered to convert the sintered material layer into a connection layer that fixes the chip to the conductive layer and the insulating layer.

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