A chip packaging method and system

Abstract

The application provides a chip packaging method and system. The method comprises the following steps: obtaining a pulse signal during packaging of a target insulated gate bipolar transistor chip, determining a pulse signal suppression domain of the pulse signal, determining a plurality of chip packaging orientation characteristic quantities according to the pulse signal suppression domain, further determining a packaging margin factor corresponding to the insulated gate bipolar transistor chip of each chip packaging orientation characteristic quantity in the pulse signal suppression domain, further obtaining a change trend segment of a surface monitoring temperature of the target insulated gate bipolar transistor chip, determining a temperature deviation coefficient during packaging of the chip by the change trend segment and a real-time monitoring temperature, further determining a packaging response displacement base of the target insulated gate bipolar transistor chip, marking the position of the target insulated gate bipolar transistor chip by the packaging response displacement base, and then packaging by the marked position, so that the chip bonding position can be prevented from deviating after the chip bonder works for a long time.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a chip packaging method and system. Background Technology

[0002] A transistor chip is an integrated circuit composed of billions to tens of billions of tiny transistors fabricated on a silicon wafer. Transistors control current by applying voltage to their gates, and have switching and amplification functions. The design and manufacture of transistor chips involve complex integrated circuit processes, including photolithography and ion implantation, making them a pillar of modern technology. They have driven the rapid development of fields such as computers, communications, and entertainment, and profoundly changed people's lifestyles and social structures.

[0003] In existing technologies, insulated gate bipolar transistor (IGBT) chips are mainly packaged by bonding the chips in a fixed position. This packaging method can cause the chip bonding position to deviate after the chip bonding machine has been working for a long time, resulting in low packaging accuracy of the IGBT chips. Therefore, how to dynamically adjust the bonding position of the IGBT chip during the packaging process to avoid chip bonding position deviation has become a research hotspot. Summary of the Invention

[0004] This application provides a chip packaging method and system that can prevent the chip bonding position from deviating after the chip bonding machine has been working for a long time.

[0005] In a first aspect, this application provides a chip packaging method, comprising the following steps: Start the packaging equipment for the insulated gate bipolar transistor (IGBT) chip and acquire the pulse signal during the packaging of the target IGBT chip; The pulse signal is segmented and filtered to obtain multiple pulse filtering sequences. The pulse signal suppression domain of the pulse signal is determined by using all the pulse filtering sequences. Based on the pulse signal suppression domain, multiple chip package orientation features are determined, and the package margin factor corresponding to each chip package orientation feature in the pulse signal suppression domain for the insulated gate bipolar transistor chip is determined. Obtain the temperature variation trend segment on the surface of the target insulated gate bipolar transistor chip, and determine the temperature deviation coefficient during chip packaging based on the temperature variation trend segment and the real-time monitored temperature. The package response shift base of the target insulated gate bipolar transistor chip is determined based on the temperature deviation coefficient and all package margin factors. The target insulated gate bipolar transistor chip is marked with the position of the package response displacement base, and then packaged according to the marked position.

[0006] In some embodiments, segmenting and filtering the pulse signal to obtain multiple pulse filtering sequences specifically includes: The pulse signal is segmented to obtain multiple transition pulse time slot domains; Determine the pulse filtering sequence for each transition pulse time slot domain.

[0007] In some embodiments, determining the pulse filtering sequence for each transition pulse time slot specifically includes: Select a transition pulse time slot domain; Determine the absolute amplitude of each signal point in the time slot domain of the transition pulse; The pulse filtering sequence for the transition pulse time slot domain is obtained by filtering the absolute amplitude of all signal points. Repeat the above steps to obtain the pulse filtering sequence in the remaining transition pulse time slot domain.

[0008] In some embodiments, determining the pulse signal suppression domain of the pulse signal through all pulse filtering sequences specifically includes: Determine the set of suppression signal points for each pulse filtering sequence; The pulse signal suppression domain of the pulse signal is determined by the set of suppression signal points of all pulse filtering sequences.

[0009] In some embodiments, determining multiple chip package orientation features based on the pulse signal suppression domain specifically includes: Convert the pulse signal suppression domain into the pulse frequency domain; Multiple chip package orientation features are determined based on the pulse frequency domain.

[0010] In some embodiments, determining the package margin factor corresponding to the insulated-gate bipolar transistor chip for each chip package orientation feature in the pulse signal suppression domain specifically includes: Determine the orientation feature matrix of each chip package in the pulse frequency domain corresponding to the orientation feature of the insulated gate bipolar transistor chip; Determine the packaging margin factor of the insulated gate bipolar transistor chip corresponding to each azimuth feature matrix in the pulse signal suppression domain.

[0011] In some embodiments, the insulated gate bipolar transistor chip may be a non-penetrating insulated gate bipolar transistor chip.

[0012] Secondly, this application discloses a chip packaging system, which includes: The acquisition module is used to acquire the pulse signal during the packaging of the target insulated gate bipolar transistor chip after the packaging equipment of the insulated gate bipolar transistor chip is started; The processing module is used to perform segmented filtering on the pulse signal to obtain multiple pulse filtering sequences, and to determine the pulse signal suppression domain of the pulse signal through all the pulse filtering sequences. The processing module is further configured to determine multiple chip package orientation features based on the pulse signal suppression domain, and to determine the package margin factor corresponding to each chip package orientation feature in the pulse signal suppression domain for the insulated gate bipolar transistor chip. The processing module is also used to obtain the trend segment of the surface temperature of the target insulated gate bipolar transistor chip, and to determine the temperature deviation coefficient during chip packaging by the trend segment and the real-time monitoring temperature. The processing module is also used to determine the package response shift base of the target insulated gate bipolar transistor chip based on all the package margin factors and the temperature deviation coefficient. An execution module is used to mark the position of the target insulated gate bipolar transistor chip by the package response displacement base, and then to package it according to the marked position.

[0013] Thirdly, this application provides a computer device, the computer device including a memory and a processor, the memory storing code, and the processor being configured to acquire the code and execute the chip packaging method described above.

[0014] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the chip packaging method described above.

[0015] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects: In this embodiment, the pulse signal is first segmented and filtered to obtain multiple pulse filtering sequences for removing abnormal signal points. The pulse signal with removed abnormal signal points is used as a pulse signal suppression domain to reduce the impact of abnormal signal points on determining the chip bonding position. Secondly, multiple chip package orientation features are obtained using the pulse signal suppression domain, which defines the displacement direction of the target insulated-gate bipolar transistor (IGBT) chip, improving the certainty of the target IGBT chip's displacement direction. Then, the package margin factor corresponding to each chip package orientation feature in the pulse signal suppression domain is determined to measure the bonding position of the target IGBT chip in different displacement directions. The degree of deviation is measured to predict potential deviations in the chip bonding position. Furthermore, the temperature deviation coefficient during chip packaging is determined using the trend segment and real-time temperature monitoring to measure the impact of chip surface temperature deviation on chip bonding position deviation. Then, a packaging response displacement base is obtained using all packaging margin factors and the temperature deviation coefficient to adjust the bonding position of the target insulated gate bipolar transistor (IGBT) chip. This allows for more dynamic adjustment of the deviated chip bonding position. Finally, the target IGBT chip is marked with the packaging response displacement base, and packaging is performed at the marked position, preventing chip bonding position deviation caused by prolonged operation of the chip bonding machine. Attached Figure Description

[0016] Figure 1 This is an exemplary flowchart of a chip packaging method according to some embodiments of this application; Figure 2 This is a flowchart illustrating the process of determining the pulse filtering sequence for each transition pulse time slot domain in some embodiments of this application; Figure 3 This is a schematic flowchart illustrating the process of determining the package response shift base of the target insulated gate bipolar transistor chip in some embodiments of this application; Figure 4 This is a structural block diagram of the chip packaging system in some embodiments of this application; Figure 5 This is a schematic diagram of the structure of a computer device implementing a chip packaging method according to some embodiments of this application. Detailed Implementation

[0017] The core of this application is to acquire the pulse signal during the packaging of the target insulated gate bipolar transistor (IGBT) chip by starting the packaging equipment, segmenting and filtering the pulse signal to obtain multiple pulse filtering sequences, determining the pulse signal suppression domain of the pulse signal through all pulse filtering sequences, determining multiple chip packaging orientation features based on the pulse signal suppression domain, determining the packaging margin factor corresponding to each chip packaging orientation feature of the IGBT chip in the pulse signal suppression domain, obtaining the temperature change trend segment of the surface monitoring temperature of the target IGBT chip, determining the temperature deviation coefficient during chip packaging through the change trend segment and the real-time monitoring temperature, determining the packaging response displacement base of the target IGBT chip based on the temperature deviation coefficient and all packaging margin factors, marking the position of the target IGBT chip with the packaging response displacement base, and then packaging according to the marked position, which can avoid the chip bonding position deviation caused by the chip bonding machine working for a long time.

[0018] To better understand the above technical solutions, a detailed description of the solutions will be provided below in conjunction with the accompanying drawings and specific implementation methods. (Reference) Figure 1 The figure is an exemplary flowchart of a chip packaging method according to some embodiments of this application. The chip packaging method 100 mainly includes the following steps: In step 101, the packaging equipment for the insulated gate bipolar transistor (IGBT) chip is started to obtain the pulse signal during the packaging of the target IGBT chip.

[0019] In specific implementation, after starting the packaging equipment of the insulated gate bipolar transistor (IGBT) chip, the packaging equipment, such as a chip bonding machine, uses a pulse radar to acquire the pulse signal of the target IGBT chip according to a preset acquisition frequency. It should be noted that the IGBT chip in this application can be a non-penetrating IGBT chip, a penetrating IGBT chip, or a field stop IGBT chip. No specific limitation is made here. In addition, the acquisition frequency in this application is usually between 10kHz and 30kHz. Furthermore, the pulse signal is composed of multiple signal points, and the signal points represent the amplitude value of the corresponding pulse waveform in the time domain.

[0020] In step 102, the pulse signal is segmented and filtered to obtain multiple pulse filtering sequences, and the pulse signal suppression domain of the pulse signal is determined by using all the pulse filtering sequences.

[0021] In some embodiments, segmenting and filtering the pulse signal to obtain multiple pulse filtering sequences can be achieved using the following steps: The pulse signal is segmented to obtain multiple transition pulse time slot domains; Determine the pulse filtering sequence for each transition pulse time slot domain.

[0022] In specific implementation, multiple transition pulse time slot domains are determined based on the pulse signal, that is: the pulse signal is divided into multiple data segments of equal duration with a time interval of 100 milliseconds, and each data segment of equal duration is used as a transition pulse time slot domain, thereby obtaining multiple transition pulse time slot domains.

[0023] In some embodiments, reference Figure 2 As shown in the figure, this is a flowchart illustrating the process of determining the pulse filtering sequence for each transition pulse time slot domain in some embodiments of this application. In this embodiment, determining the pulse filtering sequence for each transition pulse time slot domain can be achieved using the following steps: In step 1021, a transition pulse time slot domain is selected; Secondly, in step 1022, the absolute amplitude of each signal point in the time slot domain of the transition pulse is determined; Then, in step 1023, the transition pulse time slot domain is filtered by the absolute amplitude of all signal points to obtain the pulse filtering sequence of the transition pulse time slot domain; Finally, in step 1024, the above steps are repeated to obtain the pulse filtering sequence of the remaining transition pulse time slot domain.

[0024] In specific implementation, the absolute amplitude of each signal point in the transition pulse time slot domain is determined, that is: the first and second signal points in the transition pulse time slot domain are selected, the amplitude value of the second signal point is subtracted from the amplitude value of the first signal point and the absolute value is obtained, and the obtained value is used as the absolute amplitude of the first signal point. The second and third signal points in the transition pulse time slot domain are selected, the amplitude value of the third signal point is subtracted from the amplitude value of the second signal point and the absolute value is obtained, and the obtained value is used as the absolute amplitude of the second signal point. The above steps are repeated to determine the absolute amplitude of the remaining signal points in the transition pulse time slot domain in turn. It should be noted that in this application, the amplitude value of the second to last signal point in the transition pulse time slot domain is used as the absolute amplitude of the last signal point.

[0025] In practice, the transition pulse time slot domain is filtered using the absolute amplitude values ​​of all signal points to obtain the pulse filtering sequence for that transition pulse time slot domain. Specifically: S signal points are randomly selected from all signal points using a simple random sampling method. This set of S signal points is considered the signal point domain. The mean of the absolute amplitude values ​​of all signal points in the signal point domain is calculated and rounded up. This rounded value is used as the segmentation value of the signal point domain. The set of signal points whose absolute amplitude values ​​are less than the segmentation value is considered the left signal point domain. The set of signal points whose absolute amplitude values ​​are greater than or equal to the segmentation value is considered the left signal point domain. The combination of signal points from the segmented values ​​is taken as the right signal point domain of the current signal point domain. Repeating the above steps, the left signal point domain is taken as the new signal point domain, and the left and right signal point domains of the new signal point domain are divided separately until only one signal point exists in each of the left and right signal point domains. The right signal point domain is taken as the new signal point domain, and the left and right signal point domains of the new signal point domain are divided separately until only one signal point exists in each of the left and right signal point domains. Following the division order, the signal points after the division stops are collected sequentially, and the sequence of collected signal points is taken as the transition pulse time slot. For example, consider a pulse filtering sequence in a signal point domain. There are three signal points with absolute amplitudes of 1, 3, and 5. According to the partitioning rules, the average of 1, 3, and 5 is 4.5. Rounding up 4.5 gives 5. Using 5 as the partitioning value for the signal point domain, we find two signal points with absolute amplitudes less than this partitioning value. Therefore, the signal points with absolute amplitudes of 1 and 3 are partitioned into the left signal point domain, and the signal point with absolute amplitude of 5 is partitioned into the right signal point domain. Since the right signal point domain contains only one signal point, we stop partitioning there. The left signal point domain contains two signal points, so we continue partitioning it. As a new signal point domain, the above-mentioned division is performed on this new signal point domain. The signal points corresponding to the absolute amplitude of 1 and 3 are divided into the left signal point domain of the new signal point domain, which contains only the signal point corresponding to the absolute amplitude of 1, and the right signal point domain, which contains only the signal point corresponding to the absolute amplitude of 1. Since there is only one signal point in both the left and right signal point domains of the new signal point domain, the division is stopped. According to the division order, the signal points corresponding to the absolute amplitude of 5, the signal points corresponding to the absolute amplitude of 1, and the signal points corresponding to the absolute amplitude of 3 are collected in sequence. The sequence of the collected signal points is used as the pulse filtering sequence of the transition pulse time slot domain.

[0026] It should be noted that S is set to 1000 in this application, but may be set to other values ​​in other embodiments, which are not limited here.

[0027] In some embodiments, determining the pulse signal suppression region of the pulse signal through all pulse filtering sequences can be achieved by the following steps: Determine the set of suppression signal points for each pulse filtering sequence; The pulse signal suppression domain of the pulse signal is determined by the set of suppression signal points of all pulse filtering sequences.

[0028] In practice, a pulse filtering sequence is selected, and a sliding window of the pulse filtering sequence is formed by the positions of 10 consecutive signal points. The sliding window is aligned with the first signal point in the pulse filtering sequence. The suppression threshold of the first signal point is determined based on the absolute amplitude of all signal points in the sliding window corresponding to the first signal point. If the absolute amplitude of any signal point in the sliding window exceeds the suppression threshold, the signal points with absolute amplitudes exceeding the suppression threshold are taken as the suppression signal point set. The sliding window is then moved to align with the second signal point in the pulse filtering sequence, and the suppression threshold of the second signal point is determined based on the absolute amplitude of all signal points in the sliding window corresponding to the second signal point. If the absolute amplitude of a signal point in the sliding window exceeds the suppression threshold, then the signal points corresponding to the absolute amplitude exceeding the suppression threshold are taken as the suppression signal point set. The above steps are repeated, and the sliding window is moved sequentially until the last signal point in the sliding window is aligned with the last signal point in the pulse filtering sequence. The set of multiple suppression signal point sets obtained is taken as the suppression signal point set of the pulse filtering sequence. The above steps are repeated to determine the suppression signal point set of each pulse filtering sequence. Signal points in the pulse signal that are the same as the suppression signal point sets of all pulse filtering sequences are removed from the pulse signal, and the pulse signal after removal is taken as the pulse signal suppression domain of the pulse signal.

[0029] It should be noted that in some embodiments, the suppression threshold of the above signal point can be obtained by averaging the absolute values ​​of the amplitudes of all signal points in the sliding window corresponding to the signal point, and setting 1.2 times the obtained value as the suppression threshold of the signal point. In other embodiments, other methods can also be used to set the suppression threshold of the signal point, which is not limited here.

[0030] It should be noted that the pulse signal suppression domain described in this application represents a set of abnormal signal points that have been eliminated, reducing the impact of abnormal signal points on determining the chip bonding position, which helps to improve the accuracy of positioning during the bonding of the target insulated gate bipolar transistor chip.

[0031] In step 103, multiple chip package orientation features are determined based on the pulse signal suppression domain, and the package margin factor corresponding to each chip package orientation feature in the pulse signal suppression domain for the insulated gate bipolar transistor chip is determined.

[0032] In some embodiments, determining multiple chip package orientation features based on the pulse signal suppression domain can be achieved using the following steps: Convert the pulse signal suppression domain into the pulse frequency domain; Multiple chip package orientation features are determined based on the pulse frequency domain.

[0033] In specific implementation, Fourier transform is used to convert the pulse signal suppression domain from the time domain to the frequency domain, and the set of multiple frequency components obtained after Fourier transform is taken as the pulse frequency domain. It should be noted that each frequency component in this application has a corresponding amplitude value and phase.

[0034] In some embodiments, the determination of multiple chip package orientation features based on the pulse frequency domain can be achieved using the following formula: in, Represents the pulse frequency domain. Chip package orientation feature quantity Indicates the width of the pulse signal. Represents the first pulse in the pulse frequency domain. The phase of each frequency component, This indicates the distance between the pulse radar and the target insulated-gate bipolar transistor chip. This represents the arcsine function.

[0035] It should be noted that, in this application, the moving direction of the target insulated gate bipolar transistor chip can be defined by the chip packaging orientation feature, which can improve the accuracy of the moving orientation of the target insulated gate bipolar transistor chip.

[0036] In some embodiments, determining the package margin factor corresponding to the insulated gate bipolar transistor chip for each chip package orientation feature in the pulse signal suppression domain can be achieved by the following steps: Determine the orientation feature matrix of each chip package in the pulse frequency domain corresponding to the orientation feature of the insulated gate bipolar transistor chip; Determine the packaging margin factor of the insulated gate bipolar transistor chip corresponding to each azimuth feature matrix in the pulse signal suppression domain.

[0037] In some embodiments, determining the orientation feature matrix corresponding to the insulated gate bipolar transistor chip in the pulse frequency domain for each chip package orientation feature can be achieved using the following steps: Determine the harmonic factor in the pulse frequency domain. ; Obtain the first pulse frequency domain Chip package orientation feature ; Determine the variance of the amplitude values ​​of all frequency components in the pulse frequency domain. ; According to the harmonic factor in the pulse frequency domain The pulse frequency domain of the first Chip package orientation feature and the variance of the amplitude values ​​of all frequency components in the pulse frequency domain. Determine the orientation feature matrix of each chip package in the pulse frequency domain corresponding to the insulated gate bipolar transistor chip, wherein the first... The orientation feature matrix corresponding to the insulated gate bipolar transistor chip in the pulse frequency domain can be determined using the following formula:

[0038] in, Indicates the first The orientation feature quantity of each chip package is the orientation feature matrix corresponding to the insulated gate bipolar transistor chip in the pulse frequency domain.

[0039] In practice, the average amplitude values ​​of all frequency components in the pulse frequency domain are calculated. This average is then multiplied by the ratio of the maximum to the minimum amplitude values ​​of the frequency components in the pulse frequency domain. The resulting multiplication factor is used as the harmonic factor in the pulse frequency domain. For example: the harmonic factor in the pulse frequency domain. , This represents the mean of the amplitude values ​​of all frequency components. This represents the maximum amplitude value of the frequency component in the pulse frequency domain. It represents the minimum amplitude value of the frequency component in the pulse frequency domain.

[0040] It should be noted that the harmonic factor mentioned in this application represents a parameter that determines the correlation between the amplitude values ​​of the chip package orientation features and the frequency components in the orientation feature matrix. The larger the harmonic factor, the greater the correlation between the amplitude values ​​of the chip package orientation features and the frequency components in the orientation feature matrix.

[0041] In some embodiments, determining the packaging margin factor corresponding to the insulated gate bipolar transistor chip for each orientation feature matrix in the pulse signal suppression domain can be achieved using the following steps: Get the The orientation feature of each chip package is represented in the pulse frequency domain by the orientation feature matrix corresponding to the insulated gate bipolar transistor chip. ; Determine the suppression constraint factor of the pulse signal suppression domain. ; Determine the suppression variation coefficient of the pulse signal suppression domain. ; According to the first The orientation feature of each chip package is represented in the pulse frequency domain by the orientation feature matrix corresponding to the insulated gate bipolar transistor chip. The suppression constraint factor of the pulse signal suppression domain. and the suppression variation coefficient of the pulse signal suppression domain Determine the first The package margin factor corresponding to the insulated gate bipolar transistor chip in the pulse signal suppression domain can be determined using the following formula:

[0042] in, Indicates the first The azimuth feature matrix corresponds to the packaging margin factor of the insulated gate bipolar transistor chip in the pulse signal suppression domain. Indicates the first Determinant of the directional feature matrix This represents the total number of directional characteristic matrices in the pulse frequency domain.

[0043] In specific implementation, the suppression variation coefficient of the pulse signal suppression domain is determined by dividing the mean of the amplitude values ​​of all signal points in the pulse signal suppression domain by the variance of the amplitude values ​​of all signal points in the pulse signal suppression domain, and the resulting value is used as the suppression variation coefficient of the pulse signal suppression domain. The suppression constraint factor of the pulse signal suppression domain is determined by sorting the amplitude values ​​of all signal points in the pulse signal suppression domain in ascending order, selecting the W signal points with the largest amplitude values, calculating the average value of the W signal points, and using the resulting value as the maximum average suppression amplitude. The W signal points with the smallest amplitude values ​​are selected, and the average value of these W signal points is calculated, and the resulting value is used as the minimum average suppression amplitude. The minimum average suppression amplitude is divided by the maximum average suppression amplitude, and the resulting value is used as the suppression constraint factor of the pulse signal suppression domain. It should be noted that in this application, the value of W is 5000, but other values ​​can be selected in other embodiments, which are not limited here.

[0044] It should be noted that the suppression variation coefficient mentioned in this application represents a parameter indicating the degree of deviation of the average amplitude value of all signal points in the pulse signal suppression domain from its difference. The larger the suppression variation coefficient, the greater the degree of deviation of the average amplitude value of all signal points in the pulse signal suppression domain from its difference. In addition, the suppression constraint factor represents a parameter constraining the amplitude value of signal points in the pulse signal suppression domain. The larger the suppression constraint factor, the greater the constraint on the amplitude value of signal points in the pulse signal suppression domain.

[0045] It should be noted that the packaging margin factor mentioned in this application represents a parameter that measures the degree of deviation of the bonding position of the target insulated gate bipolar transistor chip in different displacement directions. The larger the packaging margin factor, the greater the degree of deviation of the bonding position of the target insulated gate bipolar transistor chip in different displacement directions, which can enable the prediction of possible deviation of the chip bonding position.

[0046] In step 104, the temperature trend segment of the target insulated gate bipolar transistor chip surface is obtained, and the temperature deviation coefficient during chip packaging is determined by the temperature trend segment and the real-time monitoring temperature.

[0047] In some embodiments, obtaining the trend segment of the surface temperature monitoring of the target insulated gate bipolar transistor chip can be achieved by the following steps: Obtain historical temperature monitoring datasets for insulated gate bipolar transistor (IGBT) chips; Extract the trend segment of the chip surface temperature from the historical temperature monitoring dataset.

[0048] It should be noted that the historical monitoring temperature data mentioned in this application refers to a collection of temperature change data of multiple high-precision insulated gate bipolar transistor chips from the start of packaging to the end of packaging. These data are usually in the form of time series.

[0049] In a specific implementation, an exponential smoothing algorithm can be used to extract the trend segment of the chip surface monitoring temperature from the historical monitoring temperature dataset. In other embodiments, other existing technologies can also be used for extraction, which is not limited here.

[0050] It should be noted that the trend segment mentioned in this application represents the fitting of the trend of the monitored temperature on the chip surface during the chip packaging process. The trend segment can be used to find the trend of the monitored temperature of chips with high packaging precision.

[0051] In specific implementation, the temperature deviation coefficient during chip packaging is determined by the trend segment and the current real-time monitored temperature. That is, the current real-time monitored temperature and the trend segment are fitted together, and the fitted value is used as the temperature fitted value. Then, the difference between the current real-time monitored temperature and the temperature fitted value is taken as the absolute value, and the value obtained by taking the absolute value is used as the temperature deviation coefficient during chip packaging.

[0052] It should be noted that temperature can cause thermal expansion, which leads to deformation of the materials inside the chip, and thus causes the bonding position to deviate. Alternatively, thermal stress caused by temperature changes can cause deformation of the materials inside the chip, which can also cause the bonding position to deviate. In this application, the temperature deviation coefficient is used to measure the degree of influence of the deviation of the chip surface temperature during the chip packaging process on the chip bonding position deviation. The larger the temperature deviation coefficient, the greater the influence of the deviation of the chip surface temperature on the chip bonding position deviation.

[0053] In step 105, the package response shift base of the target insulated gate bipolar transistor chip is determined based on the temperature deviation coefficient and all the package margin factors.

[0054] In some embodiments, reference Figure 3 As shown in the figure, this is a schematic flowchart of determining the package response shift base of the target insulated gate bipolar transistor chip in some embodiments of this application. In this embodiment, determining the package response shift base of the target insulated gate bipolar transistor chip can be achieved by the following steps: In step 1051, it is first necessary to determine the component phase equalization coefficients in the pulse frequency domain; Then, in step 1052, the package response shift base of the target insulated gate bipolar transistor chip is determined by the component phase equalization coefficient, the temperature deviation coefficient, and all the package margin factors.

[0055] In specific implementation, the component phase equalization coefficient of the pulse frequency domain is determined, that is: the average value of the phase values ​​of all frequency components in the pulse frequency domain is calculated, and the obtained value is used as the component phase equalization coefficient of the pulse frequency domain. It should be noted that the component phase equalization coefficient in this application represents a parameter that measures the degree of phase synchronization of frequency components in the pulse frequency domain. The larger the component phase equalization coefficient, the greater the degree of phase synchronization of frequency components in the pulse frequency domain.

[0056] In some embodiments, determining the package response shift base of the target insulated gate bipolar transistor chip based on the component phase equalization coefficient, the temperature deviation coefficient, and all package margin factors can be achieved using the following steps: Get the The directional feature matrix corresponds to the package margin factor of the insulated gate bipolar transistor chip in the pulse signal suppression domain. ; Obtain the temperature deviation coefficient during chip packaging ; Obtain the component phase equalization coefficient in the pulse frequency domain. ; According to the first The directional feature matrix corresponds to the package margin factor of the insulated gate bipolar transistor chip in the pulse signal suppression domain. Temperature deviation coefficient during chip packaging and the component phase equalization coefficient in the pulse frequency domain The package response shift basis of the target insulated gate bipolar transistor chip can be determined using the following formula: in, This represents the package response shift base of the target insulated gate bipolar transistor chip. This indicates the total number of encapsulation margin factors. It represents the base of the natural logarithm.

[0057] It should be noted that the package response displacement base described in this application represents a vector for adjusting the bonding position of the target insulated gate bipolar transistor (IGBT) chip. A Cartesian coordinate system is constructed with the target IGBT chip as the center. The first variable of the package response displacement base represents the length to be moved on the horizontal axis, and the second variable of the package response displacement base represents the length to be moved on the vertical axis. The positive and negative signs of the first and second variables represent the direction of movement. The package response displacement base allows for more dynamic adjustment of the chip bonding position that has deviated.

[0058] In step 106, the target insulated gate bipolar transistor chip is marked with the position by the packaging response displacement base, and then packaged according to the marked position.

[0059] In specific implementation, since the package response displacement base represents the vector for adjusting the bonding position of the target insulated gate bipolar transistor (IGBT) chip, the package position of the target IGBT chip can be marked using the package response displacement base. Based on the marked package position, an alignment device (e.g., a mechanical alignment device) can be used to adjust the position of the target IGBT chip, align the target IGBT chip with the circuit board, and then solder the pins of the aligned target IGBT chip to the circuit board before packaging. This will not be elaborated further here.

[0060] In another aspect, in some embodiments, this application provides a chip packaging system, with reference to... Figure 4 The figure is a schematic diagram of exemplary hardware and / or software of a chip packaging system according to some embodiments of this application. The chip packaging system 400 includes: an acquisition module 401, a processing module 402, and an execution module 403, which are described below: The acquisition module 401 in this application is mainly used to start the packaging equipment of the insulated gate bipolar transistor chip and acquire the pulse signal during the packaging of the target insulated gate bipolar transistor chip. Processing module 402, in this application, is used to perform segmented filtering on the pulse signal to obtain multiple pulse filtering sequences, and to determine the pulse signal suppression domain of the pulse signal through all the pulse filtering sequences; It should be noted that the processing module 402 in this application is also used to determine multiple chip package orientation feature quantities based on the pulse signal suppression domain, and to determine the package margin factor corresponding to the insulated gate bipolar transistor chip for each chip package orientation feature quantity in the pulse signal suppression domain. It should be noted that the processing module 402 described in this application is also used to obtain the trend segment of the surface temperature of the target insulated gate bipolar transistor chip, and to determine the temperature deviation coefficient during chip packaging by means of the trend segment and the real-time monitoring temperature. In addition, the processing module 402 described in this application is also used to determine the package response shift base of the target insulated gate bipolar transistor chip based on all the package margin factors and the temperature deviation coefficient; The execution module 403 in this application is mainly used to mark the position of the target insulated gate bipolar transistor chip by the packaged response displacement base, and then to package it by the marked position.

[0061] In addition, this application also provides a computer device, the computer device including a memory and a processor, the memory storing code, and the processor being configured to acquire the code and execute the chip packaging method described above.

[0062] In some embodiments, reference Figure 5 The figure is a schematic diagram of the structure of a computer device using a chip packaging method according to some embodiments of this application. The chip packaging method in the above embodiments can be achieved through... Figure 5 The computer device shown is used to implement this, and the computer device 500 includes at least one processor 501, a communication bus 502, a memory 503, and at least one communication interface 504.

[0063] The processor 501 may be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more for controlling the execution of the chip packaging method in this application.

[0064] The communication bus 502 may include a path for transmitting information between the aforementioned components.

[0065] Memory 503 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disks or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 503 may exist independently and be connected to processor 501 via communication bus 502. Memory 503 may also be integrated with processor 501.

[0066] The memory 503 stores program code that executes the scheme of this application, and its execution is controlled by the processor 501. The processor 501 executes the program code stored in the memory 503. The program code may include one or more software modules. In the above embodiments, the determination of the encapsulated response shift basis can be achieved by the processor 501 and one or more software modules in the program code in the memory 503.

[0067] Communication interface 504 uses any transceiver-like device to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0068] In a specific implementation, as one example, a computer device may include multiple processors, each of which may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0069] The aforementioned computer device can be a general-purpose computer device or a special-purpose computer device. In specific implementations, the computer device can be a desktop computer, a portable computer, a network server, a handheld digital assistant (PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device, or an embedded device. This application does not limit the type of computer device.

[0070] In addition, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the chip packaging method described above.

[0071] In summary, the chip packaging method and related equipment disclosed in this application firstly involve starting the packaging equipment for an insulated gate bipolar transistor (IGBT) chip, acquiring the pulse signal during the packaging of the target IGBT chip, segmenting and filtering the pulse signal to obtain multiple pulse filtering sequences, determining the pulse signal suppression domain of the pulse signal through all the pulse filtering sequences, determining multiple chip packaging orientation features based on the pulse signal suppression domain, determining the packaging margin factor corresponding to each chip packaging orientation feature of the IGBT chip within the pulse signal suppression domain, acquiring the trend segment of the surface temperature monitoring of the target IGBT chip, determining the temperature deviation coefficient during chip packaging through the trend segment and the real-time monitoring temperature, determining the packaging response displacement base of the target IGBT chip based on the temperature deviation coefficient and all the packaging margin factors, marking the position of the target IGBT chip using the packaging response displacement base, and then packaging based on the marked position. This avoids deviation of the chip bonding position caused by prolonged operation of the chip bonding machine.

[0072] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0073] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A chip packaging method, characterized in that, Includes the following steps: Start the packaging equipment for the insulated gate bipolar transistor (IGBT) chip and acquire the pulse signal during the packaging of the target IGBT chip; The pulse signal is segmented and filtered to obtain multiple pulse filtering sequences. The pulse signal suppression domain of the pulse signal is determined by using all the pulse filtering sequences. Based on the pulse signal suppression domain, multiple chip package orientation features are determined, and the package margin factor corresponding to each chip package orientation feature in the pulse signal suppression domain for the insulated gate bipolar transistor chip is determined. Obtain the temperature variation trend segment on the surface of the target insulated gate bipolar transistor chip, and determine the temperature deviation coefficient during chip packaging based on the temperature variation trend segment and the real-time monitored temperature. The package response shift base of the target insulated gate bipolar transistor chip is determined based on the temperature deviation coefficient and all package margin factors. The target insulated gate bipolar transistor chip is marked with the position of the package response displacement base, and then packaged according to the marked position.

2. The method as described in claim 1, characterized in that, The pulse signal is segmented and filtered to obtain multiple pulse filtering sequences, specifically including: The pulse signal is segmented to obtain multiple transition pulse time slot domains; Determine the pulse filtering sequence for each transition pulse time slot domain.

3. The method as described in claim 2, characterized in that, Determining the pulse filtering sequence for each transition pulse time slot specifically includes: Select a transition pulse time slot domain; Determine the absolute amplitude of each signal point in the time slot domain of the transition pulse; The pulse filtering sequence for the transition pulse time slot domain is obtained by filtering the absolute amplitude of all signal points. Repeat the above steps to obtain the pulse filtering sequence in the remaining transition pulse time slot domain.

4. The method as described in claim 1, characterized in that, The pulse signal suppression domain of the pulse signal is determined by all pulse filtering sequences, specifically including: Determine the set of suppression signal points for each pulse filtering sequence; The pulse signal suppression domain of the pulse signal is determined by the set of suppression signal points of all pulse filtering sequences.

5. The method as described in claim 1, characterized in that, Determining multiple chip package orientation feature quantities based on the pulse signal suppression domain specifically includes: Convert the pulse signal suppression domain into the pulse frequency domain; Multiple chip package orientation features are determined based on the pulse frequency domain.

6. The method as described in claim 1, characterized in that, Determining the package orientation characteristics of each chip in the pulse signal suppression domain, specifically the corresponding package margin factor for the insulated gate bipolar transistor chip, includes: Determine the orientation feature matrix of each chip package in the pulse frequency domain corresponding to the orientation feature of the insulated gate bipolar transistor chip; Determine the packaging margin factor of the insulated gate bipolar transistor chip corresponding to each azimuth feature matrix in the pulse signal suppression domain.

7. The method as described in claim 1, characterized in that, The insulated gate bipolar transistor chip is a non-penetrating insulated gate bipolar transistor chip.

8. A chip packaging system, characterized in that, Including: The acquisition module is used to start the packaging equipment of the insulated gate bipolar transistor chip and acquire the pulse signal during the packaging of the target insulated gate bipolar transistor chip; The processing module is used to perform segmented filtering on the pulse signal to obtain multiple pulse filtering sequences, and to determine the pulse signal suppression domain of the pulse signal through all the pulse filtering sequences. The processing module is further configured to determine multiple chip package orientation features based on the pulse signal suppression domain, and to determine the package margin factor corresponding to each chip package orientation feature in the pulse signal suppression domain for the insulated gate bipolar transistor chip. The processing module is also used to obtain the trend segment of the surface temperature of the target insulated gate bipolar transistor chip, and to determine the temperature deviation coefficient during chip packaging by the trend segment and the real-time monitoring temperature. The processing module is also used to determine the package response shift base of the target insulated gate bipolar transistor chip based on all the package margin factors and the temperature deviation coefficient. An execution module is used to mark the position of the target insulated gate bipolar transistor chip by the package response displacement base, and then to package it according to the marked position.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the chip packaging method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the chip packaging method as described in any one of claims 1 to 7.

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