Highly reliable interconnected graphene reinforced copper wire and low temperature bonding method thereof

Abstract

The application relates to the field of advanced semiconductor packaging and microelectronic interconnection technology, and discloses a graphene-reinforced copper wire with high-reliability interconnection and a low-temperature bonding method thereof. The wire is composed of a copper base and a three-dimensional continuous graphene network framework, has super-high current density ( ) and super-high axial thermal conductivity (>=600 W / (m*K)), and realizes high-strength metallurgical bonding at <=250 DEG C through surface catalytic activation and in-situ solid-solid diffusion. The application solves the problems of electromigration, heat dissipation and thermal damage in high-computing-power chip interconnection, and is suitable for high-density and high-reliability three-dimensional interconnection of GPU, HBM, Chiplet and the like.

Description

Technical Field

[0001] This invention relates to the fields of advanced semiconductor packaging and microelectronic interconnect technology, and in particular to a highly reliable interconnect graphene-reinforced copper wire and its low-temperature bonding method. Background Technology

[0002] With the explosive growth in demand for artificial intelligence and high-performance computing, chip interconnect technology faces three fundamental challenges: density, power consumption, and thermal management. Electromigration and Reliability Limits: As interconnect dimensions enter the submicron scale, current density increases dramatically, and traditional copper interconnects face challenges in ultra-high current (…). Power-down migration failures worsen, becoming a core bottleneck restricting chip frequency and reliability.

[0003] Power wall and thermal management challenges: The power density of 3D stacked chips has increased dramatically, and vertical interconnects (such as through silicon vias (TSV) and microbumps) have become the main heat dissipation bottlenecks. Local overheating leads to performance degradation and lifespan reduction.

[0004] Thermal damage and process compatibility: Traditional hot-press bonding, copper-copper hot-compression bonding and other processes require high temperatures (>400℃), which can damage heat-sensitive components such as low-k dielectrics and memory cells in the chip, limiting the number of stacked layers and yield.

[0005] In existing technologies, the use of nanomaterials such as carbon nanotubes and graphene films to enhance interconnects is a research hotspot, but key drawbacks remain: high interfacial resistance between nanomaterials and metal substrates, difficulty in achieving large-scale uniform composites, and insufficient mechanical strength and process compatibility. Therefore, there is an urgent need to develop a novel interconnect material and solution that combines ultra-high current carrying capacity, excellent thermal management characteristics, and low-temperature integration processes at the ultra-fine scale. Summary of the Invention

[0006] The purpose of this invention is to provide a highly reliable interconnect graphene-reinforced copper wire that can carry ultra-high current density with ultra-fine wire diameter, breaking through the electromigration limit; significantly improve the vertical thermal conductivity, efficiently eliminate chip hot spots; achieve ultra-low temperature and high-strength metallurgical bonding, avoid thermal damage to the chip, and meet the requirements of ultra-high density three-dimensional stacked interconnect.

[0007] The above-mentioned technical objective of this invention is achieved through the following technical solution: a highly reliable interconnect graphene-reinforced copper wire, wherein the wire has a composite structure, consisting of a copper substrate and a three-dimensional continuous graphene network framework uniformly dispersed within it, and the wire diameter is 0.5 μm to 10 μm; the three-dimensional graphene network is a porous foam-like continuous structure, with the pores completely filled by a highly dense copper substrate, and the wire's allowable operating current density at 125°C is [not specified]. .

[0008] A further setting of the present invention is that the volume fraction of the three-dimensional graphene network is 0.5 vol% to 5.0 vol%.

[0009] A further feature of the present invention is that the axial thermal conductivity of the conductor is ≥600 W / (m•K).

[0010] A further feature of the present invention is that the coefficient of thermal expansion of the conductor is 5 to 8 ppm / K.

[0011] A further feature of the present invention is that the copper substrate is high-purity oxygen-free copper with a grain size of nanocrystals (100 nm to 500 nm); the graphene framework is composed of fewer than 10 layers of graphene sheets connected to each other, which are tightly bonded to the copper substrate interface and are free of pores and harmful phases.

[0012] The purpose of this invention is to provide a low-temperature bonding method for highly reliable interconnect graphene-reinforced copper wires, enabling ultra-high current density to be carried under ultra-fine wire diameters, breaking through the electromigration limit; significantly improving the vertical thermal conductivity, efficiently eliminating chip hot spots; achieving ultra-low temperature, high-strength metallurgical bonding, avoiding thermal damage to the chip, and meeting the requirements of ultra-high density three-dimensional stacked interconnects.

[0013] The above-mentioned technical objective of this invention is achieved through the following technical solution: a low-temperature bonding method for highly reliable interconnect graphene-reinforced copper wires, comprising the following steps: S1 Surface catalytic activation treatment of the wire: A nano-catalytic layer with a thickness of 2 nm to 10 nm is prepared on the surface of the end to be bonded of the graphene-reinforced copper wire by physical vapor deposition or chemical plating; the catalytic layer material is one of Au, Pd, Ag or Sn-Ag alloy; S2 chip pad pretreatment: Plasma cleaning or wet cleaning is performed on the copper or aluminum pads of the chip to remove oxides and organic contaminants, resulting in a clean and activated metal surface. S3 Precise Positioning and Pre-connection: In an inert gas or vacuum environment, precisely position and align the wire ends processed in step S1 with the chip pads processed in step S2, and apply a light preload of 0.5 N to 2.0 N to make initial contact. S4 In-situ low-temperature solid-solid diffusion bonding: At a temperature of 180℃~250℃ and a pressure of 1 MPa~10 MPa, and held for 30 s~180 s, under the action of the catalytic layer, copper atoms on the surface of the wire and metal atoms on the chip pad undergo solid-solid interdiffusion to form a metallurgical bonding interface. S5 Interface Strengthening and Stabilization Treatment: After bonding is completed, the bonding points are briefly annealed for 30 s to 60 s in a protective atmosphere at 250℃~300℃ to promote the formation of an intermetallic compound diffusion layer with a compositional gradient at the interface, further reducing the interface resistance and enhancing the bonding strength.

[0014] The beneficial effects of this invention are: revolutionary current carrying capacity: the three-dimensional continuous graphene network, acting as a highly efficient electron transport channel and grain boundary pinning center, raises the electromigration threshold by an order of magnitude, allowing the wire to stably carry over [current carrying capacity] at 125°C. The current density meets the ultra-high I / O bandwidth requirements of next-generation AI chips.

[0015] Superior chip-level thermal management: The graphene network constructs an ultra-high thermal conductivity path, which increases the axial thermal conductivity of the wire by more than 50%, and can efficiently conduct the core heat of the chip vertically, reducing the junction temperature by 10℃~20℃ and breaking through the "power wall" limitation.

[0016] Ultra-low temperature, high-reliability interconnect process: Innovative surface catalytic activation and in-situ low-temperature solid-solid diffusion bonding technology reduce the bonding temperature to below 250℃, completely avoiding thermal damage to the chip. The resulting metallurgical interface has a shear strength >50MPa, and its electrical resistance changes by <3% after 1000 thermal cycles at 55℃~125℃.

[0017] High-density integration compatibility: Ultra-fine wires (down to 0.5 μm) combined with low-temperature bonding processes enable ultra-high-density interconnects with line spacing / line width <2 μm, providing interconnect solutions for advanced packaging such as Chiplet and 3D SoC.

[0018] The graphene-reinforced wire of this invention relies on the grain boundary pinning and high-temperature structural stabilization effect of the three-dimensional continuous graphene skeleton. Its mechanical strength is significantly higher than that of traditional pure copper wires throughout the entire temperature range, and its strength decay rate is extremely slow. Its high-temperature resistance to softening, deformation and thermal fatigue is significantly improved, making it fully suitable for the long-term high-temperature and harsh service environment of computing chips. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a process flow diagram of the low-temperature bonding method of the present invention; Figure 2 This is a schematic diagram of the longitudinal cross-sectional microstructure of the graphene-reinforced copper wire of the present invention; Figure 3 A schematic diagram of the scanning electron microscope (SEM) morphology of the three-dimensional graphene network framework; Figure 4 This is a schematic diagram of the interface structure before and after low-temperature bonding of the wires to the chip pads; Figure 5 This is a comparison curve of high-temperature current density-lifetime (J-TTF) between the conductor of the present invention and a conventional copper conductor; Figure 6 This is a schematic diagram of the structure of the wires of the present invention applied to the three-dimensional stacked interconnect of Chiplet; Figure 7 This is a curve comparing the high-temperature mechanical properties of the conductor of this invention with those of a traditional copper conductor; Figure 8 This is a graph comparing the electromigration performance of the conductor of this invention with that of a traditional copper conductor. Detailed Implementation

[0021] The technical solution of the present invention will now be clearly and completely described with reference to specific embodiments. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0022] A highly reliable graphene-reinforced copper interconnect wire is disclosed. The wire has a composite structure consisting of a copper substrate and a three-dimensional continuous graphene network framework uniformly dispersed within it. The wire diameter ranges from 0.5 μm to 10 μm. The three-dimensional graphene network is a porous, foam-like continuous structure, with pores completely filled by a highly dense copper substrate. The wire's allowable operating current density at 125°C is [not specified]. The volume fraction of the three-dimensional graphene network is 0.5 vol% to 5.0 vol%; the axial thermal conductivity of the conductor is ≥600 W / (m•K); the coefficient of thermal expansion of the conductor is 5 to 8 ppm / K; the copper matrix is ​​high-purity oxygen-free copper with a grain size of nanocrystal (100 nm to 500 nm); the graphene framework is composed of fewer than 10 layers of interconnected graphene sheets, which are tightly bonded to the copper matrix interface and free of pores and harmful phases.

[0023] A low-temperature bonding method for highly reliable interconnect graphene-reinforced copper wires includes the following steps: S1 Surface catalytic activation treatment of the wire: A nano-catalytic layer with a thickness of 2 nm to 10 nm is prepared on the surface of the end to be bonded of the graphene-reinforced copper wire by physical vapor deposition or chemical plating; the catalytic layer material is one of Au, Pd, Ag or Sn-Ag alloy; S2 chip pad pretreatment: Plasma cleaning or wet cleaning is performed on the copper or aluminum pads of the chip to remove oxides and organic contaminants, resulting in a clean and activated metal surface. S3 Precise Positioning and Pre-connection: In an inert gas or vacuum environment, precisely position and align the wire ends processed in step S1 with the chip pads processed in step S2, and apply a light preload of 0.5 N to 2.0 N to make initial contact. S4 In-situ low-temperature solid-solid diffusion bonding: At a temperature of 180℃~250℃ and a pressure of 1 MPa~10 MPa, and held for 30 s~180 s, under the action of the catalytic layer, copper atoms on the surface of the wire and metal atoms on the chip pad undergo solid-solid interdiffusion to form a metallurgical bonding interface. S5 Interface Strengthening and Stabilization Treatment: After bonding is completed, the bonding points are briefly annealed for 30 s to 60 s in a protective atmosphere at 250℃~300℃ to promote the formation of an intermetallic compound diffusion layer with a compositional gradient at the interface, further reducing the interface resistance and enhancing the bonding strength.

[0024] Reference Figure 1 , Figure 1 This is a process flow diagram for the low-temperature bonding method; 1. Material preparation: Prepare graphene-reinforced copper wire substrate, clean the surface, and remove impurities and oxide layers; 2. Surface treatment: Activation etching is performed on the bonding interface to enhance interfacial activity and atomic diffusion capability; 3. Intermediate layer preparation: A nano-gradient transition layer is laid at the interface to reduce residual stress and optimize bonding performance; 4. Low-temperature bonding: Solid-phase diffusion bonding is carried out under low temperature (150~250℃) and nitrogen / argon protection, combined with pressure, to achieve high-strength low-temperature bonding; 5. Cooling and curing: Controlled gradient cooling cures the bonded structure and eliminates internal stress; 6. Performance Testing: Conduct comprehensive testing on electrical, mechanical, and interfacial properties to ensure compliance; 7. Encapsulation Protection: The interconnect areas are protected to extend service life; 8. Quality assessment: Conduct accelerated reliability testing. If the test fails, feedback is sent to the upstream process for optimization. If the test passes, proceed to the next step. 9. Finished product: A high-strength, high-conductivity, and high-reliability graphene-reinforced copper wire interconnect is obtained.

[0025] Specific implementation: Graphene-reinforced copper wires with a diameter of 2 μm were fabricated and used for interconnection between GPU chips and HBM; Conductor fabrication: Three-dimensional graphene foam (3D-GF) was grown by CVD using nickel foam as a template; oxygen-free copper was infiltrated into the pores of 3D-GF using a vacuum pressure infiltration process to obtain a composite ingot; a conductor with a diameter of 2μm was obtained through hot extrusion, multi-pass drawing, and intermediate annealing; its current carrying capacity at 125℃ was measured to be [value missing]. The axial thermal conductivity is 620 W / (m·K); Surface catalytic treatment: A 5 nm thick Au catalytic layer was deposited at the end of the wire using magnetron sputtering; Low-temperature bonding: In a nitrogen-protected environment, the wires are aligned with the copper pads of the GPU chip and bonded at 220°C and 5 MPa pressure for 120 s, followed by annealing at 280°C for 40 s. Performance testing; Bond strength: Average shear strength is 58 MPa; Interface resistance: Single-point contact resistance ; Reliability testing: After 1000 cycles of thermal cycling at 55℃~125℃ and 1000 hours of high-temperature storage at 150℃, the resistance change rate was <2.5% and <3%, respectively. Thermal management effect: Under the same power consumption, the hot spot temperature of the GPU-HBM integrated module using this interconnect is 18°C ​​lower than that of the traditional copper bump interconnect.

[0026] Comparative example: Thermo-bonding of conventional electroplated copper wires; Conventional electroplated copper wires of the same diameter were used for thermocompression bonding at 400℃ and 10 MPa. Test results showed that the maximum permissible current density at 125℃ was... After bonding, the low-k dielectric layer of the chip was damaged, and the failure rate reached 35% after 500 thermal cycles.

[0027] Reference Figure 2 , Figure 2 This invention presents the internal microscopic cross-sectional structure of the graphene-reinforced copper composite wire. The structure consists of an outer copper matrix and an internally dispersed and uniformly distributed graphene reinforcing phase. The graphene reinforcing phase is oriented and uniformly arranged within the copper matrix, forming a continuous three-dimensional reinforced conductive network. This unique composite structure, on the one hand, relies on the copper matrix to ensure extremely excellent intrinsic conductivity; on the other hand, through the high strength, high modulus, dislocation pinning, and load transfer effects of graphene, it significantly improves the overall strength, high-temperature stability, and fatigue resistance of the material with almost no sacrifice in conductivity. This fundamentally solves the core bottleneck in the industry where the strength and conductivity of copper wires cannot be simultaneously achieved. Figure 2The paper further demonstrates the diffuse distribution of graphene-reinforced phase in a copper matrix. The graphene-reinforced phase is uniformly embedded in the grain boundaries and within the copper matrix, forming a three-dimensional network reinforcement structure. This structure can achieve synergistic improvement in dislocation pinning, grain boundary stability, and conductivity pathways, providing structural support for the high strength, high conductivity, and high stability of the material.

[0028] Reference Figure 3 , Figure 3 This is a scanning electron microscope (SEM) morphology diagram of the three-dimensional graphene network framework, which is a microscopic structural diagram of the three-dimensional porous graphene network framework, the core reinforcement of this invention. The structure is a continuous, interconnected, three-dimensional honeycomb porous graphene network with uniform pore size, excellent connectivity, large specific surface area, and extremely strong structural stability. This prefabricated three-dimensional framework can achieve complete and uniform wetting and filling of the copper matrix, forming a globally continuous conductive and reinforcing network within the copper matrix. This completely solves the industry's preparation problems of graphene agglomeration, uneven dispersion, and poor interfacial bonding, providing a core structural foundation for the synergistic improvement of high strength and high conductivity in composite materials.

[0029] Reference Figure 4 , Figure 4 This diagram illustrates the comparison of the bonding interface state between the chip and interconnect wires before and after the implementation of the low-temperature bonding process. The left side shows the bonding process before bonding: traditional copper interconnects easily form a dense oxide layer, severely hindering atomic diffusion at the interface, resulting in low bonding strength, easy solder joint failure, and poor reliability. The right side shows the bonding process after the low-temperature bonding process of this invention: the surface oxide layer can be removed in situ, achieving a clean metallurgical connection between the copper substrate and the chip pins, forming a defect-free, high-strength, and low-resistance perfect connection interface. This low-temperature bonding process significantly reduces the bonding temperature, effectively avoiding thermal damage to the precision transistor structure of computing chips caused by high temperatures, and greatly improving bonding yield and long-term interface reliability.

[0030] Reference Figure 5 , Figure 5 This is a comparison curve of high-temperature current density-lifetime (J-TTF) between the conductor of the present invention and the conventional copper conductor. This figure compares the reliability of the current density-electromigration lifetime (J-TTF) of the two interconnect conductors under a constant high-temperature environment of 200℃, with an error range of ±5%. The horizontal axis is the on-load current density (A / mm²), and the vertical axis is the device failure lifetime (hours). The blue line is the graphene-reinforced conductor of the present invention, and the green line is the conventional pure copper conductor.

[0031] Test results show that under the same current density conditions, the electromigration life of the conductor of this invention far exceeds that of traditional pure copper conductors; under high current and high current density overload conditions, the life improvement advantage is further amplified, and it has extremely strong anti-electromigration and anti-Joule thermal failure capabilities, perfectly meeting the high reliability requirements of AI computing chips with ultra-high power consumption, ultra-high current density, and long-term continuous full-load operation.

[0032] Reference Figure 6, Figure 6 This diagram illustrates the application of the conductive wires of this invention in the three-dimensional stacked interconnection of Chiplet. It shows a typical structure of the graphene-reinforced copper conductive wires of this invention in the advanced three-dimensional high-density packaging of AI computing power Chiplet. It comprises three core components: a multi-layer vertical stacked Chiplet structure, a high-density interlayer wiring layout, and interlayer vertical conductive wire interconnection. The ultra-high strength and high conductivity graphene copper conductive wires of this invention enable vertical stacking of multi-layer heterogeneous chips and ultra-high density micro-pitch wiring interconnection, completing a large number of highly reliable signals and power transmissions within an extremely compact space. This perfectly meets the interconnection requirements of high bandwidth, high integration, and three-dimensional heterogeneous stacking of AI high-computing power chips, overcoming the structural bottleneck of traditional bonding wires being unable to adapt to ultra-high density Chiplet packaging.

[0033] Reference Figure 7 , Figure 7 This is a graph comparing the high-temperature mechanical properties of the wire of this invention with those of conventional copper wire. The graph shows the comparison of the high-temperature tensile mechanical property degradation characteristics of the three-dimensional graphene-reinforced copper interconnect wire and the conventional pure copper wire within a wide temperature service range.

[0034] The horizontal axis represents the ambient test temperature (°C), and the vertical axis represents the measured mechanical strength of the material at high temperatures (MPa). The blue curve represents the graphene-reinforced wire of this invention, and the red curve represents the traditional pure copper wire. As the temperature rises, the traditional pure copper wire undergoes severe recrystallization and softening, rapid dislocation slippage, and a sharp drop in mechanical strength, resulting in rapid failure of its high-temperature load-bearing capacity.

[0035] Reference Figure 8 , Figure 8 This graph compares the electromigration performance of the wires of this invention with that of traditional copper wires; the graph also compares the electromigration lifetime of the two types of wires at a high temperature of 100℃. Compared with traditional pure copper wires, the graphene-reinforced copper wires of this invention have higher electromigration activation energy and lifetime index, and the average failure time is improved by more than two orders of magnitude across the entire current density range; in the typical operating range of computing chips, the long-term service life reaches hundreds of times that of traditional copper wires, which greatly enhances the interconnect durability and reliability under harsh environments of high current and high temperature, providing core high-reliability interconnect protection for the three-dimensional high-density heterogeneous packaging of next-generation AI computing chips.

Claims

1. A highly reliable interconnect graphene-reinforced copper wire, wherein the wire has a composite structure consisting of a copper substrate and a three-dimensional continuous graphene network framework uniformly dispersed within it, characterized in that: The wire diameter ranges from 0.5 μm to 10 μm; the three-dimensional graphene network is a porous, foam-like continuous structure, with the pores completely filled by a highly dense copper substrate. The allowable operating current density of the wire at 125°C is [not specified]. .

2. The high-reliability interconnect graphene-reinforced copper wire according to claim 1, characterized in that: The volume fraction of the three-dimensional graphene network ranges from 0.5 vol% to 5.0 vol%.

3. The high-reliability interconnect graphene-reinforced copper wire according to claim 1, characterized in that: The axial thermal conductivity of the conductor is ≥600 W / (m•K).

4. The high-reliability interconnect graphene-reinforced copper wire according to claim 1, characterized in that: The thermal expansion coefficient of the conductor is 5–8 ppm / K.

5. The high-reliability interconnect graphene-reinforced copper wire according to claim 1, characterized in that: The copper matrix is ​​high-purity oxygen-free copper with a grain size of nanocrystals (100 nm to 500 nm). The graphene framework is composed of fewer than 10 layers of interconnected graphene sheets, which are tightly bonded to the copper matrix interface and are free of pores and harmful phases.

6. The low-temperature bonding method for high-reliability interconnect graphene-reinforced copper wires according to any one of claims 1-5, characterized in that, Includes the following steps: S1 Surface catalytic activation treatment of the wire: A nano-catalytic layer with a thickness of 2 nm to 10 nm is prepared on the surface of the end to be bonded of the graphene-reinforced copper wire by physical vapor deposition or chemical plating; the catalytic layer material is one of Au, Pd, Ag or Sn-Ag alloy; S2 chip pad pretreatment: Plasma cleaning or wet cleaning is performed on the copper or aluminum pads of the chip to remove oxides and organic contaminants, resulting in a clean and activated metal surface. S3 Precise Positioning and Pre-connection: In an inert gas or vacuum environment, precisely position and align the wire ends processed in step S1 with the chip pads processed in step S2, and apply a light preload of 0.5 N to 2.0 N to make initial contact. S4 In-situ low-temperature solid-solid diffusion bonding: At a temperature of 180℃~250℃ and a pressure of 1 MPa~10 MPa, and held for 30 s~180 s, under the action of the catalytic layer, copper atoms on the surface of the wire and metal atoms on the chip pad undergo solid-solid interdiffusion to form a metallurgical bonding interface. S5 Interface Strengthening and Stabilization Treatment: After bonding is completed, the bonding points are briefly annealed for 30 s to 60 s in a protective atmosphere at 250℃~300℃ to promote the formation of an intermetallic compound diffusion layer with a compositional gradient at the interface, further reducing the interface resistance and enhancing the bonding strength.

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