A vertical power system-in-a-package structure and a manufacturing method thereof

Abstract

The application discloses a vertical power supply system level packaging structure, comprising: a first redistribution layer adopts a multi-layer fan-out redistribution interconnection structure; a first plastic packaging layer is internally provided with a plurality of copper bumps and a plurality of active and passive elements, the plurality of copper bumps are arranged above the first redistribution layer at intervals, the plurality of active and passive elements are arranged between the copper bumps, the copper bumps and the active and passive elements are externally covered with dielectric material to form a plastic packaging structure; a second redistribution layer is arranged above the copper bumps; a second plastic packaging layer comprises a plurality of active and passive elements, the plurality of active and passive elements are arranged above the second redistribution layer, and the active and passive elements are externally covered with dielectric material to form a plastic packaging structure. The application provides a vertical power supply system level packaging structure, shortens the interconnection distance of a power supply and a load chip, improves the stability of the power supply chip, and thus reliably and effectively controls power supply. The application further provides a manufacturing method of the vertical power supply system level packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a vertical power supply system-level packaging structure and its fabrication method. Background Technology

[0002] In existing system packaging technologies, power chips and load chips (such as computing chips) are arranged horizontally and interconnected using traces. In this structure, when the power chip supplies power to the load chip, the current needs to flow through long horizontal traces and interconnects on the packaging substrate, significantly increasing the actual interconnect distance between them. Since parasitic resistance, inductance, and capacitance inevitably exist in the physical interconnects and the packaging substrate, these parasitic effects are amplified when the interconnect distance is too long. The effects of parasitic inductance and capacitance are particularly prominent. In high-power-density, high-current applications with rapid load transients, such as high-performance computing, long interconnect paths can cause voltage overshoot, undershoot, power supply noise, and power supply dynamic response delays, severely interfering with power quality and hindering the packaging of high-power load chips. Summary of the Invention

[0003] The purpose of this invention is to provide a vertical power supply system-level package structure and its manufacturing method, which shortens the interconnection distance between the power supply and load chips, improves the stability of the power supply chip, and thus enables reliable and effective power supply control.

[0004] The technical solution adopted in the vertical power supply system-level packaging structure and its manufacturing method disclosed in this invention is as follows: A vertical power supply system-in-package structure, comprising: The first redistribution layer serves as a substrate and employs a multi-layer fan-out redistribution interconnect structure. The first molding layer has a plurality of copper bumps and a plurality of active and passive components inside. The plurality of copper bumps are spaced apart above the first redistribution layer, and the plurality of active and passive components are disposed between the copper bumps. The copper bumps are higher than the active and passive components. The copper bumps and the active and passive components are covered with a dielectric material to form a molding structure. A second redistribution layer is disposed above the copper bumps; The second molding layer includes a plurality of active and passive components, which are disposed above the second redistribution layer, and the surfaces of the active and passive components are covered with dielectric material to form a molding structure.

[0005] As a preferred embodiment, the first redistribution layer has a 1-6 layer structure, and the first redistribution layer includes copper lines and conductive copper pillars, the conductive copper pillars are used for conduction between layers, and the thickness of the copper lines and conductive copper pillars is 25-150um.

[0006] As a preferred embodiment, the height of the copper bump is 50-1000um, and the height difference between the copper bump and the active / passive component is greater than 20um.

[0007] As a preferred embodiment, the active and passive components in the first molding layer include a power chip, a capacitor, an inductor, and a resistor; the active and passive components in the second molding layer include a load chip, a capacitor, an inductor, and a resistor.

[0008] As a preferred embodiment, the mounting methods of the active and passive components include mounting and fixing single-sided I / O chips using I / O-down flip-chip technology or I / O-up upright mounting, mounting double-sided I / O chips using solder paste or silver paste bonding technology on a single I / O side, and mounting passive components using SMT mounting method.

[0009] As a preferred embodiment, the dielectric material is any one of EMC, PI, and ABF.

[0010] A method for fabricating the above-mentioned vertical power supply system-level package structure includes the following steps: S1. Create the first rerouting layer, using a fan-out rerouting method for rerouting design and fabrication; S2. The copper bumps are fabricated by using a thick dry film multiple-layer stacking process on the first rewiring layer to achieve the copper bump structure. S3. Mount the active and passive components. Mount and connect the active and passive components on the first redistribution layer, and place the active and passive components between the copper bumps. S4. High-voltage molding: The dielectric material is filled into the empty space of the copper bumps and active and passive components using a high-voltage molding process, so that the dielectric material molds and covers the copper bumps and active and passive components to form the first molding layer. S5. Grind out copper bumps. Grind the dielectric material on the surface of the copper bumps to expose the upper part of the copper bumps. S6. Fabricate the second rewiring structure using the same process as in step S1, and fabricate the second rewiring layer on the upper end of the copper bumps. S7. Mount the active and passive components; mount and connect the active and passive components on the corresponding second redistribution layer so that the active and passive components on the upper and lower sides are connected through the second redistribution layer.

[0011] S8. Re-encapsulation: The second layer of active and passive components is encapsulated a second time using dielectric material.

[0012] The beneficial effects of the vertical power supply system-level packaging structure disclosed in this invention are as follows: the first redistribution layer acts as a substrate, which can be connected to external circuit boards, etc., below it, while the fan-out of the active and passive component pads in the first molding layer above achieves the initial distribution. The copper bumps serve to connect the first and second redistribution layers, forming a vertical conductive channel. Active and passive components are then placed above the second redistribution layer. The active and passive components on the second redistribution layer are connected to the active and passive components on the first redistribution layer through the copper bumps. In the actual packaging process, the active and passive components in the first molding layer can be power chips, and the active and passive components in the second molding layer can be load chips, thereby forming a vertical power supply system architecture. This greatly shortens the interconnection distance between the power supply and load chips, avoiding interference from parasitic inductance, capacitance, and other factors caused by excessive distance between chips, and greatly helps the power supply chip to improve stable and reliable power supply control. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a vertical power supply system-level packaging structure according to the present invention.

[0014] Figure 2 This is a schematic diagram of step S1 of the manufacturing method of a vertical power supply system-level packaging structure according to the present invention.

[0015] Figure 3 This is a schematic diagram of steps S2 and S3 of the method for manufacturing a vertical power supply system-level package structure according to the present invention.

[0016] Figure 4 This is a schematic diagram of steps S4 and S5 of the method for manufacturing a vertical power supply system-level package structure according to the present invention.

[0017] Figure 5 This is a schematic diagram of step S6 in the manufacturing method of a vertical power supply system-level packaging structure according to the present invention.

[0018] Figure 6 This is a schematic diagram of steps S7 and S8 of the method for manufacturing a vertical power supply system-level package structure according to the present invention. Detailed Implementation

[0019] The present invention will be further described and illustrated below with reference to specific embodiments and the accompanying drawings: Please refer to Figure 1 A vertical power supply system-level package structure, comprising: The first redistribution layer 10 serves as a substrate and employs a multi-layer fan-out redistribution interconnection structure. The first redistribution layer 10 acts as a substrate, and its underside can be connected to external circuit boards, etc. The first redistribution layer 10 adopts a fan-out (FO, routing from chip I / O) redistribution method for redistribution design and fabrication, which is different from the double-sided symmetrical fabrication method of BT / ABF substrate. It is usually designed as a 1-6 layer structure. The first redistribution layer 10 includes copper lines 11 and conductive copper pillars 12. The conductive copper pillars 12 are used for conduction between layers. Based on the high current characteristics of power chips, the thickness of copper lines 11 and conductive copper pillars 12 is 25-150um, ensuring low resistance and good heat dissipation.

[0020] The first molding layer 20 has a plurality of copper bumps 21 and a plurality of active and passive components 50 inside. The plurality of copper bumps 21 are spaced apart above the first redistribution layer 10, and the plurality of active and passive components 50 are disposed between the copper bumps 21, with the copper bumps 21 being higher than the active and passive components 50. The copper bumps 21 and the active and passive components 50 are covered with a dielectric material 60 to form a molding structure.

[0021] The copper bumps 21 have a solid structure, thus providing good conductivity and enabling them to form vertical conductive channels with other layers. The active and passive components 50 are positioned between the copper bumps 21 and mounted on the first redistribution layer 10. Therefore, the active and passive components 50 can conduct to external circuit boards through the first redistribution layer 10, or to other upper layers through the first redistribution layer 10 and the copper bumps 21. To meet subsequent process requirements, the height difference between the copper bumps 21 and the active and passive components 50 is greater than 20µm, and the height of the copper bumps 21 varies from 50 to 1000µm depending on the height of the active and passive components 50. The active and passive components 50 in the first molding layer 20 include power chips, capacitors, inductors, and resistors.

[0022] The second rewiring layer 30 uses the same process as step S1. The second rewiring layer is fabricated on the upper side of the copper bump 21. The first rewiring layer 10 and the second rewiring layer 30 are vertically connected through the copper bump 21, forming a foundation for the connection. The second molding layer 40 includes a plurality of active and passive components 50, which are disposed above the second redistribution layer 30. The active and passive components 50 are covered with dielectric material 60 to form a molding structure vertical power supply system architecture. The active and passive components 50 in the second molding layer 40 include load chips, capacitors, inductors and resistors.

[0023] The active and passive components 50 in the second molding layer 40 are connected to the active and passive components 50 on the first molding layer 20 through the second redistribution layer 30, copper bumps 21 and the first redistribution layer 10, realizing a vertical power supply structure. The overall thickness can be compressed as much as possible, thereby shortening the interconnection distance between the two, without being limited by the size of the active and passive components 50 themselves.

[0024] In the above scheme, the mounting methods of active and passive components 50 include single-sided I / O chips using I / O-down flip-chip process or I / O-up upright mounting for mounting and fixing, double-sided I / O chips using solder paste or silver paste bonding process on a single I / O side, and passive components (capacitors, inductors, resistors, etc.) using SMT mounting method.

[0025] The dielectric material 60 mentioned above is any one of EMC, PI, and ABF. It is filled using a vacuum high-pressure method to avoid gaps during the filling process and to protect the active and passive components.

[0026] A method for fabricating the above-mentioned vertical power supply system-level package structure includes the following steps: Please refer to Figure 2 S1. Fabricate the first rewiring layer. The rewiring design and fabrication adopts a fan-out (FO, the wiring is led out from the chip I / O) rewiring method. Unlike the double-sided symmetrical fabrication method of BT / ABF substrate, this structure is a multi-layer fan-out rewiring interconnection structure. Based on the high current characteristics of the power chip, the thickness of the lines and conducting copper pillars 12 is usually 25-150um. Please refer to Figure 3 The fabrication of S2 and copper bump 21 is achieved by using a thick dry film multiple-layer stacking process on the first redistribution layer. Based on the requirements of subsequent processes, the height of copper bump 21 is determined according to the height of the active and passive components 50, achieving a height of 50~1000um. S3. Mount the active and passive components 50. Mount and connect the active and passive components on the first redistribution layer. The active and passive components 50 are located between the copper bumps 21. The core component is a power chip. Please refer to Figure 4 S4, High-voltage molding: Using dielectric material 60, the copper bumps 21 and the empty space of the mounted device are filled with high-voltage molding process. At this time, vacuum high-voltage method should be used to avoid gaps in the filling process and form the first molding layer 20. S5. Grind out copper bumps 21. Grind the dielectric material 60 on the surface of the copper bumps 21 to expose the upper end of the copper bumps 21. Please refer to Figure 5S6. Fabricate the second rewiring structure using the same process as in step S1, and fabricate the second rewiring layer on the upper end of the copper bump 21. Please refer to Figure 6 S7. Mount the active and passive components 50; mount and connect the active and passive components on the corresponding second redistribution layer, so that the active and passive components 50 on the upper and lower sides are connected through the second redistribution layer 30. The main component is a high-power load chip.

[0027] S8. Re-encapsulation: The second layer of active and passive components 50 is encapsulated a second time using dielectric material 60.

[0028] This invention provides a vertical power supply system-level package structure and its manufacturing method. A first redistribution layer acts as a substrate, allowing communication with external circuit boards below. The upper part of the redistribution layer, in conjunction with the fan-out of the active and passive component pads in the first molding compound layer, achieves initial distribution. Copper bumps facilitate communication between the first and second redistribution layers, forming a vertical communication channel. Active and passive components are then placed above the second redistribution layer, communicating with those on the first redistribution layer via copper bumps. In actual packaging, the active and passive components in the first molding compound layer can be power chips, and those in the second molding compound layer can be load chips, thus forming a vertical power supply system architecture. This significantly shortens the interconnection distance between the power and load chips, avoiding interference from parasitic inductance and capacitance caused by excessive chip spacing, and greatly improving the stability and reliability of power supply control.

[0029] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A vertical power supply system-level packaging structure, characterized in that, include: The first redistribution layer serves as a substrate and employs a multi-layer fan-out redistribution interconnect structure. The first molding layer has a plurality of copper bumps and a plurality of active and passive components inside. The plurality of copper bumps are spaced apart above the first redistribution layer, and the plurality of active and passive components are disposed between the copper bumps. The copper bumps are higher than the active and passive components. The copper bumps and the active and passive components are covered with a dielectric material to form a molding structure. A second redistribution layer is disposed above the copper bumps; The second molding layer includes a plurality of active and passive components, which are disposed above the second redistribution layer, and the surfaces of the active and passive components are covered with dielectric material to form a molding structure.

2. The vertical power supply system-level packaging structure as described in claim 1, characterized in that, The first redistribution layer has a 1-6 layer structure, and the first redistribution layer includes copper lines and conductive copper pillars. The conductive copper pillars are used for conduction between layers, and the thickness of the copper lines and conductive copper pillars is 25-150um.

3. The vertical power supply system-level packaging structure as described in claim 1, characterized in that, The height of the copper bump is 50-1000um, and the height difference between the copper bump and the active / passive component is greater than 20um.

4. The vertical power supply system-level packaging structure as described in claim 1, characterized in that, The active and passive components in the first molding compound include a power chip, a capacitor, an inductor, and a resistor; the active and passive components in the second molding compound include a load chip, a capacitor, an inductor, and a resistor.

5. The vertical power supply system-level packaging structure as described in claim 4, characterized in that, The mounting methods for the active and passive components include: single-sided I / O chips are mounted and fixed using a flip-chip I / O-down or I / O-up mounting process; double-sided I / O chips are mounted using a solder paste or silver paste bonding process on a single I / O side; and passive components are mounted using an SMT mounting method.

6. The vertical power supply system-level packaging structure as described in claim 1, characterized in that, The dielectric material is any one of EMC, PI, and ABF.

7. A method for manufacturing a vertical power supply system-level package structure according to any one of claims 1-6, characterized in that, Includes the following steps: S1. Create the first rerouting layer, using a fan-out rerouting method for rerouting design and fabrication; S2. The copper bumps are fabricated by using a thick dry film multiple-layer stacking process on the first rewiring layer to achieve the copper bump structure. S3. Mount the active and passive components. Mount and connect the active and passive components on the first redistribution layer, and place the active and passive components between the copper bumps. S4. High-voltage molding: The dielectric material is filled into the empty space of the copper bumps and active and passive components using a high-voltage molding process, so that the dielectric material molds and covers the copper bumps and active and passive components to form the first molding layer. S5. Grind out copper bumps. Grind the dielectric material on the surface of the copper bumps to expose the upper part of the copper bumps. S6. Fabricate the second rewiring structure using the same process as in step S1, and fabricate the second rewiring layer on the upper end of the copper bumps. S7. Mount the active and passive components; mount and connect the active and passive components on the corresponding second redistribution layer so that the active and passive components on the upper and lower sides are connected through the second redistribution layer. S8. Re-encapsulation: The second layer of active and passive components is encapsulated a second time using dielectric material.

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