A method of d2w hybrid bonding

Abstract

The application relates to a D2W hybrid bonding method, and belongs to the technical field of semiconductors, which is used to solve at least one of the problems of the bonding interface defects of a chip and a wafer being many, the quality being poor, the alignment deviation being large, the alignment deviation redundancy being small, the efficiency being low, and the cost being high. In the application, the sizes of the pads on the chip and the wafer are different. Due to the deviation of the pad sizes, the large pad can accommodate the small pad, the process difficulty of alignment can be effectively reduced, the redundancy of the alignment process is increased, the alignment deviation is greatly reduced, the pad design of different structures avoids the problem that water stored in the pad cannot be discharged from the interface when the pad is a recess structure, the bonding interface defects and cavities are reduced, and the bonding quality of the bonding interface is increased.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for D2W hybrid bonding. Background Technology

[0002] Chip-to-wafer (D2W) hybrid bonding is an important means to achieve three-dimensional integrated packaging of chips and overcome bandwidth interconnection limitations. D2W hybrid bonding differs from traditional liquid phase bonding by eliminating traditional metal solder joints and directly aligning and mounting known good chips onto the substrate wafer. It places extremely high demands on the microstructure and surface morphology of the chip and wafer surfaces. Therefore, the pad structure on the wafer surface needs to be specifically designed to meet the interface requirements of D2W hybrid bonding.

[0003] In hybrid bonding processes, due to the mismatch in thermal expansion (CTE) between the metal and dielectric materials, the metal pads are typically designed as recessed areas during chemical mechanical polishing (CMP), generally between 0.5-15 nm. During the pre-bonding stage, the surface-activated dielectric layers connect to each other under van der Waals forces, and the metal pads on both sides remain separated due to the recessed structure. Subsequently, during the high-temperature annealing stage, because the CTE of copper is higher than that of dielectric materials such as silicon oxide, the originally recessed metal pads expand, the metals of the upper and lower pads gradually come into contact, and atomic diffusion occurs, ultimately forming diffusion bonding between the metal pads, creating a metallic electrical interconnect. The current scheme has the following disadvantages: (1) Both sides are recessed structures, which are prone to leaving moisture and air in the cleaning process after plasma activation, which will increase the difficulty of metal diffusion and reduce the stability of the bonding interface; (2) The size of the metal pads of the same size on both sides increases the difficulty of alignment and is prone to introducing alignment deviation; (3) The pad structure of the same structure and size on both sides has less redundancy in the high temperature annealing process. When the annealing temperature is high or the time is long, the expansion of the metal is prone to peeling off the surrounding dielectric layer and destroying the bonding quality of the interface; (4) The pad structure of the same structure and size on both sides consumes a lot of alignment time in the D2W hybrid bonding process, which seriously reduces the process output and increases the production cost. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a D2W hybrid bonding method to solve at least one of the following problems in existing methods: numerous defects at the bonding interface between the chip and the wafer, poor quality, large alignment deviation, small alignment deviation redundancy, low efficiency, and high cost.

[0005] In a first aspect, the present invention provides a method for D2W hybrid bonding, comprising the following steps:

[0006] (1) Provide a chip with multiple cylindrical bump pads;

[0007] (2) Provide a wafer with multiple dish-shaped recessed pads;

[0008] (3) Bond the chip and the wafer to obtain a D2W hybrid bonding sample;

[0009] The cylindrical raised pads and the dish-shaped recessed pads are arranged in a one-to-one correspondence, and the diameter of the cylindrical raised pads is smaller than the diameter of the dish-shaped recessed pads.

[0010] Furthermore, the diameter of the cylindrical raised pad is 0.1–24 μm, the pitch is 0.4–50 μm, and the thickness is 0.05–5 μm.

[0011] Furthermore, the height of the cylindrical protruding pad protruding from the chip dielectric layer is less than the depth of the dish-shaped recessed pad.

[0012] Furthermore, the protrusion height of the cylindrical raised pad protruding from the chip dielectric layer is 0.01-24.5nm, and the recess depth of the dish-shaped recessed pad is 0.02-25nm.

[0013] Furthermore, the diameter of the dish-shaped recessed pad is (1.05~10) × the diameter of the cylindrical raised pad.

[0014] Furthermore, the diameter of the dish-shaped recessed pad is 0.2–25 μm, the pitch is 0.4–50 μm, and the thickness is 0.05–5 μm.

[0015] Furthermore, the dielectric layer length between adjacent raised pads is 30-200% of the diameter of the raised pads, and the dielectric layer spacing between adjacent recessed pads is 30-200% of the diameter of the recessed pads.

[0016] Furthermore, the chip has a length of 1–50 mm, a width of 1–50 mm, and a thickness of 10–1.6 × 10⁻⁶ mm. 3 μm.

[0017] Furthermore, the chip is a single-layer or multi-layer bonded chip.

[0018] Furthermore, the wafer size is 2 to 12 inches.

[0019] Furthermore, the wafer is one of the following: an unbonded wafer, a D2W hybrid bonded wafer sample with multilayer chips already bonded, or a W2W hybrid bonded wafer sample with multilayer chips already bonded.

[0020] Secondly, the present invention provides a D2W hybrid bonded sample obtained by the above method.

[0021] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0022] (1) In this invention, the pads on the chip and the wafer are different in size. Due to the deviation in pad size, the large pad can accommodate the small pad, which can effectively reduce the difficulty of alignment process, increase the redundancy of alignment process, and greatly reduce alignment deviation. The pad design with different structure avoids the problem that water stored in the pad cannot be drained from the interface when they are all recessed structures, reduces defects and voids in the bonding interface, and increases the bonding quality of the bonding interface.

[0023] (2) Compared with the traditional interconnection of two small pads of the same size, the method of the present invention uses pads of different sizes to interconnect, which can increase the reliability of electrical interconnection and avoid the increase in resistance and electromigration problems caused by the same size deviation; the pad structure with different structure and size on both sides provides a larger expansion space for the small pad in the high temperature annealing process, which can effectively reduce the peeling of the surrounding dielectric layer caused by the expansion of high temperature metal and significantly improve the stability of the hybrid bonding interface.

[0024] (3) The present invention uses pads with different structures and sizes on both sides. Due to the reduction in alignment accuracy, the alignment time of the D2W hybrid bonding process can be reduced, the process capability requirements of the bonding equipment can be reduced, the process output can be significantly increased, and the production cost can be reduced.

[0025] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0026] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0027] Figure 1 This is a schematic diagram of a D2W hybrid bonding method according to the present invention;

[0028] Figure 2 The image shows a CSAM diagram of the sample interface after bonding using the method described in Example 1 of this invention.

[0029] Figure 3 The image shows the CSAM diagram of the sample interface after bonding using the method of Comparative Example 1 of this invention.

[0030] Figure 4 The image shows a SEM image of the sample interface after bonding using the method described in Example 1 of this invention.

[0031] Figure 5 The image shows the SEM image of the sample interface after bonding using the method of Comparative Example 8 of this invention.

[0032] Figure 6 This is a schematic diagram of a D2W hybrid bonding method according to Comparative Example 1 of the present invention;

[0033] Figure 7 This is a schematic diagram of a D2W hybrid bonding method according to Comparative Example 7 of the present invention. Detailed Implementation

[0034] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part of the present invention and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0035] A specific embodiment of the present invention, such as Figure 1 As shown, a method for D2W hybrid bonding is disclosed, comprising the following steps:

[0036] (1) Provide a chip with multiple cylindrical bump pads;

[0037] (2) Provide a wafer with multiple dish-shaped recessed pads;

[0038] (3) Bond the chip and the wafer to obtain a D2W hybrid bonding sample;

[0039] The cylindrical raised pads and the dish-shaped recessed pads are arranged in a one-to-one correspondence, and the diameter of the cylindrical raised pads is smaller than the diameter of the dish-shaped recessed pads.

[0040] The dish-shaped recess of this invention is relatively easy to achieve using chemical mechanical polishing (CMP) and is obtained using existing technologies. It is particularly suitable for small-pitch structures suitable for D2W hybrid bonding. The dish-shaped recess retains the metal at the edge of the pad. During alignment, the pads of different sizes provide greater redundancy for alignment, improving accuracy and efficiency. During heating and annealing, it provides expansion space for the bonding of the metal pads, avoiding dielectric pre-bonding failure caused by CTE mismatch between the metal and the dielectric.

[0041] Compared to existing technologies, the different pad sizes on the chip and wafer in this invention allow larger pads to accommodate smaller pads, effectively reducing the difficulty of alignment and increasing the redundancy of the alignment process. This significantly reduces alignment deviation. The different pad structures avoid the problem of water trapped in the pads not being able to drain from the interface when both are recessed structures, reducing defects and voids at the bonding interface and increasing the bonding quality. Compared to the traditional interconnection of two small pads (0.5-10μm) of the same size, the method of this invention uses pads of different sizes, which increases the reliability of electrical interconnection and avoids the increase in resistance and electromigration problems caused by the same size deviation. The different structures and sizes of the pads on both sides provide a larger expansion space for the smaller pads during the high-temperature annealing process, effectively reducing the peeling of the surrounding dielectric layer caused by the expansion of the high-temperature metal and significantly improving the stability of the hybrid bonding interface. The use of pads with different structures and sizes on both sides reduces the alignment time of the D2W hybrid bonding process due to the reduced alignment accuracy, lowers the process capability requirements of the bonding equipment, significantly increases process yield, and reduces production costs.

[0042] It should be noted that the diameter of the cylindrical raised pad is smaller than the diameter of the dish-shaped recessed pad to avoid the recessed pad from connecting with the adjacent pads of the bonded raised pad, which could lead to a short circuit.

[0043] In this invention, the chip is on top and the wafer is below, and the chip and wafer are bonded together. The bump is a downward protrusion relative to the lower surface of the dielectric layer on the chip, and the depression in this invention refers to a downward depression relative to the upper surface of the dielectric layer on the wafer.

[0044] Preferably, the diameter of the dish-shaped recessed pad is (1.05 to 10, for example, 2, 3, 4, 5, 6, 7, 8, 9) × the diameter of the cylindrical raised pad.

[0045] Specifically, the diameter of the cylindrical raised pad is 0.1–24 μm, for example, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, 22 μm; the pitch is 0.4–50 μm, for example, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm; and the thickness is 0.05–5 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm.

[0046] Specifically, the height of the cylindrical protruding pad protruding from the chip dielectric layer is less than the depth of the dish-shaped recessed pad.

[0047] Preferably, the protrusion height of the cylindrical raised pads protruding from the chip dielectric layer is 0.01-24.5nm, for example, 2nm, 4nm, 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm, 22nm, 24nm, and the recess depth of the dish-shaped recessed pads is 0.02-25nm, for example, 2nm, 4nm, 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm, 22nm, 24nm, and the recess depth is greater than or equal to the protrusion height.

[0048] It should be noted that the recess depth mentioned in this invention refers to the maximum distance between the lowest point of the disc-shaped recessed pad and the interface layer.

[0049] Specifically, the diameter of the dish-shaped recessed pad is 0.2–25 μm, for example, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, 22 μm, 24 μm; the pitch is 0.4–50 μm, for example, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm; and the thickness is 0.05–5 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm.

[0050] Preferably, the pitch of the recessed pad is equal to the pitch of the recessed pad to avoid pad misalignment.

[0051] Specifically, the dielectric layer length between adjacent raised pads is 30% to 200% of the diameter of the raised pad (e.g., 40%, 50%, 60%, 70%, 80%, 90%, 100%, 110%, 120%, 130%, 140%, 150%, 160%, 170%, 180%, 190%), and the dielectric layer spacing between adjacent recessed pads is 30% to 200% of the diameter of the recessed pad (e.g., 40%, 50%, 60%, 70%, 80%, 90%, 100%, 110%, 120%, 130%, 140%, 150%, 160%, 170%, 180%, 190%). These ranges are used to avoid short circuits between adjacent upper and lower pads due to excessive alignment errors.

[0052] It should be noted that in this invention, the diameters of the multiple raised pads are the same, and the diameters of the multiple recessed pads are the same.

[0053] Specifically, the length of the chip is 1–50 mm, for example, 5 mm, 10 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, or 45 mm; the width is 1–50 mm, for example, 5 mm, 10 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, or 45 mm; and the thickness is 10–1.6 × 10⁻⁶ mm. 3 μm, for example, 1.1 × 10 3 μm, 1.2×10 3 μm, 1.3×10 3 μm, 1.4×10 3 μm, 1.5×10 3 μm.

[0054] It should be noted that the chip described in this invention is a chip with single or multiple layers bonded together. Preferably, the chip has 1 to 30 layers, for example, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, or 28 layers.

[0055] Specifically, the wafer size is 2 to 12 inches, for example, 4 inches, 6 inches, 8 inches, and 10 inches.

[0056] It should be noted that the wafer of the present invention can be a flat, unbonded wafer, or a D2W hybrid bonded wafer sample with several layers of chips already bonded; wherein the number of chip layers is 0 to 20; or it can be a wafer sample with several layers of W2W hybrid bonding already completed, wherein the number of layers of the W2W hybrid bonded wafer sample is 1 to 5.

[0057] In this invention, the dielectric layer material at the bonding interface can be one or more of silicon-based materials, optoelectronic materials, heat dissipation materials, or alumina. Preferably, the silicon-based material includes one or more of silicon oxide, silicon nitride, silicon carbide, SiCN, and SiCO; the optoelectronic material includes one or more of InP and LiNbO3; and the heat dissipation material includes diamond.

[0058] The cylindrical raised pads and the dish-shaped recessed pads described in this invention are made of metal, preferably copper, aluminum, chromium or their oxides.

[0059] It should be noted that the methods for fabricating chips with cylindrical raised pads and wafers with dish-shaped recessed pads in this invention are both based on existing technologies. For example, they can be fabricated by chemical mechanical polishing (CMP) or etching. Specific pad structures can be obtained by controlling the grinding or etching selectivity.

[0060] Another specific embodiment of the present invention discloses a D2W hybrid bonded sample obtained by the above method.

[0061] The alignment accuracy of the D2W hybrid bonding sample prepared by the method of the present invention is 100-180 nm, the alignment deviation is 200-400 nm, and the UPH is ≥1900 pieces / hour, preferably 1900-2200 pieces / hour.

[0062] The technical solution of the present invention will be further explained below with reference to specific embodiments.

[0063] Example 1

[0064] This embodiment of a D2W hybrid bonding method includes the following steps:

[0065] (1) A 12-inch wafer with a thickness of 775μm is used as the substrate wafer for bonding. The dielectric layer on the bonding surface is silicon dioxide. There are multiple pads with the same shape and size on the dielectric layer. The pad material is copper. The pad diameter is 5μm, the thickness is 1μm, and the pitch is 10μm. The wafer surface is planarized by CMP process. After CMP, the surface roughness of the dielectric layer is <0.5nm. The pads are in a dish-shaped recessed state with a recess depth of 10nm. The length of the dielectric layer between adjacent recessed pads is 150% of the diameter of the recessed pad.

[0066] (2) A 12-inch wafer with a thickness of 775μm is used as the chip wafer to be cut. The bonding surface dielectric layer is silicon dioxide. There are multiple pads with the same shape and size on the dielectric layer and the material is copper. The pad diameter is 4μm, the thickness is 1μm, and the pitch is 10μm. The wafer surface is planarized by CMP process. After CMP, the surface roughness of the dielectric layer is less than 0.5nm. After the treatment, the pads are cylindrical protrusions with a protrusion height of 8nm. The dielectric layer length between adjacent protrusion pads is 100% of the diameter of the protrusion pad.

[0067] (3) The wafer obtained in step (2) is thinned and diced to become a small chip with a size of 5mm*10mm and a thickness of 100μm. The chip is attached to the diced blue film. The wafer after step (1) and the diced chip are activated by plasma activation and cleaning processes, respectively, to activate the surface of the wafer and the chip.

[0068] (4) Place the activated chip and wafer from step (3) on the corresponding stage in the D2W hybrid bonding machine. During the chip-to-wafer bonding alignment process, identify the corresponding positions of the chip and wafer by the alignment mark. After completing the alignment correction, mount the chip on the substrate wafer to obtain the D2W hybrid bonding sample.

[0069] Example 2

[0070] This embodiment of the D2W hybrid bonding method is the same as that in Embodiment 1, except that:

[0071] In step (1), the pad diameter is 10μm, the thickness is 0.5μm, the pitch is 20μm, the recess depth is 15nm, and the dielectric layer length between adjacent recessed pads is 100% of the diameter of the recessed pad.

[0072] In step (2), the pad diameter is 8μm, the thickness is 0.8μm, the pitch is 20μm, the bump height is 12nm, and the dielectric layer length between adjacent bump pads is 88% of the bump pad diameter.

[0073] In step (3), the chip has a size of 1mm*1mm and a thickness of 50μm, and is a single-layer chip.

[0074] Example 3

[0075] This embodiment of the D2W hybrid bonding method is the same as that in Embodiment 1, except that:

[0076] In step (1), the pad diameter is 25μm, the thickness is 3μm, the pitch is 50μm, the recess depth is 25nm, and the dielectric layer length between adjacent recessed pads is 150% of the diameter of the recessed pad.

[0077] In step (2), the pad diameter is 22μm, the thickness is 2μm, the pitch is 50μm, the bump height is 23nm, and the dielectric layer length between adjacent bump pads is 127% of the bump pad diameter.

[0078] In step (3), the chip size is 50mm*50mm and the thickness is 1.6×10. 3 μm, a chip after 3-layer bonding.

[0079] Comparative Example 1

[0080] This comparative example uses a D2W hybrid bonding method similar to that in Example 1, except that the pads on the chip in steps (2) and (3) are replaced with dish-shaped recessed pads of the same size and shape as the pads on the wafer, such as... Figure 6 As shown.

[0081] Comparative Example 2

[0082] The D2W hybrid bonding method in this comparative example is the same as that in Example 1, except that the diameter of the pad is 6μm in step (2).

[0083] Comparative Example 3

[0084] The D2W hybrid bonding method in this comparative example is the same as that in Example 1, except that the pitch is 55 μm in step (1).

[0085] Comparative Example 4

[0086] The D2W hybrid bonding method in this comparative example is the same as that in Example 1, except that the indentation depth is 30nm in step (1).

[0087] Comparative Example 5

[0088] The D2W hybrid bonding method in this comparative example is the same as that in Example 1, except that the protrusion height is 30nm in step (2).

[0089] Comparative Example 6

[0090] The D2W hybrid bonding method in this comparative example is the same as that in Example 1, except that the pitch is 60 μm in step (2).

[0091] Comparative Example 7

[0092] This comparative example uses a D2W hybrid bonding method similar to Example 1, except that the dish-shaped recessed pads in steps (1) and (3) are replaced with planar recessed pads with the same diameter and recess depth as the dish-shaped recessed pads (i.e., the distance from any position on the pad surface to the upper surface of the dielectric layer is the same). Figure 7 As shown.

[0093] Comparative Example 8

[0094] This comparative example of a D2W hybrid bonding method is the same as that in Example 1, except that the diameter of the cylindrical raised pad is equal to the diameter of the dish-shaped recessed pad.

[0095] Experimental Example 1

[0096] The alignment accuracy, alignment deviation, and UPH (uptake per hour) of the D2W hybrid bonding machine were tested for the chips mounted on the substrate wafers in Examples 1-3 and Comparative Examples 1-8, respectively. The results are shown in Table 1.

[0097] Table 1

[0098]

[0099]

[0100] Experimental Example 2

[0101] (1) Interfacial bonding voids were observed using scanning ultrasonic microscopy (CSAM). The interface morphology of the bonded samples in Example 1 and Comparative Example 1 was tested respectively. Example 1 is as follows: Figure 2As shown, Comparative Example 1 is as follows Figure 3 As shown. By Figure 2 and 3 It can be seen that the embodiment has fewer voids and better quality, while the comparative example has more voids and defects.

[0102] (2) The interface morphology of the bonded samples of Example 1 and Comparative Example 8 was tested by SEM, respectively. Example 1 is as follows: Figure 4 As shown, Comparative Example 8 Figure 5 As shown. By Figure 4 and 5 As can be seen, the pad protrusions and depressions used in Comparative Example 8 only partially make complete contact. This will cause interfacial stress during annealing, destroying the covalent bonds of the dielectric layer around the pads and leading to interfacial failure. The method of this invention, however, provides redundancy for high-temperature annealing, avoids excessive interfacial stress, and improves interfacial stability and reliability.

[0103] The same experiments were also conducted on other embodiments of the present invention, and the results were basically the same. Due to space limitations, they will not be listed one by one.

[0104] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for D2W hybrid bonding, characterized in that, Includes the following steps: (1) Provide a chip with multiple cylindrical bump pads; (2) Provide a wafer with multiple dish-shaped recessed pads; (3) Bond the chip and the wafer to obtain a D2W hybrid bonding sample; The cylindrical raised pads and the dish-shaped recessed pads are arranged in a one-to-one correspondence, and the diameter of the cylindrical raised pads is smaller than the diameter of the dish-shaped recessed pads.

2. The method for D2W hybrid bonding according to claim 1, characterized in that, The cylindrical raised pads have a diameter of 0.1–24 μm, a pitch of 0.4–50 μm, and a thickness of 0.05–5 μm.

3. The method for D2W hybrid bonding according to claim 1, characterized in that, The height of the cylindrical protruding pad protruding from the chip dielectric layer is less than the depth of the dish-shaped recessed pad.

4. The method for D2W hybrid bonding according to claim 3, characterized in that, The protrusion height of the cylindrical raised pad protruding from the chip dielectric layer is 0.01-24.5nm, and the recess depth of the dish-shaped recessed pad is 0.02-25nm.

5. The method for D2W hybrid bonding according to claim 1, characterized in that, The diameter of the dish-shaped recessed pad is (1.05~10) × the diameter of the cylindrical raised pad.

6. A method for D2W hybrid bonding according to any one of claims 1-5, characterized in that, The diameter of the dish-shaped recessed pad is 0.2-25 μm, the pitch is 0.4-50 μm, and the thickness is 0.05-5 μm.

7. A method for D2W hybrid bonding according to any one of claims 1-5, characterized in that, The dielectric layer length between adjacent raised pads is 30% to 200% of the diameter of the raised pads. The dielectric layer spacing between adjacent recessed pads is 30% to 200% of the diameter of the recessed pads.

8. The method for D2W hybrid bonding according to claim 1, characterized in that, The chip has a length of 1–50 mm, a width of 1–50 mm, and a thickness of 10–1.6 × 10⁻⁶ mm. 3 μm.

9. A method for D2W hybrid bonding according to claim 7, characterized in that, The chip is a single-layer or multi-layer bonded chip.

10. A D2W hybrid bonded sample obtained by any one of claims 1-9.

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