Bonded semiconductor structure and method of manufacturing the same

Abstract

A bonded semiconductor structure and a method of manufacturing the same are disclosed. The bonded semiconductor structure includes a first wafer including a first through-silicon via, and a second wafer bonded on the first wafer. A second through-silicon via passes through the second wafer and includes a lower portion in direct contact and electrically connected with the first through-silicon via, and an upper portion disposed on the lower portion. A sidewall of the lower portion, a bottom surface of the upper portion, and a sidewall of the upper portion form a stepped profile.

Description

Technical Field

[0001] This invention relates to a bonding semiconductor structure and a method for manufacturing the same, and particularly to a bonding semiconductor structure including through-silicon vias and a method for manufacturing the same. Background Technology

[0002] 3D integrated circuit (3D IC) technology transforms traditional two-dimensional chips into three-dimensional stacked chips. Because 3D ICs can effectively utilize space, reduce package size, shorten circuit transmission distance, and provide extremely low resistance connections, they have gradually become the mainstream technology for components such as power converters, low-noise amplifiers, radio frequency (RF) or millimeter-wave (MMW) circuits.

[0003] To achieve high-density stacking and heterogeneous integration of multifunctional devices in three-dimensional integrated circuits, wafer-level bonding technology plays a crucial role. Achieving high bonding strength, enabling the stacking of multiple wafer layers, and ensuring precise alignment so that through-silicon / through-substrate vias (TSVs) can connect the upper and lower wafer layers for circuit transmission are active research goals in this field. Summary of the Invention

[0004] One embodiment of the present invention provides a bonding semiconductor structure including a first wafer with a first through-silicon via (TSV) and a second wafer bonded to the first wafer. A second TSV passes through the second wafer and includes a lower portion that is in direct contact with and electrically connected to the first TSV, and an upper portion disposed on the lower portion. A sidewall of the lower portion, a bottom surface of the upper portion, and a sidewall of the upper portion form a stepped profile.

[0005] Another embodiment of the present invention provides a method for manufacturing a semiconductor structure, the steps of which include first providing a first wafer, the first wafer including a first through-silicon via (TSV). Next, a second wafer is bonded to the first wafer, and then a first etching process is performed to form an opening in the second wafer, the opening stopping at an etch stop layer on the second wafer. Subsequently, a second etching process is performed to extend the opening through the etch stop layer and the second wafer, exposing a conductive structure of the second wafer and a top surface of the first TSV, and then forming a second TSV within the opening. Attached Figure Description

[0006] Figures 1 to 8 This is a schematic diagram of the manufacturing steps of a bonding semiconductor structure according to an embodiment of the present invention;

[0007] Figure 9 This is a schematic cross-sectional view of a junction semiconductor structure according to an embodiment of the present invention;

[0008] Figure 10 This is a cross-sectional schematic diagram of a bonding semiconductor structure according to an embodiment of the present invention.

[0009] Symbol Explanation

[0010] 10: Carrier

[0011] 100: First Wafer

[0012] 102: Base

[0013] 104: Interconnection Layer

[0014] 106: Semiconductor components

[0015] 108: Etching Stop Layer

[0016] 110: Conductive structure

[0017] 112: Subbase

[0018] 114: Lining

[0019] 116: Barrier Layer

[0020] 118: Conductive materials

[0021] 120: First through-silicon via

[0022] 132: Bonding layer

[0023] 200: Second wafer

[0024] 202: Base

[0025] 204: Interconnection Layer

[0026] 206: Semiconductor components

[0027] 208: Etching Stop Layer

[0028] 210: Conductive structure

[0029] 212: Subbase

[0030] 214: Lining

[0031] 216: Barrier Layer

[0032] 218: Conductive materials

[0033] 220: Second through-silicon via

[0034] 300: Third wafer

[0035] 302: Base

[0036] 304: Interconnect layer

[0037] 306: Semiconductor components

[0038] 308: Etching Stop Layer

[0039] 310: Conductive structure

[0040] 314: Lining

[0041] 316: Barrier Layer

[0042] 318: Conductive materials

[0043] 320: Third through-silicon via

[0044] 404: Interconnection layer

[0045] 406: Interconnection Structure

[0046] 410: Joint pad

[0047] 102a: Front

[0048] 102b: Back

[0049] 202a: Front

[0050] 202b: Back

[0051] 220a:lower part

[0052] 220b: Upper part

[0053] 232a: Bonding layer

[0054] 232b: Bonding layer

[0055] 302a: Front

[0056] 302b: Back

[0057] 332a: Bonding layer

[0058] OP: Open

[0059] S1: Sidewall

[0060] S2: Sidewall

[0061] S3: Bottom

[0062] STP: Stepped profile

[0063] V1: Open

[0064] V1'': Opening

[0065] V2: Opening

[0066] V2': Opening

[0067] W1: Width

[0068] W2: Width

[0069] W0: Width Detailed Implementation

[0070] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below, along with accompanying drawings, to explain in detail the composition and desired effects of the invention. It should be understood that features in several different embodiments can be substituted, rearranged, or mixed to complete other embodiments without departing from the spirit of the invention.

[0071] To facilitate reader comprehension and maintain the simplicity of the illustrations, many of the diagrams in this invention depict only a portion of the semiconductor structure, and specific components are not drawn to scale. Furthermore, the number and dimensions of each component in the diagrams are for illustrative purposes only and are not intended to limit the scope of this invention. The descriptions of the vertical relationships between relative components in the diagrams should be understood by those skilled in the art to refer to their relative positions; therefore, the same structure can be presented by flipping the diagrams, and all of this should fall within the scope of this specification.

[0072] Figures 1 to 8 This is a schematic diagram illustrating the manufacturing steps of a bonding semiconductor structure according to an embodiment of the present invention. Please refer to... Figure 1 First, a first wafer 100 is provided. The first wafer 100 includes a substrate 102, which includes a front side 102a and a back side 102b. Semiconductor elements 106 and interconnect layers 104 are disposed on the front side 102a of the substrate 102. The substrate 102 is made of a semiconductor material, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, a group III-V semiconductor substrate, or other suitable semiconductor materials. In some embodiments, the material of the substrate 102 may be a non-conductive material, such as glass or plastic, or a sapphire wafer. The semiconductor elements 106 are, for example, various active (powerful) or passive (passive) elements such as transistors, diodes, capacitors, inductors, and resistors, but are not limited thereto. The interconnect layer 104 has a multilayer structure, including multiple dielectric material layers and conductive layers, conductive structures, and conductive plugs disposed in these dielectric material layers. In some embodiments, the interconnect layer 104 may also include circuit elements, such as capacitors, inductors, resistors, embedded memory, etc., but are not limited thereto. For simplicity, only the portion for use with the first through-silicon via 120 (reference) is shown in the figure. Figure 4The conductive structure 110 is electrically connected. The dielectric material suitable for the interconnect layer 104 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, nitrogen-doped silicon carbide, low-dielectric-constant dielectric materials such as fluorosilicone glass, silicon carbide oxide, spin-coated silicon glass, porous low-dielectric-constant dielectric materials, and organic polymer dielectric materials, but is not limited thereto. The conductive material suitable for the conductive structure 110 may include metal materials or metal compounds such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride, but is not limited thereto. The conductive structure 110 may be disposed in any dielectric material layer of the interconnect layer 104. According to one embodiment of the present invention, the conductive structure 110 and the first metal layer of the interconnect layer 104 are co-layered. In other embodiments, the conductive structure 110 and the second metal layer, third metal layer, or any metal layer of the interconnect layer 104 are co-layered.

[0073] According to one embodiment of the present invention, the front side 102a of the substrate 102 is further provided with an etch stop layer 108, which at least partially overlaps with the conductive structure 110 in the vertical direction and is separated from each other by dielectric material regions of the interconnect layer 104. The material of the etch stop layer 108 may include oxides, such as silicon oxide, but is not limited thereto. In this document, the vertical direction is defined as the stacking direction of the wafer.

[0074] Next, the first wafer 100 is bonded to the carrier 10 with the front side 102a of the substrate 102 facing the carrier 10, to obtain the following... Figure 1 The back side 102b of the substrate 102 shown faces upwards, and the interconnect layer 104 is a structure between the substrate 102 and the carrier 10. The carrier 10 can be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, or a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. According to an embodiment of the present invention, the first wafer 100 is bonded to the carrier 10 by forming oxide bonds with the carrier 10 through the interconnect layer 104 or a bonding layer (not shown) on the interconnect layer 104.

[0075] Please refer to Figure 2 Next, a grinding process is performed on the back surface 102b of the substrate 102 to thin the substrate 102. Then, a pad layer 112 is formed to cover the back surface 102b of the substrate 102. The substrate 102 is then etched to form an opening V1 that passes through the pad layer 112 and the substrate 102 and stops at the etch stop layer 108. Subsequently, a liner layer 114 is formed to conformally cover the pad layer 112 and the sidewalls and bottom surface of the opening V1. According to one embodiment of the present invention, the material of the pad layer 112 includes silicon nitride, and the material of the liner layer 114 includes silicon oxide, but is not limited thereto.

[0076] Please refer to Figure 3Then, another etching process is performed, etching through the liner 114, the etch stop layer 108, and part of the interconnect layer 104 on the bottom surface of the opening V1 until the conductive structure 110 is exposed, thus obtaining the opening V1'. The liner 114 still covers the sidewall of the portion of the opening V1' that penetrates the substrate 102 to ensure electrical isolation between the first through-silicon via 120 subsequently formed in the opening V1' and the substrate 102. In some embodiments, the liner 114 on the back surface 102b of the substrate 102 is also removed after the etching process, exposing the pad layer 112.

[0077] Please refer to Figure 4 Next, a barrier layer 116 is formed to conformally cover the sidewalls and bottom surface of the pad layer 112 and the opening V1'. Then, a conductive material 118 is formed on the barrier layer 116 and fills the opening V1'. A chemical mechanical polishing process is then performed to remove the conductive material 118 and the barrier layer 116 outside the opening V1', thereby forming a first through-silicon via 120 within the opening V1'. According to one embodiment of the present invention, the pad layer 112 is also removed after the chemical mechanical polishing process, exposing the back surface 102b of the substrate 102. The barrier layer 116 may have a single-layer or multi-layer structure, and the material may include, but is not limited to, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. The conductive material 118 may include, but is not limited to, metallic materials or metal compounds such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride. According to one embodiment of the present invention, the conductive material 118 includes copper. According to one embodiment of the present invention, sputter etching can be performed to thin or remove the barrier layer 116 on the bottom surface of the opening V1', and then a conductive material 118 can be formed to reduce the contact resistance between the first through-silicon via 120 and the conductive structure 110. Subsequently, a bonding layer 132 is formed to completely cover the back surface 102b of the substrate 102 and the first through-silicon via 120. According to one embodiment of the present invention, the material of the bonding layer 132 includes silicon carbonitride.

[0078] Please refer to Figure 5 Next, a second wafer 200 is provided, which includes a substrate 202. The substrate 202 includes a front side 102a and a back side 102b. Semiconductor elements 206 and an interconnect layer 204 are disposed on the front side 102a, and a bonding layer 232a is disposed on the interconnect layer 204. The interconnect layer 204 has a multilayer structure, including multiple dielectric material layers and conductive layers, conductive structures, and conductive plugs disposed in the dielectric material layers. In some embodiments, the interconnect layer 204 may also include circuit elements, such as capacitors, inductors, resistors, embedded memory, etc., but is not limited thereto. For the sake of simplicity, only the part for connecting to the second through-silicon via 220 (reference) is shown in the figure. Figure 8A conductive structure 210 for electrical connection is provided. The conductive structure 210 may be disposed in any dielectric material layer of the interconnect layer 204. According to one embodiment of the present invention, the conductive structure 210 and the first metal layer of the interconnect layer 204 are co-layered. In other embodiments, the conductive structure 210 and the second metal layer, third metal layer, or any metal layer of the interconnect layer 204 are co-layered. According to one embodiment of the present invention, the front side 202a of the substrate 202 is further provided with an etch stop layer 208, which at least partially overlaps with the conductive structure 210 in the vertical direction and is separated from each other by the dielectric material regions of the interconnect layer 204. The constituent materials of the components of the second wafer 200 described above can be referred to the constituent materials of the components of the first wafer 100 described above, and will not be repeated here. It is worth noting that the portion where the conductive structure 210 overlaps with the etch stop layer 208 includes an opening OP, which may be a closed opening completely surrounded by the conductive structure 210, or an open opening partially surrounded by the conductive structure 210.

[0079] Please continue to refer to this. Figure 5 Next, the second wafer 200 is positioned with the front side 202a of the substrate 202 facing the back side 102b of the substrate 102 of the first wafer 100, and is bonded to the first wafer 100 by fusion bonding between the bonding layer 232a and the bonding layer 132. The opening OP of the conductive structure 210 is positioned directly above the first through-silicon via 120, and the width of the opening OP is smaller than the width of the top of the first through-silicon via 120.

[0080] Please refer to Figure 6 Next, a grinding process is performed on the back side 202b of the substrate 202 to thin the substrate 202. Then, a pad 212 is formed to cover the back side 202b of the substrate 202. The substrate 202 is then etched to form an opening V2 that passes through the pad 212 and the substrate 202 and stops at the etch stop layer 208. Subsequently, a liner 214 is formed to conformally cover the sidewalls and bottom surface of the pad 212 and the opening V2. The materials for the pad 212 and the liner 214 can refer to the materials applicable to the pad 112 and the liner 114 described above, and will not be repeated here.

[0081] Please refer to Figure 7Next, another etching process is performed, etching through the liner 214, the etch stop layer 208, and part of the interconnect layer 204 at the bottom of opening V2, exposing the conductive structure 210 and opening OP. Etching continues downwards through opening OP, passing through interconnect layer 204, bonding layer 232a, and bonding layer 132, until the top surface of the first through-silicon via 120 is exposed, obtaining opening V2'. Opening V2' extends through the etch stop layer 208 and the second wafer 200, exposing part of the top surface and sidewalls of the conductive structure 210 and the top surface of the first through-silicon via 120 of the first wafer 100. The liner 214 still covers the sidewalls of the portion of opening V2' that penetrates the substrate 202, ensuring electrical isolation between the second through-silicon via 220 subsequently formed within opening V2' and the substrate 202. In some embodiments, the liner 214 on the back surface 202b of the substrate 202 is also removed after the etching process, exposing the pad layer 212.

[0082] Please refer to Figure 8 Next, a barrier layer 216 is formed to conformally cover the sidewalls and bottom surface of the pad layer 212 and the opening V2'. A conductive material 218 is then formed on the barrier layer 216 and fills the opening V2'. A chemical mechanical polishing (CMP) process is then performed to remove the conductive material 218 and the barrier layer 216 outside the opening V2', thereby forming a second through-silicon via 220 within the opening V2'. According to one embodiment of the invention, the pad layer 212 is also removed after the CMP process, exposing the back surface 202b of the substrate 202. The materials for the barrier layer 216 and the conductive material 218 can refer to the materials applicable to the barrier layer 116 and the conductive material 118 described above, and will not be repeated here. According to one embodiment of the invention, sputter etching can be performed to thin or remove the barrier layer 116 on the bottom surface of the opening V2' before forming the conductive material 118 to reduce the contact resistance between the second through-silicon via 220 and the first through-silicon via 120.

[0083] With this step in the fabrication process, the bonded semiconductor structure of this embodiment is obtained. For example... Figure 8As shown, the semiconductor bonding structure includes a first wafer 100 and a second wafer 200, wherein the second wafer 200 is bonded to the first wafer 100 with its front side facing the back side of the first wafer 100. The first wafer 100 includes a first through-silicon via (TSV) 120. A second TSV 220 penetrates the second wafer 200 perpendicularly and is positioned directly above the first TSV 120. The second TSV 220 has an integrally formed structure including a lower portion 220a that is in direct contact with and electrically connected to the first TSV 120, and an upper portion 220b located directly above the lower portion 220a. The width W1 of the lower portion 220a is smaller than the width W2 of the upper portion 220b, and the sidewall S1 of the lower portion 220a, the bottom surface S3 of the upper portion 220b, and the sidewall S2 of the upper portion 220b form a stepped profile STP. According to one embodiment of the present invention, the width W1 of the lower portion 220a is also smaller than the width W0 of the first through-silicon via 120. The bottom surface of the first through-silicon via 120 is in direct contact and electrically connected to the conductive structure 110 of the interconnect layer 104 of the first wafer 100, and then electrically connected to the semiconductor element 106 and circuit element (not shown) of the first wafer 100 through other conductive structures of the interconnect layer 104. The second through-silicon via 220 is in direct contact and electrically connected to the conductive structure 210 of the interconnect layer 204 of the second wafer 200 through the sidewall S1 of the lower portion 220a and the bottom surface S3 of the upper portion 220b, and then electrically connected to the semiconductor element 206 and circuit element (not shown) of the second wafer 200 through other conductive structures of the interconnect layer 204. In other words, the second through-silicon via 220 achieves circuit transmission with the second wafer 200 by straddling the conductive structure of the second wafer 200 through the stepped portion on its side. Compared to existing technologies that require additional interconnect layers to provide electrical connections from the top or bottom surface of through-silicon vias, the design of this invention reduces fabrication steps and lowers the height of the stacked structure.

[0084] Please refer to Figure 9 This is a schematic cross-sectional view of a bonded semiconductor structure according to an embodiment of the present invention. (Repeatable) Figures 4 to 8The process continues by bonding a third wafer 300 onto the second wafer 200. The third wafer 300 may have a similar structure to the second wafer 200. For example, the third wafer 300 includes a substrate 302, which includes a front side 302a and a back side 302b. A semiconductor element 306 and an interconnect layer 304 are disposed on the front side 302a, and a bonding layer 332a is disposed on the interconnect layer 304. The interconnect layer 304 has a multilayer structure, including multiple dielectric material layers and conductive layers, conductive structures, and conductive plugs disposed within these dielectric material layers. In some embodiments, other circuit elements, such as capacitors, inductors, resistors, embedded memory, etc., may also be disposed within the interconnect layer 304, but are not limited thereto. For simplicity, only the conductive structure 310 electrically connected to the third through-silicon via 320 is shown in the figure. The conductive structure 310 may be disposed in any dielectric material layer of the interconnect layer 304. According to an embodiment of the present invention, the conductive structure 310 and the first metal layer of the interconnect layer 304 are co-layer structures. In other embodiments, the conductive structure 310 is co-located with the second metal layer, the third metal layer, or any metal layer of the interconnect layer 304. The front side 202a of the substrate 302 also has an etch stop layer 308, which overlaps with the conductive structure 310 in the vertical direction and is separated from it by dielectric material regions of the interconnect layer 304.

[0085] In detail, after forming the second through-silicon via 220, a bonding layer 232b is then formed to fully cover the back side 202b of the substrate 202 of the second wafer 200 and the second through-silicon via 220. Then, the third wafer 300 is bonded to the second wafer 200 with the front side 302a of the substrate 302 facing the second wafer 200 through fusion bonding between the bonding layer 232b and the bonding layer 332a. Then, a third through-silicon via 320 is formed through the third wafer 300 and positioned directly above the second through-silicon via 220. The third through-silicon via 320 includes a barrier layer 316 and a conductive material 318, and has an integrally formed structure including a narrower lower portion and a wider upper portion, wherein a stepped profile exists between the upper and lower portions. A portion of this stepped profile directly contacts and is electrically connected to the conductive structure 310 of the interconnect layer 304, enabling circuit transmission between the third through-silicon via 320 and the third wafer 300. The sidewalls of the third through-silicon via 320 are separated from and electrically isolated from the substrate 302 by a liner 314. The constituent materials of the components of the third wafer 300 and the third through-silicon via 320 can be referred to the constituent materials of the components of the first wafer 100 described above, and will not be repeated here. In some embodiments, this process can be repeated. Figures 4 to 8 The next step is to continue bonding more wafers on the third wafer 300 (not shown).

[0086] Please refer to Figure 10This is a cross-sectional schematic diagram of a bonding semiconductor structure according to an embodiment of the present invention. After the wafer stacking is completed, an interconnect layer 404 and a bonding pad 410 can be formed on the topmost wafer (in this embodiment, the third wafer 300 is used as an example) as external contacts of the bonding semiconductor structure. The interconnect layer 404 may have a single layer or multiple layers of dielectric material and interconnect structures 406 disposed in the dielectric material, such as conductive layers, conductive structures, and / or conductive plugs. The dielectric material of the interconnect layer 404 may include silicon oxide or silicon nitride, but is not limited thereto. The materials of the interconnect structure 406 and the bonding pad 410 may include metal materials or metal compounds such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride, but are not limited thereto.

[0087] In summary, the semiconductor bonding structure and its manufacturing method disclosed in this invention bond the wafer face to back, and combine it with a through-silicon via (TSV-last) fabrication process and a design that enables circuit transmission between the TSV and the wafer from the side of the TSV. This allows for the stacking of more wafer layers and the fabrication of three-dimensional integrated circuit chips with higher stacking density.

[0088] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A junction semiconductor structure, comprising: The first wafer, including the first through-silicon via; The second wafer is bonded to the first wafer; as well as The second through-silicon via (TSV) passes through the second wafer and includes: The lower part is in direct contact with and electrically connected to the first through-silicon via; as well as The upper part is disposed on the lower part, wherein the sidewall of the lower part, the bottom surface of the upper part, and the sidewall of the upper part form a stepped profile.

2. The bonding semiconductor structure of claim 1, wherein the width of the lower portion is smaller than the width of the upper portion.

3. The bonding semiconductor structure of claim 1, wherein the width of the lower portion is smaller than the width of the first through-silicon via.

4. The bonding semiconductor structure of claim 1 further includes a barrier layer disposed along the lower sidewall, the upper bottom surface, and the upper sidewall.

5. The bonding semiconductor structure as claimed in claim 1, further comprising a conductive structure disposed in the second wafer, wherein the lower sidewall and the upper bottom surface of the second through-silicon via are in direct contact with and electrically connected to the conductive structure.

6. The bonding semiconductor structure of claim 1 further includes a bonding layer located between the first wafer and the second wafer, and directly contacting the sidewall of the lower portion of the second through-silicon via and the top surface of the first through-silicon via.

7. The bonding semiconductor structure of claim 1, further comprising an etch stop layer located in the second wafer and in direct contact with the upper sidewall of the second through-silicon via.

8. The bonding semiconductor structure of claim 1, further comprising a liner disposed along the sidewall of the upper portion of the second through-silicon via.

9. The bonding semiconductor structure of claim 1, further comprising a bonding pad disposed on the second wafer and overlapping the upper portion of the second through-silicon via.

10. The junction semiconductor structure of claim 1, further comprising: The third wafer is bonded to the second wafer and is disposed opposite to the first wafer; The third through-silicon via passes through the third wafer and is in direct contact with and electrically connected to the second through-silicon via.

11. A method for manufacturing a semiconductor structure, comprising: A first wafer is provided, the first wafer including a first through-silicon via; The second wafer is bonded to the first wafer; A first etching process is performed to form an opening in the second wafer, which stops on the etch stop layer of the second wafer; A second etching process is performed to extend the opening through the etch stop layer and the second wafer, exposing the top surface and sidewalls of the conductive structure of the second wafer and the top surface of the first through-silicon via of the first wafer. as well as A second through-silicon via is formed within this opening.

12. The method for manufacturing a semiconductor structure as claimed in claim 11, wherein the second through-silicon via comprises: The lower part is in direct contact with and electrically connected to the first through-silicon via; as well as The upper part is disposed on the lower part, wherein the sidewall of the lower part, the bottom surface of the upper part, and the sidewall of the upper part form a stepped profile.

13. The method of manufacturing a bonded semiconductor structure as claimed in claim 12, wherein the width of the lower portion is smaller than the width of the upper portion.

14. The method of manufacturing a bonded semiconductor structure as claimed in claim 12, wherein the width of the lower portion is smaller than the width of the first through-silicon via.

15. The method of manufacturing a bonded semiconductor structure as claimed in claim 11, wherein prior to the second etching process, a liner is formed on the sidewall of the opening.

16. The method of manufacturing a semiconductor structure as claimed in claim 11, wherein the step of forming the second through-silicon via includes: A barrier layer is formed on the sidewall of the opening, and the barrier layer is in direct contact with the conductive structure. as well as A conductive material is formed to fill the opening.

17. The method of manufacturing a semiconductor structure as claimed in claim 11, wherein the second through-silicon via is electrically connected to the conductive structure and the first through-silicon via.

18. The method of manufacturing a semiconductor structure as claimed in claim 11, wherein the second wafer is bonded to the first wafer by fusion bonding.

19. The method of manufacturing a semiconductor structure as claimed in claim 11, further comprising forming a bonding pad on the second wafer, the bonding pad overlapping the second through-silicon via.

20. The method for manufacturing a semiconductor structure as claimed in claim 11, further comprising: A bonding layer is formed on the second wafer, and the bonding layer covers the second through-silicon via. as well as The third wafer is bonded to the second wafer through the bonding layer.

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