Method for manufacturing a semiconductor device

Abstract

A semiconductor device manufacturing method capable of manufacturing a semiconductor device well. A semiconductor device (MD) manufacturing method includes: a step of layering a first layer (162) containing germanium and oxygen with silicon as a main component on a first wafer (SS); a step of forming a first element (MCA) and a first bonding electrode (P I1 ) on the first wafer; a step of forming a second element (Tr) and a second bonding electrode (P I2 ) on a second wafer (SB); a step of bonding the first wafer and the second wafer via the first bonding electrode and the second bonding electrode; and a step of causing the first layer to crack by irradiating laser through the first substrate (150) to the first layer.

Description

Technical Field

[0001] This embodiment relates to a method for manufacturing a semiconductor device. Background Technology

[0002] A method for manufacturing a semiconductor device is known, which includes the steps of bonding a wafer having a substrate and a predetermined layer to other wafers and irradiating the predetermined layer with a laser to peel off the substrate. Summary of the Invention

[0003] Provides a method for manufacturing semiconductor devices that can effectively manufacture semiconductor devices.

[0004] One embodiment of a semiconductor device manufacturing method includes: a step of stacking a first layer, which is mainly composed of silicon and contains germanium and oxygen, on a first wafer having a first substrate; a step of forming a first element and a first bonding electrode on the first wafer; a step of forming a second element and a second bonding electrode on a second wafer; a step of bonding the first wafer and the second wafer via the first bonding electrode and the second bonding electrode; and a step of cracking the first layer by irradiating the first layer through the first substrate with a laser. Attached Figure Description

[0005] Figure 1 This is a schematic circuit diagram showing the configuration of a portion of the semiconductor device according to the first embodiment.

[0006] Figure 2 This is a schematic exploded perspective view showing an example of the configuration of a semiconductor device according to the first embodiment.

[0007] Figure 3 This illustrates the chip C included in the semiconductor device according to the first embodiment. M A schematic bottom view of the constituent examples.

[0008] Figure 4 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to the first embodiment.

[0009] Figure 5 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to the first embodiment.

[0010] Figure 6 This shows chip C M A schematic bottom view of a portion of the composition.

[0011] Figure 7 This shows chip C M A schematic cross-sectional view of a portion of the composition.

[0012] Figure 8This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0013] Figure 9 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0014] Figure 10 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0015] Figure 11 This is a schematic bottom view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0016] Figure 12 This is a schematic bottom view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0017] Figure 13 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0018] Figure 14 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0019] Figure 15 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0020] Figure 16 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0021] Figure 17 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0022] Figure 18 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0023] Figure 19 This is a schematic top view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0024] Figure 20 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0025] Figure 21 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0026] Figure 22This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0027] Figure 23 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0028] Figure 24 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0029] Figure 25 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0030] Figure 26 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0031] Figure 27 This is a schematic top view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0032] Figure 28 This is a schematic top view used to illustrate the manufacturing method of the semiconductor device according to the first embodiment.

[0033] Figure 29 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the second embodiment.

[0034] Figure 30 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the second embodiment.

[0035] Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the second embodiment.

[0036] Figure 32 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the second embodiment.

[0037] Figure 33 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the second embodiment.

[0038] Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the third embodiment.

[0039] Figure 35 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the fourth embodiment.

[0040] Figure 36This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the fourth embodiment.

[0041] Figure 37 This is a schematic circuit diagram showing the configuration of a portion of the semiconductor device according to the fifth embodiment.

[0042] Figure 38 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to the fifth embodiment.

[0043] Figure 39 This is a schematic perspective view showing the configuration of a portion of the semiconductor device according to the sixth embodiment.

[0044] Figure 40 This is a schematic perspective view showing the configuration of a portion of the semiconductor device according to the sixth embodiment.

[0045] Explanation of reference numerals in the attached figures

[0046] 110…Conductive layer (gate electrode), 120…Semiconductor pillar, 130…Gate insulating film, 150…First substrate, 150B…Outer periphery, 151, 152…Insulating layer (protective layer), 153…Reflective layer, 154…Barrier metal layer, 161A…Second layer, 161B…Third layer, 162…First layer, 200…Semiconductor substrate (second substrate), 200…Second substrate, MCA…Memory cell array (first element), MD, MD2…Memory die (semiconductor device), Tr…Transistor (second element), P I1 …first bonding electrode, P I2 …Second bonding electrode, SS, SS2…First wafer, SB…Second wafer Detailed Implementation

[0047] Next, with reference to the accompanying drawings, a detailed description of the manufacturing method of the semiconductor device according to the embodiments will be provided. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic, and for ease of explanation, some components may be omitted. Also, sometimes the same reference numerals are used to denote common parts in multiple embodiments, and descriptions are omitted.

[0048] Furthermore, in this specification, the term "semiconductor device" sometimes means a semiconductor memory device, and sometimes it means a semiconductor device other than that. Additionally, in this specification, the term "semiconductor memory device" sometimes means a memory die, and sometimes it means a memory chip, memory card, SSD (Solid State Drive), or other storage system including a controller die. Moreover, it sometimes refers to the configuration of a smartphone, tablet, personal computer, or other host device.

[0049] Furthermore, in this specification, when the first component and the second component are described as "electrically connected," it can mean that the first component and the second component are directly connected, or that the first component is connected to the second component via wiring, a semiconductor component, or a transistor. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0050] Additionally, in this specification, when it is stated that the first component is "electrically connected" between the second and third components, it sometimes means that the first, second, and third components are connected in series and the second component is connected to the third component via the first component.

[0051] Furthermore, in this specification, when it is stated that a circuit or the like "conducts" two wires or the like, it sometimes means, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wires, and that the transistor or the like is in a conducting (ON) state.

[0052] In addition, in this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0053] In addition, in this specification, the direction intersecting the predetermined surface is sometimes referred to as the first direction. Furthermore, the direction along the predetermined surface is sometimes referred to as the second direction, and the direction along the predetermined surface and intersecting the second direction is sometimes referred to as the third direction. These first, second, and third directions may or may not correspond to any of the Z, X, and Y directions.

[0054] Furthermore, in this specification, the terms "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when a configuration is described as "lower surface" or "lower end," it refers to the surface or end of that configuration on the substrate side; when described as "upper surface" or "upper end," it refers to the surface or end of that configuration on the side opposite to the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0055] In addition, in this specification, when the terms "width", "length" or "thickness" are used to describe the structure, components, etc., in a predetermined direction, they sometimes mean the width, length or thickness in a cross-section or the like observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), etc.

[0056] In addition, in this specification, when referred to as "wiring", it may sometimes include wiring, contact electrodes, connecting parts for connecting wiring to contact electrodes, bonding electrodes, etc.

[0057] [First Implementation]

[0058] [Circuit configuration for storing a bare die MD]

[0059] Figure 1 This is a schematic circuit diagram illustrating the configuration of a portion of the semiconductor device according to the first embodiment. In the first embodiment, a memory die (MD) is illustrated as an example of a semiconductor device. Figure 1 As shown, the memory die MD includes a memory cell array MCA and peripheral circuitry PC. The memory cell array MCA is an example of the first element. Additionally, the peripheral circuitry PC includes multiple transistors Tr (see reference). Figure 4 These multiple transistors Tr are an example of the second element.

[0060] [Circuit configuration of a memory cell array (MCA)]

[0061] like Figure 1 As shown, the memory cell array MCA has multiple memory blocks BLK. Each of these memory blocks BLK has multiple string cells SU. Each of these string cells SU has multiple memory strings MS. One end of each of these memory strings MS is connected to the peripheral circuit PC via a bit line BL. In addition, the other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0062] The memory string (MS) includes a drain-side select transistor (STD), multiple memory cells (MCs) (memory transistors), and a source-side select transistor (STS). The STD, MCs, and STS are connected in series between the bit line BL and the source line SL. Hereinafter, the STD and STS are sometimes simply referred to as select transistors (STD, STS).

[0063] The memory cell MC is a field-effect transistor. The memory cell MC has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as the channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. The memory cell MC stores one bit or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to a memory string MS. These word lines WL are each connected to all memory strings MS in a memory block BLK.

[0064] Select transistors (STD, STS) are field-effect transistors. Each select transistor (STD, STS) has a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as the channel region. The gate insulating film may also include a charge storage film. The gate electrode of the drain-side select transistor (STD) is connected to a drain-side select gate line (SGD), and the gate electrode of the source-side select transistor (STS) is connected to a source-side select gate line (SGS). One drain-side select gate line (SGD) is connected to all memory strings (MS) in a single string cell (SU). One source-side select gate line (SGS) is connected to all memory strings (MS) in a single memory block (BLK).

[0065] [Construction of raw disk MD]

[0066] Figure 2 This is a schematic exploded perspective view showing an example of the configuration of the semiconductor device according to the first embodiment. Figure 2 As shown, the storage die MD has a chip C on the storage cell array MCA side. M And the peripheral circuit PC side chip C P .

[0067] In chip C M The upper surface is provided with multiple external pad electrodes P that can be connected to bonding lines (not shown). X Additionally, in chip C... M Multiple bonding electrodes (first bonding electrode) are provided on the lower surface of P. I1 Additionally, in chip C... P Multiple bonding electrodes P are provided on the upper surface. I2 The following is about chip C. MMultiple bonding electrodes P will be set. I1 The surface is called the surface, and multiple external pad electrodes P will be set there. X The side facing out is called the back side. Additionally, regarding chip C... P Multiple bonding electrodes P will be set. I2 The side facing out is called the surface, and the side opposite the surface is called the back surface. In the illustrated example, chip C P The surface is set on the chip C P On the back, near the top, is chip C. M The back is set on the chip C M The upper part of the surface.

[0068] Chip C M And chip C P With chip C M Surface and chip C P The surfaces are arranged in a relative manner. Multiple bonding electrodes P I1 With multiple bonding electrodes (second bonding electrode) P I2 Each is respectively configured to be able to attach to multiple electrodes P I2 The bonding location. Bonding electrode P I1 With the attached electrode P I2 As for using chip C M With chip C P The bonding electrodes, which are attached and electrically conductive, function.

[0069] In addition, Figure 2 In the example, chip C M The corners a1, a2, a3, a4 and chip C P The corners b1, b2, b3, and b4 correspond to respectively.

[0070] Figure 3 This shows chip C M A schematic bottom view of the constituent examples. Figure 3 In the text, the bonding electrode P is omitted. I1 It is a component of, etc. Figure 4 as well as Figure 5 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to the first embodiment. Figure 6 This shows chip C M A schematic bottom view of a portion of the composition. Figure 6 In the image, the XY cross-section of the word line WL is shown in the left region, and the XY cross-section of the drain-side select gate line SGD is shown in the right region. Furthermore, in... Figure 6 In the area on the right, to indicate the connection between the semiconductor pillar 120 and the bit line BL, contact electrodes ch, Vy, and the bit line BL are also shown. Figure 6 The left side region also contains contact electrodes ch, Vy, and bit line BL. Figure 7 This shows chip C M A schematic cross-sectional view of a portion of the composition. Figure 7 The YZ section is shown, but when observing sections other than the YZ section along the central axis of the semiconductor pillar 120 (e.g., the XZ section), the same pattern is also observed. Figure 7 Same construction.

[0071] [Chip C] M [Construction]

[0072] exist Figure 3 In the example, chip C M It has four storage planes, MP0 to MP3, arranged in the X direction. Sometimes, these four storage planes MP0 to MP3 are simply referred to as storage plane MP. Furthermore, each of these four storage planes MP0 to MP3 has multiple storage blocks BLK arranged in the Y direction. Additionally, in... Figure 3 In this example, each of the four storage planes MP0 to MP3 has a storage hole region R. MH (Storage area) and relative to the storage hole area R MH The joint area R is located on one side in the X direction. HU Additionally, chip C M It has a peripheral region R located at one end of the four storage planes MP0 to MP3 in the Y direction. P .

[0073] Furthermore, in the illustrated example, the joining region R HU Relative to the storage hole region R MH It is positioned on one side in the X direction. However, this configuration is merely an example, and the specific configuration can be adjusted accordingly. For example, the joining region R... HU It can also be relative to the storage hole area R MH It is located on both sides in the X direction. Additionally, the joining area R... HU It can also be set at the center or near the center of the storage plane MP in the X direction.

[0074] For example, such as Figure 4 As shown, chip C M Features: matrix layer L SB Set in the substrate layer L SB The lower storage cell array layer L MCA , Set in the storage cell array layer L MCA The contact electrode layer CH below the contact electrode layer CH, the multiple wiring layers M0 and M1 disposed below the contact electrode layer CH, and the chip bonding electrode layer MB disposed below the wiring layers M0 and M1.

[0075] [Chip C] M The base layer L SB [Construction]

[0076] For example, such as Figure 4 As shown, the matrix layer L SB Features: Located in the storage cell array layer L MCA The conductive layer 100 on the upper surface, the insulating layer 101 disposed on the upper surface of the conductive layer 100, the back wiring layer MA disposed on the upper surface of the insulating layer 101, and the insulating layer 102 disposed on the upper surface of the back wiring layer MA.

[0077] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or may contain metals such as tungsten (W), or may include silicides such as tungsten silicide (WSi).

[0078] Conductive layer 100 serves as source line SL ( Figure 1 It functions as part of the conductive layer 100 and the four storage planes MP0 to MP3. Figure 3 Four are correspondingly provided. Regions VZ that do not contain the conductive layer 100 are provided at the ends of the storage plane MP in the X and Y directions.

[0079] The insulating layer 101 contains, for example, silicon oxide (SiO2).

[0080] The back-side wiring layer MA comprises multiple wiring layers MA. These multiple wiring layers MA may, for example, contain aluminum (Al).

[0081] A portion of the multiple wiring ma is used as the source line SL ( Figure 1 This wiring ma is part of the 4 storage planes MP0 to MP3 ( Figure 3 There are four corresponding wiring ma. Each of these wiring ma is electrically connected to the conductive layer 100.

[0082] Additionally, a portion of the multiple wiring ma serves as the external pad electrode P. X To perform its function. The wiring MA is set in the surrounding area R. P The wiring ma is in the region VZ that does not contain the conductive layer 100 and is connected to the memory cell array layer L. MCA The contact electrode CC is connected. In addition, a portion of the wiring ma is exposed to the outside of the storage die MD through an opening TV provided in the insulating layer 102.

[0083] The insulating layer 102 is, for example, a passivation layer formed of an insulating material such as polyimide.

[0084] [Chip C] MStorage cell array layer L MCA Storage hole area R MH [Construction in]

[0085] For reference Figure 3 As explained, in the memory cell array layer L MCA Multiple storage blocks (BLKs) are configured and arranged in the Y direction. For example... Figure 4 As shown, an interblock insulating layer ST of silicon oxide (SiO2) or the like is provided between two adjacent memory blocks BLK in the Y direction.

[0086] For example, such as Figure 4 As shown, the memory block BLK includes: a plurality of conductive layers 110 arranged (stacked) in the Z direction, and a plurality of semiconductor pillars 120 extending in the Z direction. Additionally, as... Figure 7 As shown, a gate insulating film 130 is disposed between multiple conductive layers 110 and multiple semiconductor pillars 120.

[0087] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may use tungsten (W) or molybdenum (Mo) as the main component, for example. Alternatively, the conductive layer 110 may use polycrystalline silicon containing impurities such as phosphorus (P) or boron (B) as the main component. Furthermore, the conductive layer 110 may use titanium nitride (TiN) as the main component. An interlayer insulating layer 111, such as silicon oxide (SiO2), is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0088] One or more of the uppermost conductive layers 110 among a plurality of conductive layers 110 serve as source-side selected transistors (STS). Figure 1 The gate electrode and source-side select gate line (SGS) function (see reference). Figure 4 These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0089] Additionally, multiple conductive layers 110 located below the topmost conductive layer serve as memory cells MC ( Figure 1 The gate electrode and word line WL function. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0090] Additionally, one or more conductive layers 110 located further below it function as the gate electrode of the drain-side select transistor (STD) and the drain-side select gate line (SGD). For example, as... Figure 6 As shown, the width Y in the Y direction of these multiple conductive layers 110 SGD The width Y in the Y direction of the conductive layer 110, which functions as the word line WL, is smaller than that of the other layer. WLIn addition, a string-unit insulating layer SHE of silicon oxide (SiO2) or the like is provided between two adjacent conductive layers 110 in the Y direction.

[0091] For example, such as Figure 6 As shown, the semiconductor pillars 120 are arranged in a predetermined pattern in the X and Y directions. Each semiconductor pillar 120 serves as a memory string (MS). Figure 1 The semiconductor pillar 120 comprises multiple memory cells (MCs) and the channel region of selection transistors (STDs, STSs) that function. The semiconductor pillar 120 is an oxide with at least one of titanium and indium as its main component. Specifically, the semiconductor pillar 120 may use at least one of titanium oxide (TiO2), indium oxide (In2O3), indium gallium oxide (InGaO3), and indium gallium zinc oxide (InGaZnO, IGZO). The semiconductor pillar 120 has a generally cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in its central portion. The outer peripheral surfaces of the semiconductor pillar 120 are surrounded by multiple conductive layers 110, with the conductive layers 110 facing each other.

[0092] In addition, the upper end of the semiconductor pillar 120 is connected to the aforementioned conductive layer 100 (see reference). Figure 4 ).

[0093] In addition, the lower end of the semiconductor pillar 120 is connected to the bit line BL via the contact electrode ch and the contact electrode Vy.

[0094] For example, such as Figure 6 As shown, the gate insulating film 130 has a generally cylindrical shape that covers the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 includes a ferroelectric film.

[0095] The gate insulating film 130 includes, for example, a generally cylindrical ferroelectric film 132 extending along the Z direction in a range corresponding to the Z direction of the plurality of conductive layers 110 along the outer peripheral surface of the semiconductor pillar 120; a generally cylindrical insulating film 131 extending along the Z direction in a range corresponding to the Z direction of the plurality of conductive layers 110 along the inner peripheral surface of the ferroelectric film 132; and a generally cylindrical insulating film 133 extending along the Z direction in a range corresponding to the Z direction of the plurality of conductive layers 110 along the outer peripheral surface of the ferroelectric film 132.

[0096] The ferroelectric film 132 has at least one of silicon (Si), aluminum (Al), hafnium (Hf), and zirconium (Zr) as its main component. The ferroelectric film 132 can also be, for example, an insulating film containing orthorhombic hafnium oxide. The hafnium oxide contained in the ferroelectric film 132 can also be predominantly orthorhombic. More specifically, the hafnium oxide contained in the ferroelectric film 132 can also be predominantly orthorhombic III (space group Pbc21, space group number 29). In the crystallization of the hafnium oxide contained in the ferroelectric film 132, the proportion of orthorhombic crystals can be the largest. Furthermore, orthorhombic crystals are also called orthorhombic crystals. The crystal structure in the ferroelectric film 132 can be observed, for example, by methods such as ACOM-TEM (Automated Crystal Orientation Mapping Transmission Electron Microscopy).

[0097] In addition, the ferroelectric film 132 may contain at least one additive element selected from silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), strontium (Sr), lanthanum (La), samarium (Sm), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lutetium (Lu), and barium (Ba). Hereinafter, these additive elements are sometimes referred to as "the first additive element." Furthermore, the presence and concentration of the additive element can be confirmed, for example, by methods such as EDX (Energy Dispersive X-ray Spectroscopy).

[0098] From the viewpoint of enabling hafnium oxide to exhibit ferroelectricity, the concentration of the first additive element is preferably 0.1 atomic% or more and 80 atomic% or less. The suitable range of the concentration of the first additive element for enabling hafnium oxide to exhibit ferroelectricity varies depending on the type of the first additive element. For example, when the first additive element is silicon (Si), the suitable range of the concentration of the first additive element for exhibiting ferroelectricity is 3 atomic% or more and 7 atomic% or less. For example, when the first additive element is barium (Ba), the suitable range of the concentration of the first additive element for exhibiting ferroelectricity is 0.1 atomic% or more and 3 atomic% or less. For example, when the first additive element is zirconium (Zr), the suitable range of the concentration of the first additive element for exhibiting ferroelectricity is 10 atomic% or more and 80 atomic% or less.

[0099] [Chip C] M Storage cell array layer L MCA The joint area R HU [Construction in]

[0100] like Figure 5 As shown, in the joint region RHU A platform portion is provided with multiple conductive layers 110 (WL, SGD, SGS). The platform portion is the portion on the lower surface of the conductive layers 110 that does not overlap with other conductive layers 110 when viewed from below. The space beneath the multiple conductive layers 110 is filled with an insulating layer 105 primarily composed of silicon oxide. Additionally, in the bonding region R... HU Multiple contact electrodes CC are provided. Each of these multiple contact electrodes CC extends through the insulating layer 105 in the Z direction and is connected at its upper end to the platform portion of the conductive layer 110 (WL, SGD, SGS).

[0101] [Chip C] M Storage cell array layer L MCA The surrounding area R P [Construction in]

[0102] For example, such as Figure 4 As shown, the surrounding area R P It is buried under insulation layer 105. Additionally, in the surrounding area R... P , with external pad electrode P X Correspondingly, multiple contact electrodes CC are provided. Each of these multiple contact electrodes CC extends the insulating layer 105 through the Z direction, and connects to the external pad electrode P at its upper end. X connect.

[0103] [Chip C] M [Construction of CH contact electrode layer]

[0104] The contact electrode layer CH is buried by the insulating layer 105. Furthermore, multiple contact electrodes ch are provided in the contact electrode layer CH. Each of these multiple contact electrodes ch extends through the insulating layer 105 in the Z direction, for example, to the memory cell array layer L. MCA The composition and chip C in P At least one of the components is electrically connected.

[0105] The contact electrode layer CH includes multiple contact electrodes ch as multiple wirings. These multiple contact electrodes ch may also include, for example, a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The contact electrodes ch are disposed corresponding to multiple semiconductor pillars 120 and connected to the lower end of the multiple semiconductor pillars 120.

[0106] [Chip C] M [Construction of wiring layers M0 and M1]

[0107] Wiring layers M0 and M1 have multiple wirings m0 and m1, and an insulating layer 105 surrounding these wirings. The multiple wirings m0 and m1 are, for example, connected to the memory cell array layer L. MCA The composition and chip C in PAt least one of the components is electrically connected.

[0108] Multiple wirings m0 may include, for example, barrier conductive films such as stacked films of titanium nitride (TiN), tantalum nitride (TaN), tantalum nitride (TaN), and tantalum (Ta), as well as stacked films of metal films such as copper (Cu). Furthermore, a portion of the multiple wirings m0 functions as bit lines BL. For example, such as... Figure 6 As shown, the bit lines BL are arranged in the X direction and extend in the Y direction.

[0109] This includes multiple wirings m1. These multiple wirings m1 may, for example, include a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Additionally, for example, such as... Figure 4 as well as Figure 5 As shown, these multiple wirings m1 are electrically connected to wiring m0 via contact electrode V1.

[0110] [Structure of the chip bonding electrode layer (MB)]

[0111] The chip bonding electrode layer MB has multiple bonding electrodes P I1 An insulating layer 105 is filled around these bonded electrodes. Multiple bonded electrodes P I1 For example, with the memory cell array layer L MCA The composition and chip C in P At least one of the components is electrically connected.

[0112] Multiple bonding electrodes P I1 For example, it can also include barrier conductive films such as stacked films of titanium nitride (TiN), tantalum nitride (TaN), tantalum nitride (TaN), and tantalum (Ta). I1B Metal films such as copper (Cu) p I1M Laminated films, etc.

[0113] [Chip C] P [Construction]

[0114] For example, such as Figure 4 As shown, chip C P The device includes a semiconductor substrate (second substrate) 200, an electrode layer GC disposed above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, D4 disposed above the electrode layer GC, and a chip bonding electrode layer DB disposed above the wiring layers D0, D1, D2, D3, D4.

[0115] [Chip C] P [Structure of semiconductor substrate 200]

[0116] The semiconductor substrate 200 includes, for example, P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 200, for example, are formed an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S without N-type well regions 200N and P-type well regions 200P, and an insulating region STI. A portion of the P-type well region 200P is disposed in the semiconductor substrate region 200S, and a portion of the P-type well region 200P is disposed in the N-type well region 200N. The N-type well region 200N, the P-type well region 200P disposed in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as part of multiple transistors Tr and multiple capacitors constituting a peripheral circuit PC. The insulating region STI includes, for example, silicon oxide (SiO2) and extends in the Z direction.

[0117] [Chip C] P [Construction of the electrode layer GC]

[0118] An electrode layer GC is disposed on the upper surface of the semiconductor substrate 200, separated by an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc opposite to the surface of the semiconductor substrate 200, and an insulating layer 205, mainly composed of silicon oxide, filling the periphery of these electrodes. Each region of the semiconductor substrate 200 and each of the plurality of electrodes gc included in the electrode layer GC are connected to a contact electrode CS.

[0119] The multiple electrodes gc included in the electrode layer GC each function as the gate electrode of multiple transistors Tr that constitute the peripheral circuit PC.

[0120] The contact electrode CS extends in the Z direction and is connected to the upper surface of the semiconductor substrate 200 or the electrode gc at its lower end. An impurity region containing N-type or P-type impurities is provided at the connection portion between the contact electrode CS and the semiconductor substrate 200. The contact electrode CS may also include, for example, a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0121] [Chip C] P [Construction of wiring layers D0, D1, D2, D3, and D4]

[0122] For example, such as Figure 4 As shown, wiring layers D0, D1, D2, D3, and D4 have multiple wirings d0, d1, d2, d3, and d4, and an insulating layer 205 filling the periphery of these wirings. The multiple wirings d0, d1, d2, d3, and d4 are, for example, connected to the memory cell array layer L. MCA The composition and chip C in P At least one of the components is electrically connected.

[0123] Multiple wirings d0, d1, d2 may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0124] Multiple wirings d3 and d4 may include, for example, stacked films of titanium nitride (TiN), tantalum nitride (TaN), tantalum nitride (TaN) and tantalum (Ta), as well as stacked films of metal films such as copper (Cu).

[0125] [Structure of the chip bonding electrode layer DB]

[0126] The chip bonding electrode layer DB has multiple bonding electrodes P I2 An insulating layer 205 is filled around these bonded electrodes. Multiple bonded electrodes P I2 For example, with the memory cell array layer L MCA The composition and chip C in P At least one of the components is electrically connected.

[0127] Multiple bonding electrodes P I2 For example, it can also include barrier conductive films such as stacked films of titanium nitride (TiN), tantalum nitride (TaN), tantalum nitride (TaN), and tantalum (Ta). I2B Metal films such as copper (Cu) p I2M Laminated films, etc.

[0128] Furthermore, if a metal film of copper (Cu) or the like is applied... I1M p I2M Used for bonding electrode P I1 and bonding electrode P I2 Then the metal film p I1M With metal film p I2M The integration makes it difficult to define the boundaries between the parts. However, this can be mitigated by adjusting the bonding electrode P due to positional misalignment during bonding. I1 With the attached electrode P I2 Deformation of the shape after bonding, blocking the conductive film p I1B p I2B The bonding structure is confirmed by the positional offset (the generation of discontinuities on the side). Additionally, the bonding electrode P is formed using an inlay method. I1 and bonding electrode P I2 In this case, each side has a tapered shape. Therefore, regarding the bonding electrode P I1 With the attached electrode P I2 The cross-sectional shape along the Z-direction of the bonded portion shows that the sidewalls are not straight, but rather non-rectangular. Furthermore, when bonding electrode P... I1 With the attached electrode P I2When bonded, the structure consists of a barrier metal covering the bottom, side, and top surfaces of each Cu electrode. In contrast, in a typical Cu wiring layer, an insulating layer (SiN or SiCN, etc.) with Cu oxidation protection is placed on the top surface of the Cu, but no barrier metal is provided. Therefore, even without any offset in the bonding position, it can be distinguished from a typical wiring layer.

[0129] [Manufacturing Method]

[0130] Next, refer to Figures 8 to 28 The manufacturing method of the semiconductor device according to the first embodiment will be described. Figures 8-10 , Figures 13-18 as well as Figures 20-26 It is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 11 as well as Figure 12 This is a schematic bottom view used to illustrate the manufacturing method. Figure 19 , Figure 27 as well as Figure 28 This is a schematic top view used to illustrate the manufacturing method.

[0131] In this manufacturing method, such as Figure 8 As shown, firstly, a first substrate 150 is prepared. The first substrate 150 is a silicon substrate or a silicon carbide substrate, and is a light-transmitting substrate. In this embodiment, "light-transmitting" means having the property of being able to transmit laser light, as described later. For example, the transmittance of laser light on the first substrate 150 can be set to 40% or more. In addition, as the first substrate 150, a substrate with a resistivity of, for example, 1 to 100 Ω·cm (ohm-cm) can be used.

[0132] Next, after cleaning both sides of the first substrate 150, an insulating layer 151 with silicon nitride or the like as the main component is formed on the first substrate 150. The insulating layer 151 is formed, for example, using CVD (Chemical Vapor Deposition). The thickness of the insulating layer 151 can be 300 nm or less, or 200 nm or less, preferably 50 nm or more and 100 nm or less, for example, 70 nm.

[0133] Additionally, for example, an insulating layer 152, such as a silicon oxide layer, is formed on the insulating layer 151. The thickness of the insulating layer 152 can be 300 nm or less, or 200 nm or less, and is preferably 50 nm or more and 100 nm or less. Insulating layers 151 and 152 are examples of protective layers stacked on the first substrate. Furthermore, as other embodiments, either insulating layer 151 or 152 may be formed, or neither may be formed.

[0134] Next, as Figure 8 As shown, a first layer 162, which is mainly composed of silicon (Si) and contains germanium (Ge) and oxygen (O), is stacked on the insulating layer 152.

[0135] The first layer 162 contains germanium dioxide (GeO2). Alternatively, the first layer 162 may also contain germanium (Ge) monomers, silicon (Si) monomers, or silicon oxide (SiO2). Moreover, the first layer 162 is polycrystalline.

[0136] The proportions of each component in the first layer 162 are not particularly limited, but from the viewpoint of etching resistance and thermal stability, for example, the proportion of germanium (Ge) in the first layer 162 is preferably 10 atomic% or more and less than 50 atomic%, more preferably 20 atomic% or more and less than 40 atomic%, and even more preferably 25 atomic% or more and less than 35 atomic%. Furthermore, for example, the proportion of silicon (Si) in the first layer 162 can be more than the combined proportions of germanium (Ge) and oxygen (O), and can be set to 50 atomic% or more, 60 atomic% or more, or 70 atomic% or more. Furthermore, for example, the proportion of oxygen (O) in the first layer 162 can be set to less than 50 atomic%, 40 atomic% or less, or 30 atomic% or less.

[0137] The thickness of the first 162 layer is not particularly limited; it can be set to less than 500nm, less than 300nm, or less than 200nm.

[0138] The method for forming the first layer 162 is not particularly limited. For example, an unoxidized layer containing silicon and germanium can be formed by PVD (physical vapor deposition) such as CVD or sputtering. Then, the unoxidized layer is oxidized by oxidation treatments such as thermal oxidation or atmospheric exposure. The formation and oxidation of the unoxidized layer are repeated as needed to form the first layer 162. For example, the content ratio of each component in the first layer 162 can be appropriately changed by adjusting the concentration of the raw materials used in PVD or by adjusting the oxidation treatment time.

[0139] Hereinafter, the configuration having a first substrate 150, insulating layers 151 and 152 and a first layer 162 will be referred to as the first wafer SS. In addition, insulating layers 151, 152 and the first layer 162 will be referred to as the stacked portion 160.

[0140] Next, as Figure 9 As shown, a conductive layer 100 is formed on the laminate 160 by CVD or the like. A Conductive layer 100 A This then becomes the conductive layer 100 (source line SL) in the storage die MD. Then, as... Figure 10 As shown, conductive layer 100 is formed by CVD or similar methods. A Multiple silicon nitride layers and multiple silicon oxide layers are alternately stacked to form a laminate MCA. A Then, in the stacked body MCA A Apply corrosion inhibitor RG1.

[0141] Next, for example, such as Figure 11 as well as Figure 12 As shown, patterning is performed using methods such as photolithography. During patterning, a photolithography machine or similar device is used to pattern multiple bare die regions R throughout the entire area of ​​the first wafer SS. MD The corresponding pattern (hereinafter referred to as the "exposure pattern SP") is sequentially transferred onto the resist. In the illustrated example, the exposure pattern SP includes a total of eight die regions R, four in the X direction and two in the Y direction. MD The corresponding pattern. Furthermore, in Figure 11 The image shows the result after the 10th transfer. Figure 12 The image shows the situation after the 11th printing.

[0142] In addition, Figure 11 as well as Figure 12 The example illustrates settings in multiple die regions R. MD The cut-off area R between K Multiple bare die regions R MD Each region is monolithized through a cutting process described later, thus becoming a region part of the storage die MD. Cut region R K Includes the cutting line. Cutting area R K It has multiple cutting regions R that extend along a cutting line in the Y direction and are arranged in the X direction. KY And multiple cut regions R extending in the X direction and arranged in the Y direction along a portion of the cutting line. KX .

[0143] Next, as Figure 13 As shown, a portion of the resist RG1 is removed, leaving the laminate MCA covered by resist RG1 exposed. A Part of it is exposed. This process is carried out, for example, by methods such as wet etching.

[0144] Next, as Figure 14 As shown, multiple stacked bodies MCA A The process involves partitioning the stack-up MCA (memory cell array) into individual memory planes (MPs). In this step, the stack-up MCA is repeatedly processed using methods such as Reactive Ion Etching (RIE). A Removal of silicon oxide layer in, and MCA of laminates based on RIE and other methodsA The process involves the removal of the silicon nitride layer and the refinement of the resist RG1 based on methods such as wet etching. Through this process, the silicon nitride layer in the MCA laminate is refined. A Each silicon nitride layer in the process is formed in a portion corresponding to the platform section (the portion that does not overlap with other silicon nitride layers when viewed from the negative side in the Z direction). Furthermore, by repeatedly performing this process, the laminate MCA... A It is divided into each memory cell array (MCA) (each memory plane (MP)).

[0145] Next, as Figure 15 As shown, multiple memory cell arrays (MCAs) are formed. A memory cell array (MCA) can be formed, for example, through the following steps. First, a stacked MCA is formed. A The area between them is filled with an insulating layer 105. Next, a multilayer MCA is formed at multiple locations corresponding to the multiple semiconductor pillars 120. A Penetrates and reaches the conductive layer 100 A The memory holes are then formed. Next, a gate insulating film 130 and semiconductor pillars 120 are formed within these memory holes. Next, trenches are formed at multiple locations corresponding to the multiple inter-block insulating layers ST. Next, the stacked body MCA is formed by methods such as wet etching through these trenches. A The silicon nitride layer in the trench is removed, forming multiple voids. Next, multiple conductive layers 110 are formed using methods such as CVD. Then, an inter-block insulating layer ST is formed inside the trench.

[0146] Furthermore, before the laser irradiation described later, in order to suppress the irradiation in the first layer 162 ( Figure 8 The GeO removal reaction, described later, is carried out in the cell array MCA, which is formed at a temperature lower than the temperature at which the GeO removal reaction takes place (e.g., below 600 degrees Celsius).

[0147] Next, a reference is formed. Figure 4 , Figure 5 The wiring layers CH, Vy, M0, M1, MB, etc., have been described. This process is performed, for example, through an inlay process.

[0148] Next, as Figure 16 As shown, a second wafer SB is formed separately from the first wafer SS. Specifically, a transistor Tr (which serves as a second element) is formed on the semiconductor substrate 200. Figure 5 Multiple peripheral circuits PCs are formed, for example, corresponding to multiple memory cell arrays (MCAs). An insulating layer 205 is formed covering the peripheral circuits PCs. Adhesive electrodes P, electrically connected to transistors Tr and other components of the peripheral circuits PCs, are formed on the surface of the insulating layer 205. I2 .

[0149] Next, as Figure 16 as well as Figure 17 As shown, the first wafer SS is bonded to the second wafer SB. Specifically, as... Figure 16 As shown, the surface of the first wafer SS where the memory cell array MCA is formed is positioned opposite the surface of the second wafer SB where the peripheral circuitry PC is formed. Next, as... Figure 17 As shown, the first wafer SS and the second wafer SB are bonded together. In this process, the insulating layer 105 in the first wafer SS is bonded to the insulating layer 205 in the second wafer SB.

[0150] Furthermore, when bonding the first wafer SS to the second wafer SB, multiple bonding electrodes P are used. I1 With multiple bonding electrodes P I2 Alignment of wafer SS and wafer SB is performed in a manner that prevents overlap when viewed from the Z direction.

[0151] After bonding the insulating layers 105 and 205, an annealing process is performed, for example, by Cu-Cu bonding to bond the two electrodes P together. I1 P I2 The corresponding memory cell arrays MCA are thus electrically connected to the peripheral circuit PC, and the first chip SS and the second chip SB are bonded together (via bonding electrode P). I1 and bonding electrode P I2 (The first substrate 150 is bonded to the semiconductor substrate 200). In the following description, the structure after bonding the first wafer SS and the second wafer SB is referred to as the bonded body SA.

[0152] like Figure 17 As shown, in this embodiment, the outer periphery 150B of the first substrate 150 is not trimmed. Specifically, in the first substrate 150, the outer periphery 150B constituting the outer periphery of the body portion 150A is circular in cross-sectional view. The outer periphery 150B is not a cut shape in cross-sectional view, for example, and no trimming process to form such a cut shape is performed. Such trimming process may be omitted, for example, from the process of preparing the first substrate 150 to the process of bonding the first wafer SS and the second wafer SB, or it may be omitted before the reuse process described later, or it may be omitted in the entire manufacturing process of the semiconductor device.

[0153] like Figure 18 As shown, on the bonding surface SA of the first wafer SS and the second wafer SB, a laser beam passes through the first substrate 150 and irradiates the first layer 162. The wavelength of the laser is preferably in the range of 9.2 to 10.8 μm. For example, a carbon dioxide (CO2) laser can be used as the laser.

[0154] There are no particular limitations on the method of laser irradiation, but pulsed irradiation is preferred, for example. Figure 19 As shown, the bonding body SA of the first wafer SS and the second wafer SB can be placed on a worktable RT that can be rotated. While the worktable RT is rotated, laser is sequentially pulsed from the laser oscillator OSC.

[0155] That is, by rotating the stage RT while irradiating the first wafer SS with laser at regular time intervals, laser can be irradiated at multiple positions LR along a predetermined circle centered on the rotation axis of the stage RT. Furthermore, by moving the irradiation position closer to or further away from the rotation axis of the stage RT, laser can be irradiated at multiple positions LR along other circles centered on the rotation axis of the stage RT. In this way, laser can be irradiated concentrically across the entire surface of the first wafer SS.

[0156] The spacing between the laser irradiation positions can be set to, for example, tens of micrometers. The pulse frequency can be set to, for example, above 10 kHz and below 100 kHz.

[0157] By irradiating the first wafer SS with a laser, such as Figure 20 As shown, the laser passes through the first substrate 150 and the insulating layers 151 and 152 to reach the first layer 162. The laser light reaching the first layer 162 is absorbed by the first layer 162, causing the temperature of the first layer 162 to rise sharply. As a result, the GeO removal reaction (germanium monoxide removal) shown in the following formula (1) occurs in the first layer 162 to generate GeO gas.

[0158] GeO2 + Ge → 2GeO…(1)

[0159] From the viewpoint of ensuring a smooth GeO removal reaction, the temperature at which the first layer 162 is heated by laser irradiation is preferably 500 degrees Celsius or higher and 700 degrees Celsius or lower, more preferably 550 degrees Celsius or higher and 650 degrees Celsius or lower, and even more preferably 570 degrees Celsius or higher and 630 degrees Celsius or lower. Such a heating temperature may also be set to 600 degrees Celsius, for example.

[0160] By generating GeO gas in the first layer 162, a stress difference is created between the vicinity of where the GeO gas is generated and its lateral portion. For example, by generating GeO gas in the first layer 162, a stress difference is created between the vicinity 162A1 of where the GeO gas is generated and the lateral portion 162A2 located to its side (such a stress difference can also be generated in the insulating layers 152 and 151, for example). Furthermore, due to this stress difference, deformation occurs between the vicinity 162A1 and the lateral portion 162A2, for example, cracking occurs at the interface between the first layer 162 and the insulating layer 152, or within the first layer 162 itself.

[0161] Through the cracks produced in this way, such as Figure 21As shown, the first substrate 150 is peeled off from other components in the first wafer SS (components formed after the first layer 162 in the first wafer SS). At this time, all or part of the insulating layers 151 and 152, and a part of the first layer 162, are attached to the first substrate 150 as an appendage 160A and are peeled off together with the first substrate 150. In addition, another part of the first layer 162 remains on the second wafer SB side as a residual portion 160B. Hereinafter, the component remaining on the second wafer SB side in the first wafer SS will be referred to as structure SC.

[0162] Next, the residual portion 160B remaining in the SC structure is removed by grinding using CMP (Chemical Mechanical Polishing) or similar methods. Thus, as... Figure 22 As shown, make the conductive layer 100 A It is exposed on the upper surface of the second wafer SB.

[0163] Next, as Figure 23 As shown, in conductive layer 100 A A resist RG2 is formed having a pattern that matches the configuration of each memory cell array (MCA, memory plane, MP). During the formation of the resist RG2, for example, the resist is applied by referring to... Figure 11 as well as Figure 12 Various methods have been described for patterning, and a portion of the resist has been removed by methods such as wet etching.

[0164] Next, as Figure 24 As shown, conductive layer 100 is separated by resist RG2. A An etching process is performed to form multiple conductive layers 100 (source lines SL) separated according to each memory cell array (MCA).

[0165] After the conductive layer 100 is formed, the resist RG2 is removed by ashing treatment using oxygen plasma or the like. Then, as... Figure 25 As shown, a matrix layer L is formed. SB .

[0166] Next, as Figure 26 As shown, this is done by monolithization, forming multiple raw memory dies (MDs). That is, for example, as... Figure 27 As shown, multiple die regions R are provided in the structure of SC and the second wafer SB. MD Additionally, in these multiple bare die regions R MD A cutting area R is set between them. KX R KY In the monolithization process, for example, along the cutting region R... KX R KYThe cutting lines in the middle are used to cut the bonding body of the SC and the second chip SB as follows: Figure 28 As shown, multiple bare die regions R MD Each of these is then modularized. The modularized components then form the memory die (MD).

[0167] In addition, for ease of illustration, in Figure 3 In the example, each memory die MD has 4 memory cell arrays MCA (memory planes MP). Figure 26 In the example, each memory die MD has two memory cell arrays (MCAs) (memory planes, MPs), but the number of memory cell arrays (MCAs) (memory planes, MPs) in each memory die MD can be adjusted appropriately.

[0168] In addition, in reference Figure 21 The first substrate 150, after being stripped in the described process, can be used for the manufacture of a new memory die MD by performing the following reuse process.

[0169] In the reuse process, a polishing pad can also be used to remove the attachment portion 160A (refer to) that has adhered to the SS side of the first wafer due to the crack in the first layer 162. Figure 21 Grinding can remove the 160A. Alternatively, during the recycling process, the 160A portion can be removed by wet etching or similar methods.

[0170] After removing the appendage 160A from the first substrate 150, the reference is executed again. Figure 8 The described processes and subsequent processes enable the first substrate 150 to be used multiple times in the manufacturing process of the storage die MD.

[0171] [Effect]

[0172] In semiconductor device manufacturing methods, when a substrate having a predetermined layer is bonded to another substrate and then peeled off by irradiating the predetermined layer with a laser, localized stress may occur in the predetermined layer and / or its vicinity, leading to crystal defects, structural damage, etc., in the substrate and / or the structure formed on the substrate. Furthermore, after the process of peeling off the two substrates, if the substrate having the predetermined layer is to be reused, deep grinding is required, for example, to remove the portions that have caused the aforementioned crystal defects, structural damage, etc. (hereinafter referred to as damage). As a result, the substrate for reuse becomes thinner, and the number of times the substrate can be reused decreases.

[0173] In the semiconductor device manufacturing method according to this embodiment, as referred to Figure 8 As described, the process includes the following steps: A first layer 162, primarily composed of silicon and containing germanium and oxygen, is deposited on the first substrate 150. Additionally, as referred to... Figure 15As described, the process includes the following steps: forming a memory cell array MCA (first element) on the first wafer SS and attaching electrodes P. I1 (First bonding electrode). Additionally, see reference... Figure 16 As described, the process includes the following steps: forming transistor Tr (the second element) on the second wafer SB and attaching electrode P. I2 Additionally, as referenced Figure 17 As described, the process includes the following steps: via bonding electrode P I1 and bonding electrode P I2 The first wafer SS is bonded to the second wafer SB. Additionally, as shown in the reference... Figures 18-20 As described, the process includes the following steps: cracking the first layer 162 by irradiating the first layer 162 with a laser through the first substrate 150.

[0174] With this configuration, the first layer 162 can absorb laser light to generate GeO gas, and a stress difference can be generated around the portion where the GeO gas is generated to properly peel off the first substrate 150. Therefore, damage to the first substrate 150, the memory cell array (MCA) (first element), etc., that occurs during the peeling of the first substrate 150 can be suppressed. Thus, assuming the first substrate 150 is to be reused, for example, the grinding depth of the first substrate 150 can be suppressed, and the number of times the first substrate 150 can be reused can be prevented from decreasing.

[0175] Furthermore, in this embodiment, the first substrate 150 is a silicon substrate or a silicon carbide substrate. With this configuration, since the laser appropriately passes through the first substrate 150, evaporation and the like can be effectively generated in the first layer 162.

[0176] Here, when the substrate of the wafer including the memory cell array (MCA) is removed by grinding from the laminate obtained by bonding a wafer including a wafer including a peripheral circuit (PC), the outer periphery of the substrate becomes extremely thin during the grinding process, and the outer periphery may break. Therefore, there is a technique to pre-trim the outer periphery to suppress breakage.

[0177] On the other hand, in this embodiment, by irradiating the first layer 162 with a laser to cause the first layer 162 to crack, the process of grinding the first substrate 150 to remove it is not included. Therefore, the outer periphery 150B of the first substrate 150 is not trimmed.

[0178] With this configuration, there is no need for a finishing process on the outer periphery 150B of the first substrate 150, thus enabling efficient manufacturing of semiconductor devices.

[0179] In addition, in this embodiment, as referred to Figure 8 As explained, before the first layer 162 is stacked on the first wafer SS, insulating layers 151 and 152 are stacked on the first substrate 150.

[0180] With this configuration, the insulating layers 151 and 152 can more appropriately suppress damage to the first substrate 150 caused by the generation and cracking of GeO gas in the first layer 162. In addition, the heat generated by the absorption of laser light in the first layer 162 can be suppressed from being transferred to the first substrate 150.

[0181] In addition, the gate insulating film 130 includes a ferroelectric film with at least one of silicon, aluminum, chromium and zirconium as the main component.

[0182] Based on this configuration, a memory cell array (MCA) can be constructed such that it can suppress the GeO detachment reaction in the first layer 162 before the process of irradiating the first layer 162 with a laser and causing the first layer 162 to crack is performed.

[0183] [Second Implementation]

[0184] The semiconductor device manufacturing method according to the first embodiment can be appropriately adjusted. Hereinafter, as a second embodiment, the process of manufacturing the memory die MD2 by reusing the first substrate 150 will be described. Furthermore, in the second embodiment, the same reference numerals are used for the same parts as in the first embodiment, and repeated descriptions of the structure, process, function, and effect are omitted.

[0185] Figures 29-33 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the second embodiment.

[0186] The semiconductor device manufacturing method according to the second embodiment is performed in the semiconductor device manufacturing method according to the first embodiment, with reference to... Figure 25 The procedures have been explained up to this point. However, in reference... Figure 25 In the described process, the substrate layer L is formed. SB ′ to replace the matrix layer L SB Matrix layer L SB Basically constitutes a matrix layer L SB Similarly. However, in the matrix layer L SB The upper surface of ′ forms and adheres to electrode P I1 P I2 The same configuration is used to replace the external pad electrode P. X .

[0187] Next, execution and reference. Figures 8 to 16The same process described above is used to form wafer SS2. Wafer SS2 has the same structure as the first wafer SS.

[0188] Next, as Figure 29 as well as Figure 30 As shown, the substrate layer L SB ' is bonded to wafer SS2. This process is similar to the reference. Figure 16 as well as Figure 17 The procedures described are performed in the same manner.

[0189] Next, execution and reference. Figures 18-25 The same procedures have been described. However, in reference... Figure 25 In the described process, the substrate layer L is formed. SB ′ to replace the matrix layer L SB Therefore, as Figure 31 As shown, a bonding body is formed on the upper surface of the second wafer SB, wherein the first structure SC is bonded and the second structure SC is bonded on the upper surface of the first structure SC.

[0190] Similarly, the following will be achieved through repeated execution and reference. Figures 8 to 25 The same process described above forms the same result as described above. Figure 32 As shown, multiple bonding bodies with a structure SC are bonded to the second wafer SB.

[0191] Next, execution and reference. Figures 26-28 The same process described above is used to monolithize the bonding body on the second wafer SB, which has multiple structures SC, to form multiple memory dies MD2.

[0192] [Third Implementation]

[0193] The configuration of the laminated portion 160 according to the first embodiment can be appropriately adjusted. Hereinafter, as a third embodiment, a laminated portion 360 with a different configuration from the laminated portion 160 will be described. Furthermore, in the third embodiment, the same reference numerals are used for the same parts as in the first embodiment, and repeated descriptions of the structure, process, function, and effect are omitted.

[0194] Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the third embodiment.

[0195] The method for manufacturing a semiconductor device according to the third embodiment is performed in essentially the same way as the method for manufacturing a semiconductor device according to the first embodiment. However, in the third embodiment, in conjunction with... Figure 8 In the corresponding process, a laminated section 360 is formed to replace the laminated section 160.

[0196] Specifically, such as Figure 34 As shown, layer 161 is stacked on the surface of insulating layer 152, first layer 162 is stacked on the surface of layer 161, and layer 161 is stacked again on the surface of first layer 162 to form a stacked portion 360. In the stacked portion 360, the portion with layer 161 and first layer 162 stacked is called a multilayer stacked portion 365.

[0197] exist Figure 34 In the example, the multilayer stack 365 has two layers 161 and one first layer 162. The first layer 162 is sandwiched between layers 161 in the Z direction. In the multilayer stack 365, the first layer 161 counting from the positive side in the Z direction (the side of the first substrate 150) is designated as the second layer 161A, and the second layer 161 is designated as the third layer 161B.

[0198] The second layer 161A and the third layer 161B have higher Young's moduli compared to the first layer 162. The Young's moduli of the first layer 162, the third layer 161B, and the second layer 161A are not particularly limited. For example, the Young's moduli of the first layer 162 can be set to be around 190 GPa, and the Young's moduli of the second layer 161A and the third layer 161B can be set to be around 310 GPa.

[0199] Additionally, the second layer 161A and the third layer 161B contain compounds comprising at least one of tungsten (W), titanium (Ti), and silicon (Si). Furthermore, the second layer 161A and the third layer 161B may also contain a transparent metallic compound. For example, the second layer 161A and the third layer 161B may also contain at least one of tungsten oxide (WO3), titanium oxide (TiO2), and silicon nitride (SiN).

[0200] Furthermore, the melting points of the second layer 161A and the third layer 161B can be higher than that of the first layer 162. With this configuration, melting of the second layer 161A and the third layer 161B can be suppressed when GeO gas is generated by irradiating the first layer 162 with a laser. Moreover, damage to the first substrate 150 and the memory cell array MCA (first element) can be suppressed by using the second layer 161A and the third layer 161B.

[0201] The thickness of the second layer 161A and the third layer 161B is not particularly limited. It can be set to less than 300nm or less than 200nm, and preferably to more than 50nm and less than 100nm.

[0202] The film formation methods for the second layer 161A and the third layer 161B are not particularly limited; for example, CVD, sputtering, and other PVD (Physical Vapor Deposition) methods can be used. Furthermore, the second layer 161A and the third layer 161B can be made of the same material or different materials.

[0203] Then, in the process of irradiating the first wafer SS3 with the stacked portion 360 with a laser (see reference) Figure 18 as well as Figure 20 The laser beam passes through the first substrate 150, insulating layers 151 and 152, and the second layer 161A to reach the first layer 162. The laser beam reaching the first layer 162 is absorbed by the first layer 162, causing the temperature of the first layer 162 to rise sharply. As a result, the GeO desorption reaction shown in the above formula (1) occurs to generate GeO gas, and cracks are generated in the first layer 162.

[0204] With the above configuration, since layers 161 (second layer 161A and third layer 161B) are provided on the upper and lower surfaces of the first layer 162, the second layer 161A and the third layer 161B can prevent cracks and other defects that may occur in the first layer 162 due to cracking in the first layer 162. Furthermore, the second layer 161A and the third layer 161B can further suppress damage to the first substrate 150 and the first element MCA. Therefore, assuming the first substrate 150 is reused, for example, the grinding depth of the first substrate 150 can be further suppressed, and the decrease in the number of times the first substrate 150 can be reused can be further suppressed. In addition, by providing a first layer 162 between the second layer 161A and the third layer 161B, a portion of the laser light that passes through the upper second layer 161A is reflected by the lower third layer 161B. The reflected laser light interferes with the laser light that passes through the upper second layer 161A, thereby enabling the laser light to be effectively absorbed in the first layer 162.

[0205] [Fourth Implementation]

[0206] Next, another configuration of the laminated portion 160 according to the first embodiment will be illustrated. Hereinafter, as the fourth embodiment, the laminated portion 460, which has a different configuration from the laminated portion 160, will be described. Furthermore, in the fourth embodiment, the same reference numerals are used for the same parts as in the first embodiment, and repeated descriptions of the structure, process, function, and effect are omitted.

[0207] Figure 35 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor device according to the fourth embodiment.

[0208] The semiconductor device manufacturing method according to the fourth embodiment is performed in essentially the same way as the semiconductor device manufacturing method according to the first embodiment. However, in the third embodiment, in comparison with... Figure 8 In the corresponding process, a laminated section 460 is formed to replace the laminated section 160.

[0209] Specifically, such as Figure 35As shown, after the first layer 162 is stacked on the first wafer SS, a reflective layer 153 for reflecting laser light is stacked. The reflective layer 153 is a layer with a higher reflectivity than the first layer 162, and may contain at least one of tungsten (W), molybdenum (Mo), titanium-tungsten alloy (TiW), titanium (Ti), and titanium nitride (TiN).

[0210] Based on this structure, in reference Figure 18 In the described process, the laser light that is not absorbed by the first layer 162 and passes through is reflected by the reflective layer 153 and re-enters the first layer 162, thereby generating heat appropriately.

[0211] Furthermore, the configuration of the laminated portion 460 can also be adjusted appropriately.

[0212] Figure 36 This is a schematic cross-sectional view used to illustrate a method for manufacturing a semiconductor device according to the fourth embodiment. When forming the laminate 460, for example, it may be as follows: Figure 36 As shown, anti-diffusion barrier metal layers 154 are formed above and below the reflective layer 153. The barrier metal layers may contain, for example, titanium nitride (TiN).

[0213] [Fifth Implementation]

[0214] In the first to third embodiments, FeFET or NAND flash memory were exemplified as the manufactured semiconductor devices. However, the techniques described in this specification can also be applied to configurations other than NAND flash memory, such as NOR flash memory. Furthermore, the techniques described in this specification can also be applied to configurations other than flash memory, such as DRAM.

[0215] Hereinafter, as the fifth embodiment, an example of applying the previously described technology to DRAM will be described.

[0216] Figure 37 This is a schematic circuit diagram illustrating a portion of the configuration of the semiconductor device according to the fifth embodiment. The semiconductor device according to the fifth embodiment, for example, includes... Figure 37 The storage cell array MCA4 and the peripheral circuit PC4 are shown as shown.

[0217] The memory cell array MCA4 includes multiple bit lines BL4, multiple word lines WL4, multiple board lines PL, and multiple memory cells MC4 connected to these bit lines BL4, word lines WL4, and board lines PL. Multiple memory cells MC4 connected to one word line WL4 are each connected to a different bit line BL4. Additionally, multiple memory cells MC4 connected to one bit line BL4 are each connected to a different word line WL4.

[0218] Each memory cell MC4 has a selection transistor ST connected in series between bit line BL4 and board line PL, and a capacitor Cap.

[0219] The selector transistor ST is a field-effect transistor that has a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. The gate electrode of the selector transistor ST is connected to the word line WL4.

[0220] A capacitor (Cap) is a capacitor that has a pair of electrodes and an insulating film. The capacitor (Cap) functions as a storage unit.

[0221] The peripheral circuit PC4 includes, for example, a voltage generation circuit that generates an operating voltage and outputs it to the voltage supply line, a decoding circuit that connects the desired voltage supply line to each wiring (bit line BL4, word line WL4, and board line PL) in the memory cell array MC4A, and a sensing amplifier circuit that detects the current or voltage of the bit line BL4.

[0222] Next, the structure of the semiconductor device according to the fifth embodiment will be described. The semiconductor device according to the fifth embodiment is basically the same as the semiconductor device according to the first embodiment. However, the chip C of the semiconductor device according to the fifth embodiment... M This includes a memory cell array MCA4 instead of a memory cell array MCA. Additionally, the fifth embodiment relates to a semiconductor device chip C. P This includes replacing the peripheral circuit PC with the peripheral circuit PC4.

[0223] Figure 38 This is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to the fifth embodiment. Figure 38 The chip C of the semiconductor device according to the fifth embodiment is shown in the figure. M It is a component of something.

[0224] like Figure 38 As shown, the chip C of the semiconductor device according to the fifth embodiment M It has bitline layers L arranged sequentially from bottom to top. BL Transistor layer L TR Capacitor layer L CP and board line layer L PL .

[0225] Bitline layer L BL The device includes multiple wirings 411 arranged in the X direction and extending in the Y direction. The wirings 411 function as bit lines BL4. A via contact electrode 412 is connected to the upper end of the lower surface of the wirings 411, and a via contact electrode 413 is connected to the lower end of the upper surface of the wirings 411. The wirings 411 are connected to the via contact electrode 412 via a reference... Figure 4 as well as Figure 5 The described bonding electrode P I1 connect.

[0226] transistor layer L TR It includes multiple wirings 421 arranged in the Y direction and extending in the X direction, multiple semiconductor pillars 422 arranged in the X and Y directions corresponding to wirings 411 and 421 and electrically connected to wirings 411 and opposite to wirings 421, and multiple insulating layers 423 disposed on the opposite surface of semiconductor pillars 422 opposite to wirings 421.

[0227] Wiring 421 serves as the gate electrode of multiple selection transistors ST arranged in the X direction, and word line WL4 ( Figure 37 To perform its function. Wiring 421 may also include, for example, a tungsten (W) or titanium nitride (TiN) and a tungsten (W) stack structure.

[0228] Semiconductor pillar 422, for example, serves as a selection transistor ST ( Figure 37 The channel region functions as a semiconductor pillar 422. The semiconductor pillar 422 extends, for example, in the Z direction and has a generally cylindrical shape. The outer peripheral surfaces of a plurality of semiconductor pillars 422 arranged in the X direction are surrounded by the same wiring 421, opposite to which the semiconductor pillar 422 is located. The lower ends of the semiconductor pillars 422 are electrically connected to the wiring 411 via via contact electrodes 413.

[0229] Semiconductor pillar 422 comprises an oxide semiconductor. Semiconductor pillar 422 may contain, for example, at least one element selected from indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), calcium (Ca), titanium (Ti), manganese (Mn), cadmium (Cd), and tin (Sn), zinc (Zn), and oxygen (O). Semiconductor pillar 422 may contain, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O).

[0230] Insulating layer 423 serves as the selection transistor ST( Figure 37 The gate insulating film functions as a barrier. The insulating layer 423 extends in the Z direction along the outer peripheral surface of the semiconductor pillar 422, insulating the semiconductor pillar 422 from the wiring 421. The insulating layer 423 may also be, for example, silicon oxide (SiO2) or silicon nitride (SiN), or a laminate of them with other insulating layers with high dielectric constant.

[0231] Capacitor layer L CP It includes: a plurality of conductive pillars 431 arranged in the X and Y directions corresponding to a plurality of semiconductor pillars 422, an insulating layer 432 extending in the Z direction along the outer peripheral surface of the conductive pillars 431, and a conductive layer 433 extending in the Z direction along the outer peripheral surface of the insulating layer 432.

[0232] Conductive post 431 serves as capacitor Cap ( Figure 37 A portion of one electrode of the semiconductor pillar 422 functions. The conductive pillar 431 extends in the Z direction and is connected at its lower end to the upper end of the semiconductor pillar 422. The conductive pillar 431 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0233] Insulating layer 432 serves as capacitor Cap( Figure 37 The insulating layer between the electrodes functions as a conductor. The insulating layer 432 may contain, for example, aluminum oxide (AlO). Alternatively, the insulating layer 432 may be silicon oxide (SiO2) or other insulating metal oxides.

[0234] Conductive layer 433, for example, serves as a capacitor Cap ( Figure 37 The other electrode functions. The conductive layer 433 is separated from the outer peripheral surface of the conductive pillar 431 by the insulating layer 432. The conductive layer 433 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0235] Board line layer L PL A conductive layer 441 is provided, which is connected to the upper ends of a plurality of conductive layers 433 arranged in the X and Y directions. The conductive layer 441 is, for example, a plate line PL ( Figure 37 To perform its function. The conductive layer 441 may also include, for example, a stacked structure of tungsten (W), or titanium nitride (TiN) and tungsten (W).

[0236] When manufacturing the semiconductor device according to the fifth embodiment, the reference is performed. Figure 8 The described process involves forming a stacked portion 160 on the first wafer SS. Next, a reference layer is formed on the stacked portion 160. Figure 38 The plate line layer L has been described. PL The composition and formation of capacitor layer L CP The composition and formation of transistor layers L TR The composition and formation of bit line layers L BL The composition within. Next, create a reference. Figure 4 The bonding electrode P has been described. I1 wait.

[0237] Next, as the second wafer SB, a wafer including peripheral circuit PC4 is formed to replace the peripheral circuit PC. Then, by executing the semiconductor device manufacturing method according to the first embodiment, referring to... Figure 16 as well as Figure 17 The processes described thereafter form the semiconductor device according to the fifth embodiment.

[0238] [Sixth Implementation]

[0239] In the fifth embodiment, DRAM is illustrated as a semiconductor device manufactured. Here, various structures can be applied as the structure of DRAM.

[0240] Hereinafter, as the sixth embodiment, examples of applying the previously described techniques to other DRAM structures will be described.

[0241] Figure 39 as well as Figure 40 This is a schematic perspective view showing the configuration of a portion of the semiconductor device according to the sixth embodiment. Figure 40 Enlarged display Figure 39 Part of it.

[0242] The memory cell array MCA4 according to the sixth embodiment includes multiple memory layers ML arranged in the Z direction. In addition, insulating layers 503 such as silicon oxide (SiO2) are respectively provided between the multiple memory layers ML.

[0243] Furthermore, the memory cell array MCA4 according to the sixth embodiment is provided with a conductive layer 502. The conductive layer 502 extends in the Y direction and the Z direction, dividing the memory layer ML in the X direction.

[0244] The conductive layer 502 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 502 may serve as, for example, a plate line PL (…). Figure 37 To fulfill its function.

[0245] In addition, multiple vias 504 are provided in the memory cell array MCA4. The multiple vias 504 are arranged in the Y direction and extend in the Z direction through multiple memory layers ML.

[0246] like Figure 40 As shown, the via wiring 504 includes, for example, a conductive oxide film 504a containing a conductive oxide, a barrier conductive film 504b such as titanium nitride (TiN), and a conductive member 504c such as tungsten (W). Furthermore, the via wiring 504 may also contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 504a. Additionally, the via wiring 504 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals.

[0247] In this embodiment, "conductive oxide" is defined as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials.

[0248] The conductive member 504c has a generally cylindrical shape extending in the Z direction. The barrier conductive film 504b has a generally cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive member 504c. The conductive oxide film 504a has a generally cylindrical shape extending in the Z direction along the outer peripheral surface of the barrier conductive film 504b. The via wiring 504 is, for example, a bit line BL4. Figure 37 To fulfill its function.

[0249] The storage layer ML includes: a plurality of transistor structures 510 disposed corresponding to a plurality of via wirings 504, a conductive layer 520 disposed on the opposite side of the conductive layer 502 relative to the plurality of transistor structures 510, and a plurality of capacitor structures 530 disposed between the plurality of transistor structures 510 and the conductive layer 502.

[0250] For example, such as Figure 40 As shown, the transistor structure 510 includes: a semiconductor layer 511 that is connected to the outer peripheral surface of the via wiring 504 and extends in the X direction; an insulating layer 512 disposed on the upper surface, lower surface, two sides in the Y direction and one side (conductive layer 520 side) in the X direction of the semiconductor layer 511; and a conductive layer 513 disposed on the upper surface, lower surface, two sides in the Y direction and one side (conductive layer 520 side) in the X direction of the insulating layer 512.

[0251] In the XY cross-section including the height of semiconductor layer 511, one side of semiconductor layer 511 in the X direction (the side of conductive layer 502) can also be formed along a circle centered on the center of via wiring 504. Additionally, the other side of semiconductor layer 511, insulating layer 512, and conductive layer 513 in the X direction (the side of conductive layer 520) can also be formed as a straight line along the side of conductive layer 520. Furthermore, the two sides of semiconductor layer 511, insulating layer 512, and conductive layer 513 in the Y direction can also be formed as a straight line along the side of insulating layer 515.

[0252] Semiconductor layer 511, for example, serves as a selection transistor ST. Figure 37 The channel region of the semiconductor layer 511 functions. The semiconductor layer 511 can be, for example, a semiconductor containing at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. Multiple semiconductor layers 511 arranged in the Z direction are collectively connected to a via wiring 504 extending in the Z direction.

[0253] Insulating layer 512, for example, serves as the selection transistor ST. Figure 37 The gate insulating film of the insulating layer 512 performs its function. The insulating layer 512 contains, for example, silicon oxide (SiO2).

[0254] Conductive layer 513, for example, serves as a selection transistor ST. Figure 37 The gate electrode functions as a conductive layer 513. The conductive layer 513 comprises, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). Multiple conductive layers 513 arranged in the Y direction are connected to a conductive layer 520 extending in the Y direction (see reference). Figure 39 The conductive layer 513 is separated from the insulating layer 512 and is opposite to the upper surface, lower surface, two sides in the Y direction, and one side (the conductive layer 520 side) in the X direction of the semiconductor layer 511.

[0255] An insulating layer 515, such as silicon oxide (SiO2), is disposed between two adjacent semiconductor layers 511 in the Y direction. The insulating layer 515 extends in the Z direction through multiple memory layers ML.

[0256] Conductive layer 520, for example, is used as word line WL4 ( Figure 37 It functions as follows. The conductive layer 520 extends in the Y direction and is connected to a plurality of conductive layers 513 arranged in the Y direction. The conductive layer 520 may include, for example, a barrier conductive film 521 of titanium nitride (TiN) and a conductive film 522 of tungsten (W).

[0257] For example, such as Figure 40 As shown, the capacitor structure 530 includes: a conductive layer 531; a conductive layer 532 disposed on the upper surface, lower surface, two sides in the Y direction, and one side in the X direction (transistor structure 510 side) of the conductive layer 531; an insulating layer 533 disposed on the upper surface, lower surface, two sides in the Y direction, and one side in the X direction (transistor structure 510 side) of the conductive layer 532; a conductive layer 534 disposed on the upper surface, lower surface, two sides in the Y direction, and one side in the X direction (transistor structure 510 side) of the insulating layer 533; an insulating layer 535 disposed on the upper surface, lower surface, and two sides in the Y direction of the conductive layer 534; a conductive layer 536 disposed on the upper surface, lower surface, and two sides in the Y direction of the insulating layer 535; and a conductive layer 537 disposed on the upper surface, lower surface, and two sides in the Y direction of the conductive layer 536.

[0258] Conductive layers 531, 532, 536, and 537 serve as capacitor Cap( Figure 37 One electrode functions as the conductive layer. Conductive layers 531 and 537 contain, for example, tungsten (W). Conductive layers 532 and 536 contain, for example, titanium nitride (TiN). Conductive layers 531, 532, 536, and 537 are connected to conductive layer 502.

[0259] Insulating layers 533 and 535 serve as capacitor caps ( Figure 37The insulating layer 533 and 535 can function as an insulating layer. The insulating layers 533 and 535 can also be, for example, zirconium oxide (ZrO2), aluminum oxide (Al2O3), or other insulating metal oxides. Alternatively, the insulating layers 533 and 535 can also be, for example, a laminate of multiple insulating metal oxides (e.g., a laminate of zirconium oxide and aluminum oxide).

[0260] Conductive layer 534, for example, serves as a capacitor Cap ( Figure 37 The other electrode functions. The conductive layer 534 contains, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 534 is insulated from the conductive layers 531, 532, 536, and 537 through insulating layers 533 and 535. The conductive layer 534 is connected to the side surface of the semiconductor layer 511 in the X direction.

[0261] When manufacturing the semiconductor device according to the sixth embodiment, the reference is performed. Figure 8 The described process involves forming a stacked portion 160 on the first wafer SS. Next, a plurality of memory layers ML and an insulating layer 503 are formed on the stacked portion 160. Figure 39 Next, create a reference. Figure 4 The bonding electrode P has been described. I1 wait.

[0262] Next, as the second wafer SB, a wafer including peripheral circuit PC4 is formed to replace the peripheral circuit PC. Then, by executing the semiconductor device manufacturing method according to the first embodiment, referring to... Figure 16 as well as Figure 17 The processes described thereafter form the semiconductor device according to the sixth embodiment.

[0263] [Other Implementation Methods]

[0264] The manufacturing methods of the semiconductor devices according to Embodiments 1 to 6 have been described above. However, their configurations are merely illustrative, and the specific configurations can be appropriately adjusted.

[0265] For example, in the third embodiment, a laminate 360 ​​is shown having two layers 161 (a second layer 161A and a third layer 161B) and one first layer 162. However, the number of first layers 162 and layers 161 in the laminate can be appropriately varied. For example, the laminate may also be constructed by alternately laminating three or more layers 161 and two or more first layers 162 on the insulating layer 152.

[0266] Furthermore, in the above embodiments, a semiconductor memory device was exemplified as a manufactured semiconductor device. However, the techniques described in this specification can also be applied to configurations other than semiconductor memory devices, such as arithmetic devices.

[0267] Furthermore, in the above embodiments, the following item 1 was disclosed.

[0268] [Item 1]

[0269] A method for manufacturing a semiconductor device includes:

[0270] A process of stacking a first layer containing germanium and oxygen as the main component on a first wafer having a first substrate;

[0271] The process of forming the first element and the first bonding electrode on the first wafer;

[0272] The process of forming the second element and the second bonding electrode on the second wafer;

[0273] The process of bonding the first wafer and the second wafer via the first bonding electrode and the second bonding electrode; and

[0274] The process of causing the first layer to crack by irradiating the first layer through the first substrate with a laser.

[0275] Furthermore, in the fifth embodiment, the following items 2 to 5 are disclosed.

[0276] [Item 2]

[0277] According to the semiconductor device manufacturing method described in Item 1,

[0278] The first element comprises:

[0279] The second semiconductor pillar extends in a first direction intersecting the first substrate;

[0280] The second gate electrode is opposite to the outer peripheral surface of the second semiconductor pillar;

[0281] A second gate insulating film is disposed between the second semiconductor pillar and the second gate electrode;

[0282] The first electrode is connected to one end of the second semiconductor pillar in the first direction and extends in the first direction;

[0283] A dielectric layer extends along the outer peripheral surface of the first electrode in the first direction; and

[0284] The second electrode extends along the outer peripheral surface of the dielectric layer in the first direction and is opposite to the outer peripheral surface of the first electrode across the first dielectric layer.

[0285] [Item 3]

[0286] According to the semiconductor device manufacturing method described in Item 2,

[0287] The second gate insulating film contains oxygen and silicon.

[0288] [Item 4]

[0289] According to the semiconductor device manufacturing method described in Item 2,

[0290] The second semiconductor pillar comprises an oxide semiconductor.

[0291] [Item 5]

[0292] According to the semiconductor device manufacturing method described in Item 4

[0293] The oxide semiconductor uses at least one of titanium and indium as its main component.

[0294] [other]

[0295] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: A process of stacking a first layer containing germanium and oxygen as the main component on a first wafer having a first substrate; The process of forming the first element and the first bonding electrode on the first wafer; The process of forming the second element and the second bonding electrode on the second wafer; The process of bonding the first wafer and the second wafer via the first bonding electrode and the second bonding electrode; and The process of causing the first layer to crack by irradiating the first layer through the first substrate with a laser.

2. The method for manufacturing a semiconductor device according to claim 1, The first substrate is a silicon substrate or a silicon carbide substrate.

3. The method for manufacturing a semiconductor device according to claim 1, The first layer is polycrystalline.

4. The method for manufacturing a semiconductor device according to claim 1, The first layer contains germanium dioxide.

5. The method for manufacturing a semiconductor device according to claim 1, The outer periphery of the first substrate is not trimmed.

6. The method for manufacturing a semiconductor device according to claim 1, Before the first layer is stacked on the first wafer, a protective layer is stacked on the first substrate.

7. The method for manufacturing a semiconductor device according to claim 1, Before the first layer is stacked on the first wafer, a second layer with a higher Young's modulus than the first layer is stacked on the first wafer. After the first layer is stacked on the first wafer, a third layer with a higher Young's modulus than the first layer is stacked on the first layer.

8. The method for manufacturing a semiconductor device according to claim 7, The second layer is a compound containing at least one of tungsten, titanium, and silicon.

9. The method for manufacturing a semiconductor device according to claim 1, After the first layer is stacked on the first wafer, a fourth layer with a higher reflectivity than the first layer is stacked on the first wafer.

10. The method for manufacturing a semiconductor device according to claim 9, The fourth layer contains at least one of tungsten (W), molybdenum (Mo), titanium-tungsten alloy (TiW), titanium (Ti), and titanium nitride (TiN).

11. The method for manufacturing a semiconductor device according to claim 1, The first element comprises: Multiple semiconductor layers are stacked in a first direction intersecting the first substrate; A plurality of third gate electrodes are stacked in the first direction corresponding to the plurality of semiconductor layers, each facing one side and the other side of one of the semiconductor layers in the first direction; A third gate insulating film is disposed between the plurality of semiconductor layers and the third gate electrode; Via wiring extends in the first direction and is electrically connected to the plurality of semiconductor layers; as well as Multiple storage units are stacked in the first direction corresponding to the multiple semiconductor layers, and are connected to the side surfaces of the multiple semiconductor layers in a second direction that intersects the first direction.

12. The method for manufacturing a semiconductor device according to claim 11, The plurality of semiconductor layers are oxides with at least one of titanium and indium as the main components.

13. The method for manufacturing a semiconductor device according to claim 11, The plurality of storage units are capacitors.

14. The method for manufacturing a semiconductor device according to claim 1, The first element comprises: A plurality of first gate electrodes are stacked in a first direction intersecting the first substrate; A first semiconductor pillar extends in the first direction; and A first gate insulating film is disposed between the plurality of first gate electrodes and the first semiconductor pillar.

15. The method for manufacturing a semiconductor device according to claim 14, The first gate insulating film includes a ferroelectric film with at least one of silicon, aluminum, hafnium and zirconium as the main components.

16. The method for manufacturing a semiconductor device according to claim 14, The first semiconductor pillar is an oxide with at least one of titanium and indium as the main component.

17. The method for manufacturing a semiconductor device according to claim 14, The first gate electrode uses at least one of polycrystalline silicon, tungsten, molybdenum and titanium nitride as its main components.

18. The method for manufacturing a semiconductor device according to claim 1, The wavelength of the laser is in the range of 9.2 to 10.8 μm.

19. The method for manufacturing a semiconductor device according to claim 1, After the process of cracking the first layer, the second wafer is monolithized into multiple chips.

20. The method for manufacturing a semiconductor device according to claim 7, The melting point of the second layer is higher than that of the first layer.

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