Bonding method for semiconductor wafer and semiconductor structure thereof

Abstract

The application relates to a bonding preparation method of a semiconductor wafer and a semiconductor structure thereof. The preparation method comprises the following steps: providing a logic wafer and a storage wafer, the logic wafer and the storage wafer are formed with mirror-distributed metal bonding pads, the two wafers are polished respectively to form planarization interfaces, and hexagonal boron nitride films are integrally grown on the two wafers respectively through chemical vapor deposition; on the hexagonal boron nitride film, a windowing treatment is performed on a region corresponding to the metal bonding pad, the hexagonal boron nitride film in the region is removed to expose the underlying metal bonding pad; graphene is filled in the windowing region, so that the graphene directly covers the metal bonding pad to form a van der Waals ohmic contact; the graphene regions of the two wafers are accurately aligned, and bonding is realized through the van der Waals force between the hexagonal boron nitride layers and the graphene layers. The wafer-level permanent bonding under normal temperature and pressure is realized, the wafer has reverse reworkability after bonding, and the electrical function and the thermal management function are coordinated.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular to a method for bonding and fabricating a semiconductor wafer and its semiconductor structure. Background Technology

[0002] In the rapid evolution of advanced logic processes, a severe deep process incompatibility problem has emerged between traditional embedded flash memory (eFlash) technology and advanced logic processes, becoming a core bottleneck restricting the application of advanced processes in the field of memory and logic integrated chips. For example, in traditional monolithic integration solutions, logic devices and eFlash devices need to be manufactured on the same wafer. This means that the high-voltage process required for eFlash can cause irreversible damage to advanced logic transistors. At the same time, in order to be compatible with two different processes, additional photomasks are needed, and process parameters need to be adjusted multiple times, which leads to a significant increase in manufacturing costs. This greatly limits the application of advanced logic processes in fields requiring non-volatile memory, causing a large number of IoT and automotive electronic chips to be unable to upgrade to advanced process nodes and to remain on mature older nodes, unable to enjoy the performance and power consumption improvements brought by advanced processes.

[0003] On the other hand, existing wafer-level bonding technologies, such as the currently mainstream copper-copper hot-press bonding and dielectric fusion bonding, have serious defects and cannot meet the needs of advanced heterogeneous integration, nor can they fully leverage the advantages of three-dimensional heterogeneous integration. Summary of the Invention

[0004] Therefore, it is necessary to propose a bonding preparation method for semiconductor wafers and its semiconductor structure to address the aforementioned technical problems.

[0005] In a first aspect, the present invention provides a method for bonding and fabricating a semiconductor wafer, comprising the following steps: A logic wafer and a memory wafer are provided, both of which have mirror-distributed metal bonding pads. The two wafers are polished to form a planarized interface. On the planarized interface of the two wafers, hexagonal boron nitride thin films were grown in an integral layer by chemical vapor deposition. On the hexagonal boron nitride film, a windowing process is performed in the area corresponding to the metal bonding pads, and the hexagonal boron nitride film in that area is removed to expose the underlying metal bonding pads; Graphene is filled into the windowed area so that it directly covers the metal bonding pads to form a van der Waals contact. The graphene regions of the two wafers are precisely aligned and bonded by van der Waals forces between the hexagonal boron nitride layers and the graphene layers.

[0006] Furthermore, the step of filling the windowed area with graphene, so that the graphene directly covers the metal bonding pads to form a van der Waals contact, includes: Graphene is filled into the windowed area by selective chemical vapor deposition or dry transfer combined with patterning process; Make the upper surface of the graphene flush with the upper surface of the surrounding hexagonal boron nitride film; The graphene is applied over the metal bonding pads to form a van der Waals contact.

[0007] Furthermore, the precise alignment of the graphene regions on the two wafers, achieved through van der Waals forces between the hexagonal boron nitride layers and between the graphene layers, includes: Argon plasma cleaning was performed on the bonding surfaces of the two wafers. In a vacuum environment, uniform pressure is applied to two wafers for alignment and bonding, so that the graphene regions of the two wafers are precisely aligned. Wafer-level bonding is achieved through van der Waals forces between hexagonal boron nitride thin film layers and between graphene layers, forming a van der Waals bonding interface.

[0008] Furthermore, the room temperature in the vacuum environment is 15℃-30℃, and the pressure is... The uniform pressure applied to the two wafers is 0.5MPa-5MPa.

[0009] Furthermore, the method for bonding and fabricating the semiconductor wafer further includes: After bonding is completed, an array of edge-through silicon vias is fabricated that penetrates the upper logic wafer to enable electrical interconnection between the logic wafer and the memory wafer.

[0010] Furthermore, bonding is achieved through van der Waals forces between hexagonal boron nitride layers and between graphene layers, resulting in a graphene electrode-hexagonal boron nitride dielectric structure in the metal bonding pad region.

[0011] Furthermore, the thickness of the hexagonal boron nitride thin film grown by chemical vapor deposition is 1-3 nm.

[0012] Furthermore, the bonding between the logic wafer and the memory wafer can also be achieved through... Graphene patterned conductive bonding; Alternatively, hexagonal boron nitride insulating bonding combined with edge silicon through-hole array bonding; Or graphene and / or hexagonal boron nitride capacitive coupling bonding.

[0013] Furthermore, when a bonding defect is detected between the logic wafer and the storage wafer, a separation driving force is applied to the bonding interface to overcome the interlayer van der Waals forces, thereby achieving non-destructive separation of the two wafers, which can then be rebonded.

[0014] On the other hand, the present invention also provides a semiconductor structure based on a wafer bonding fabrication method, wherein the semiconductor structure is fabricated by the above-described fabrication method and includes: The logic wafer and the memory wafer have mirror-distributed metal bonding pads on their surfaces, and each wafer has a planarized interface formed after polishing. The planarized interface has a hexagonal boron nitride film grown in an integral layer by chemical vapor deposition. A windowed groove is provided on the hexagonal boron nitride film in the area corresponding to the metal bonding pads. The windowed groove removes the hexagonal boron nitride film and exposes the underlying metal bonding pads. The windowed groove is formed with graphene, which directly covers the metal bonding pad to form a van der Waals contact. The graphene regions of the logic wafer and the storage wafer are arranged correspondingly to each other, and the logic wafer and the storage wafer are bonded together by interlayer bonding of hexagonal boron nitride and interlayer bonding of graphene.

[0015] The above-mentioned bonding fabrication method for semiconductor wafers and its semiconductor structure achieve the following beneficial effects: 1. This invention independently manufactures logic wafers and eFlash memory wafers at their respective optimal process nodes, and then achieves three-dimensional stacking through van der Waals bonding. This completely avoids the damage to advanced logic transistors and eFlash devices caused by high-voltage processes in traditional monolithic integration solutions, while also avoiding additional photomask costs and ensuring full compatibility with existing logic and memory processes. Furthermore, the entire bonding process is completed at room temperature, avoiding the impurity diffusion problem in ultra-shallow junctions of the logic wafer caused by high temperatures, and the threshold voltage drift of the transistors is negligible. Simultaneously, for the eFlash memory wafer, it avoids floating gate charge escape caused by high temperatures, and the defects in the tunneling oxide layer are not increased.

[0016] 2. The bonding interface of the present invention achieves vertical conductive ohmic contact in the graphene region through the combination of h-BN (Hexagonal Boron Nitride) and graphene, with a contact resistance lower than that of traditional copper-copper bonding. This enables the bonding interface to achieve rapid heat equalization in the lateral direction while achieving effective heat insulation in the vertical direction, separating the heat of the logic wafer from that of the eFlash wafer and protecting the eFlash memory cell from the heat of the logic chip.

[0017] 3. The bonding interface in this invention eliminates the dangling bond charge traps and interface state defects present in traditional bonding. The electrical noise at the interface is reduced by more than an order of magnitude, meeting the requirements for permanent bonding and significantly improving signal transmission reliability. Furthermore, van der Waals bonding is based on the van der Waals forces between two-dimensional material layers. This bonding force is reversible. If bonding defects are detected after bonding is complete, a separation driving force can be applied to the interface to separate the two wafers without damage, allowing for rebonding. This solves the problem of discarding wafers upon bonding failure in existing technologies, greatly enhancing product competitiveness.

[0018] 4. The entire process of this invention uses existing mature processes. The growth of two-dimensional materials can use existing CVD (Chemical Vapor Deposition) processes, and bonding uses standard commercial wafer bonding machines. The entire process is fully compatible with existing CMOS (Complementary Metal Oxide Semiconductor) production lines and can be directly applied without large-scale modifications to existing production lines, making it very suitable for large-scale mass production. Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of a semiconductor wafer bonding fabrication method in one embodiment; Figure 2 This is a schematic diagram of the structure of a logic wafer provided in a bonding fabrication method for semiconductor wafers in one embodiment; Figure 3 This is a schematic diagram of the structure of a storage wafer provided in a bonding fabrication method for a semiconductor wafer in one embodiment; Figure 4 This is a schematic flowchart of a semiconductor wafer bonding fabrication method in one embodiment; Figure 5 This is a schematic flowchart of a semiconductor wafer bonding fabrication method in one embodiment; Figure 6 This is a schematic diagram of a semiconductor structure based on a wafer bonding fabrication method in one embodiment; Figure 7 This is a schematic diagram of a semiconductor structure prepared using graphene patterned conductive bonding in another embodiment; Figure 8 This is a schematic diagram of a semiconductor structure fabricated using a hexagonal boron nitride insulating bonding array with an edge silicon via array in another embodiment; Figure 9 This is a schematic diagram of a semiconductor structure prepared using a capacitive coupling bonding method in another embodiment. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Example 1

[0021] In one embodiment, such as Figure 1 As shown, a van der Waals bonding technology based on two-dimensional materials is proposed. Through a novel process, it overcomes many shortcomings of traditional technologies, achieving efficient heterogeneous integration of advanced logic and memory. The technical solution of this application will be comprehensively described below through detailed embodiments. This embodiment is applicable to most scenarios of advanced logic and eFlash integration; the specific fabrication process is as follows: S1: Provide a logic wafer 101 and a memory wafer 201, both of which have mirror-distributed metal bonding pads 102. Polish the two wafers to form a planarized interface 103. S2: On the planarized interface 103 of the two wafers, a hexagonal boron nitride thin film 104 is grown in an integral layer by chemical vapor deposition. S3: On the hexagonal boron nitride film 104, a windowing process is performed in the area corresponding to the metal bonding pad 102, and the hexagonal boron nitride film 104 in this area is removed to expose the underlying metal bonding pad 102. S4: Graphene 105 is filled into the windowed area so that the graphene 105 directly covers the metal bonding pad 102 to form a van der Waals contact. S5: Precisely align the graphene 105 regions of the two wafers, achieving bonding through van der Waals forces between the hexagonal boron nitride layers and between the graphene 105 layers.

[0022] Specifically, in step S1, wafer preparation and planarization are first performed. For example... Figure 2 and Figure 3 As shown, two wafers that have completed front-end fabrication are selected, among which... Figure 2 One wafer is logic wafer 101, which has completed all front-end logic device manufacturing processes and is capable of realizing the expected logic operation functions; the other wafer... Figure 3The storage wafer 201 enables stable data storage. During the front-end manufacturing stage of the two wafers, mirror-distributed metal bonding pads 102 are pre-fabricated. These metal bonding pads (also called pads / bond points) are the metal contact areas on the surface of the die, serving as the sole electrical and mechanical interface between the internal circuitry and external packaging / testing. The positions of these bonding pads are precisely designed to ensure accurate alignment of the bonding pads on the two wafers after bonding, providing the basic structural conditions for electrical interconnection between the two wafers and ensuring effective signal and power transmission between them. After wafer preparation, the surfaces of the two wafers to be bonded are planarized using a mature planarization process to remove surface damage layers, achieving atomic-level planarization and providing suitable surface conditions for subsequent van der Waals bonding. Since van der Waals bonding requires a high degree of contact at the interface, a smooth surface can effectively avoid poor contact caused by local unevenness, thereby ensuring the quality of subsequent bonding and avoiding bonding failure due to surface problems.

[0023] By employing this step-by-step manufacturing and subsequent bonding method, this embodiment independently manufactures the logic wafer 101 and the memory wafer 201 on their respective optimal process nodes. Then, three-dimensional stacking is achieved through van der Waals bonding. This completely avoids the damage to advanced logic transistors and memory devices caused by high-voltage processes in traditional monolithic integration solutions. It also avoids additional photomask costs, is fully compatible with existing logic and memory processes, and solves the deep mutual exclusion problem between the two types of processes. This allows chips in fields such as IoT and automotive electronics, which were previously unable to be upgraded due to process compatibility issues, to smoothly adopt advanced process nodes and enjoy the performance and power consumption improvements brought by advanced processes. It breaks the limitations of traditional processes and opens up a new feasible path for heterogeneous integration.

[0024] In this embodiment, after the wafer planarization process is completed, step S2 is performed to grow a hexagonal boron nitride thin film 104. Specifically, two wafers are fed into a chemical vapor deposition apparatus, and a hexagonal boron nitride thin film 104 is grown integrally on the planarized interface 103 of the two wafers, with a thickness of 1-3 nm. As a two-dimensional material similar to graphene 105, hexagonal boron nitride has an atomically flat surface and no dangling bonds. This means that the subsequent bonding interface does not have dangling bond charge traps and interface state defects found in traditional bonding, effectively reducing the electrical noise at the interface, meeting the requirements for permanent bonding, and significantly improving the reliability of signal transmission. The whole-layer growth process can ensure the uniformity of film thickness across the entire wafer, providing a foundation for subsequent uniform bonding. Moreover, this growth process uses existing mature chemical vapor deposition technology, which is fully compatible with existing CMOS production lines. It can be applied directly without large-scale modifications to existing production lines, making it very suitable for large-scale mass production. This can help companies quickly implement the technology without investing a lot of money in production line modifications, allowing them to apply the technical solution of this application to their existing production processes.

[0025] In this embodiment, after the growth of the hexagonal boron nitride thin film 104 is completed, a windowing process is performed on the hexagonal boron nitride layer. A window is made in the area corresponding to the metal bonding pad 102 on the grown hexagonal boron nitride thin film 104, and the hexagonal boron nitride thin film 104 in this area is removed to expose the underlying metal bonding pad 102, preparing for subsequent conductive interconnection. Since hexagonal boron nitride is an insulating material, the windowing process enables electrical interconnection between two wafers. After the windowing process, an etching process is used to etch the exposed hexagonal boron nitride film 104, completely removing the corresponding area of ​​the hexagonal boron nitride film 104 and exposing the underlying metal bonding pads 102. The entire etching process has a high selectivity, causing no damage to the underlying metal bonding pads 102 or the surrounding hexagonal boron nitride film 104, ensuring the integrity of the windowed area and protecting the surrounding insulating film, ensuring that the performance of the insulating area is not affected. This completes the windowing process, preparing for the subsequent graphene 105 filling. Next, graphene 105 is filled into the windowed area to achieve conductive interconnection. In this embodiment, selective chemical vapor deposition or dry transfer combined with patterning is used to fill the graphene 105. Both processes can achieve the same effect, and those skilled in the art can choose according to actual production needs.

[0026] Specifically, firstly, high-quality graphene 105 is grown on a substrate. Then, the graphene 105 is transferred to the surface of the wafer, covering the entire wafer. Next, the graphene 105 in the non-windowed areas is removed, leaving only the graphene 105 in the windowed areas. Then, the wafer surface is slightly planarized, polishing the upper surface of the graphene 105 to be flush with the upper surface of the surrounding hexagonal boron nitride film 104, ensuring the flatness of the entire bonding surface and eliminating height differences, guaranteeing effective bonding in all areas simultaneously. After filling, the graphene 105 directly covers the metal bonding pads 102, forming a van der Waals contact. This contact achieves very low contact resistance without high-temperature annealing, offering superior contact performance compared to traditional copper-copper bonding. It also further reduces the overall thermal budget of the process, avoiding thermal damage to the device from high temperatures. By combining hexagonal boron nitride and graphene 105, the bonding interface of this application can achieve rapid heat dissipation in the lateral direction and effective heat insulation in the vertical direction, separating the heat of the logic wafer 101 from that of the storage wafer 201, protecting the storage cells from the heat of the logic chip, realizing the synergy of electrical functions and thermal management functions, and taking into account the dual needs of electrical interconnection and thermal management, solving the problem that traditional technologies cannot simultaneously meet these two needs.

[0027] In this embodiment, selective processing was used to achieve localized filling of graphene 105 while ensuring interface flatness, thus preparing the surface for bonding. After completing all surface preparation work, the next step is room-temperature van der Waals bonding. First, the bonding surfaces of the two wafers are cleaned with argon plasma. In this embodiment, plasma cleaning can prevent bonding failure or insufficient bonding strength. Simultaneously, plasma cleaning can activate van der Waals bonding sites on the surface, improving subsequent bonding strength and ensuring bonding reliability. After cleaning, the two wafers are fed into a commercial wafer bonding machine. High-precision alignment is performed to ensure accurate alignment of the graphene 105 regions on the two wafers, avoiding interconnect failures caused by alignment deviations. This ensures that the graphene 105 in each bonding pad area accurately corresponds, achieving effective electrical interconnection.

[0028] After alignment, uniform pressure is applied to both wafers under a vacuum environment at room temperature to maintain pressure and complete the bonding process. The room temperature under vacuum is 15℃-30℃, and the pressure is... The uniform pressure applied to the two wafers is 0.5MPa-5MPa. During the bonding process, the hexagonal boron nitride layers and the graphene 105 layers of the two wafers are bonded together by van der Waals forces, without any high-temperature annealing treatment, achieving permanent bonding. The bonding strength fully meets the requirements of subsequent packaging and processing, and there will be no detachment problem, ensuring the stability of the chip in subsequent processing. Since the entire bonding process is completed at room temperature, zero thermal budget bonding is achieved, completely protecting the two types of heat-sensitive devices and avoiding the problem of impurity diffusion in the ultra-shallow junction of the logic wafer 101 due to high temperature. At the same time, the room temperature bonding process allows the original performance of both types of devices to be completely preserved without being affected by the bonding process. This is one of the core advantages of this application compared with traditional bonding technology, completely solving the problem of excessively high thermal budget in traditional bonding technology and effectively protecting the performance of heat-sensitive devices. In this embodiment, through a reasonable bonding process, wafer-level bonding based on van der Waals forces is achieved, forming a stable van der Waals bonding interface 301.

[0029] This embodiment is based on the semiconductor structure prepared by the above method, such as... Figure 5 As shown, the structure specifically includes: a logic wafer 101 and a memory wafer 201. The surfaces of both wafers have mirror-distributed metal bonding pads 102, and both wafers are polished to form a planarization interface 103. A hexagonal boron nitride thin film 104 is integrally grown on the planarization interface 103. On the hexagonal boron nitride thin film 104, a window groove is provided corresponding to the area of ​​the metal bonding pad 102. This groove exposes the underlying metal bonding pad 102 by removing the corresponding area of ​​the hexagonal boron nitride thin film 104. Graphene 105 is formed within the window groove, directly covering the metal bonding pad 102 to form a van der Waals contact. The graphene 105 areas of the two wafers are correspondingly arranged, and bonding is achieved through the van der Waals forces between the hexagonal boron nitride layers and between the graphene 105 layers, combining the two wafers into a stable whole, forming a complete three-dimensional integrated structure.

[0030] Furthermore, the bonding process in this embodiment is reworkable. Since the van der Waals bonding provided in this embodiment is based on the van der Waals forces between two-dimensional material layers, this bonding force is reversible. After bonding is completed, the bonding interface is inspected using appropriate detection methods. If bonding defects are detected, a separation driving force can be applied to the bonding interface to overcome the van der Waals forces between layers, achieving non-destructive separation of the two wafers. The entire separation process is very gentle and will not cause any damage to the devices on the two wafers, nor will it affect the performance of the devices. After separation, the two wafers are cleaned to remove residual substances on the surface, and then plasma cleaning can be performed again to remove adsorbates on the surface. After that, alignment and bonding are performed again. The rebonding process is completely consistent with the first process. After rebonding, the bonding quality is completely consistent with normal bonding, with no difference, and can fully meet the requirements of use. This reworkable feature significantly improves product yield, reduces manufacturing costs, solves the problem of direct scrapping due to bonding failure in existing technologies, greatly enhances product competitiveness, effectively controls the cost of large-scale mass production, and improves the industrialization feasibility of this solution. Example 2

[0031] For low-cost applications, this embodiment can also employ a graphene patterned conductive bonding process, through which a semiconductor structure such as... Figure 7 As shown, the specific process flow is as follows: First, the logic wafer and memory wafer, which have completed front-end manufacturing, are prepared, with mirrored metal bonding pads reserved. Then, the two wafers are planarized to obtain atomically flat surfaces, consistent with the planarization steps in Example 1. Next, patterned graphene is fabricated on the surfaces of the two wafers, retaining graphene only in the corresponding areas of the metal bonding pads, while the graphene in the remaining areas is etched away, exposing the original wafer surface. The silicon dioxide passivation layer process eliminates the need for hexagonal boron nitride (BON) growth and windowing, simplifying the process and reducing manufacturing costs. After patterning, the bonding surfaces of the two wafers are plasma-cleaned. Then, under room temperature vacuum, uniform pressure is applied for alignment and bonding. During bonding, the graphene in the bonding pad areas achieves conductive bonding through van der Waals forces. The passivation layers bond to the insulating regions through direct contact, a very simple process that can be completed quickly. This technology simplifies the manufacturing process, reduces costs, and is suitable for cost-sensitive applications. Example 3

[0032] This embodiment can also employ a process of hexagonal boron nitride insulating bonding combined with an edge silicon via array, through which the semiconductor structure is as follows: Figure 8 As shown, the specific process flow is as follows: First, the logic wafer and memory wafer for front-end manufacturing are prepared. Both wafers are planarized, and then a hexagonal boron nitride (BN) thin film is grown uniformly on the surface of both wafers without any patterning. The entire surface of the wafer is covered with the BN film, providing excellent insulation properties for the entire interface. Next, the two wafers are plasma-cleaned. Then, under room temperature vacuum, uniform pressure is applied for bonding. The van der Waals forces between the BN layers achieve insulating bonding across the entire wafer. The entire interface is an insulating BN layer, possessing excellent insulation properties, capable of withstanding higher operating voltages, and avoiding leakage problems. After bonding is complete, an edge-mounted via array penetrating the upper logic wafer is fabricated. Specifically, the via regions are defined by photolithography, followed by deep silicon etching of the logic wafer. An insulating layer is then deposited to insulate the sidewalls of the vias, followed by filling with conductive material. Finally, planarization is performed to form the edge-mounted via array. These vias enable electrical interconnection between the logic wafer and the memory wafer. Since the vias are located at the edge of the wafer, they do not affect the central device areas or the core device areas. In this embodiment, the entire bonding interface is a monolayer of hexagonal boron nitride, possessing excellent insulation and thermal management properties. The vias, located at the edge, do not affect the central devices and maintain stable performance under high voltage conditions, meeting high reliability requirements. Example 4

[0033] This embodiment can also employ a capacitive coupling bonding process, through which the semiconductor structure is as follows: Figure 9 As shown, the specific process flow is as follows: First, the logic wafer and memory wafer, which have completed front-end manufacturing, are prepared, with mirrored metal bonding pads reserved. The two wafers are planarized, consistent with previous steps. Then, on the surface of the logic wafer, the corresponding area of ​​the bonding pads is patterned to fabricate a single-layer graphene electrode, while the graphene in the remaining areas is etched away. On the surface of the memory wafer, a hexagonal boron nitride thin film is grown in its entirety as a dielectric layer. The two wafers are then plasma-cleaned and aligned for bonding. After bonding, a MIM (Metal-Insulator-Metal) capacitor structure is formed in the area of ​​the bonding pads, consisting of a graphene electrode, a hexagonal boron nitride dielectric, and a metal electrode. This capacitor structure enables capacitive coupling communication between the two wafers. Simultaneously, the two wafers are DC isolated, enabling signal transmission between different power domains. This capacitively coupled interconnection method achieves high-speed signal transmission without DC contact, meeting the requirements of high-speed data transmission.

[0034] The aforementioned bonding methods correspond to different bonding schemes. The bonding between the logic wafer and the memory wafer in this application can be achieved by selecting different bonding methods according to different application requirements. These include graphene patterned conductive bonding, hexagonal boron nitride insulating bonding combined with edge silicon via array bonding, or graphene and / or hexagonal boron nitride capacitive coupling bonding. All of these methods can achieve effective bonding and are suitable for different application scenarios, making this solution more applicable and able to meet the requirements of customers in different fields and with different needs.

[0035] In all the above embodiments, the use of two-dimensional materials as bonding interfaces, with their atomically flat surfaces, significantly reduces electrical noise, meeting the requirements for permanent bonding and greatly improving signal transmission reliability. This ensures the long-term reliability of the device and enhances the overall performance and reliability of the chip. Furthermore, in all the above embodiments, the entire process utilizes existing mature technologies. The growth of the two-dimensional material can employ existing chemical vapor deposition processes, and bonding uses standard commercial wafer bonding machines. The entire process is fully compatible with existing CMOS production lines, requiring no large-scale modifications to existing lines. It is highly suitable for mass production, enabling rapid industrialization without requiring significant investment in production line upgrades. This allows companies to quickly apply the technology and upgrade their products.

[0036] It should be understood that although the steps in the above embodiments are described sequentially, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps described above may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0037] Those skilled in the art will understand that the structure of this application is merely a block diagram of a portion of the structure related to the solution of this application, and does not constitute a limitation on the device to which the solution of this application is applied. The specific device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0038] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0039] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for bonding and fabricating a semiconductor wafer, characterized in that, Includes the following steps: A logic wafer and a memory wafer are provided, both of which have mirror-distributed metal bonding pads. The two wafers are polished to form a planarized interface. On the planarized interface of the two wafers, hexagonal boron nitride thin films were grown in an integral layer by chemical vapor deposition. On the hexagonal boron nitride film, a windowing process is performed in the area corresponding to the metal bonding pads, and the hexagonal boron nitride film in that area is removed to expose the underlying metal bonding pads; Graphene is filled into the windowed area so that it directly covers the metal bonding pads to form a van der Waals contact. The graphene regions of the two wafers are precisely aligned and bonded by van der Waals forces between the hexagonal boron nitride layers and the graphene layers.

2. The bonding fabrication method for semiconductor wafers according to claim 1, characterized in that, The step of filling the windowed area with graphene, so that the graphene directly covers the metal bonding pads to form a van der Waals contact, includes: Graphene is filled into the windowed area by selective chemical vapor deposition or dry transfer combined with patterning process; Make the upper surface of the graphene flush with the upper surface of the surrounding hexagonal boron nitride film; The graphene is applied over the metal bonding pads to form a van der Waals contact.

3. The bonding fabrication method for semiconductor wafers according to claim 1, characterized in that, The precise alignment of the graphene regions on the two wafers, achieved through van der Waals forces between hexagonal boron nitride layers and between graphene layers, includes: Argon plasma cleaning was performed on the bonding surfaces of the two wafers. In a vacuum environment, uniform pressure is applied to two wafers for alignment and bonding, so that the graphene regions of the two wafers are precisely aligned. Wafer-level bonding is achieved through van der Waals forces between hexagonal boron nitride thin film layers and between graphene layers, forming a van der Waals bonding interface.

4. The bonding fabrication method for semiconductor wafers according to claim 3, characterized in that, The vacuum environment is characterized by a room temperature of 15℃-30℃ and a pressure of [missing information]. The uniform pressure applied to the two wafers is 0.5MPa-5MPa.

5. The bonding fabrication method for semiconductor wafers according to claim 1, characterized in that, Also includes: After bonding is completed, an array of edge-through silicon vias is fabricated that penetrates the upper logic wafer to enable electrical interconnection between the logic wafer and the memory wafer.

6. The bonding fabrication method for semiconductor wafers according to claim 4, characterized in that, Bonding is achieved through van der Waals forces between hexagonal boron nitride layers and between graphene layers, resulting in a graphene electrode-hexagonal boron nitride dielectric structure in the metal bonding pad region.

7. The bonding fabrication method for semiconductor wafers according to claim 1, characterized in that, The thickness of the hexagonal boron nitride thin film grown by chemical vapor deposition is 1-3 nm.

8. The bonding fabrication method for semiconductor wafers according to claim 1, characterized in that, The bonding between the logic wafer and the memory wafer can also be achieved through: Graphene patterned conductive bonding; Alternatively, hexagonal boron nitride insulating bonding combined with edge silicon through-hole array bonding; Or graphene and / or hexagonal boron nitride capacitive coupling bonding.

9. The bonding fabrication method for semiconductor wafers according to claim 1, characterized in that, When a bonding defect is detected between the logic wafer and the storage wafer, a separation driving force is applied to the bonding interface to overcome the interlayer van der Waals forces, thereby achieving non-destructive separation of the two wafers. After separation, they can be rebonded.

10. A semiconductor structure, characterized in that, include: The logic wafer and the memory wafer have mirror-distributed metal bonding pads on their surfaces, and each wafer has a planarized interface formed after polishing. The planarized interface has a hexagonal boron nitride film grown in an integral layer by chemical vapor deposition. A windowed groove is provided on the hexagonal boron nitride film in the area corresponding to the metal bonding pads. The windowed groove removes the hexagonal boron nitride film and exposes the underlying metal bonding pads. The windowed groove is formed with graphene, which directly covers the metal bonding pad to form a van der Waals contact. The graphene regions of the logic wafer and the storage wafer are arranged correspondingly to each other, and the logic wafer and the storage wafer are bonded together by interlayer bonding of hexagonal boron nitride and interlayer bonding of graphene.

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