A packaging structure based on a chiplet double-layer stacked chip and a preparation method thereof

Abstract

The application provides a packaging structure based on Chiplet double-layer stacked chips, which comprises a first chip unit and a second chip unit, the first chip unit comprises a first interconnection layer, a plurality of first chiplets connected to the first interconnection layer, and a medium layer arranged between adjacent first chiplets, and a vertical conductive structure is arranged in the medium layer; the second chip unit comprises a second substrate formed with a plurality of grooves, a second chiplet installed in each groove in one-to-one correspondence, and a second interconnection layer arranged above the second chiplet and the second substrate, and the first chiplet and the vertical conductive structure are bonded to the second interconnection layer. Horizontal interconnection in the two chip units is realized through the first interconnection layer and the second interconnection layer respectively, and vertical interconnection between the two units is realized through the bonding of the vertical conductive structure and the second interconnection layer. In the whole process, the chiplet itself does not need TSV, and the interconnection function is borne by the peripheral interconnection layer and the conductive structure, so that high-density three-dimensional integration is realized without modifying the chiplet.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a packaging structure and fabrication method based on a chiplet double-layer stacked chip. Background Technology

[0002] In the post-Moore's Law era, chiplet technology, as an emerging heterogeneous integration solution, significantly improves chip performance and flexibility by modularizing and interconnecting small chips with different functions. However, existing chiplet packaging technologies typically rely on interposers and through-silicon vias (TSV / TGV) processes to achieve chip-to-chip interconnection, which not only increases design complexity but also raises manufacturing costs. There is an urgent need for a novel chiplet packaging structure that can achieve high-density, low-latency, and reliable chip-to-chip interconnection without increasing process complexity, while simultaneously reducing packaging costs and improving overall performance. Summary of the Invention

[0003] The main objective of this invention is to provide a packaging structure based on a Chiplet double-layer stacked chip and its fabrication method, so as to solve the problems of low integration, low interconnect density, poor heat dissipation performance and complex fabrication process of the existing Chiplet packaging structure.

[0004] To achieve the above objectives, according to one aspect of the present invention, a packaging structure based on a chiplet dual-layer stacked chip is provided, comprising a first chip unit and a second chip unit. The first chip unit includes a first interconnect layer, a plurality of first chips connected to the first interconnect layer, and a dielectric layer connected between adjacent first chips, wherein a vertical conductive structure is disposed within the dielectric layer. The second chip unit includes a second substrate having a plurality of grooves, second chips mounted one-to-one within the grooves, and a second interconnect layer disposed above the second chips and the second substrate. The first chips and the vertical conductive structure are both bonded to the second interconnect layer.

[0005] Preferably, the second core is completely embedded in the groove of the second substrate, and the upper surface of the second core is flush with the upper surface of the second substrate.

[0006] Preferably, a bottom filler adhesive is provided between the second core and the sidewall and / or bottom wall of the groove.

[0007] Preferably, a first heat dissipation unit is connected above the first interconnect layer, and a second heat dissipation unit is connected to the outside of the first interconnect layer and the second interconnect layer, and the first heat dissipation unit and the second heat dissipation unit are connected together.

[0008] Preferably, the first heat dissipation unit and the second heat dissipation unit are metal heat sinks or microchannel heat sinks. Preferably, a thermal interface material layer is disposed between the second substrate and the second interconnect layer. A method for preparing the aforementioned packaging structure includes the following steps: A first interconnect layer is formed on a first substrate, and a plurality of first chips are connected on the first interconnect layer. A dielectric layer is formed between adjacent first chips, and a vertical conductive structure is disposed in the dielectric layer to form a first chip unit. A plurality of grooves are formed on the second substrate, and second chips are installed in the grooves one by one, and a second interconnect layer is formed on the second chips and the second substrate to form a second chip unit. Both the first chip and the vertical conductive structure are bonded to the second interconnect layer, thereby stacking and connecting the first chip unit and the second chip unit.

[0009] Preferably, the preparation method further includes removing the first substrate after bonding.

[0010] Preferably, the preparation method further includes: after removing the first substrate, forming a first heat dissipation unit above the first interconnect layer, forming a second heat dissipation unit outside the first interconnect layer and the second interconnect layer, and connecting the first heat dissipation unit and the second heat dissipation unit.

[0011] Preferably, the bonding connection is achieved using any one of thermo-press bonding, laser-assisted bonding, or hybrid bonding processes.

[0012] The present invention has the following beneficial effects: First, horizontal interconnections within two chip cells are achieved using a first interconnect layer and a second interconnect layer, respectively. Then, vertical interconnections between the two cells are achieved by bonding a vertical conductive structure to the second interconnect layer. Throughout this process, the chip itself does not require a TSV (Transient Viaduct), and the interconnection function is handled by the surrounding interconnect layers and conductive structures, thus achieving high-density three-dimensional integration without modifying the chip itself.

[0013] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0014] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 A schematic diagram of the structure after forming a first interconnect layer on a first substrate and connecting multiple first chips on the first interconnect layer in the method for fabricating a packaging structure based on a chiplet dual-layer stacked chip provided in the embodiments of the present invention. Figure 2 This is a schematic diagram of the structure after a dielectric layer is formed between adjacent first chips in the method for fabricating a packaging structure based on a Chiplet double-layer stacked chip provided in an embodiment of the present invention. Figure 3 The schematic diagram of the structure after the first chip unit is formed by setting a vertical conductive structure in the dielectric layer in the method for fabricating a packaging structure based on a chip double-layer stacked chip provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after the second chip unit is formed in the method for fabricating a packaging structure based on a Chiplet double-layer stacked chip provided in the embodiments of the present invention. Figure 5 In the method for fabricating a packaging structure based on a chiplet dual-layer stacked chip provided in the embodiments of the present invention, the first chiplet and the vertical conductive structure are both bonded to the second interconnect layer, thereby forming a schematic diagram of the structure after the first chip unit and the second chip unit are stacked and connected. Figure 6 A schematic diagram of the structure after removing the first substrate in the method for fabricating a packaging structure based on a Chiplet double-layer stacked chip provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure after forming the first heat dissipation unit and the second heat dissipation unit in the method for fabricating a packaging structure based on a Chiplet double-layer stacked chip provided in the embodiments of the present invention. Detailed Implementation

[0016] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0017] like Figure 6 As shown, the present invention provides a packaging structure based on a two-layer stacked chip, which includes a first chip unit and a second chip unit. The first chip unit and the second chip unit are stacked in the vertical direction.

[0018] The first chip unit includes a first interconnect layer 11, a plurality of first chips 2 connected to the first interconnect layer 11, and a dielectric layer 3 connected between adjacent first chips 2. A vertical conductive structure 4 is disposed within the dielectric layer 3. The first interconnect layer 11 is located above the first chips 2 and is used to realize horizontal interconnection between the plurality of first chips 2 and electrical connection between the first chips 2 and the outside.

[0019] The second chip unit includes a second substrate 5 with a plurality of grooves, second chips 6 mounted one-to-one in the grooves, and a second interconnect layer 7 disposed above the second chips 6 and the second substrate 5. The second substrate 5 serves as a carrier substrate and can be made of silicon, glass, or organic substrate material. The second chips 6 are mounted one-to-one in the grooves of the second substrate 5, and the second interconnect layer 7 is located above the second chips 6 and the second substrate 5 to enable electrical connection between the second chips 6 and the outside.

[0020] Both the first chip 2 and the vertical conductive structure 4 are bonded to the second interconnect layer 7. Through this bonding connection, the first chip unit and the second chip unit are stacked and assembled, while the first chip 2 is vertically interconnected with the second chip 6 through the vertical conductive structure 4 and the second interconnect layer 7.

[0021] In this embodiment, the second chip 6 is completely embedded in the groove of the second substrate 5, and the upper surface of the second chip 6 is flush with the upper surface of the second substrate 5. By completely embedding the second chip 6 in the groove and making its upper surface flush, a flat bonding surface can be obtained, which is beneficial for the formation of the second interconnect layer 7 and its bonding connection with the first chip unit. An underfill adhesive is provided between the second chip 6 and the sidewall and / or bottom wall of the groove. The underfill adhesive can effectively disperse thermal cycling stress and improve the reliability of the packaging structure.

[0022] In this embodiment, the first interconnect layer 11 includes at least one redistribution layer (RDL). The second interconnect layer 7 also includes at least one redistribution layer (RDL). The redistribution layer rearranges the positions of the aluminum / copper solder pads on the chip, so that the new solder pads meet the minimum spacing requirements for solder balls and are arranged in an array.

[0023] In this embodiment, the dielectric layer 3 is made of an organic polymer material, specifically photosensitive polyimide (PSPI). Photosensitive polyimide is widely used in wafer-level advanced packaging; both the passivation layer on the wafer surface and the redistribution layer for wafer signal routing require photosensitive insulating dielectric materials. Due to its superior mechanical and material properties, polyimide is the mainstream choice for advanced packaging companies. Polymer materials, with their lower dielectric constant and smaller loss tangent, can achieve lower transmission loss during high-speed signal transmission.

[0024] In this embodiment, the vertical conductive structure 4 includes conductive pillars penetrating the dielectric layer 3. The conductive pillars are made of copper, and the linewidth / spacing of the conductive pillars is 3μm / 3μm. The vertical conductive structure 4 is used to achieve a vertical electrical connection between the first interconnect layer 11 and the second interconnect layer 7.

[0025] In this embodiment, the first core 2 and the vertical conductive structure 4 are bonded to the second interconnect layer 7 via microbumps. Microbump bonding generally refers to a bonding method in which Cu / Sn microbumps prepared by electroplating are used as the connection medium, and electrical connections between cores are achieved through physical pressing or hot pressing.

[0026] In this embodiment, the first core 2 and the second core 6 are manufactured using different process nodes. The first core 2 is manufactured using an advanced process node to pursue high performance, while the second core 6 is manufactured using a mature process node to reduce costs.

[0027] like Figure 7 As shown, a first heat dissipation unit 81 is connected above the first interconnect layer 11, and a second heat dissipation unit 82 is connected to the outside of the first interconnect layer 11 and the second interconnect layer 7. The first heat dissipation unit 81 and the second heat dissipation unit 82 are connected together.

[0028] In this embodiment, the first heat dissipation unit 81 is a metal heat sink, disposed above the first interconnect layer 11, for dissipating heat generated by the first chip unit upwards. The second heat dissipation unit 82 is also a metal heat sink, disposed outside the first interconnect layer 11 and the second interconnect layer 7, for dissipating heat generated by the first chip unit and the second chip unit laterally. The first heat dissipation unit 81 and the second heat dissipation unit 82 are interconnected to form a continuous heat conduction path.

[0029] Through the synergistic effect of the first heat dissipation unit 81 and the second heat dissipation unit 82, a dual-path heat conduction architecture is formed—a heat conduction path that is simultaneously upward (in the direction of the first heat dissipation unit 81) and to the side (in the direction of the second heat dissipation unit 82). This can effectively prevent heat from accumulating between chip layers and solve the problem of heat being difficult to effectively dissipate in a double-layer stacked structure.

[0030] In this embodiment, the first heat dissipation unit 81 and the second heat dissipation unit 82 are formed at their respective positions by an adhesive bonding process. In other embodiments, the first heat dissipation unit 81 and the second heat dissipation unit 82 may also be formed by electroplating, electroless plating, or sputtering processes.

[0031] In this embodiment, a thermal interface material (TIM) layer is disposed between the second substrate 5 and the second interconnect layer 7. The TIM layer can reduce the contact thermal resistance between the second substrate 5 and the second interconnect layer 7 and improve the heat conduction efficiency. The TIM layer can be made of thermally conductive silicone grease, thermally conductive pads, or phase change materials, etc.

[0032] like Figure 1-7 As shown in the figure, this embodiment of the invention also provides a method for fabricating a packaging structure based on a Chiplet double-layer stacked chip, including the following steps: Step S1: Form the first chip unit.

[0033] A first substrate 1 is provided, and a first interconnect layer 11 is formed on the first substrate 1. The first interconnect layer 11 is fabricated using a wafer-level process and includes at least one redistribution layer (RDL). A plurality of first chips 2 are connected on the first interconnect layer 11. The first chips 2 can be connected to the first interconnect layer 11 by a flip-chip process or a pick-and-place process.

[0034] A dielectric layer 3 is formed between adjacent first core particles 2. The dielectric layer 3 is formed by spin coating or lamination process, and its material is an organic polymer material selected from any one of photosensitive polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO).

[0035] A vertical conductive structure 4 is formed within the dielectric layer 3. The vertical conductive structure 4 is fabricated using photolithography, etching, and electroplating processes. Specifically, a via pattern is first formed in the dielectric layer 3 by photolithography, then the vias are formed by etching, and finally, the vias are filled with copper by electroplating to form conductive pillars. The vertical conductive structure 4 and the first interconnect layer 11 are fabricated using wafer-level processes.

[0036] Step S2: Form the second chip unit.

[0037] A second substrate 5 is provided, on which a plurality of grooves are formed. The grooves can be formed by means of etching, machining, or laser processing. The depth of the grooves matches the thickness of the second core 6.

[0038] The second core 6 is installed in the groove in a one-to-one correspondence. The second core 6 is installed in the groove by a flip-chip process or a pick-and-place process. The second core 6 is completely embedded in the groove, and the upper surface of the second core 6 is flush with the upper surface of the second substrate 5. Bottom filler is filled between the second core 6 and the sidewalls and / or bottom walls of the groove to disperse thermal cycling stress.

[0039] A second interconnect layer 7 is formed above the second core 6 and the second substrate 5. The second interconnect layer 7 is fabricated using a wafer-level process and includes at least one redistribution layer (RDL).

[0040] Step S3: Bonding connection.

[0041] Both the first chip 2 and the vertical conductive structure 4 are bonded to the second interconnect layer 7, thereby stacking the first chip unit and the second chip unit. The bonding connection adopts any one of the following processes: thermoforming, laser-assisted bonding, or hybrid bonding.

[0042] After bonding, the first substrate 1 is removed. The first substrate 1 can be removed by mechanical peeling, chemical peeling, or laser debonding.

[0043] Step S4: Form a heat dissipation structure.

[0044] After removing the first substrate 1, a first heat dissipation unit 81 is formed above the first interconnect layer 11, and a second heat dissipation unit 82 is formed outside the first interconnect layer 11 and the second interconnect layer 7, and the first heat dissipation unit 81 and the second heat dissipation unit 82 are connected together. The first heat dissipation unit 81 and the second heat dissipation unit 82 are formed by electroplating, chemical plating, sputtering or bonding processes. The first heat dissipation unit 81 and the second heat dissipation unit 82 are metal heat sinks or microchannel heat sinks. The present invention provides a chiplet-based dual-layer stacked chip packaging structure and its fabrication method. First, multiple first chips are horizontally interconnected through RDL wiring in a first interconnect layer to form a first chip unit. Second chips are then embedded in grooves in a second substrate and covered with a second interconnect layer to form a second chip unit. Then, by bonding the first chips and the vertical conductive structures in the dielectric layer to the second interconnect layer, the two units are stacked and assembled to establish a vertical signal transmission channel. This ultimately achieves high-density interconnection in both the horizontal direction (RDL wiring within each unit) and the vertical direction (bonding of the vertical conductive structures to the second interconnect layer). This achieves the following beneficial effects: High integration: By stacking the first chip unit and the second chip unit, multiple first chips in the first chip unit are horizontally interconnected through the first interconnect layer, and the first chip unit and the second chip unit are vertically interconnected through the vertical conductive structure and the second interconnect layer, achieving high-density integration of chips in both horizontal and vertical dimensions.

[0045] High interconnect density: The first and second interconnect layers adopt redistribution layers (RDL), with line width / spacing up to 3μm / 3μm. The line width / spacing of the vertical conductive structure can also reach 3μm / 3μm, achieving high-density interconnection.

[0046] Excellent heat dissipation performance: Through the synergistic effect of the first and second heat dissipation units, a dual-path heat conduction architecture is formed, which can effectively solve the problem of heat accumulation in the double-layer stacked structure.

[0047] The fabrication process is simple: the first and second chip units can be fabricated independently before bonding and assembling, resulting in a clear process flow suitable for mass production. The vertical conductive structure and interconnect layer are fabricated using wafer-level processes, achieving high production efficiency and precision.

[0048] Good compatibility: No need to modify existing TSV-free chips, suitable for existing chip mass production systems.

[0049] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A packaging structure based on a chipplet double-layer stacked chip, characterized in that, The first chip unit includes a first interconnect layer (11), a plurality of first chips (2) connected to the first interconnect layer (11), and a dielectric layer (3) connected between adjacent first chips (2). A vertical conductive structure (4) is provided in the dielectric layer (3). The second chip unit includes a second substrate (5) with a plurality of grooves, second chips (6) installed in the grooves one by one, and a second interconnect layer (7) disposed above the second chips (6) and the second substrate (5). The first chips (2) and the vertical conductive structure (4) are both bonded to the second interconnect layer (7).

2. The packaging structure according to claim 1, characterized in that, The second core (6) is completely embedded in the groove of the second substrate (5), and the upper surface of the second core (6) is flush with the upper surface of the second substrate (5).

3. The packaging structure according to claim 1, characterized in that, A bottom filler is provided between the second core (6) and the sidewall and / or bottom wall of the groove.

4. The packaging structure according to claim 1, characterized in that, A first heat dissipation unit (81) is connected above the first interconnect layer (11), and a second heat dissipation unit (82) is connected to the outside of the first interconnect layer (11) and the second interconnect layer (7). The first heat dissipation unit (81) and the second heat dissipation unit (82) are connected together.

5. The packaging structure according to claim 4, characterized in that, The first heat dissipation unit (81) and the second heat dissipation unit (82) are metal heat sinks or microchannel heat sinks.

6. The packaging structure according to claim 1, characterized in that, A thermal interface material layer is disposed between the second substrate (5) and the second interconnect layer (7).

7. A method for preparing a packaging structure according to any one of claims 1-6, characterized in that, Includes the following steps: A first interconnect layer (11) is formed on a first substrate (1), and a plurality of first chips (2) are connected on the first interconnect layer (11). A dielectric layer (3) is formed between adjacent first chips (2), and a vertical conductive structure (4) is provided in the dielectric layer (3) to form a first chip unit. A plurality of grooves are formed on the second substrate (5), and a second chip (6) is installed in each groove in a corresponding manner. A second interconnect layer (7) is formed on the second chip (6) and the second substrate (5) to form a second chip unit. The first chip (2) and the vertical conductive structure (4) are both bonded to the second interconnect layer (7), thereby stacking the first chip unit and the second chip unit.

8. The preparation method according to claim 7, characterized in that, The preparation method further includes: removing the first substrate (1) after bonding.

9. The preparation method according to claim 8, characterized in that, The preparation method further includes: after removing the first substrate (1), forming a first heat dissipation unit (81) above the first interconnect layer (11), forming a second heat dissipation unit (82) on the outside of the first interconnect layer (11) and the second interconnect layer (7), and connecting the first heat dissipation unit (81) and the second heat dissipation unit (82).

10. The preparation method according to claim 7, characterized in that, The bonding connection is achieved using any one of the following processes: thermo-press bonding, laser-assisted bonding, or hybrid bonding.

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