An integrated chip of a computing power perception system integrated power supply and a packaging method thereof

Abstract

The application relates to the technical field of unmanned system integration, and particularly relates to an integrated chip of a computing power sensing system integrated power supply and a packaging method thereof. The chip comprises a power supply integrated layer and a computing power sensing layer which are vertically stacked from top to bottom. The power supply units are arranged on the front surface of the power supply integrated layer. The power supply signals output by the power supply units are connected and led out from the back surface of the power supply integrated layer through magnetic beads, so as to realize electrical connection between the power supply units and the chips of the computing power sensing layer and structural support between the layers. The computing chips and the interface chips are arranged on the front surface of the computing power sensing layer. The first power supply grooves which are matched with the magnetic beads and are electrically connected with the chips on the front surface of the computing power sensing layer are arranged on the front surface of the computing power sensing layer. The digital signals are connected between the chips of the computing power sensing layer. The deep integration and performance leap of the core functions of sensing, computing and electricity are realized in the single chip packaging body, and the requirements of an unmanned system on extreme integration, energy efficiency and reliability are met.

Description

Technical Field

[0001] This invention relates to the field of unmanned system integration technology, specifically to an integrated chip for a computing power sensing system power supply and its packaging method. Background Technology

[0002] In unmanned systems (including drones, unmanned dogs, unmanned vehicles, etc.), the most core hardware component is the computing chip. The computing chip and the perception chip together constitute the "computing power perception system", which serves as the foundation for the unmanned system to achieve autonomous control and environmental perception.

[0003] Currently, the computing power and sensing systems of existing unmanned systems mainly rely on two technical approaches: one is to integrate multiple independently packaged finished chips on a PCB board, and the other is to integrate a limited number of chips using SiP packaging technology. In the PCB board integration approach, chips with different functions such as sensing, computing, and power management are assembled like... Figure 1 Generally, chips are soldered separately onto the motherboard plane, forming a two-dimensional board-level system. More integrated SiP (System-in-Package) solutions typically integrate a few functionally similar chips (such as a central processing unit and its associated memory) into a single package, forming a relatively specialized composite chip module. However, both mainstream implementations face a series of profound and interconnected technical limitations, severely restricting the development of unmanned systems towards miniaturization, efficiency, and reliability. The most obvious drawback is the difficulty in further reducing the overall size of unmanned system products: PCB solutions require several millimeters of spacing between chips to ensure wiring and heat dissipation, resulting in module sizes often exceeding ten millimeters; while SiP solutions, limited to homogeneous chip integration, have very limited effect on compressing the final system-level size. Deeper technical problems are rooted in the existing hardware architecture of unmanned systems:

[0004] 1. In terms of physical layout, in existing unmanned systems or traditional SIP packaging solutions, the power management unit is usually divided into multiple discrete modules and distributed around different functional loads such as the main control chip. This dispersion not only directly occupies a large amount of valuable PCB area, which seriously restricts the further miniaturization of the overall system size, but also introduces significant parasitic resistance and inductance due to the increased power supply path and the long traces between the computing chip and high-speed memory and various peripheral interfaces. This results in increased power supply ripple and slower dynamic response, making it difficult to meet the computing chip's stringent requirements for "high stability and low noise" power supply. In particular, it is prone to voltage drops when dynamic load changes, affecting computing stability.

[0005] 2. In terms of thermal management, the heat generated by each power supply unit is dispersed, resulting in multiple heat sources. Especially when the power supply unit is located close to high-power units such as the main control chip, heat can easily couple and accumulate in space, forming localized high-temperature "hot spots," which directly affects chip performance and long-term system reliability. At the same time, the dispersed heat sources also complicate the system-level heat dissipation design.

[0006] 3. Regarding electromagnetic interference management, long power supply lines act like antennas, easily radiating and receiving noise. High-frequency switching noise generated by the power supply unit may interfere with nearby sensitive high-speed digital signals through spatial or conductive coupling. To suppress this interference, existing technologies often require additional filtering circuits and shielding measures, further increasing the design complexity and cost of the computing power sensing system.

[0007] 4. Traditional SIP technology uses ball-and-grid (BGA) interconnection between layers. When carrying the high current of tens of watts of various chips in unmanned systems, its current carrying capacity and mechanical strength face challenges, becoming one of the bottlenecks of high power density integration solutions.

[0008] Therefore, existing technical solutions have multiple intertwined technical defects in terms of space utilization, heat dissipation management, electromagnetic compatibility, heterogeneous chip integration, signal performance and mechanical load-bearing capacity, making it difficult to meet the requirements of next-generation unmanned systems for extreme integration, energy efficiency and reliability. Summary of the Invention

[0009] To address the aforementioned technical issues, this invention proposes an integrated chip for a computing power sensing system and its packaging method. The aim is to achieve deep integration and performance leap of the core functions of "sensing, computing, and power" of unmanned systems within a single chip package, meeting the requirements of unmanned systems for ultimate integration, energy efficiency, and reliability.

[0010] In a first aspect, this application provides an integrated chip for a computing power sensing system integrated power supply, including a power integration layer and a computing power sensing layer that are vertically stacked and packaged from top to bottom.

[0011] The front side of the power integration layer is equipped with several power supply units for powering each chip in the computing power sensing layer. The power signals output by each power supply unit are merged and connected, and then led out from the back side of the power integration layer using ferrite beads to realize the electrical connection between the power supply units and each chip in the computing power sensing layer, as well as the interlayer structural support.

[0012] The front of the computing power sensing layer is integrated with chips for performing computing tasks and interface chips. A first power supply groove is provided on the front of the computing power sensing layer. The first power supply groove is matched with the magnetic bead and electrically connected to each chip on the front of the computing power sensing layer to receive power from the power supply integration layer. The chips of the computing power sensing layer are interconnected by digital signals. Solder balls are provided on the back of the computing power sensing layer.

[0013] In some embodiments, the power integration layer further includes a first substrate. The first substrate adopts a multi-layer design. Each layer inside the first substrate is formed into a power trace layer with different voltages using a large-area copper pouring process. The output pins of each power unit are respectively connected to the corresponding power trace layer inside the first substrate. Each power trace layer is connected to a set of ferrite beads. Each ferrite bead serves as a noise suppression channel for vertical transmission of a large current.

[0014] In some embodiments, a second power supply groove is formed on the back side of the first substrate. The second power supply groove is provided with electrical connection points and is respectively connected to each power supply trace layer. One end of the ferrite bead is partially embedded in the second power supply groove to realize the electrical connection between the ferrite bead and each power supply unit.

[0015] In some embodiments, the computing power sensing layer further includes a second substrate, a first power groove is disposed on the front side of the second substrate, and a plurality of first power grooves are provided with electrical connection points and are respectively electrically connected to each chip of the computing power sensing layer, so as to realize that the power supply current of the power integration layer flows into each chip of the computing power sensing layer through the magnetic bead and the first power grooves provided with electrical connection points.

[0016] In some embodiments, the second substrate adopts a multilayer design, with each layer inside the second substrate forming a signal routing layer and power routing layers of different voltages, and each layer inside the second substrate adopts a stacked structure to ensure that the adjacent layers of each signal routing layer have a complete ground plane or power plane.

[0017] In some embodiments, the signal routing layer of the second substrate preferentially routes high-speed signal lines to ensure that the outgoing path of the high-speed signal lines is the shortest.

[0018] In some embodiments, the power integration layer is encapsulated using a molding process, and a heat sink is embedded in the top of the power integration layer to achieve centralized heat dissipation of the power unit.

[0019] In some embodiments, the magnetic beads are distributed on the four sides of the back of the power integration layer.

[0020] Secondly, this application provides a packaging method for an integrated chip for a computing power sensing system power supply, comprising the following steps:

[0021] S1, power integration layer package:

[0022] Power trace layers with different voltages are formed inside the first substrate, and a second power groove matching the ferrite bead is formed on the back of the first substrate to connect to the power supply.

[0023] The power unit is mounted on the front side of the first substrate using a flip-chip bonding process and then cured.

[0024] The output pins of each power unit are electrically connected to the corresponding power trace layer inside the first substrate using a gold wire bonding process.

[0025] Vacuum encapsulation is performed on the first substrate and the power supply unit to form an encapsulation on the front side of the first substrate;

[0026] Solder paste is applied to the second power groove on the back of the first substrate, and a magnetic bead is partially embedded.

[0027] Perform reflow soldering to ensure the magnetic beads are firmly soldered, and clean the first substrate.

[0028] A damming and self-leveling process is used to inject a base filler around the magnetic beads to form a magnetic bead fixing layer, which is then cured to form a power integrated layer with exposed magnetic beads.

[0029] S2, Computational Power Awareness Layer Encapsulation:

[0030] Signal trace layers and power trace layers of different voltages are formed inside the second substrate, and each layer inside the second substrate adopts a stacked structure to ensure that the adjacent layers of each signal trace layer have a complete ground plane or power plane. A first power groove matching the ferrite bead is opened on the front side of the first substrate to connect the power supply.

[0031] A chip for performing computing tasks is mounted on the front side of the second substrate using a flip-chip bonding process;

[0032] Perform reflow soldering to ensure a strong weld, and clean the second substrate.

[0033] The chip on the front side of the second substrate is filled with adhesive and then cured by heating.

[0034] The interface chip is mounted on the front side of the second substrate using conductive adhesive and then cured.

[0035] The output pins of each chip on the front side of the second substrate are electrically connected to the corresponding signal and power trace layers inside the second substrate using a gold wire bonding process.

[0036] S3, an integrated chip package for the power integration layer and the computing power sensing layer:

[0037] Insert the exposed ferrite bead of the power integration layer into the first power groove on the front side of the second substrate.

[0038] Perform reflow soldering to ensure a strong weld.

[0039] The gap between the front of the computing power sensing layer and the back of the power integration layer is filled with adhesive and then heated and cured to form an integrated chip with two layers of encapsulation.

[0040] Solder balls are placed on the back of the computing power sensing layer to complete the packaging process.

[0041] In some embodiments, S1, the power integration layer package, further includes:

[0042] Before vacuum potting the power integration layer, a heat sink is embedded in the top of the power integration layer to achieve centralized heat dissipation of the power unit.

[0043] The beneficial technical effects of the present invention include at least the following:

[0044] 1. An integrated chip and packaging method for a computing power sensing system power supply are adopted. Through a systematic design with a two-layer vertical stacking architecture and ferrite beads as the core, the three functional units of power supply, computing power, and sensing are deeply coordinated and reconstructed from the physical layout to the electrical, thermal, and mechanical performance. This collaboratively overcomes the multiple technical bottlenecks in existing technologies, such as space utilization, heat dissipation management, electromagnetic compatibility, heterogeneous chip integration, signal performance, and mechanical load-bearing. Specifically, in terms of space utilization, all power supply units are integrated into an independent power integration layer and vertically stacked with the underlying computing power sensing layer. This completely eliminates the PCB area occupied by the dispersed layout of power modules in traditional solutions, compressing the system projection area to a minimum and achieving ultimate three-dimensional integration and miniaturization. In terms of electrical performance and electromagnetic compatibility, ferrite beads, as the key carrier of inter-layer interconnection, create the shortest vertical power supply path from the power supply unit to the computing power chip, greatly reducing parasitic parameters and ensuring high power supply stability and low noise. At the same time, as a distributed filter device built into the vertical power supply channel, ferrite beads can efficiently suppress the propagation of power switching noise to sensitive digital signals from the source, eliminating the complexity of external filtering and shielding. In terms of thermal management, the power supply unit is concentrated in an independent upper layer, spatially isolated from the computing power sensing layer. This avoids the formation of local hotspots due to the coupling of multiple heat sources, which is beneficial for the directional dissipation of heat and system-level heat dissipation design. Regarding heterogeneous chip integration and signal performance, computing and interface chips are centrally located within the computing power sensing layer and achieve high-speed digital signal exchange through short-distance interconnection. Power supply integration is moved to an independent layer, achieving spatial and electrical decoupling and coordination between analog power and digital signals, ensuring optimal performance for each. In terms of mechanical load-bearing capacity, columnar magnetic beads form a robust mechanical interlocking framework between layers. Their load-bearing capacity and bending resistance are far superior to traditional solder balls, effectively coping with thermal stress and vibration, ensuring structural reliability under high power density integration. Ultimately, this achieves multi-functional interconnection of electrical, thermal, and mechanical components, fundamentally reconstructing the computing power sensing system architecture and achieving synergistic optimization of performance across multiple dimensions, including spatial, electrical, thermal, and mechanical aspects.

[0045] 2. By employing a layered design for the power traces on the first substrate, physical isolation of different voltage networks is achieved, avoiding crosstalk. A large-area copper plating process is used to directly address high-power transmission requirements. Increasing the copper foil area reduces conductor resistance, which is crucial for ensuring the combined power quality (low ripple, low impedance) and current-carrying capacity. Simultaneously, ferrite beads replace traditional solder balls, providing a low-impedance, high-current path. This process internally completes the electrical "merging" of different power chips within the first substrate, "pooling" multiple discrete power outputs into several stable and powerful common power networks. Through collaborative and specialized design, extremely low power loss and voltage drop from the power integration layer to the lower load are ensured, significantly improving the current-carrying capacity and withstand voltage of the first substrate to meet high-power transmission requirements. This systematically solves multiple problems in existing technologies caused by dispersed power supplies, such as large space occupation, limited efficiency, and insufficient current carrying capacity and mechanical support. Together, they contribute to the synergistic benefits of miniaturization, robust power supply, and structural stability, providing a key power solution for chip-level integration of core modules in unmanned systems and improving overall energy efficiency.

[0046] 3. The integrated chip design of the power supply in the computing power sensing system achieves the ability to integrate heterogeneous chips such as computing power chips, high-speed memory chips, and various interface chips on the same layer of the computing power sensing layer while effectively overcoming electromagnetic interference and achieving stable and reliable high-speed signal transmission. Its core lies in the synergistic optimization of power integrity and signal integrity at the system level through a vertical stacking architecture and precise internal design. The design scheme of the computing power sensing layer substrate is not a simple stacking of layers, but rather actively constructs an electromagnetic environment conducive to high-speed signal transmission through a set of highly refined design principles based on electromagnetic field theory and signal integrity engineering. Specifically, firstly, the power integration layer uses vertical power supply via ferrite beads, eliminating key interference at both the "source" and "path." Ferrite beads not only minimize parasitic parameters in the power supply circuit, ensuring fast and stable dynamic response, but their series connection in each power supply also constitutes a distributed high-frequency noise filter, physically blocking the upward transmission of power switching noise to the computing power sensing layer. This provides an exceptionally "clean" common power source for various chips in the lower computing power sensing layer, fundamentally avoiding the conduction interference of power supply noise to different types of chips. Secondly, the computing power sensing layer itself adopts a precise stacked structure and wiring design to construct an internal barrier. Its multi-layer substrate provides a closely adjacent complete reference plane for high-speed signals (such as DDR and PCIe), effectively constraining the signal electromagnetic field and significantly reducing crosstalk in signal transmission between chips. Therefore, the ferrite bead filtering in the upper layer (power integration layer) solves the problems of clean power supply and power contamination of signals, while the stacked structure design in the lower layer (computing power sensing layer) solves the problem of mutual interference between signals. Together, they create a collaborative working environment for the computing power chips, high-speed memory, and various interface chips on the computing power sensing layer, enabling them to obtain high-quality power supply and conduct high-speed, low-noise digital communication. This achieves high-density, high-performance co-layer integration of heterogeneous chips.

[0047] 4. By concentrating the main heat source—the power supply unit—on a separate top layer, the heat source is concentrated, and its heat generation is physically isolated from the temperature-sensitive computing chip below. This "layered heat source" design provides the structural basis for centralized design and heat dissipation of the power integration layer. Combined with a heat sink embedded on top of the power integration layer, it forms a highly efficient "heat concentration-diffusion" channel with a clear and efficient heat dissipation path. This allows the heat generated by all internal power supply units to be quickly dissipated, improving the heat conduction efficiency between the power supply layer and external heat sinks (such as cooling fans and heat sinks). It also prevents the heat from different power supply units from accumulating and forming "hot spots," and prevents heat dispersion from affecting the lower-layer chips. This effectively solves the thermal coupling problem of existing technologies, while also giving the power integration layer good mechanical strength, improving the overall thermal reliability and performance stability of the system.

[0048] Other features and advantages of the present invention will be disclosed in detail in the following detailed description and accompanying drawings. Attached Figure Description

[0049] The invention will be further described below with reference to the accompanying drawings:

[0050] Figure 1 This is a schematic diagram of the integrated chip structure of the computing power sensing system integrated power supply according to Embodiment 1 of the present invention.

[0051] Figure 2 This is a side cross-sectional view of the power integration layer in Embodiment 1 of the present invention.

[0052] Figure 3 This is a side cross-sectional structural diagram of the computing power sensing layer in Embodiment 1 of the present invention.

[0053] Figure 4 This is a schematic diagram of the front structure of the second substrate in Embodiment 1 of the present invention.

[0054] Figure 5 This is a side cross-sectional view of the power integration layer in Embodiment 2 of the present invention.

[0055] Figure 6 This is a flowchart of the integrated chip packaging method for the integrated power supply of the computing power sensing system according to Embodiment 3 of the present invention. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be explained and described below with reference to the accompanying drawings. However, the following embodiments are only preferred embodiments of the present invention and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments in the implementation methods without creative effort are all within the protection scope of the present invention.

[0057] In the following description, terms such as “inner,” “outer,” “upper,” “lower,” “left,” and “right” are used only to indicate orientation or positional relationship for the convenience of describing the embodiments and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0058] Example 1:

[0059] Please see the appendix Figure 1 , Figure 1 A schematic diagram of the integrated chip for the integrated power supply of a computing power sensing system provided in one embodiment of this specification is shown.

[0060] like Figure 1As shown, the integrated chip for the power supply of this computing power sensing system can include at least: a power integration layer and a computing power sensing layer, which are vertically stacked and packaged from top to bottom. The front side of the power integration layer has several power supply units integrated to power each chip in the computing power sensing layer. The power signals output from each power supply unit are combined and connected, and then led out from the back side of the power integration layer using ferrite beads to achieve electrical connection between the power supply units and each chip in the computing power sensing layer, as well as inter-layer structural support.

[0061] In this embodiment, the power supply unit may include one or more of the following: a DC-DC converter chip, an LDO linear regulator chip, an ARM-specific PMIC chip, and corresponding passive components (such as resistors, capacitors, inductors, etc.).

[0062] For example, taking an externally supplied 12VDC power supply as an example, the power supply unit is designed to provide various voltage conversions required by the chips in the lower-level computing power sensing layer:

[0063] (1) 12VDC to 5VDC, used for power supply and voltage reduction of external interfaces;

[0064] (2) 12VDC to 3.3VDC, used to power the computing chip or for primary voltage drop;

[0065] (3) 3.3VDC to 1.8VDC, 0.9VDC, etc., used to power interface chips or high-quality secondary voltage divider.

[0066] Understandably, in common SIP packaging technology or 3D stacking designs, power supply units are usually integrated as auxiliary modules alongside other functional chips or placed on the periphery, often using solder ball connections. However, this embodiment reconstructs all power conversion and distribution functions required by the entire "Synchronous Computing" system from a traditional discrete, planar layout into a highly integrated, fully functional, and independently packaged layer—the power integration layer—serving as the mechanical and electrical foundation. A ferrite bead is semi-embedded at the bottom of the power integration layer, abandoning the conventional solder ball (BGA) interconnect method. Innovatively, the ferrite bead integrates the three major functions of electrical connection, high-frequency filtering, and mechanical support between the power integration layer and the lower layer (computing power sensing layer). A vertical stacking architecture with the power integration layer on top and the computing power sensing layer below is constructed around the ferrite bead. This design is a customized solution for the specific structure of this solution (the power integration layer needs to draw multiple high-current paths) and is not a universal or obvious connection method. On the one hand, this embodiment directly superimposes the originally dispersed power supply units and the chips of the computing power sensing layer in three-dimensional space, minimizing the planar wiring distance between them and compressing the PCB area occupied by the computing power sensing system to a single projected area. More importantly, after the current is output from the power supply unit, it converges within the internal plane of the power integration layer and immediately passes through the ultra-short channel of the ferrite bead to the power supply pins of the chips in the lower computing power sensing layer. This near-ideal straight path minimizes the parasitic inductance and resistance of the circuit, thereby effectively suppressing power supply ripple and improving dynamic response speed, ensuring the core requirements of the computing power chip for "high stability and low noise" from a physical structure perspective. On the other hand, addressing the complex problem of electromagnetic interference management, this embodiment innovatively integrates the filtering function of the ferrite bead with the interconnection structure. The ferrite bead is not an external device, but is connected in series in each vertical power supply channel, forming a distributed, embedded filtering network. When the high-frequency switching noise generated by the power supply attempts to propagate through the ferrite bead, it is absorbed by its ferrite material and converted into heat dissipation. This "path-as-filter" design achieves efficient suppression at the source of noise and along its inevitable propagation path, preventing it from interfering with high-speed digital signals in the lower layers that are in the same compact space. This simplifies or even eliminates the reliance on additional filtering circuits and shielding measures, significantly reducing the complexity of the computing power sensing system design.

[0067] Specifically, please refer to the appendix. Figure 1 In this embodiment, the power integration layer also includes a first substrate. The first substrate adopts a multi-layer design. Each layer inside the first substrate is formed into a power trace layer with different voltages using a large-area copper pouring process. The output pins of each power unit are respectively connected to the corresponding power trace layer inside the first substrate. Each power trace layer is connected to a set of ferrite beads. Each ferrite bead serves as a noise suppression channel for vertical transmission of a large current.

[0068] Preferably, the first substrate in this embodiment is a multilayer aluminum nitride substrate (AlN). The thermal conductivity of the multilayer aluminum nitride substrate is as high as 170-180 W / m·K, and the coefficient of thermal expansion of this material is very close to that of the chip (silicon material, Si) and third-generation semiconductor materials (silicon carbide SiC, gallium nitride GaN). This matching can minimize the thermomechanical stress caused by temperature changes, thereby significantly improving the long-term reliability of the chip solder joints and the entire module.

[0069] Furthermore, in this embodiment, to meet high current requirements and reduce the current density of a single ferrite bead, the ferrite beads are typically distributed in a column grid array on the four sides of the back of the first substrate. Electrically, several ferrite beads are connected in parallel as a group to jointly carry the tens of watts of high current transmission of one power supply, which is equivalent to significantly increasing the total cross-sectional area of ​​the conductor, improving the current carrying capacity, and thus reducing the impedance and heat generation of a single channel. At the same time, mechanically, the ferrite beads are a robust rigid structure. Multiple ferrite beads form a high-density rigid column grid array between the two substrates, providing shear and bending strength far exceeding that of conventional solder ball interconnects, ensuring long-term structural reliability under high power density integration.

[0070] Each power supply unit (such as a DC-DC chip, LDO chip, or PMIC chip) has its own power input / output pads. Through gold wire bonding and flip-chip bonding, the input / output pins of these power supply units are connected to a dedicated power trace layer with a large copper foil area pre-laid inside the first substrate. For example, the "12V input" pins of all power supply units are connected to the "12V power trace layer" inside the substrate; the "5V output" generated by each power supply unit is collected into the "5V power trace layer".

[0071] Specifically, please refer to the appendix. Figure 2 In this embodiment, a second power groove is provided on the back side of the first substrate. The second power groove is provided with electrical connection points and is respectively connected to each power trace layer. One end of the magnetic bead is partially embedded in the second power groove to realize the electrical connection between the magnetic bead and each power unit.

[0072] In this embodiment, the diameter, position, and precision of the second power supply groove are matched with the magnetic beads led out from the back of the power integration layer.

[0073] Understandably, in this embodiment, the large-area copper foil is equivalent to extremely low DC resistance and inductance. This ensures that the large current (total power at least 20W+) merged from the power supply unit can be transmitted within the first substrate with minimal loss and voltage drop, ultimately converging at the contact point connected to the ferrite bead (i.e., the electrical connection point set in the second power supply recess). In this embodiment, the layered design of the power supply traces on the first substrate achieves physical isolation between different voltage networks, avoiding crosstalk. The large-area copper plating process directly addresses the high-power transmission requirements, reducing wire resistance by increasing the area of ​​the copper foil. This is crucial for ensuring the power quality (low ripple, low impedance) and current carrying capacity after merging. Simultaneously, the ferrite bead replaces the traditional solder ball, providing a low-impedance, high-current path. This process completes the electrical "merging" of different power chips within the first substrate, "pooling" multiple discrete power outputs into several stable and powerful common power networks. Through collaborative and specialized design, extremely low power loss and voltage drop from the power integration layer to the lower load are ensured, significantly improving the current carrying capacity and withstand voltage of the first substrate, meeting the high-power transmission requirements, and systematically solving multiple problems caused by the dispersed power supply in the prior art, such as large space occupation, limited efficiency, and insufficient current carrying capacity and mechanical support. Together, they have achieved the synergistic benefits of miniaturization, powerful power supply, and stable structure, providing a key power solution for the chip-level integration of core modules of unmanned systems and improving overall energy efficiency.

[0074] Appendix Figure 3 This is a side cross-sectional structural diagram of the computing power sensing layer provided in the embodiments of this specification. Please refer to the appendix. Figure 3 The front of the computing power sensing layer is integrated with chips for performing computing tasks and interface chips. A first power supply groove is provided on the front of the computing power sensing layer. The first power supply groove is matched with the magnetic bead and electrically connected to each chip on the front of the computing power sensing layer to receive power from the power supply integration layer. The chips of the computing power sensing layer are interconnected by digital signals. Solder balls are provided on the back of the computing power sensing layer.

[0075] In this embodiment, the chip on the front of the computing power perception layer used to perform computing tasks can be a computing power chip integrating a multi-core CPU, GPU, NPU (Neural Processing Unit), and VPU, and can also integrate Flash memory chips, DDR memory chips, etc., but it is not limited to these. Those skilled in the art can select appropriate control chips according to actual conditions. The interface chip on the front of the computing power perception layer can be a network port, serial port, etc.

[0076] In this embodiment, the diameter, position, and precision of the first power supply groove are matched with the magnetic beads led out from the back of the power integration layer.

[0077] The solder balls on the back of the computing power sensing layer form a standard BGA package shape, serving as the interface for soldering the entire integrated chip to the external unmanned system motherboard. High-speed data and control signals processed by the computing power chip are connected to the solder balls on the back through wiring inside the substrate, thus connecting to the external unmanned system motherboard. Simultaneously, the heat generated by the chips in the computing power sensing layer (especially the computing power chip) can also be directly conducted to the large-area grounded copper trace on the motherboard through the solder balls, serving as one of the heat dissipation paths.

[0078] Appendix Figure 4 This is a schematic diagram of the front structure of the second substrate provided in an embodiment of this specification. Please refer to the appendix. Figure 4 In this embodiment, the computing power sensing layer also includes a second substrate. A first power groove is disposed on the front side of the second substrate. Several first power grooves are provided with electrical connection points and are electrically connected to each chip of the computing power sensing layer, so as to realize that the power supply current of the power integration layer flows into each chip of the computing power sensing layer through the magnetic bead and the first power grooves provided with electrical connection points.

[0079] Understandably, in terms of mechanical support, the ferrite bead, as a rigid columnar structure, forms a robust mechanical interlocking framework after being inserted into the corresponding first power groove of the lower computing power sensing layer and cured (e.g., with conductive adhesive or solder). This allows the entire stacked packaged integrated chip to effectively disperse and resist bending moments caused by thermal expansion coefficient mismatch or external stress, improving vibration resistance and solving the problem of insufficient mechanical strength of traditional solder ball (BGA) connections. In terms of electrical connection, the combined and reinforced power supplies within the first layer (power integration layer) are led out through ferrite beads at specific locations. This mechanical configuration directly serves optimal electrical performance. The two ends of the ferrite bead form low-resistance, high-reliability ohmic contacts with the metal pads of the upper and lower layers through this design, thereby efficiently and directly delivering the combined power from the power integration layer to the required chips within the computing power sensing layer. This design achieves the shortest and lowest-impedance vertical power supply path from the power integration layer to the computing chip, while perfectly supporting high current demands of 20W+.

[0080] Furthermore, in this embodiment, the second substrate adopts a multilayer design, with each layer inside the second substrate forming a signal routing layer and power routing layers of different voltages, and each layer inside the second substrate adopts a stacked structure to ensure that the adjacent layers of each signal routing layer have a complete ground plane or power plane.

[0081] Preferably, the second substrate is made of ABF material, which has excellent high-frequency electrical characteristics such as low dielectric constant and low loss tangent, and can significantly reduce dielectric loss and signal distortion during signal transmission.

[0082] For example, taking the second substrate as an example of a stacked structure of "signal-ground-signal-power-signal-ground-signal-signal", the sequence and functional allocation of its stacked structure can be as follows:

[0083] L1 (Top Layer, Signal_1): Signal / Component Layer. Primarily used to place pads for critical chips (such as computing chips, memory chips, and interface chips), and to fan out the high-speed signal lines that need to be brought out first (such as some DDR data lines and clock lines).

[0084] L2 (GND_1): Complete ground plane. Serves as the primary reference plane for signal routing layer L1, providing the shortest and most complete return path for signals in layer L1.

[0085] L3 (Signal_2): Inner signal layer. Typically used to house high-speed signals that are sensitive to noise or require strict impedance control, such as the DDR address / command bus and some PCIe differential pairs;

[0086] L4 (PWR): Core Power Plane. Provides a low-impedance power distribution network for the core voltage of the computing chip (e.g., VDD_CORE, 0.9V) or other major power domains. It forms a reference relationship with the adjacent L3 and L5 layers.

[0087] L5 (Signal_3): Inner signal layer. Used to arrange other high-speed signals, such as MIPI, USB, Gigabit Ethernet, and other differential signals;

[0088] L6 (GND_2): Complete ground plane. Serves as the primary reference plane for signals in layers L5 and L7.

[0089] L7 (Signal_4): Inner signal layer. Typically used to house relatively low-speed signals or more general-purpose I / O;

[0090] L8 (bottom layer, Signal_5): Signal / solder layer. This layer may be used to connect BGA solder balls, bringing signals from within the package to the external motherboard. Its routing must meet impedance requirements.

[0091] The ingenuity of this design lies in the synergy between the layers of the second substrate, aiming to create a controllable electromagnetic transmission environment and provide an adjacent, complete reference plane (ground plane or power plane) for each signal layer. This stack-up structure ensures that L1 references L2, L3 references L2 and L4, L5 references L4 and L6, and L7 references L6. In this embodiment, it is ensured that the adjacent layer (above or below) of any high-speed signal trace layer is a complete ground plane or power plane, providing a low-impedance, continuous mirror path for the return current of high-speed signals. When a signal propagates in a signal line, changing electric and magnetic fields induce "mirror return currents" of equal magnitude and opposite direction on adjacent reference planes. The return current is tightly confined to the reference plane path above or below the signal line, so that most of the signal energy is confined within the "transmission line" structure formed by the signal line and the reference plane, greatly reducing the energy radiated into space and also reducing crosstalk caused by magnetic field coupling with adjacent signal lines.

[0092] Furthermore, the stacked structure used in the layers of the second substrate in this design is also used to achieve tight coupling between the power and ground planes. As shown in the example, L4 (power layer) and L6 (ground layer) are directly adjacent, separated only by a dielectric layer (the spacing between the L5 signal layer and both is controlled by the stack thickness). These two parallel metal planes form a natural distributed planar capacitor, which can provide rapid local charge replenishment for the chip's instantaneous high current demands, making it the most effective decoupling capacitor. This design effectively reduces the AC impedance of the power distribution network, filters out power supply noise, and is key to improving power integrity, directly affecting the stability of the chip's power supply and clock / data jitter performance.

[0093] In this embodiment, because the second substrate uses ABF low-loss material and the stacked structure is designed with each adjacent layer of the signal trace having a complete reference plane, signal transmission loss can be significantly reduced, signal edges can be maintained steeply, and the signal electromagnetic field is tightly confined between the signal path and the reference plane, greatly suppressing crosstalk. This fundamentally guarantees the quality of signals such as PCIe and high-speed SerDes, laying the foundation for stable transmission of high data rates and long links, and achieving excellent signal integrity.

[0094] It is understandable that the integrated chip design of the computing power sensing system power supply proposed in this embodiment can effectively overcome electromagnetic interference and achieve stable and reliable high-speed signal transmission by integrating heterogeneous chips such as computing power chips, high-speed memory chips, and various interface chips on the same layer of the computing power sensing layer. The core of this design lies in the synergistic optimization of power integrity and signal integrity at the system level through a vertical stacking architecture and precise internal design. The design scheme of the computing power sensing layer substrate is not a simple stacking of layers, but rather actively constructs an electromagnetic environment conducive to high-speed signal transmission through a set of highly refined design principles based on electromagnetic field theory and signal integrity engineering. Specifically, firstly, the power integration layer is vertically powered by ferrite beads, eliminating key interference from both the "source" and the "path." The ferrite beads not only minimize parasitic parameters in the power supply circuit, ensuring fast and stable dynamic response, but their series connection in each power supply also constitutes a distributed high-frequency noise filter, physically blocking the upward transmission of power switching noise to the computing power sensing layer. This provides an exceptionally "clean" common power source for various chips in the lower computing power sensing layer, fundamentally avoiding the conduction interference of power supply noise to different types of chips. Secondly, the computing power sensing layer itself employs a precise stacked structure and wiring design to construct an internal barrier. Its multi-layer substrate provides a closely adjacent complete reference plane for high-speed signals (such as DDR and PCIe), effectively constraining the signal electromagnetic field and significantly reducing crosstalk in signal transmission between chips. Simultaneously, strict impedance control and equal-length wiring rules ensure the signal quality of the high-speed bus itself. This design allows for extremely low levels of mutual interference even when multiple high-speed interfaces are arranged close together on the same layer. Therefore, the ferrite bead filtering in the upper layer (power integration layer) solves the problems of clean power supply and power contamination of signals, while the stacked structure design in the lower layer (computing power sensing layer) solves the problem of mutual interference between signals. Together, they create a collaborative working environment for the computing power chips, high-speed memory, and various interface chips on the computing power sensing layer, enabling both high-quality power supply and high-speed, low-noise digital communication. This achieves high-density, high-performance co-layer integration of heterogeneous chips.

[0095] Furthermore, in this embodiment, the signal routing layer of the second substrate prioritizes routing high-speed signal lines to ensure that the outgoing path of the high-speed signal lines is the shortest and to avoid being blocked by other low-speed signals.

[0096] Specifically, in the first and second routing layers (usually the top layer and its adjacent inner layer) closest to the BGA pads of each chip in the computing power perception layer, dedicated, radially outward-extending channels are allocated for high-speed signal networks. These channels are given priority to occupy the most direct outgoing positions closest to the center of the pads.

[0097] Understandably, the shorter the path of a high-speed signal, the less it is affected by losses, crosstalk, and reflections. The preferential fan-out of high-speed signal lines ensures that they can enter the controlled impedance transmission line environment with the shortest distance after leaving the chip, avoiding long detours in dense solder ball arrays.

[0098] Furthermore, in this embodiment, the equal length rule must be strictly followed for ultra-high-speed buses such as DDR. By performing precise serpentine winding compensation on the ultra-high-speed signal lines, it is ensured that all signal lines within the same group of buses have the same electrical length, thereby guaranteeing that the signal transmission delay (i.e., electrical length) is strictly consistent and can be accurately sampled by the receiving end simultaneously, meeting strict timing margins.

[0099] For example, length matching is not arbitrary; it is divided according to functional groups. For instance, a byte channel in DDR4 (8 bits DQ + 1 bit DQS + 1 bit DM) constitutes a matching group. Within a group, the length of the clock or strobe signal (such as DQS) is typically used as a reference. The lengths of other data lines must match this reference, with a tolerance typically within ±5 mil (approximately 0.127 mm). For differential signals such as PCIe and USB, in addition to length matching between groups, priority must be given to ensuring length matching between the two lines (P and N) within the differential pair. The tolerance requirements (such as ±1 mil) are more stringent than for inter-group matching. This is because differential signals rely on the voltage difference between the two lines to transmit information. If the P and N lines are not the same length, the signal edge arrival times will differ, leading to a "phase difference," which can severely generate common-mode noise and reduce signal integrity. Internal length matching is a prerequisite for maintaining the excellent anti-interference characteristics of differential signals.

[0100] Understandably, high-speed signal priority fan-out is to create a dedicated, unobstructed, fast trunk for the most critical high-speed signals; equal-length routing ensures that all signals of a set of critical signals (such as DDR data groups) arrive at their destination simultaneously, avoiding confusion caused by timing misalignment. The optimized routing strategy of both reduces impedance discontinuities on the path, further ensuring the timing and reliability of the high-speed bus.

[0101] It can be seen that every structural detail (magnetic bead filter, stacked structure, power supply groove, solder ball, etc.) is not isolated. They are all designed to work precisely with the upper and lower layers in an extremely integrated three-dimensional space to solve the inherent electrical, thermal, and interference contradictions in heterogeneous chip integration, and ultimately achieve a leap in system-level performance and improved reliability.

[0102] Example 2:

[0103] This embodiment only applies to comparisons with... Figure 1 The differences between the two embodiments will be described in the following descriptions. The technical concepts of the remaining designs are similar to those of the first embodiment, and will not be repeated here.

[0104] Please see the appendix Figure 5 In this embodiment, the power integration layer is encapsulated using a molding process, and a heat sink is embedded in the top of the power integration layer to achieve centralized heat dissipation of the power unit.

[0105] Specifically, after the chip mounting, gold wire bonding, and semi-embedded ferrite beads of the power integration layer are completed, the entire power integration layer module is encapsulated with a molding compound. This molding compound fixes and protects the fragile gold wires, power units (DC-CDC chips, LDO chips, PMIC chips, and associated passive devices, etc.) and solder joints from moisture, dust, and mechanical damage. It is the physical guarantee for the stable operation of the precision electrical structure in the aforementioned embodiment one, enhances the mechanical strength, insulation, and environmental adaptability of the power integration layer, and ensures the long-term reliability of the integrated chip.

[0106] Understandably, this embodiment concentrates the main heat source—the power supply unit—on a separate top layer, thus concentrating the heat source and physically isolating its heat generation from the temperature-sensitive computing chip below. This "layered heat source" design provides the structural basis for centralized design and heat dissipation of the power integration layer. Combined with a heat sink embedded on top of the power integration layer, it forms a highly efficient "heat concentration-diffusion" channel with a clear and efficient heat dissipation path. This allows the heat generated by all internal power supply units to be quickly dissipated, improving the heat conduction efficiency between the power supply layer and external heat sinks (such as cooling fans and heat sinks). It also prevents the heat from different power supply units from accumulating and forming "hot spots," and avoids heat dispersion affecting the lower-layer chip. This effectively solves the thermal coupling problem of existing technologies, while also giving the power integration layer good mechanical strength, improving the overall thermal reliability and performance stability of the system.

[0107] Example 3:

[0108] Please see the appendix Figure 6 , Figure 6 A flowchart illustrating an integrated chip packaging method for a computing power sensing system power supply provided in one embodiment of this specification is shown.

[0109] like Figure 6 As shown, the packaging method of the integrated chip for the computing power sensing system includes at least the following steps:

[0110] S1, power integration layer package:

[0111] A large-area copper plating process is used to form power trace layers of different voltages inside the first substrate. A second power groove matching the ferrite bead is opened on the back of the first substrate to connect the power supply.

[0112] The power unit is mounted on the front side of the first substrate using a flip-chip bonding process and then cured.

[0113] The output pins of each power unit are electrically connected to the corresponding power trace layer inside the first substrate using a gold wire bonding process.

[0114] The first substrate and the power unit are vacuum encapsulated with liquid epoxy resin to enhance heat dissipation, insulation and mechanical strength, forming an encapsulation on the front side of the first substrate.

[0115] Solder paste is applied to the second power groove on the back of the first substrate, and a magnetic bead is partially embedded.

[0116] Perform reflow soldering to ensure the magnetic beads are firmly soldered, and clean the first substrate.

[0117] A damming and self-leveling process is used to inject a primer around the magnetic beads, forming a magnetic bead fixing layer, which is then cured. This step provides dual fixation for the magnetic beads: soldering provides electrical connection and primary support, while the primer relieves stress and enhances overall mechanical strength. At this point, a power integration layer with exposed magnetic beads is formed.

[0118] In this embodiment, the power supply units are interconnected using gold wire bonding, a mature and reliable process suitable for the interconnection requirements of power supply units. Combined with other processes such as flip-chip bonding, high-density, highly reliable internal connections are achieved.

[0119] S2, Computational Power Awareness Layer Encapsulation:

[0120] Signal trace layers and power trace layers of different voltages are formed inside the second substrate, and each layer inside the second substrate adopts a stacked structure (such as "signal-ground-signal-power-...") to ensure that the adjacent layers of each signal trace layer have a complete ground plane or power plane to control impedance and reduce crosstalk. A first power groove matching the ferrite bead is opened on the front side of the first substrate to connect the power supply.

[0121] A chip for performing computing tasks is mounted on the front side of the second substrate using a flip-chip bonding process;

[0122] Perform reflow soldering to ensure a strong weld, and clean the second substrate.

[0123] The chip on the front side of the second substrate is filled with adhesive and then cured by heating.

[0124] The interface chip is mounted on the front side of the second substrate using conductive adhesive and then cured.

[0125] The output pins of each chip on the front side of the second substrate are electrically connected to the corresponding signal and power trace layers inside the second substrate using a gold wire bonding process.

[0126] S3, an integrated chip package for the power integration layer and the computing power sensing layer:

[0127] Insert the exposed ferrite bead of the power integration layer into the first power groove on the front side of the second substrate.

[0128] Reflow soldering is performed to ensure a strong solder joint. During this process, the solder paste in the first power groove melts, soldering the other end of the ferrite bead to the electrical connection point in the groove (connected to the power input terminal of the computing layer chip). At this point, power is transmitted vertically and with low noise from the power integration layer through the ferrite bead to the chips in the computing perception layer. Simultaneously, the ferrite bead also serves as a robust structural support pillar between the two layers.

[0129] The gap between the front of the computing power sensing layer and the back of the power integration layer is filled with adhesive and then heated and cured to form an integrated chip with two layers of encapsulation.

[0130] Balls are soldered onto the back of the computing power sensing layer to form a standard BGA (Ball Grid Array) packaging interface, which facilitates the soldering of the entire integrated chip onto the motherboard of the unmanned system, thus completing the packaging process and ultimately generating a highly integrated, compact, electromagnetically compatible, and heat-dissipating "sensing, computing, and power" integrated system-in-package product.

[0131] Furthermore, in this embodiment, before vacuum potting the power integration layer, a heat sink is embedded in the top of the power integration layer to achieve centralized heat dissipation of the power unit.

[0132] Understandably, through the proprietary packaging process described above—"independent process, vertical stacking, ferrite bead interconnection, and integrated encapsulation"—a high-power power supply system and a high-performance computing system are successfully integrated into a single chip-sized package. This design significantly shortens the power supply distance, reduces power network impedance and losses, effectively suppresses power supply noise interference to sensitive computing chips through ferrite bead series connection, and achieves extremely high system integration density and performance through three-dimensional stacking. Moreover, this integrated chip packaging method reduces the design difficulty of the PCB motherboard for unmanned systems and reduces the number of peripheral discrete components. The standardized ferrite bead stacking interface (ferrite bead array) also simplifies the integrated chip packaging process, ultimately achieving improved performance while reducing overall packaging difficulty and system cost.

[0133] It is understood that the technical concept of the integrated chip packaging method for the integrated power supply of the computing power sensing system provided in this embodiment is similar to the technical concept of the integrated chip for the integrated power supply of the aforementioned computing power sensing system. Correspondingly, a complete set of exclusive packaging process flows are formed, from chip mounting, plastic encapsulation, semi-embedded magnetic beads, to double-layer substrate alignment and conductive adhesive curing. This embodiment will not elaborate further here.

[0134] The above description is merely a preferred embodiment disclosed in this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this disclosure.

[0135] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

Claims

1. An integrated chip for a computing power sensing system with integrated power supply, characterized in that, It includes a power integration layer and a computing power sensing layer that are vertically stacked from top to bottom; The front side of the power integration layer is equipped with several power supply units for powering each chip in the computing power sensing layer. The power signals output by each power supply unit are merged and connected, and then led out from the back side of the power integration layer using ferrite beads to realize the electrical connection between the power supply units and each chip in the computing power sensing layer, as well as the interlayer structural support. The front of the computing power sensing layer is integrated with chips for performing computing tasks and interface chips. A first power supply groove is provided on the front of the computing power sensing layer. The first power supply groove is matched with the magnetic bead and electrically connected to each chip on the front of the computing power sensing layer to receive power from the power supply integration layer. The chips of the computing power sensing layer are interconnected by digital signals. Solder balls are provided on the back of the computing power sensing layer.

2. The integrated chip for a computing power sensing system power supply as described in claim 1, characterized in that, The power integration layer also includes a first substrate. The first substrate adopts a multi-layer design. Each layer inside the first substrate uses a large-area copper pouring process to form power trace layers with different voltages. The output pins of each power unit are connected to the corresponding power trace layers inside the first substrate. Each power trace layer is connected to a set of ferrite beads. Each ferrite bead serves as a noise suppression channel for vertical transmission of a large current.

3. The integrated chip for a computing power sensing system power supply as described in claim 2, characterized in that, A second power supply groove is provided on the back side of the first substrate. The second power supply groove is provided with electrical connection points and is connected to each power supply trace layer respectively. One end of the ferrite bead is partially embedded in the second power supply groove to realize the electrical connection between the ferrite bead and each power supply unit.

4. The integrated chip for a computing power sensing system power supply as described in claim 1, characterized in that, The computing power sensing layer also includes a second substrate. A first power groove is disposed on the front side of the second substrate. Several first power grooves are provided with electrical connection points and are electrically connected to each chip of the computing power sensing layer, so as to realize that the power supply current of the power integration layer flows into each chip of the computing power sensing layer through the magnetic bead and the first power grooves provided with electrical connection points.

5. The integrated chip for a computing power sensing system power supply as described in claim 4, characterized in that, The second substrate adopts a multi-layer design. Each layer inside the second substrate forms a signal routing layer and a power routing layer with different voltages. Furthermore, each layer inside the second substrate adopts a stacked structure to ensure that the adjacent layers of each signal routing layer have a complete ground plane or power plane.

6. The integrated chip for a computing power sensing system power supply as described in claim 5, characterized in that, The signal routing layer of the second substrate prioritizes routing high-speed signal lines to ensure the shortest possible outgoing path for high-speed signal lines.

7. The integrated chip for a computing power sensing system power supply as described in claim 1, characterized in that, The power integration layer is encapsulated using a plastic encapsulation process, and a heat sink is embedded in the top of the power integration layer to achieve centralized heat dissipation of the power unit.

8. The integrated chip for a computing power sensing system power supply as described in claim 1, characterized in that, The magnetic beads are distributed on the four sides of the back of the power integration layer.

9. A packaging method for an integrated chip for a computing power sensing system power supply, characterized in that, Includes the following steps: S1, power integration layer package: Power trace layers with different voltages are formed inside the first substrate, and a second power groove matching the ferrite bead is formed on the back of the first substrate to connect to the power supply. The power unit is mounted on the front side of the first substrate using a flip-chip bonding process and then cured. The output pins of each power unit are electrically connected to the corresponding power trace layer inside the first substrate using a gold wire bonding process. Vacuum encapsulation is performed on the first substrate and the power supply unit to form an encapsulation on the front side of the first substrate; Solder paste is applied to the second power groove on the back of the first substrate, and a magnetic bead is partially embedded. Perform reflow soldering to ensure the magnetic beads are firmly soldered, and clean the first substrate. A damming and self-leveling process is used to inject a base filler around the magnetic beads to form a magnetic bead fixing layer, which is then cured to form a power integrated layer with exposed magnetic beads. S2, Computational Power Awareness Layer Encapsulation: Signal trace layers and power trace layers of different voltages are formed inside the second substrate, and each layer inside the second substrate adopts a stacked structure to ensure that the adjacent layers of each signal trace layer have a complete ground plane or power plane. A first power groove matching the ferrite bead is opened on the front side of the first substrate to connect the power supply. A chip for performing computing tasks is mounted on the front side of the second substrate using a flip-chip bonding process; Perform reflow soldering to ensure a strong weld, and clean the second substrate. The chip on the front side of the second substrate is filled with adhesive and then cured by heating. The interface chip is mounted on the front side of the second substrate using conductive adhesive and then cured. The output pins of each chip on the front side of the second substrate are electrically connected to the corresponding signal and power trace layers inside the second substrate using a gold wire bonding process. S3, an integrated chip package combining the power integration layer and the computing power sensing layer: Insert the exposed ferrite bead of the power integration layer into the first power groove on the front side of the second substrate. Perform reflow soldering to ensure a strong weld. The gap between the front of the computing power sensing layer and the back of the power integration layer is filled with adhesive and then heated and cured to form an integrated chip with two layers of encapsulation. Solder balls are placed on the back of the computing power sensing layer to complete the packaging process.

10. The packaging method for an integrated chip for a computing power sensing system power supply as described in claim 9, characterized in that, S1, the power integration layer package, also includes: Before vacuum potting the power integration layer, a heat sink is embedded in the top of the power integration layer to achieve centralized heat dissipation of the power unit.

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