Integrated package structure and method of manufacturing the same

Abstract

The application provides a preparation method of an integrated packaging structure, which comprises the following steps: providing a glass substrate; manufacturing a cavity structure on the front surface and the back surface of the glass substrate respectively; embedding a silicon bridge chip into the cavity structure on the front surface of the glass substrate and pressing insulating material; embedding a gallium nitride chip into the cavity structure on the back surface of the glass substrate and pressing insulating material; and mounting a GPU and a memory chip on the surface of the insulating material pressed on the silicon bridge chip. The technical scheme of the application integrates the GPU and a GaN (gallium nitride) chip for supplying power for the GPU, replaces the partial functions of a separate power module in the related art by the gallium nitride chip, and can also reduce the area of the substrate and improve the response speed of the GPU.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and specifically relates to an integrated packaging structure and its fabrication method. Background Technology

[0002] GPUs (Graphics Processing Units) are the core hardware for tasks such as gaming, AI computing, and 3D rendering. The ever-increasing computing demands place higher requirements on power supply, such as higher current, faster response, and higher conversion efficiency.

[0003] In related technologies, a VRM (Voltage Regulator Module) is used near the GPU. This module contains common power supply chips, such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) / DrMOS (Driver-MOSFET), which, together with related capacitors and inductors, are interconnected with the GPU through a PCB (Printed Circuit Board) to control the power supply to the GPU.

[0004] However, GPUs, responsible for massive data processing and rendering, have high power consumption requirements. Insufficient power supply will cause performance degradation, and long-term voltage instability can also damage the hardware. Common power management modules, whether silicon-based MOSFETs or DrMOS, are increasingly unable to meet the switching frequency and transient response time requirements of high-performance GPUs. At the same time, since the power management module is placed near the GPU, it needs to be paired with a varying number of capacitors and inductors, increasing the PCB area and number of layers.

[0005] Therefore, a new solution is needed to address the above problems. Summary of the Invention

[0006] The purpose of this application is to provide an integrated packaging structure and its fabrication method.

[0007] According to a first aspect of this application, a method for fabricating an integrated packaging structure is provided, comprising: Provide a glass substrate; Cavity structures are formed on both the front and back sides of the glass substrate. A silicon bridge chip is embedded in the cavity structure on the front side of the glass substrate and an insulating material is pressed together. A gallium nitride chip is embedded in the cavity structure on the back side of the glass substrate and an insulating material is pressed together. GPU and memory chips are mounted on the insulating material surface of the laminated silicon bridge chip.

[0008] In an optional embodiment, a glass substrate is provided, comprising: Using glass as the core material, holes are drilled and wiring is performed on the core material according to the wiring diagram to form a glass substrate; wherein, the silicon bridge chip and the gallium nitride chip are connected through wiring in the holes obtained by drilling on the glass substrate.

[0009] In an optional embodiment, cavity structures are formed on both the front and back sides of the glass substrate, including: An insulating material is pressed onto the front or back of the glass substrate to form an insulating layer; A cavity structure is fabricated on the insulating layer according to the size of the silicon bridge chip or gallium nitride chip.

[0010] In an optional implementation, the method further includes: A capacitor cavity structure is formed on the front side of the glass substrate; A silicon capacitor is embedded in the capacitor cavity structure.

[0011] In an optional implementation, the number of silicon bridge chips is equal to the number of memory chips.

[0012] In an optional implementation, the silicon bridge chip is used to connect the GPU and the memory chip.

[0013] In an optional implementation, the method further includes: A heat dissipation structure is attached to the insulating material surface of the laminated silicon bridge chip.

[0014] According to a second aspect of this application, an integrated packaging structure is provided, comprising: Glass substrate; A silicon bridge chip is fabricated on the front side of the glass substrate; GPU and memory chips are mounted on the insulating material surface of the silicon bridge chip; Gallium nitride chip fabricated on the back side of the glass substrate.

[0015] In an optional embodiment, the glass substrate has a through-hole, and the silicon bridge chip and the gallium nitride chip are connected through wiring within the through-hole.

[0016] In an optional embodiment, an insulating layer is formed on the back and front sides of the glass substrate, and a cavity structure is formed on the insulating layer. The silicon bridge chip is embedded in the cavity structure on the front side of the glass substrate, and the gallium nitride chip is embedded in the cavity structure on the back side of the glass substrate.

[0017] In an optional embodiment, the integrated packaging structure further includes a silicon capacitor; the silicon capacitor is embedded in the capacitor cavity structure on the front side of the glass substrate.

[0018] In an optional implementation, the number of silicon bridge chips is equal to the number of memory chips.

[0019] In an optional implementation, the silicon bridge chip is used to connect the GPU and the memory chip.

[0020] In an optional embodiment, the integrated packaging structure further includes a heat dissipation structure; the heat dissipation structure is attached to the surface of the insulating material on which the silicon bridge chip is pressed.

[0021] Compared with related technologies, the technical solution of this application has at least the following advantages: This application integrates the GPU with a GaN (gallium nitride) chip that powers the GPU. GaN chips are characterized by high electron mobility, high breakdown electric field strength, low on-resistance, no reverse recovery charge, high thermal conductivity, and high-temperature resistance. Integrating the GaN chip with the GPU can replace some functions of the discrete power supply module in related technologies, reduce the substrate area, and improve the GPU's response speed. Furthermore, this application uses glass as a core material, improving the signal transmission quality of the chip.

[0022] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures and processes shown in the description and the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic flowchart of a method for fabricating an integrated packaging structure according to an exemplary embodiment of this application.

[0025] Figures 2A-2E This is a cross-sectional schematic diagram of the integrated packaging structure in the fabrication process according to an exemplary embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] To address the problems raised in the background art, the inventors of this application have improved an integrated packaging structure and its fabrication method to increase switching frequency and transient response time while reducing PCB area and number of layers. This integrated packaging structure is manufactured through advanced packaging and integrates the GPU with a GaN (gallium nitride) chip that powers the GPU. GaN chips are characterized by high electron mobility, high breakdown electric field strength, low on-resistance, no reverse recovery charge, high thermal conductivity, and high-temperature resistance. Integrating the GaN chip with the GPU can replace some functions of the discrete power supply module in related technologies, and can also reduce the substrate area and improve the GPU's response speed. Furthermore, this application uses glass as a core material, improving the signal transmission quality of the chip.

[0028] See Figure 1 As shown, the method for fabricating the integrated packaging structure provided in this application includes: Step 101: Provide a glass substrate; Step 102: Create cavity structures on the front and back sides of the glass substrate respectively; Step 103: Embed the silicon bridge chip in the cavity structure on the front side of the glass substrate and press the insulating material together; Step 104: Embed a gallium nitride chip in the cavity structure on the back side of the glass substrate and press insulating material together; Step 105: Mount the GPU and memory chips onto the insulating material surface of the laminated silicon bridge chip.

[0029] In this embodiment, glass is used as the core material to fabricate a glass substrate. Cavity structures are fabricated on both the front and back sides of the glass substrate. A silicon bridge chip is embedded in the cavity structure on the front side of the glass substrate and pressed together with an insulating material. A gallium nitride chip is embedded in the cavity structure on the back side of the glass substrate and similarly pressed together with an insulating material.

[0030] It should be noted that the order in which the cavity structures are fabricated on the front and back sides of the glass substrate is not restricted. The cavity structures can be fabricated on the front side of the glass substrate first, or on the back side first. Similarly, the order between the steps of embedding the silicon bridge chip and embedding the gallium nitride chip is also not restricted. Alternatively, the cavity structures can be fabricated on the front side of the glass substrate first, followed by embedding the silicon bridge chip and laminating the insulating material, and then the cavity structures can be fabricated on the back side of the glass substrate first, followed by embedding the gallium nitride chip and laminating the insulating material, and then the cavity structures can be fabricated on the front side of the glass substrate first, followed by embedding the silicon bridge chip and laminating the insulating material.

[0031] In some embodiments, the cavity structure can be implemented using a layering method or a layer subtraction method.

[0032] In some embodiments, silicon bridge chips and gallium nitride chips are laminated using ABF (Ajinomoto Build-up Film) insulating material.

[0033] In some embodiments, after the silicon bridge chip is embedded, a GPU and a memory chip are mounted on its insulating material surface. The memory chip may be, for example, HBM (High Bandwidth Memory).

[0034] In some optional implementations of this embodiment, providing a glass substrate includes: Using glass as the core material, holes are drilled and wiring is performed on the core material according to the wiring diagram to form a glass substrate; wherein, the silicon bridge chip and the gallium nitride chip are connected through wiring in the holes obtained by drilling on the glass substrate.

[0035] In this optional implementation, glass is used as the core material. Holes are drilled and wiring is performed on the glass substrate according to the wiring diagram to form a wiring layer. This wiring layer can be multiple wiring layers, and the specific design depends on actual needs. This application does not impose specific limitations on this.

[0036] Wiring is also fabricated in the through-holes obtained by drilling into the glass substrate, allowing the wiring layers on the front and back sides of the glass substrate to connect through the wiring within the through-holes. The silicon bridge chip is connected to the wiring layer on the front side of the glass substrate, and the gallium nitride chip is connected to the wiring layer on the back side of the glass substrate.

[0037] In some optional implementations of this embodiment, the step of fabricating cavity structures on the front and back sides of the glass substrate includes: An insulating material is pressed onto the front or back of the glass substrate to form an insulating layer; A cavity structure is fabricated on the insulating layer according to the size of the silicon bridge chip or gallium nitride chip.

[0038] In this optional implementation, the process for fabricating the cavity structure on both the front and back sides of the glass substrate can be the same, such as using either an additive or subtractive layer method. Of course, the processes for fabricating the cavity structure on the front and back sides of the glass substrate can also be different, such as using an additive layer method on the front and a subtractive layer method on the back, depending on the specific needs. This application does not impose any specific restrictions on this.

[0039] In the fabrication of the cavity structure, an insulating material can be laminated onto a glass substrate to form an insulating layer, and a cavity structure capable of accommodating a silicon bridge chip or a gallium nitride chip can be fabricated on this insulating layer. In other words, the size of the cavity structure is adapted to the silicon bridge chip or the gallium nitride chip.

[0040] It should be noted that during the fabrication of the cavity structure and embedding of the silicon bridge chip or gallium nitride chip, a wiring layer connecting the silicon bridge chip or gallium nitride chip can also be fabricated according to the wiring design. For example, an insulating material can be laminated onto a glass substrate first, and holes can be made at the cavity structure locations of this insulating material layer to embed the silicon bridge chip or gallium nitride chip. At the same time, a wiring layer can be prepared according to the wiring design using processes such as photolithography and etching, and then the insulating material can be laminated to form the insulating material surface.

[0041] In some optional implementations of this embodiment, the method further includes: A capacitor cavity structure is formed on the front side of the glass substrate; A silicon capacitor is embedded in the capacitor cavity structure.

[0042] In this optional implementation, depending on design requirements, if silicon capacitors are needed, a capacitor cavity structure can be fabricated on the front side of the glass substrate, and the silicon capacitor can be embedded within this cavity structure. It should be noted that the capacitor cavity structure and the cavity structure for embedding the silicon bridge chip can be fabricated in the same step.

[0043] In some optional implementations of this embodiment, the silicon bridge chip is used to connect the GPU and the memory chip.

[0044] In some optional implementations of this embodiment, the number of silicon bridge chips is equal to the number of memory chips.

[0045] In this optional implementation, the silicon bridge chip can be used to connect the memory chip and the GPU, so the number of silicon bridge chips is equal to the number of memory chips, each silicon bridge chip connects to one memory chip, and different silicon bridge chips connect to different memory chips.

[0046] In some optional implementations of this embodiment, the method further includes: A heat dissipation structure is attached to the insulating material surface of the laminated silicon bridge chip.

[0047] In this optional implementation, a heat dissipation structure can also be attached to the insulating material surface of the silicon bridge chip on the front side of the glass substrate. The heat dissipation structure can be selected from heat dissipation covers or other materials as needed.

[0048] The following is through Figures 2A-2E The embodiment shown describes the detailed fabrication process of the integrated packaging structure of this application.

[0049] 1. Using glass as the core material, TSV (Through-Silicon Via) holes are drilled and traced on the glass core material according to the connection requirements.

[0050] 2. Press ABF (Ajinomoto Build-up Film, insulating material) onto the glass core material and create a cavity. The cavity can be created using either an additive or subtractive layer method, as long as the cavity structure is achieved. Embed a silicon bridge chip that serves as a connector in the cavity. In addition, silicon capacitors can be added as needed.

[0051] 3. After the silicon bridge structure (including the silicon bridge chip and the wiring layer connecting the silicon bridge chip) is completed, the same cavity fabrication process is used to fabricate the cavity on the back of the substrate. After placing the GaN (gallium nitride) chip, ABF lamination is performed.

[0052] 4. Attach the GPU, HBM and other IC chips to the side where the silicon bridge structure is located and fill the bottom. Then attach heat dissipation structures, such as rings (reinforcing rings) or lids (heat sinks), to the substrate.

[0053] 5. Balls are placed on the substrate surface where the gallium nitride chip is located to complete the packaging.

[0054] Accordingly, this application provides an integrated packaging structure in a second aspect, comprising: Glass substrate; A silicon bridge chip is fabricated on the front side of the glass substrate; GPU and memory chips are mounted on the insulating material surface of the silicon bridge chip; Gallium nitride chip fabricated on the back side of the glass substrate.

[0055] The glass substrate has through holes, and the silicon bridge chip and the gallium nitride chip are connected through wiring within the through holes.

[0056] In some optional implementations of this embodiment, insulating layers are respectively formed on the back and front sides of the glass substrate, and cavity structures are formed on the insulating layers. The silicon bridge chip is embedded in the cavity structure on the front side of the glass substrate; the gallium nitride chip is embedded in the cavity structure on the back side of the glass substrate.

[0057] In some optional implementations of this embodiment, the integrated packaging structure further includes: a silicon capacitor; the silicon capacitor is embedded in the capacitor cavity structure on the front side of the glass substrate.

[0058] In some optional implementations of this embodiment, the number of silicon bridge chips is equal to the number of memory chips.

[0059] In some optional implementations of this embodiment, the silicon bridge chip is used to connect the GPU and the memory chip.

[0060] In some optional implementations of this embodiment, the integrated packaging structure further includes a heat dissipation structure; the heat dissipation structure is attached to the surface of the insulating material on which the silicon bridge chip is pressed.

[0061] The above-mentioned integrated packaging structure is prepared by the preparation method of the integrated packaging structure provided in the above embodiments. For specific details, please refer to the description of the preparation method of the integrated packaging structure in the above embodiments, which will not be repeated here.

[0062] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating an integrated packaging structure, characterized in that, include: Provide a glass substrate; Cavity structures are formed on both the front and back sides of the glass substrate. A silicon bridge chip is embedded in the cavity structure on the front side of the glass substrate and an insulating material is pressed together. A gallium nitride chip is embedded in the cavity structure on the back side of the glass substrate and an insulating material is pressed together. GPU and memory chips are mounted on the insulating material surface of the laminated silicon bridge chip.

2. The preparation method according to claim 1, characterized in that, A glass substrate is provided, comprising: Using glass as the core material, holes are drilled and wiring is performed on the core material according to the wiring diagram to form a glass substrate; wherein, the silicon bridge chip and the gallium nitride chip are connected through wiring in the holes obtained by drilling on the glass substrate.

3. The preparation method according to claim 1, characterized in that, Cavity structures are formed on both the front and back sides of the glass substrate, including: An insulating material is pressed onto the front or back of the glass substrate to form an insulating layer; A cavity structure is fabricated on the insulating layer according to the size of the silicon bridge chip or gallium nitride chip.

4. The preparation method according to claim 1, characterized in that, The method further includes: A capacitor cavity structure is formed on the front side of the glass substrate; A silicon capacitor is embedded in the capacitor cavity structure.

5. The preparation method according to claim 1, characterized in that, The number of silicon bridge chips is equal to the number of memory chips.

6. The preparation method according to claim 1, characterized in that, The silicon bridge chip is used to connect the GPU and the memory chip.

7. The preparation method according to claim 1, characterized in that, The method further includes: A heat dissipation structure is attached to the insulating material surface of the laminated silicon bridge chip.

8. An integrated packaging structure, characterized in that, include: Glass substrate; A silicon bridge chip is fabricated on the front side of the glass substrate; GPU and memory chips are mounted on the insulating material surface of the silicon bridge chip; Gallium nitride chip fabricated on the back side of the glass substrate.

9. The integrated packaging structure according to claim 8, characterized in that, The glass substrate has through holes, and the silicon bridge chip and the gallium nitride chip are connected through wiring within the through holes.

10. The integrated packaging structure according to claim 8, characterized in that, An insulating layer is formed on the back and front sides of the glass substrate, and a cavity structure is formed on the insulating layer. The silicon bridge chip is embedded in the cavity structure on the front side of the glass substrate, and the gallium nitride chip is embedded in the cavity structure on the back side of the glass substrate.

11. The integrated packaging structure according to claim 10, characterized in that, The integrated packaging structure further includes a silicon capacitor; the silicon capacitor is embedded in the capacitor cavity structure on the front side of the glass substrate.

12. The integrated packaging structure according to claim 8, characterized in that, The number of silicon bridge chips is equal to the number of memory chips.

13. The integrated packaging structure according to claim 8, characterized in that, The silicon bridge chip is used to connect the GPU and the memory chip.

14. The integrated packaging structure according to claim 8, characterized in that, The integrated packaging structure further includes a heat dissipation structure; the heat dissipation structure is attached to the surface of the insulating material on which the silicon bridge chip is pressed.

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