Robust and accurate overlay target design for cmp

Abstract

A metrology system can receive a plurality of candidate design variations for a target layout of a target stack. The metrology system can determine one or more process-induced target defects for the plurality of candidate design variations when fabricated using a known fabrication process. The metrology system can determine one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured using a known metrology recipe. The metrology system can select a final design variation from the plurality of candidate design variations that provides a minimum aggregate overlay error based on the one or more process-induced overlay errors.

Description

Cross-reference of related applications

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 563,851, filed March 11, 2024, and U.S. Provisional Application No. 63 / 573,302, filed April 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to stacked metering, and more specifically, to optimizing the design of stacked targets. Background Technology

[0003] Pair metrology provides measurements of registration or misregistration of features on a sample associated with two or more patterning processes (e.g., photolithography and etching). The accuracy of the reported pairing relative to device features is critical for pair metrology. Several factors can impair pair metrology accuracy, including process-induced target defects stemming from manufacturing effects. Manufacturing process steps (e.g., etching, deposition, and chemical mechanical planarization (CMP)) adversely affect pair targets, introducing asymmetry and reducing pair metrology accuracy. Specifically, CMP process steps can introduce pitting and other erosion effects on large unpatterned areas within the pair target, resulting in less accurate pair metrology. Although pair target design methodologies have been used to design pair targets capable of aligning features between layers, these methods cannot predict how pair target markings will be affected by process-induced effects.

[0004] Therefore, there is a need to develop systems and methods to address the aforementioned shortcomings. Summary of the Invention

[0005] According to one or more embodiments of this disclosure, a metrology system is disclosed. In one embodiment, the metrology system includes a controller comprising one or more processors configured to execute program instructions stored on a memory device, wherein the program instructions cause the one or more processors to receive a plurality of candidate design variations of a target layout for stacked targets. In another embodiment, the instructions cause the one or more processors to determine one or more process-induced target defects of the plurality of candidate design variations when manufactured using a known manufacturing process. In another embodiment, the instructions cause the one or more processors to determine one or more process-induced stacking errors associated with the one or more process-induced target defects of the plurality of candidate design variations when measured using a known metrology formulation. In another embodiment, the instructions cause the one or more processors to select a final design variation from the plurality of candidate design variations that provides a minimum aggregate stacking error based on the one or more process-induced stacking errors.

[0006] According to one or more embodiments of this disclosure, a method for designing a stacked target is disclosed. In one embodiment, the method includes identifying a plurality of candidate design variations of the target layout of the stacked target. In another embodiment, the method includes determining one or more process-induced target defects of the plurality of candidate design variations when manufactured using a known manufacturing process. In another embodiment, the method includes determining one or more process-induced stacking errors associated with the one or more process-induced target defects of the plurality of candidate design variations when measured using a known metrology formula. In another embodiment, the method includes selecting a final design variation from the plurality of candidate design variations that provides a minimum aggregate stacking error based on the one or more process-induced stacking errors.

[0007] According to one or more embodiments of this disclosure, a metrology system is disclosed. In one embodiment, the metrology system includes one or more process tools configured to manufacture a stacked target on a sample using a known manufacturing process. In another embodiment, the metrology system includes a controller comprising one or more processors configured to execute program instructions stored on a memory device, wherein the program instructions cause the one or more processors to receive a plurality of candidate design variations of the target layout of the stacked target. In another embodiment, the instructions cause the one or more processors to determine one or more process-induced target defects of the plurality of candidate design variations when manufactured using a known manufacturing process. In another embodiment, the instructions cause the one or more processors to determine one or more process-induced stacking errors associated with the one or more process-induced target defects of the plurality of candidate design variations when measured using a known metrology formulation. In another embodiment, the instructions cause the one or more processors to select a final design variation from the plurality of candidate design variations that provides a minimum aggregated stacking error based on the one or more process-induced stacking errors. In another embodiment, the instructions cause the one or more processors to direct the one or more process tools to manufacture the stacked target material with the final design changes on the sample.

[0008] It should be understood that the above general description and the following detailed description are for illustrative purposes only and do not necessarily limit the scope of the invention claimed. The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention. Attached Figure Description

[0009] Those skilled in the art can better understand the many advantages of this disclosure by referring to the accompanying drawings.

[0010] Figure 1A A block diagram illustrating a system for designing, manufacturing, and measuring stacked targets according to one or more embodiments of the present disclosure.

[0011] Figure 1B A block diagram view illustrating a stacked metering system according to one or more embodiments of the present disclosure.

[0012] Figure 2 This is a flowchart illustrating the steps performed in a method for designing stacked targets according to one or more embodiments of the present disclosure.

[0013] Figure 3 This is a top view of a stacked target material according to one or more embodiments of the present disclosure.

[0014] Figure 4 A close-up top view illustrating a section of a stacked target material according to one or more embodiments of the present disclosure.

[0015] Figure 5A A side view illustrating a section of a stacked target according to one or more embodiments of the present disclosure, with an illustration showing a portion of the stacked target section.

[0016] Figure 5B A side view illustrating a section of a stacked target according to one or more embodiments of the present disclosure, with an illustration showing a portion of the stacked target section.

[0017] Figure 6 This is a conceptual view illustrating one or more embodiments of an optical subsystem according to the present disclosure.

[0018] Figure 7 This is a conceptual view illustrating a process tool configured as a photolithography tool according to one or more embodiments of the present disclosure. Detailed Implementation

[0019] The disclosed objects will now be described in detail with reference to the accompanying drawings. This disclosure has been particularly shown and described with respect to specific embodiments and their particular features. The embodiments set forth herein should be considered illustrative rather than limiting. It will be readily apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of this disclosure.

[0020] Embodiments of this disclosure relate to systems and methods for optimizing process-induced sputtering target designs by selecting candidate design variations that provide low aggregate sputtering errors based on predicted process-induced sputtering errors. For example, multiple candidate design variations may be designed for a sample (e.g., a wafer) undergoing a known manufacturing process. The manufacturing process may include one or more steps known for generating one or more types of process-induced sputtering defects in the sputtering target. Process-induced sputtering errors associated with these process-induced sputtering defects are determined, and candidate design variations predicted to provide minimum aggregate sputtering errors are selected for manufacturing.

[0021] For the purposes of this disclosure, the term "overlay" is generally used to describe the relative position of features on a sample fabricated by two or more photolithographic patterning steps, while the term "overlay error" describes the deviation of a feature from its nominal arrangement. For example, a multilayer device may comprise features patterned on multiple sample layers using different photolithographic steps for each layer, where the alignment of features between layers must typically be tightly controlled to ensure proper device performance. Overlay measurements in this context can characterize the relative position of features from different photolithographic steps on a single layer. Overlay measurements are typically performed on a dedicated overlay target printed using the same steps as the device features. In this way, the features of the overlay target can be designed to facilitate overlay measurements, and the accuracy of the overlay target measurements is important for determining the accuracy of the overlay placement.

[0022] Several categories of factors exist that can compromise the accuracy of sputtering metrology. One category of these factors stems from process effects arising from process steps such as etching, deposition, and chemical mechanical planarization (CMP). These process steps are typically tuned to the performance of device features. Unfortunately, sputtering targets cannot be manufactured to perfectly resemble the device structure. Sputtering targets have relatively large periodicity or structural dimensions, while the periodicity and structural dimensions of device features are much smaller. Therefore, process effects on sputtering targets can be more detrimental to the sputtering targets than to the device structure tuned to its process steps.

[0023] For a set of target layouts, the inaccuracy of the stacking measurement between two stacked targets (e.g., stacking error) can generally be determined by evaluating both the phase asymmetry and amplitude asymmetry of the two stacked targets:

[0024] (1)

[0025] Where P is the interval between features. and And is phase asymmetry and and That is, amplitude asymmetry.

[0026] Based on Equation 1, if the target layout can be designed by controlling phase asymmetry and amplitude asymmetry, then the accuracy of the stacked target measurement will vary with or be proportional to the pitch, making the design of stacked targets with smaller pitches and increased accuracy an easy task. However, process steps (e.g., etching, deposition, CMP) can increase the phase asymmetry and amplitude asymmetry of the stacked features, which counteracts attempts to increase the accuracy of the target layout by producing variations in known stacked targets with smaller pitches.

[0027] This paper describes a system and method for determining the effect of process steps on asymmetry and selecting candidate design variations of the target layout based on these process effects.

[0028] For reference Figures 1A to 7 The system and method for selecting qualified stacked targets are described in more detail according to one or more embodiments of the present disclosure.

[0029] Figure 1A A block diagram illustrating a system 1 for designing, manufacturing, and measuring stacked targets according to one or more embodiments of the present disclosure.

[0030] In this embodiment, system 1 includes a target design system 10, a manufacturing system 20, and a stacking metrology system 30. The target design system 10 generates candidate design variations for the target layout and selects a final design variation based on the predicted design and design error measurements. The manufacturing system 20 includes process tools 22 for manufacturing one or more stacked targets based on the final design variation. The stacking metrology system 30 generates measurements of the manufactured stacked targets. The target design system 10, manufacturing system 20, and stacking metrology system 300 can communicate with each other within system 1, can operate separately within system 1, or can selectively communicate with each other within system 1. Therefore, Figure 1A System 1 in this document is presented for illustrative purposes and is not intended to limit this disclosure to its exact form.

[0031] In some embodiments, the target design system 10, manufacturing system 20, and stacking metrology system 30 include a controller 32 having one or more processors 34 configured to execute program instructions stored in memory 36. For example, each of the target design system 10, manufacturing system 20, and stacking metrology system 30 may include a corresponding controller 32a to 32c having one or more corresponding processors 34a to 34c and corresponding memories 36a to 36c. In another example, one or more of the target design system 10, manufacturing system 20, and stacking metrology system 30 are controlled by a main system controller.

[0032] Figure 1B A block diagram view illustrating a stacked metering system according to one or more embodiments of the present disclosure.

[0033] In an embodiment, the stacking metrology system 30 includes an optical subsystem 102 for generating metrology data from a stacking target 104 on a sample 106 (e.g., a wafer). The optical subsystem 102 can provide various types of measurements related to semiconductor manufacturing. For example, the optical subsystem 102 can provide one or more metrological measurements on one or more metrological targets, such as, but not limited to, critical dimensions (e.g., the width of a manufactured feature at a selected height), stacking of two or more layers, sidewall angles, film thickness, or process-related parameters (e.g., the focus position of the sample during a lithography step or the exposure dose of the illumination during a lithography step).

[0034] Process tool 22 may comprise any type of manufacturing tool known in the art suitable for manufacturing one or more patterned layers of an electronic device. Printed features on a sample associated with the sample layer may be manufactured by a series of additive or subtractive process steps, such as, but not limited to, one or more material deposition steps, one or more photolithography steps, one or more etching steps, or one or more stripping steps. Therefore, process tool 22 may comprise, but is not limited to, a material deposition system, a photolithography system, an etching system, or a stripping system.

[0035] Figure 2 This is a flowchart illustrating the steps performed in a method 200 for designing a stacked target according to one or more embodiments of the present disclosure. The embodiments and implementation techniques previously described herein in the context of the stacked metrology system 30 are intended to be interpreted as extending to method 200. However, it should be further noted that method 200 is not limited to the architecture of the stacked metrology system 30.

[0036] In an embodiment, method 200 includes step 202: identifying or receiving multiple candidate design variations of the target layout of the stacked target 104. The stacked target can be manufactured based on layout data of the target layout. Many candidate design variations (e.g., stacking variations) can be generated from known target layouts via the target design system 10. Candidate design variations can also be identified / manufactured from other known target layouts or generated target layouts that have been regenerated.

[0037] In an embodiment, the method includes step 204: determining one or more process-induced target defects among multiple candidate design variations when manufactured using a known manufacturing process (e.g., etching, CMP). For example, process-induced target defects may include defects induced by polishing processes, such as target feature asymmetry. Process-induced target defects arising from known manufacturing processes can be determined empirically through experiments. As an example, for a manufacturing process step such as mechanical polishing, a set of stacked targets with different pitches can be manufactured and polished to determine which target features at a specific pitch are sensitive to mechanical polishing. In another example, different deposition processes can be applied to a set of stacked targets to determine whether the metal deposited or a specific type of metal used in the deposition is sensitive to mechanical polishing. Process-induced target defects arising from known manufacturing processes can also be determined via simulation. For example, virtual stacked targets can be tested for sensitivity to mechanical polishing based on data from previous experiments or based on a trained model via target design system 10 or other computational systems.

[0038] In an embodiment, method 200 includes step 206: determining one or more process-induced overlap errors associated with one or more process-induced target defects among multiple candidate design variations when measured using a known metrology formulation. For example, the metrology formulation may include data that scans the target pair at a specific angle relative to a specific wavelength of light, generating determined data that includes asymmetries (e.g., phase asymmetry and amplitude asymmetry) of the target pair or one or more features of the target pair. After quantifying the asymmetry, overlap errors associated with the asymmetry can be calculated. Asymmetries in the overlap features can affect the accuracy of measurements performed on the overlap target 104. For example, measurements of overlap features with high asymmetry can result in less accurate measurements (e.g., fewer measurements representing the actual dimensions of the overlap features) than measurements of overlap features with low asymmetry. Step 206 may further include determining one or more process-induced overlap errors associated with one or more process-induced target defects among multiple candidate design variations when measured using a known metrology formulation based on simulation.

[0039] In one embodiment, method 200 includes step 208: selecting a final design variation from a plurality of candidate design variations that provides the minimum aggregated overlay error based on one or more process-induced overlay errors. For example, the impact of asymmetry in measurement errors that could cause one or more features within a particular candidate design variation on accuracy measurements can be individually assessed, and then the overall aggregated overlay error measurement impact can be determined for said particular candidate design variation. After determining the aggregated overlay errors of the plurality of candidate design variations (via one or more processors 34a of the target design system 10), the candidate design variation with the minimum aggregated error can be selected.

[0040] In one embodiment, method 200 includes step 210: fabricating a stacked target 104 with a final design change on sample 106. For example, the stacked target 104 with the final design change can be fabricated on a wafer via process tool 22.

[0041] In an embodiment, method 200 includes step 212: determining a stacking measurement of the stacked targets using a known metrology. For example, the stacking measurement may be measured via optical subsystem 102.

[0042] In embodiments, one or more process-induced overlay errors include categories of avoidable process-induced overlay errors associated with categories of avoidable process-induced defects, wherein the categories of avoidable process-induced target defects are subsets of one or more process-induced target defects. For example, avoidable process-induced target defects include process-induced target defects that can be avoided by selecting specific design features that resist the effects of defects, such as asymmetric effects caused by the manufacturing process. For example, avoidable process-induced target defects may include defects in metal-filled etched trenches on the oxide surface of a polished overlay target 104. Polishing the metal introduces asymmetric defect errors on the surface, which are worse when the trenches are not etched or have been filled with oxide.

[0043] In embodiments, one or more process-induced stacking errors include categories of unavoidable process-induced stacking errors associated with categories of unavoidable process-induced target defects, wherein the category of unavoidable process-induced target defects is a subset of one or more process-induced target defects. For example, unavoidable process-induced target defects may include process-induced target defects caused by processes in which anti-process design features cannot be selected. For example, for stacks consisting only of oxide surfaces, there may be no other alternatives for reducing errors generated by polishing steps (e.g., removal of metal surfaces as described above).

[0044] Although embodiments of method 200 are discussed herein, it should be further considered that various steps of method 200 may be included, excluded, rearranged, and / or implemented in many ways without departing from the spirit of this disclosure. Therefore, the above embodiments and implementations of method 200 are included by way of example only and are in no way intended to limit this disclosure. It should be further considered that each of the embodiments of the methods described above may include any other steps of any other method described herein.

[0045] Figure 3 This is a conceptual diagram of a stacked target 104 according to one or more embodiments of the present disclosure. The stacked target 104 corresponds to a target layout, and design candidate variations of the target layout may include changes or alterations to one or more features or sections of the target layout.

[0046] Figure 3The stacking target 104 is suitable for image-based stacking or various diffraction-based stacking methods. For example, the stacking target 104 may comprise four units 304a to 304d, referred to herein as quadrants of the stacking target 104. Each unit 304a to 304d may comprise a first layer printed feature 306 positioned on a first layer 308 of the sample 106 and a second layer printed feature 310 positioned on a second layer 312 of the sample 106. The printed features may comprise segmented features separated by thick monolithic features and / or grooved features (e.g., constructed with repeatable structures pitched and with critical dimensions according to design rules or approximate design rules). It should be understood that... Figure 3 , 4 The stacked target 104 shown in 5A to 5B is representative of the stacked target 104 and is not intended to limit the scope of the stacked target 104 or the design of the stacked target.

[0047] Cells 304b and 304d can be configured to provide stacking measurements along the X direction, such as... Figure 3 As illustrated in the description. For example, overlay measurements along the X direction can be performed by directly comparing the relative positions of the first layer printed features 306 and the second layer printed features 310 within each cell or between cells 304b and 304d. In another example, overlay measurements along the X direction can be performed by comparing points of rotational symmetry (e.g., rotational symmetry, reflection symmetry, or mirror symmetry) between the first layer printed features 306 distributed across cells 304b and 304d with points of symmetry between the second layer printed features 310 distributed across cells 304b and 304d. Similarly, cells 304a and 304c can be configured to provide overlay measurements along the Y direction, such as... Figure 3 As explained in the document. The candidate design changes for section 314 of the first layer 308 are as follows: Figure 4 Further details are provided below.

[0048] Figure 4 This is a close-up top view illustrating candidate design variations of segments 314 (segments 314a and 314b) of the stacked target 104 according to one or more embodiments of the present disclosure. Segments 314a to 314b are considered candidate design variations of the same target layout. It should be considered that one or more categories of features exhibited in segments 314a to 314b are process-robust, relying on reduced asymmetry effects for post-process measurement accuracy.

[0049] Segments 314a and 314b each contain feature groups 400a to 400j (e.g., each feature group 400a to 400j is displayed as a design regular grating with finely spaced vertical lines), and each feature group 400a to 400j has coarse pitch spacings 402a to 402h. Although both segments 314a and 314b originate from the stacked target 104, segment 314a is shown to have flat (e.g., non-grooved, as indicated by the white appearance) coarse pitch spacings 402a to 402d, while the coarse pitch spacings 402f to 402h of segment 314b contain trenches 404a to 404d filled with a layer of metal (e.g., copper).

[0050] Figure 5A A side view 500 illustrating a segment 314a of a stacked target 104 according to one or more embodiments of the present disclosure, and an illustration 502 illustrating a portion 504 of the segment 314a of the stacked target 104.

[0051] Illustration 502 shows two features 506a to 506b from feature group 400b. These features 506a to 506b contain trenches 508a to 508b that are filled with metal (e.g., copper). The trenches 508a to 508b extend into layer 510 of sample 106.

[0052] Figure 5A Further illustration is provided of process-induced target defects 514a to 514b (e.g., “V”-shaped indentations appearing on surface 516 of the stacked target 104). These process-induced target defects 514a to 514b are caused by one or more manufacturing processes (specifically, polishing), resulting in increased asymmetry. In contrast, surface 516 corresponding to coarse pitch 402a contains a non-grooved oxide layer, which is relatively unaffected by the polishing step, resulting in a flat surface 516 with high symmetry. Because the contribution of the asymmetry of surface 516 corresponding to coarse pitch 402a to the overall asymmetry of segment 314a is minimal, the main contribution of asymmetry to segment 314a is provided by the small asymmetries 514a to 514b of fine features 506a to 506b. These process-induced target defects 512a to 512b refer to unavoidable process-induced target defects, as there appear to be no feasible design changes that could be made to these fine structures to attempt to reduce the relatively small asymmetry effect. Any defects detected in surface 516 corresponding to coarse pitch 402a also refer to unavoidable errors, since there are no feasible design changes that would reduce any asymmetric effect, such as removing the metal layer.

[0053] produce Figure 5AThe overlapping features of unavoidable process-induced target defects shown in the diagram can be further classified into priority and non-priority features. For example, although the process-induced defects associated with coarse pitch 402a are unavoidable, the applicant has found that reducing the design parameters (pitch) of coarse pitch 402a can reduce post-process measurement errors and also reduce the impact of the asymmetry of adjacent features 506a to 506b on measurement errors. Features susceptible to unavoidable process defects that can be redesigned to reduce the impact of asymmetry by changing design parameters are called "priority features." In contrast, changes to the design parameters of features 506a to 506b in feature group 400b do not appear to change their asymmetry or the impact of the asymmetry of adjacent features on measurement errors and are considered non-priority features.

[0054] Figure 5B A side view 500 illustrating a segment 314b of a stacked target 104 according to one or more embodiments of the present disclosure, and an illustration 502 illustrating a portion 504 of the segment 314b of the stacked target 104.

[0055] Section 314b is similar to Figure 5A Section 314a is polished and contains elements similar to Figure 5A The process-induced target defects 514a to 514b in section 314a are characterized by 506a to 506b. However, Figure 5B Segment 314b further includes a deep recessed surface 520 (e.g., process-induced target defect 514c) corresponding to the coarse pitch spacing 402a, which includes wide trenches 404a filled with metal (e.g., copper). The polishing effect is more pronounced in the coarse trenches 404a than in the fine trenches 508a to 508b, resulting in a greater asymmetry effect. The asymmetry in the coarse pitch spacings 508a to 508b significantly contributes to the aggregate overlap error of segment 314b, and the polished stacked target 104 including the metal-filled trenches 404a can have a higher aggregate overlap error than the polished stacked target 104 not including the metal-filled trenches 404a.

[0056] Process-induced target defects 512a to 512b (e.g. Figure 5B The process-induced target defects generated in section 314b are referred to as avoidable process-induced target defects because the error caused by the asymmetry of the coarse pitch spacing 402a is large and can be avoided by not generating wide grooves 404a in the coarse pitch spacing 402a or by filling the grooves 404a with oxide.

[0057] like Figures 5A to 5BAs shown, process-induced target defects 514 can be determined based on their tendency to generate asymmetry and / or based on design parameters to reduce asymmetry and errors. For example, process-induced target defects 514a to 514b may contain small asymmetries formed by small features (e.g., features 506a to 506b of feature group 400b), where the asymmetry is limited to approximately the width of each groove 508a to 508b (e.g., feature asymmetry is periodic with pitch). Due to the proximity of features 516a to 516b of the fine grating feature group 400, it is almost impossible to change the design regarding the spacing between features 516a to 516b, which would otherwise have an impact on reducing asymmetry effects and overlap errors.

[0058] and Figure 5A The surface 516 associated with the coarse pitch spacing 402 exhibits negligible asymmetry and negligible target defects, and the asymmetry effects of the coarse pitch spacing 402a and adjacent features 506a to 506b (e.g., characteristic of the phase shift of the measurement signal associated with phase asymmetry) vary with or are proportional to the pitch. Therefore, when with Figure 5A When the phase shift of the measurement signal of the surface 516 associated with the coarse pitch spacing 402a is transformed into the overlay error (e.g., by multiplying the phase shift by P / 2π), the resulting overlay error varies with or is proportional to the pitch, and efforts to design candidate design variations with pitch reduction at the coarse pitch spacing 402a may reduce the overlay error of the overlay target 104.

[0059] In comparison, with Figure 5B The surface 516 associated with the coarse pitch 402 exhibits large process target defects 514c with relatively large asymmetry associated with the coarse pitch 402. When the large phase shift signal of this section 314b is converted into overlap error, the resulting overlap error does not change with pitch or is not proportional to pitch, suggesting... Figure 5B A reduction in the pitch between any of the features in segment 314b will not result in a reduction in the stacking error of the stacked target 104. The determination of the type of process-induced target defects associated with the features of the candidate design change (e.g., avoidable and unavoidable) and whether the feature contains parameters that can be improved (e.g., prioritized) can be used as criteria for selecting the final design change.

[0060] By selecting a stacking target 104 that is more manageable for semiconductor manufacturing process steps, candidate design variations of the stacking target can lead to improved accuracy designs for stacking metrology performed after the manufacturing process steps. For example, when process effects on the coarse pitch 402 are unavoidable, if the stacking error scales with the pitch, the pitch of the coarse pitch 402 can be reduced (e.g., by reducing coarse periodicity). In another instance, easily manageable auxiliary features (e.g., material-filled trenches that do not produce large asymmetries) can be added to the coarse pitch 402. For example, some processes (e.g., polishing steps, as described herein) can have little effect on the asymmetry of the coarse pitch 402, provided that the etched areas are filled with oxide rather than copper.

[0061] In an embodiment, the target layout includes features distributed at a coarse pitch (e.g., coarse pitch spacing 402a), wherein a first subset of multiple candidate design variations includes oxides in the spaces between the features, wherein a second subset of multiple candidate design variations includes metals in the spaces between the features, wherein categories of avoidable process-induced target defects include target asymmetries associated with the metals in the spaces between the features, and wherein selecting a final design variation from multiple candidate design variations includes selecting a final design variation from a first subset of multiple candidate design variations. For example, the multiple candidate target variations may include a first subset (which is similar to a flat oxide surface containing coarse pitch spacing 402a). Figure 5A The stacked target 104) and the second subset (which is similar to the metal-filled trench between the coarse pitch spacing 402a associated with avoiding process-induced target defects and large target asymmetries) are included. Figure 5B (The splicing of splices in the process). When selecting the final design variation from two subsets (e.g., via splice design system 10), the first subset may be selected because it is associated with the reduction of asymmetry changes after the process steps and thus the reduction of splicing error.

[0062] In an embodiment, the value of the aggregated overlap error associated with the category of unavoidable process-induced overlap error scales with the design parameters of the target layout, wherein selecting the final design variation from multiple candidate design variations includes selecting the final design variation with the value of the design parameters that provides the minimum aggregated overlap error. For example, Figure 5A The stacked target 104 in the model has a coarse pitch spacing 402a associated with unavoidable process-induced stacking errors that scale with design parameters (pitch). In contrast, Figure 5B The stacked target 104 in the middle has a property that does not scale with pitch and therefore has a higher value than Figure 5A The coarse pitch spacing in the coarse pitch 402a is an avoidable process-induced overlap error associated with the overlap error. Because Figure 5A and Figure 5BThe difference between the coarse pitch spacing 402 is the only design difference between the two stacked targets, and the error associated with the coarse pitch spacing 402 is... Figure 5B The stacked target material 104 is higher than Figure 5A The stacked target material is 104, so Figure 5B The total stacking error of the stacked target 104 must be higher than Figure 5A The stacked target material 104, and selected Figure 5A The stacked target material 104.

[0063] Furthermore, because Figure 5A The stacked target 104 is selected and includes design parameters (e.g., pitch) that scale with the stacking error, so it can be based on design parameter values ​​that provide the minimum aggregate stacking error. Figure 5A The stacked target 104 selects the final design variation from multiple candidate design variations. For example, based on Figure 5A Multiple candidate design variations of the stacked target 104 may include a group of candidate design variations with reduced pitch values ​​having a coarse pitch spacing 402a, and the candidate design variation with the smallest pitch that provides the minimum aggregate stacking error is selected.

[0064] In embodiments, one or more process-induced overlap errors may include additional categories of unavoidable process-induced overlap errors associated with additional categories of unavoidable process-induced target defects, wherein the categories of unavoidable process-induced target defects are additional subsets of one or more process-induced target defects, wherein the value of the aggregate overlap error associated with the additional categories of unavoidable process-induced overlap errors remains unchanged relative to additional design parameters of the target layout, and wherein selecting a final design change from multiple candidate design changes includes de-prioritizing the additional categories of unavoidable process-induced target defects. For example, fine grating features 506a to 506b of polishing feature group 400 may produce unavoidable process-induced target defects, resulting in unavoidable process-induced overlap errors. Unlike Figure 5A The error in the coarse pitch spacing 402a of the splice target, and the unavoidable process-induced splice error of features 506a to 506b of feature group 400a, can remain constant relative to the pitch. If the unavoidable process-induced splice error of features 506a to 506b of feature group 400a remains constant relative to the pitch, then the aggregate splice error associated with features 506a to 506b of feature group 400 can also remain constant relative to the pitch. Therefore, the categories of fine features 506a to 506b of feature group 400a and the unavoidable process-induced splice defects associated with fine features 506a to 506b of feature group 400a can be de-prioritized during the selection process.

[0065] In an embodiment, determining the process-induced overlap error associated with process-induced target defects of multiple candidate design variations when measured using a known metrology may include manufacturing and testing the candidate design variations. For example, one or more test sample candidate design variations may be manufactured, and one or more test measurements may be generated on the test samples using a known metrology. The process-induced overlap error associated with one or more process-induced target defects of multiple candidate design variations can be determined from the test measurements.

[0066] In the embodiments, the selection of candidate design variations includes a method based on overlap error (e.g., OVL). err Candidates are selected based on the relationship between the feature and the pitch. For example, if a candidate contains one or more features in which the overlap error varies with the pitch, then the candidate design variation feature can be selected. For example, if a candidate contains one or more features in which the overlap error is proportional to the pitch (e.g., where the asymmetry is constant or decreases as the pitch decreases), then the candidate design variation feature can be selected. Candidate design variations can also be discarded based on identifying one or more features in which the overlap error does not vary with the pitch (e.g., is not proportional to the pitch). Whether a feature has an overlap error that varies with the pitch is partly based on the process-induced target defects that affect feature asymmetry, as described herein. For example, mechanical polishing of a set of coarse or wide periodic features can produce asymmetry, which causes the overlap error to be non-variable with or non-proportional to the pitch. Features classified as having an overlap error that varies with the pitch may have specific values. For example, selected candidate design variations (e.g., final design variations) containing features associated with overlap error that varies with pitch can also be selected to undergo further design iterations, which include features designed with smaller pitches to reduce overlap error.

[0067] After the final design changes are determined, the overlay target 104 based on the final design changes is printed onto the sample 106 via process tool 22. For example, the printed overlay target 104 may include the final design changes, such as not including a coarse pitch 402a that does not include a copper-filled trench 404a. As another example, the printed overlay target 104 may include the final design changes, which include a pitch smaller than the coarse pitch 402a of the original target layout.

[0068] After the stacked target 104 is manufactured, it can then be measured via optical subsystem 102 or other metrological tools. The measurement may include a stacking measurement between the stacked target 104 and another stacked target previously printed in a lower layer of sample 106.

[0069] Additional embodiments of this disclosure generate overlay correction numbers for overlay measurements based on overlay targets 104 (e.g., overlay targets 104 based on a final design change). These overlay correction numbers can then be provided to process tools (e.g., lithography tools) as feedback and / or feedforward data. For example, overlay measurements measured on a sample and associated with the current process step can be used to compensate for drift and maintain the overlay within selected tolerances for process steps on subsequent samples in the same or subsequent batches. As another example, overlay measurements associated with the current process step can be feedforwarded to adjust subsequent process steps to compensate for any measured overlay errors.

[0070] As used throughout this disclosure, the term "correction number" generally refers to data that can be used to correct the alignment of process tools to improve control over subsequent photolithographic patterning relative to the stack-up performance. In general, the correction number allows wafer fabrication to proceed within predetermined desired limits by providing feedback and feedforward to improve process tool alignment.

[0071] Figure 6 A simplified schematic diagram illustrating a view of a stacked metering system 30 according to one or more embodiments of the present disclosure.

[0072] In an embodiment, the overlay metrology system 30 includes an optical subsystem 102 for acquiring overlay signals from overlay targets based on any number of overlay formulations. For example, the optical subsystem 102 may direct illumination to sample 106 and may further collect light or other radiation emitted from sample 106 to generate overlay signals suitable for determining overlays of two or more sample layers. The optical subsystem 102 may be any type of optical subsystem known in the art suitable for generating overlay signals suitable for determining overlays associated with overlay targets on sample 106. The optical subsystem 102 may operate selectively in an imaging mode or a non-imaging mode. The optical subsystem 102 includes an illumination source 602 configured to generate at least one illumination beam 604.

[0073] In one embodiment, optical subsystem 102 guides illumination beam 604 to sample 106 via illumination path 606. Illumination path 606 may include one or more optical components adapted to modify and / or adjust illumination beam 604 and guide illumination beam 604 to sample 106. In one embodiment, illumination path 606 includes one or more illumination path lenses 608. In one embodiment, illumination path 606 includes one or more illumination path optics 610 for shaping or otherwise controlling illumination beam 604. Optical subsystem 102 includes objective lens 612 for focusing illumination beam 604 onto sample 106 (e.g., a stacked target having stacked target features positioned on two or more layers of sample 106). Optical subsystem 102 may include beam splitter 613, which is oriented such that objective lens 612 can simultaneously guide illumination beam 604 to sample 106 and collect light from sample 106. In another embodiment, sample 106 is placed on sample stage 614, which is adapted to fix sample 106 and is further configured to position sample 106 relative to illumination beam 604.

[0074] In one embodiment, the optical subsystem 102 includes one or more detectors 616 configured to capture light or other light emitted from the sample 106 (e.g., a stacked target on the sample 106) via a light-collecting path 618. The light-collecting path 618 may include one or more optical elements suitable for modifying and / or adjusting the collected light from the sample 106. In one embodiment, the light-collecting path 618 includes one or more light-collecting path lenses 620 (e.g., for collimating the illumination beam 604 or for relaying the pupil and / or field plane), which may include (but are not required to include) an objective lens 612. In another embodiment, the light-collecting path 618 includes one or more light-collecting path optics 622 for shaping or otherwise controlling the collected light 130. For example, the light-collecting path optics 622 may include, but are not limited to, one or more field stops, one or more pupil stops, one or more polarizers, one or more filters, one or more beam splitters, one or more diffusers, one or more homogenizers, one or more apodizers, one or more beam shapers, or one or more mirrors (e.g., static mirrors, translational mirrors, or scanning mirrors).

[0075] Figure 7 This is a conceptual diagram illustrating a process tool 22 configured as a photolithography tool according to one or more embodiments of the present disclosure.

[0076] For example, a process tool 22 configured as a photolithography tool can fabricate a device structure including transistors and corresponding metrology targets (including the stacked target 104 previously described herein). In embodiments, the process tool 22 includes a photolithography illumination source 700 configured to generate one or more illumination beams 704. The illumination from the photolithography illumination source 700 can have any spatial distribution (e.g., illumination pattern). For example, the photolithography illumination source 700 can generate any number of on-axis illumination beams 704 in which illumination propagates along (or parallel to) the optical axis 706 and / or any number of off-axis illumination beams 704 in which illumination propagates at an angle to the optical axis 706.

[0077] In another embodiment, the process tool 22 includes a mask support 708. The mask support 708 is configured to hold the pattern mask 710. In another embodiment, the process tool 22 includes a set of projection optics 712 configured to project an image of the pattern mask 710, illuminated by one or more illumination beams 704, onto a sample 106 placed on a sample stage 614 to produce printed pattern elements corresponding to the image of the pattern mask 710. In another embodiment, the mask support 708 may be configured to actuate or position the pattern mask 710. For example, the mask support 708 may actuate the pattern mask 120 to a selected position relative to the projection optics 712 of the system 30.

[0078] One or more processors 34 of the controller 32 may comprise any processor or processing element known in the art. For the purposes of this disclosure, the terms “processor” or “processing element” may be broadly defined to cover any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application-specific integrated circuit (ASIC) devices, one or more field-programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, one or more processors 34 may comprise any device configured to execute algorithms and / or instructions (e.g., program instructions stored in memory). In embodiments, one or more processors 34 may embody a desktop computer, a host computer system, a workstation, a graphics computer, a parallel processor, a network computer, or any other computer system configured to execute programs configured to operate or be combined with operations on the metering system 30, as described throughout this disclosure.

[0079] Furthermore, different subsystems of the stacking metering system 30 (e.g., detector 616) may include processors or logic elements suitable for implementing at least a portion of the steps described in this disclosure. Therefore, the above description should not be construed as limiting the embodiments of this disclosure but is merely illustrative. Additionally, the steps described throughout this disclosure may be implemented by a single controller 32 or, alternatively, by multiple controllers. Furthermore, controller 32 may comprise one or more controllers housed within a common housing or multiple housings. In this manner, any controller or combination of controllers may be individually packaged as a module suitable for integration into the stacking metering system 30.

[0080] Memory media 36 may comprise any storage medium known in the art suitable for storing program instructions executable by one or more associated processors 132. For example, memory media 36 may comprise non-transitory memory media. As another example, memory media 36 may comprise, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical storage devices (e.g., magnetic disks), magnetic tape, solid-state drives, and the like. It should be further noted that memory media 36 may be housed together with one or more processors 34 in a common controller housing. In embodiments, memory media 36 may be remotely located relative to the physical location of one or more processors 34 and controller 32. For example, one or more processors 34 of controller 32 may access remote storage (e.g., a server) accessible via a network (e.g., the Internet, an intranet, and the like).

[0081] The objects described herein sometimes refer to different components contained within or connected to different other components. It should be understood that such depicted architectures are merely illustrative, and in fact, many other architectures can be implemented to achieve the same functionality. Conceptually, any arrangement of components that achieve the same function is effectively “associated” to achieve the desired function. Therefore, regardless of the architecture or intermediate components, any two components combined herein to achieve a particular function can be considered “associated” with each other to achieve the desired function. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” with each other to achieve the desired function, and any two components that can be suchly associated can also be considered “operably coupled” with each other to achieve the desired function. Specific examples of “operably coupled” include, but are not limited to, physically mating and / or physically interacting components and / or wirelessly interacting and / or logically interacting components.

[0082] Those skilled in the art will understand that, in general, the terms used herein and, in particular, the appended claims (e.g., the body of the appended claims) are intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “including but not limited to,” etc.). Those skilled in the art will further understand that if a particular number of claims is intended to be introduced, this intention will be explicitly stated in the claims, and if such a statement is not made, then this intention does not exist. For example, to aid understanding, the appended claims may contain the use of introductory phrases “at least one” and “one or more” to introduce the claims. However, the use of such phrases should not be construed as implying that the introduction of a claim statement by the indefinite article "a" limits any particular claim containing such an introductory claim statement to an invention containing only one such statement, even if the same claim contains the introductory phrase "a or more" or "at least one" and an indefinite article such as "a" (e.g., "a" should generally be interpreted as meaning "at least one" or "a or more"); the same applies to the use of definite articles used to introduce claim statements. Furthermore, even if a specific number of claim statements is explicitly stated, those skilled in the art will recognize that such a statement should generally be interpreted as meaning at least a number of statements (e.g., a bare statement of "two statements" without other modifiers generally means at least two statements or two or more statements). Furthermore, in examples where the convention of "at least one of A, B, and C, etc." is used, this structure is generally intended to have the meaning commonly understood by those skilled in the art (e.g., "a system having at least one of A, B, and C" includes, but is not limited to, systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or both A, B, and C, etc.). In examples where the convention of "at least one of A, B, or C, etc." is used, this structure is generally intended to have the meaning commonly understood by those skilled in the art (e.g., "a system having at least one of A, B, or C" includes, but is not limited to, systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or both A, B, and C, etc.). Those skilled in the art will further understand that virtually any disjunctive terms and / or phrases presenting two or more alternatives, whether in the detailed description, claims, or drawings, should be understood to consider the possibility of including one, any one, or both of the items. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0083] Although specific aspects of the subject matter described herein have been shown and described, those skilled in the art will understand that, based on the teachings herein, changes and modifications can be made without departing from the subject matter and its broader aspects as described herein, and therefore the appended claims should cover all such changes and modifications within their scope, as they are true in spirit and within the scope of the subject matter described herein. Furthermore, it should be understood that the invention is defined by the appended claims.

Claims

1. A system comprising: A controller includes one or more processors configured to execute program instructions stored on a memory device, wherein the program instructions cause the one or more processors to: Multiple candidate design variations for the target layout of the stacked target materials are received; Determine one or more process-induced defects in the target material when the plurality of candidate design variations are manufactured using a known manufacturing process; Identify one or more process-induced stacking errors associated with one or more process-induced target defects of the plurality of candidate design variations when measured using a known metrology formulation; and A final design variation is selected from the plurality of candidate design variations, which provides the minimum aggregated overlap error based on the one or more process-induced overlap errors.

2. The system of claim 1, wherein the program instructions cause the one or more processors to direct the one or more process tools to manufacture the stacked target having the final design change on the sample.

3. The system of claim 2, wherein the program instructions cause the one or more processors to determine the stacking measurement of the stacked targets based on measurement data from one or more metrology tools generated using the known metrology formulation.

4. The system according to claim 1, wherein the one or more process-induced overlap errors include: A category of avoidable process-induced splicing errors associated with a category of avoidable process-induced splice defects, wherein the category of avoidable process-induced splice defects is a subset of the one or more process-induced splice defects. The selection of the final design variation from the plurality of candidate design variations includes selecting the final design variation of the category that does not have avoidable process-induced target defects.

5. The system of claim 4, wherein the target layout comprises features distributed by a coarse pitch, wherein a first subset of the plurality of candidate design variations comprises oxides in the space between the features, wherein a second subset of the plurality of candidate design variations comprises metals in the space between the features, wherein the category of avoiding process-induced target defects comprises target asymmetry associated with the metals in the space between the features, wherein selecting the final design variation from the plurality of candidate design variations comprises selecting the final design variation from the first subset of the plurality of candidate design variations.

6. The system according to claim 1, wherein the one or more process-induced overlap errors include: A category of unavoidable process-induced splice errors associated with a category of unavoidable process-induced target defects, wherein the category of unavoidable process-induced target defects is a subset of the one or more process-induced target defects.

7. The system of claim 6, wherein the value of the aggregated overlap error associated with the category of unavoidable process-induced overlap error scales with the design parameters of the target layout, wherein selecting the final design variation from the plurality of candidate design variations includes selecting the final design variation having a value of the design parameters that provides the minimum aggregated overlap error.

8. The system according to claim 7, wherein the design parameters include: The pitch of the features in the target material layout.

9. The system of claim 7, wherein the one or more process-induced overlap errors include: An additional category of unavoidable process-induced sputtering errors associated with an additional category of unavoidable process-induced sputtering defects, wherein the category of unavoidable process-induced sputtering defects is an additional subset of the one or more process-induced sputtering defects, wherein the value of the aggregated sputtering error associated with the additional category of unavoidable process-induced sputtering errors remains unchanged relative to additional design parameters of the sputtering layout, wherein selecting the final design change from the plurality of candidate design changes includes de-prioritizing the additional category of unavoidable process-induced sputtering defects.

10. The system of claim 1, wherein at least one of the one or more process-induced target defects comprises: Asymmetry in target features induced by the polishing process.

11. The system of claim 1, wherein determining the one or more process-induced overlap errors associated with the one or more process-induced target defects of the plurality of candidate design variations when measured using a known metrology formula comprises: Simulate the process-induced overlap error associated with the one or more process-induced target defects of the multiple candidate design variations when measured using the known metrology formula.

12. The system of claim 1, wherein determining the one or more process-induced overlap errors associated with the one or more process-induced target defects of the plurality of candidate design variations when measured using the known metrology formula comprises: The candidate design variations are fabricated on one or more test samples; One or more test measurements are generated using the known metrology formula to produce the multiple candidate design variations; and Determine the one or more process-induced overlap errors associated with the one or more process-induced target defects of the one or more candidate design variations when measured using the known metrology formula based on one or more test measurements.

13. The system of claim 1, wherein the program instructions cause the one or more processors to provide one or more stacking correction numbers based on one or more stacking measurements.

14. A method for designing stacked targets, comprising: Identify multiple candidate design variations of the target layout for the stacked targets; Determine one or more process-induced defects in the target material when the plurality of candidate design variations are manufactured using a known manufacturing process; Identify one or more process-induced stacking errors associated with one or more process-induced target defects of the plurality of candidate design variations when measured using a known metrology formulation; and A final design variation is selected from the plurality of candidate design variations, which provides the minimum aggregated overlap error based on the one or more process-induced overlap errors.

15. The method of claim 14, further comprising fabricating the stacked target having the final design change on a sample.

16. The method of claim 15, further comprising determining a stacking measurement of the stacked target using the known metrological formulation.

17. The method of claim 14, wherein the one or more process-induced overlap errors include: A category of avoidable process-induced splicing errors associated with a category of avoidable process-induced splice defects, wherein the category of avoidable process-induced splice defects is a subset of the one or more process-induced splice defects. The selection of the final design variation from the plurality of candidate design variations includes selecting the final design variation of the category that does not have avoidable process-induced target defects.

18. The method of claim 17, wherein the target layout comprises features distributed by a coarse pitch, wherein a first subset of the plurality of candidate design variations comprises oxides in the space between the features, wherein a second subset of the plurality of candidate design variations comprises metals in the space between the features, wherein the category of avoiding process-induced target defects comprises target asymmetry associated with the metals in the space between the features, wherein selecting the final design variation from the plurality of candidate design variations comprises selecting the final design variation from the first subset of the plurality of candidate design variations.

19. The method of claim 14, wherein the one or more process-induced overlap errors include: A category of unavoidable process-induced splice errors associated with a category of unavoidable process-induced target defects, wherein the category of unavoidable process-induced target defects is a subset of the one or more process-induced target defects.

20. The method of claim 19, wherein the value of the aggregated overlap error associated with the category of unavoidable process-induced overlap error scales with the design parameters of the target layout, wherein selecting the final design variation from the plurality of candidate design variations includes selecting the final design variation having the value of the design parameters that provides the minimum aggregated overlap error.

21. The method of claim 20, wherein the design parameters include: The pitch of the features in the target material layout.

22. The method of claim 20, wherein the one or more process-induced overlap errors include: An additional category of unavoidable process-induced sputtering errors associated with an additional category of unavoidable process-induced sputtering defects, wherein the category of unavoidable process-induced sputtering defects is an additional subset of the one or more process-induced sputtering defects, wherein the value of the aggregated sputtering error associated with the additional category of unavoidable process-induced sputtering errors remains unchanged relative to additional design parameters of the sputtering layout, wherein selecting the final design change from the plurality of candidate design changes includes de-prioritizing the additional category of unavoidable process-induced sputtering defects.

23. The method of claim 14, wherein at least one of the one or more process-induced target defects comprises: Asymmetry in target features induced by the polishing process.

24. The method of claim 14, wherein determining the one or more process-induced overlap errors associated with the one or more process-induced target defects of the plurality of candidate design variations when measured using the known metrology comprises: Simulate the process-induced overlap error associated with the one or more process-induced target defects of the multiple candidate design variations when measured using the known metrology formula.

25. The method of claim 14, wherein determining the one or more process-induced overlap errors associated with the one or more process-induced target defects of the plurality of candidate design variations when measured using the known metrology comprises: The candidate design variations are fabricated on one or more test samples; One or more test measurements are generated using the known metrology formula to produce the multiple candidate design variations; and Determine the one or more process-induced overlap errors associated with the one or more process-induced target defects of the one or more candidate design variations when measured using the known metrology formula based on one or more test measurements.

26. The method of claim 14, further comprising providing a stacking correction number based on the values ​​of the stacking measurements to the lithography system.

27. A system comprising: One or more process tools configured to manufacture a stacked target on a sample using a known manufacturing process; A controller comprising one or more processors configured to execute program instructions stored on a memory device, wherein the program instructions cause the one or more processors to: Receive multiple candidate design variations of the target layout for the stacked target materials; Determine one or more process-induced defects in the target material when the plurality of candidate design variations are manufactured using a known manufacturing process; Identify one or more process-induced stacking errors associated with one or more process-induced target defects of the plurality of candidate design variations when measured using a known metrology formulation; A final design variation is selected from the plurality of candidate design variations, which provides the minimum aggregated stacking error based on the one or more process-induced stacking errors; and The one or more process tools are guided to manufacture the stacked target material with the final design changes on the sample.

28. The system of claim 27, wherein the program instructions cause the one or more processors to determine the stacking measurement of the stacked targets based on measurement data from one or more metrology tools generated using the known metrology formulation.

29. The system of claim 27, wherein the program instructions cause the one or more processors to provide one or more stacking correction numbers based on one or more stacking measurements.

Images