Computer-implemented method for testing a controller of an electronic with a simulator and corresponding simulator

Abstract

A computer-implemented method (1) for testing an electronic controller (2) with a simulator (3) is shown and described, wherein the simulator (3) numerically simulates a mathematical circuit model (5) of an electrical circuit (6) with at least one arithmetic unit (4), the calculation of the circuit model (5) is carried out in successive simulation steps (k) with a simulation step duration (T), one simulation step (k) comprises a plurality of temporally successive sub-simulation steps (a, b, c), the circuit (6) comprises at least one switching element (7) which can assume either a switched-on switching state or a switched-off switching state, the current switching state of the switching element (7) of the circuit (6) is determined within one simulation step (k) and the circuit model (5) is adapted to the switching state of the switching element (7), the input variables (u, g) of the circuit model (5) are detected within one simulation step (k), the output variables (y) of the circuit model (5) are calculated, and the output variables (y) are transmitted at least partially to the controller (2) to be tested via a simulator interface (8). Thereby a better testing of the controller (2) corresponding to the actual physical situation is achieved, i.e. at the same time at least a part of the sub-simulation steps (a, b, c) is simulated and the corresponding output variables (y n‑1 , y n , y n+1 ) of the circuit model (5) are calculated and the output variables are averaged to an average output variable (y ‑ n‑1 , y ‑ n , y ‑ n+1 ) and the average output variable is transmitted as an output variable (y n‑1 , y n , y n+1 ) via the controller interface (8) to the controller (2) to be tested.

Description

Technical Field

[0001] This invention relates to a computer-implemented method for testing an electronic controller using a simulator, wherein the simulator numerically simulates a mathematical circuit model of an electrical circuit using at least one arithmetic unit. The calculation of the circuit model is performed in successive simulation steps having a duration of simulation step duration. Each simulation step includes multiple temporally successive sub-simulation steps. The circuit includes at least one switching element, which can be in either an on or off switching state. Within one simulation step, the current switching state of the circuit's switching element is determined and the circuit model is matched to the switching state of the switching element. Within one simulation step, input parameters of the circuit model are detected, output parameters of the circuit model are calculated, and the output parameters are transmitted at least partially to the controller to be tested via a simulator interface. Furthermore, this invention relates to a corresponding simulator for implementing the method and a computer program that, if executed on the simulator's arithmetic unit, implements the method. Background Technology

[0002] The computer-based implementation method mentioned here comes from the field of hardware-in-the-loop (HIL) simulation, in which the controller's environment is simulated partially or completely using a simulator. This makes it possible to verify and test the controller in a simulated environment, rather than in a real physical process—in which the controller will subsequently be applied—without risk.

[0003] A typical example is a controller for an electric drive or an onboard charger, such as a controller from the automotive field, whose environment (in the case of a controller for an electric drive), i.e., the electric drive and, if necessary, other environmental components (such as the vehicle chassis), is simulated using a simulator. For this purpose, the controller connects to the corresponding simulator interface of the simulator via its controller interface so that appropriate signals (power signals of the semiconductor bridge, sensor signals, etc.) can be exchanged as in a real-world controller application. In the case of the controller for an electric drive mentioned as an example, the simulator also includes suitable power electronics modules to simulate the corresponding electrical load (motor, generator, battery) for the controller.

[0004] The controller can exist in different forms: as a research and development controller, which differs from the final hardware implementation; as a final series controller; and as a virtual controller, existing as a software simulation. In the latter case, the simulator and controller are also connected through corresponding I / O interfaces, even if the interfaces are implemented only using data technology.

[0005] The testing of the controller involves running it alongside a simulator to confirm whether the controller and the controls implemented on it achieve the expected performance. This requires not only calculating the mathematical circuit model numerically as accurately as possible, but also performing these calculations in real-time during the simulation: calculations of system performance within a one-second simulation time interval must conclude no later than one second of physical real time so that the simulation results also exist in the desired real-time. The simulation of electrical circuits with high-frequency switching semiconductors is particularly demanding, for example, in power electronic systems with controlled half-bridges, because these systems often have large eigenvalues ​​and thus high rates of change in state parameters compared to mechanical systems.

[0006] The foundation for numerical simulation of electrical circuits is largely the mathematical description of the circuit in time-sequential state space, followed by the time-discretion of the state-space representation required for numerical simulation. This is described in detail in the applicant's published document EP3418924 A1. The time-discrete state-space representation of an electrical circuit then has, for example, the following form (Equation 1, state and output equations):

[0007] z SW These are the switching parameters (current, voltage) of switching elements in an electrical circuit. Li This refers to the measurement parameters of the circuit that are of interest to the user of the simulation. There exist switching elements that are actively turned on or off via control connections. Other switching elements in the electrical circuit are diodes, which, for example, are used in a bridge circuit in antiparallel to the power switch, and the inductor-driven current through these diodes can be eliminated when the power switch is on. These freewheeling diodes—as are naturally other diodes—cannot be actively turned on or off via control connections; rather, the circuit state of these diodes is determined by their electrical connection parameters, i.e., by their terminal voltage or internal diode current.

[0008] To determine the overall switching state of a circuit, it is necessary to consider not only externally imposed switching signals but also internal natural switching conditions. The determination of the overall switching state of the circuit (i.e., the total number of switching states of the existing switching elements) is typically performed once in each simulation step in the prior art, and the calculations of sub-simulation steps are based on the assumption that the switching states of the electrical circuit's switching elements are immutable within a simulation step. The determination of the overall switching state is not reflected in the state-space equations (Equation 1), which involves a separate process that is not performed iteratively but rather occasionally until a stable switching state emerges in all the switching elements of the circuit.

[0009] Switching elements can be mathematically represented differently in circuit models, thus the different types of matching of the switching states of the switching elements to the circuit model are known. In an ideal representation, a closed switching element is an ideally conducting connection, while an open switching element is an ideally interrupted connection in the circuit. The switching of the switching elements thus leads to changes in the circuit structure, and each circuit variant (with 2 in the case of N switching elements) N A circuit variant leads to another state-space representation of the circuit, thus requiring multiple different state-space representations to be used. Other schemes use R-, RC-, and RL equivalent circuits to represent the switching elements with variable values ​​of RLC elements according to the switching state, so that the state-space representation during simulation is non-structurally variable but parametrically variable as the total switching state of the circuit varies.

[0010] Regardless of the type of modeling chosen, it is common practice across various approaches that a simulation step comprises multiple temporally successive sub-simulation steps. The temporal order of these sub-simulation steps depends, for example, on whether subsequent sub-simulation steps are related to the results of earlier sub-simulation steps. In the simulation of circuit models, in the prior art, successive simulation steps are executed strictly sequentially, with the (k+1)th simulation step only executed after the (k)th simulation step has completely concluded. Summary of the Invention

[0011] The objective of this invention is to improve the simulation of electrical circuits so that the output parameters better reflect the actual characteristics of the electrical circuits, and to achieve a more accurate test of the actual physical facts of the controller by transmitting the output parameters to the controller to be tested via the simulator interface.

[0012] This task is solved by the features of the feature portion of independent claim 1 in the computer-implemented method for testing an electronic controller using a simulator as described at the beginning, and by the features of the feature portion of independent claim 10 in the simulator described at the beginning.

[0013] The method according to the invention is characterized in that the simulator simultaneously simulates at least a portion of the sub-simulation steps, thereby calculating multiple time-staggered input parameters based on the circuit model and multiple time-staggered switching states based on the switching elements of the circuit model within the duration of a simulation step, as well as corresponding multiple time-staggered output parameters of the circuit model. The multiple time-staggered calculated output parameters are averaged to obtain an average output parameter, and the average output parameter is transmitted, at least partially, as an output parameter to the controller to be tested via the controller interface.

[0014] The method according to the present invention significantly improves the accuracy of circuit simulation, thereby obtaining output parameters that more accurately reflect the actual physical performance of the circuit. This, in turn, allows for more realistic and precise excitation of the controller under test by the simulator. This results in more reliable test results.

[0015] The present invention is based on the understanding that, in known methods—in which simulation steps are executed strictly sequentially without any time overlap—a response to a changed switching state can only be made relatively late, because the checking of the switching state of each switching element occurs only once per simulation step. Therefore, a response to a change in the switching state of the overall circuit can only occur with a very large delay.

[0016] In the method according to the invention, the sub-simulation steps are performed not only strictly sequentially, but also at least partially simultaneously, i.e., overlapping in time. This makes it possible to respond to changes in the switching state of the switching element in the circuit with a higher repetition rate. Similarly, by averaging the current output parameters at a higher rate, the changing switching states become effective in the output signal even more rapidly, thereby achieving lower delays in responding to changes in the switching states.

[0017] In an advantageous design of the method, the output parameters calculated at multiple staggered times are averaged using a moving average to obtain an average output parameter, preferably using the last output value obtained during the duration of a simulation step.

[0018] The simultaneous simulation of at least a portion of the sub-simulation steps has different possibilities.

[0019] According to a first variant of the preferred method, the simulator simultaneously simulates at least a portion of the sub-simulation steps in such a way that the simulator simultaneously simulates multiple independent instances of the mathematical circuit model with corresponding independent instances of the sub-simulation steps, wherein the calculation of the instances of the circuit model is performed in each simulation step, and the simulation steps are implemented at time intervals of a small fraction of the duration of the simulation steps.

[0020] In this variant of the solution, the circuit model is actually calculated multiple times (at least twice), so the simulator's arithmetic unit must naturally have the necessary capability for this. In the processor-based arithmetic unit of a command-driven programmable calculator, different cores of the arithmetic unit can be applied for this purpose. In programmable gate devices, such as field-programmable gate arrays (FPGAs), a corresponding gate capacity must exist so that the circuit model can be implemented multiple times and executed in staggered time.

[0021] The solution concept does not lie in simply running the existing circuit model with a shorter simulation step duration, because if the simulation step duration is only slightly larger than the required computation time (often called turnaround time)—which is used to fully compute the sub-simulation steps within a single simulation step—this is often entirely impractical. If, for example, 10 µs is chosen as the simulation step duration, but the actual computation time within a simulation step already requires 8 µs, then there is no possibility of achieving higher time resolution by reducing the simulation step duration. However, simulator hardware configurations often provide the possibility of using parallel hardware architectures, thus allowing the method according to the invention to be implemented without problems.

[0022] The more instances of the circuit model that are computed in parallel within the duration of a simulation step, the higher the time resolution. This time resolution allows for a response to changes in the input parameters of the circuit model and changes in the switching states of the switching elements of the circuit model. Furthermore, the output parameters and the averaged output parameters respond more accurately and rapidly to changes in the switching states of passive and active switching elements.

[0023] A further extension of the method is characterized in that the time dislocations between simulation steps of instances of the circuit model executed sequentially in a time-staggered manner are the same, particularly in the case of n instances of the circuit model, where the time dislocation is the simulation step duration divided by n. A further extension of this alternative is characterized in that the time dislocations between simulation steps of instances of the circuit model executed sequentially are different. This should prevent adverse effects that might arise from strictly periodic and temporally symmetric calculations. Particularly preferably, the sum of the time dislocations is chosen to be less than the simulation step duration. In a particularly preferred design of the method, the time dislocations between simulation steps of instances of the circuit model executed sequentially are varied during simulation.

[0024] In a further extension of the method, a sliding arithmetic mean is calculated to average the output parameters, specifically wherein the output parameters of all instances of the circuit model are used to calculate the average. Preferably, in the case of n instances of the circuit model, the output parameters of the last n calculated instances of the circuit model are averaged.

[0025] According to a preferred second variation of the method, the simulator simultaneously simulates at least a portion of the sub-simulation steps by implementing these sub-simulation steps of the circuit model on individually executable hardware units, and executing the sub-simulation steps multiple times with the corresponding current input parameters during the duration of the simulation step, thereby calculating the current average output parameter multiple times during the duration of the simulation step. Different sub-simulation steps are then executed on different hardware units; that is, a first sub-simulation step is executed on a first hardware unit, a second sub-simulation step is executed on a second hardware unit (different from the first hardware unit), etc., wherein a specific hardware unit always executes a specific sub-simulation step.

[0026] In this variation of the method, instead of multiple instances of the circuit model as described in the first variation, there is only one circuit model that partially and simultaneously implements multiple sub-simulation steps during the simulation process. The individually executable hardware units can involve, for example, multiple successive stages of an FPGA implementation.

[0027] In existing technologies, only one sub-simulation step is always active within a simulation step, while the others remain inactive. The concept in the second method variation is that new data is supplied to the sub-simulation step before the final sub-simulation step's calculation concludes. This also allows for the calculation of multiple output parameters not only once within a simulation step, but also during the simulation step's duration, based on the current input and state parameters of the circuit model. The maximum scalability of the method is achieved if all sub-simulation steps are executed in parallel on their respective hardware units, since no individually executable hardware unit remains idle.

[0028] A preferred design of the method specifies that the calculations of sub-simulation steps are performed sequentially as quickly as possible to obtain the largest possible amount of current average output parameters within the duration of a simulation step. This achieves minimal idle time in individual hardware units and thus maximizes overlap in the calculations of sub-simulation steps.

[0029] Regardless of method variations, it has proven advantageous in a preferred further extension of the method to choose a simulation step frequency, i.e., the reciprocal of the simulation step duration, to be greater than the maximum switching frequency of the switching elements of the electrical circuit. This facilitates the practical consideration of changes in the switching states of the switching elements during simulation. Otherwise, it would be possible for changes in the switching states to remain unnoticed.

[0030] As mentioned at the beginning, the present invention also relates to a simulator having a computing unit for numerically simulating an electrical circuit having a mathematical circuit model, wherein, during the operation of the simulator, the calculation of the circuit model is performed in successive simulation steps having a simulation step duration, a simulation step comprising multiple temporally successive sub-simulation steps, the circuit including at least one switching element that can be in either an on or off switching state, the current switching state of the switching element of the circuit being detected within a simulation step and the circuit model being matched to the switching state of the switching element, the input parameters of the circuit model being detected and the output parameters of the circuit model being calculated within a simulation step, and the simulator having a simulator interface for connecting a controller to be tested, the simulator transmitting the output parameters at least partially through the simulator interface to the controller to be tested when the controller to be tested is connected during operation.

[0031] The simulator is characterized in that the computing unit is programmed such that it implements the aforementioned method for testing electronics using a simulator during operation.

[0032] The simulator's arithmetic unit can be a processor-based arithmetic unit of a command-driven programmable calculator (as well as multiprocessor and multicore implementations), but it can also involve programmable gate devices, such as field-programmable gate arrays (FPGAs).

[0033] The present invention also relates to a computer program comprising commands that, when executed by the computing unit of a simulator, cause the simulator to perform the aforementioned method.

[0034] Computer programs may involve executable machine code for a processor, provided that the arithmetic unit is based on an application processor, and / or computer programs may involve hardware descriptions for programmable logic gates, particularly for field-programmable gate arrays (FPGAs), provided that the arithmetic unit is based on application-programmable logic gates. Attached Figure Description

[0035] As clarified, there are different possibilities for designing and extending the method and simulator according to the invention, as described in the claims subsequently placed in the independent claims. Preferred embodiments are described below with reference to the accompanying drawings. The drawings show: Figure 1 The diagram schematically illustrates a computer-based method for testing an electronic controller using a simulator, and a corresponding simulator. Figure 2 An electrical circuit with switching elements is schematically shown. Figure 3This schematically illustrates a method for calculating a mathematical circuit model of an electrical circuit using successive simulation steps and sub-simulation steps. Figure 4 The method for numerically simulating a mathematical circuit model in the case of multiple independent instances of the applied mathematical circuit model, according to the present invention, is illustrated. Figure 5 The method for numerically simulating a mathematical circuit model according to the invention is illustrated in the case of time-overlapping calculations of multiple sub-simulation steps applying a unique circuit model. Figure 6 Show Figure 2 The simulation of the circuit utilizes a solution that is as error-free as possible (without real-time requirements), a time discretization method according to the prior art, and a time discretization method according to the present invention, which uses the same duration for each simulation step. Detailed Implementation

[0036] exist Figures 1 to 6 The diagram schematically illustrates different aspects of method 1, which is a computer-implemented controller 2 used to test electronics using simulator 3, and simulator 3.

[0037] Figure 1 Simulator 3 is shown, equipped with an arithmetic unit 4 (not shown in detail) in the form of a field-programmable gate array (FPGA) based on programmable gate devices. Computer program 10—not shown in detail—contains a corresponding hardware description for the FPGA, enabling the computer program to execute method 1. Simulator 3 numerically simulates a mathematical circuit model 5 of electrical circuit 6. In the illustrated embodiment, the controller 2 to be tested relates to a series of controllers for manipulating electrical drives. The electrical drives are not physically present but are simulated by simulator 3. Simulator 3 also includes a power electronic load simulation, which is manipulated within the simulation framework to mimic the real drives, along with their electrical connection parameters and dynamic performance, as closely as possible to the real controller 2. This arrangement is a so-called hardware-in-the-loop (HIL) simulation, in which the physical environment of the controller 2 to be tested is simulated in real time.

[0038] Figure 2An electrical circuit 6, exemplified by a buck converter, is shown. The circuit has two switching elements 7: an active semiconductor switching element Q1, whose switching state is influenced by an active control signal g, and a diode Q2, which relates to the passive switching element 7, the switching state (on, off) of which is determined by internal switching conditions (current and connection voltage). Generally, it applies that the switching elements 7 included in circuit 6 can be in either an on or off switching state. As described in the general description section, circuit 6 is transferred to a mathematical circuit model 5 by establishing time-discrete state equations, which forms the basis for numerical simulation. In simulation step k, the current switching state of the switching elements 7 of circuit 6 is determined, and circuit model 5 is matched to the switching state of the switching elements 7. As described in the general description section, this can occur in different ways, but this is not the focus of this application and is not important for illustrating method 1 according to the invention and simulator 3 according to the invention.

[0039] like Figure 3 As shown, the numerical simulation and calculation of circuit model 5 are performed in successive simulation steps k-1, k, k+1, etc., each with a simulation step duration T. The time at which the successive simulation steps k are separated from each other is denoted by t. k-1 t k t k+1 t k+2 The simulation step k includes multiple time-sequential sub-simulation steps a, b, and c, wherein, within simulation step k, the input parameters u and g of circuit model 5 are detected, and the output parameter y of circuit model 5 is calculated. k y k+1 y k+2 And output parameter y k y k+1 y k+2 (y should be understood here as a vector parameter including multiple vector elements) is transmitted at least partially to the controller 2 to be tested through simulator interface 8 and controller interface 9 of the controller to be tested. Figure 1 ).

[0040] Figure 3 This refers to the prior art, in which the sub-simulation steps a, b, and c of the unique circuit model 5, I are executed strictly sequentially, that is, sub-simulation step b is executed only after sub-simulation step a has ended, and sub-simulation step c is executed only after sub-simulation step b has completely ended; this applies to all illustrated simulation steps k-1, k, and k+1. For in Figure 3The reason why sub-simulation steps a, b, and c are executed in a strict, non-overlapping order may be that the result of sub-simulation step a is the input parameters of sub-simulation step b, and / or the operation unit 4 only allows the sequential execution of sub-simulation steps. Figure 3 Similarly, the curve of the actual active switching signal g of switching element 7 is illustrated, wherein the switching signal g transitions from cutoff to on in simulation step k-1 and then from on to cutoff in simulation step k+1. In the prior art shown, the actual switching state g of switching element 7 is obtained only once in each simulation step k. This results in: the obtained switching state g... I The switch transitions from cutoff to on only at the beginning of simulation step k, and the obtained switch state g... I The switch transitions from on to off only in simulation step k+2. According to the principle, there is a very large delay in considering the current and actual switching state g. As known from this invention, there are significant deficiencies in the achievable accuracy during the simulation of electrical circuit 6 and the calculation and output of the output parameter y.

[0041] exist Figure 4 and 5 Method 1 shown is based on a new method procedure. Here, simulator 3 simultaneously simulates at least a portion of sub-simulation steps a, b, and c, thereby obtaining input parameters u and g based on multiple time-staggered acquisitions of circuit model 5 and switching states z based on multiple time-staggered calculations of switching elements 7 of circuit model 5 within a simulation step duration T. sw Also calculate multiple time-staggered output parameters y of circuit model 5. n-1 y n y n+1 The output parameter y calculated at multiple staggered times. n-1 y n y n+1 The output parameters appear as result values ​​at the end of each simulation step i, j, k (e.g., in...). Figure 3 (As shown in the figure) — the average value to be calculated is the average output parameter y. - n-1 y - n y - n+1 The average output parameter y - n-1 y - n y - n+1 At least partially, the output parameter y is transmitted to the controller 2 to be tested via controller interface 8. As can be seen in both figures, sub-simulation steps a, b, and c are executed partially and simultaneously, thus overlapping in time with a start time t.i t j t k The simulation steps i, j, and k are performed. This method allows for a high repetition rate in responding to changes in the switching state g of the switching element 7 in circuit 6. Similarly, the current output parameter y is calculated at a high rate, and by averaging the output parameter, the changing switching state g is reflected more rapidly in the average output signal y. - The same applies to the middle, thereby achieving lower latency in response to changes in the switching state g.

[0042] exist Figure 4 and 5 In method 1 shown, the output parameter y is calculated at staggered times for the plurality of times. n-1 y n y n+1 At least partially, the moving average is used to calculate the average output parameter y. - n-1 y - n y - n+1 .

[0043] Figure 4 A first variation of the method 1 previously described in general is shown. This variation is characterized in that the simulator 3 simultaneously simulates at least a portion of sub-simulation steps a, b, and c, in such a way that the simulator 3 simultaneously simulates multiple independent instances I, II, and III of the mathematical circuit model 5 as corresponding independent instances of sub-simulation steps a, b, and c. Figure 4 In the example, all sub-simulation steps a, b, and c are executed simultaneously at each time step, where the simultaneously executed sub-simulation steps a, b, and c belong to different instances I, II, and III of circuit model 5.

[0044] The calculations for examples I, II, and III of circuit model 5 are performed in simulation steps i, j, and k, respectively, with each simulation step i, j, and k being staggered from the others by a small fraction of the simulation step duration T. The start time of the corresponding simulation steps i, j, and k is denoted by t. i t j t k This indicates that the processing unit 4 of simulator 3 does not necessarily need to be compared to the one described above. Figure 3 The existing technology can compute the unique circuit model 5 more quickly, but the arithmetic unit 4 must have the ability to compute other instances of the circuit model in parallel, for example, by implementing instances I, II, III in parallel on the FPGA using additional cores of the processor-based arithmetic unit or by using additional gates of the FPGA.

[0045] exist Figure 4 Method 1 shown in the figure is compared to that in Figure 3 The advantages of the prior art shown in the figure are particularly evident when the time curve of the actual active switching signal g of the semiconductor switching element is combined with the switching signal g detected in the simulation by different instances I, II, and III of circuit model 5. I g II g III The time curves are considered together. Because the switching state of the involved switching element 7 is always determined in the simulation of each instance of circuit model 5, including the analysis of the switching signal g, the determination of the changing switching conditions of the switching element 7 based on circuit model 5, implemented multiple times within a simulation step duration T, identifies the changes in the switching state of the switching element 7 with lower delay. This allows circuit model 5 to match the changing switching states with higher accuracy than possible in the prior art. Correspondingly, the output parameter y of instances I, II, and III of the circuit model, and therefore the average output parameter y, are also considered. - It can respond more accurately to changes in the switching state of switching element 7. This is because the average output parameter y... - As an output parameter y, it is output to the controller 2 to be tested, so the simulation in the time performance simulation is closer to the actual performance of the simulated circuit 6 than the previous possible situation.

[0046] Figure 4 Method 1 is implemented such that the time dislocations between simulation steps i, j, and k in successive executions of instances I, II, and III of circuit model 5 are identical. In the case of the three instances I, II, and III of circuit model 5, the time dislocation is the simulation step duration T divided by three, i.e., T / 3.

[0047] In accordance with Figure 4 In addition to the above, Method 1 is implemented as follows, that is, in order to output the parameter y i y j y k The sliding arithmetic mean is calculated by averaging, where the output parameter y of all instances of circuit model 5 is used to calculate the average. n-1 y n y n+1 In the case of N instances of circuit model 5, the output parameter y for the last N calculated instances of circuit model 5. n-1 y n y n+1 Calculate the average. Then apply (Equation 2), where the output parameter y(t) of the instance of circuit model 5 involves an output parameter vector, which includes the various output parameters:

[0048] Figure 5 A second variation of the implementation of method 1 is shown. Based on... Figure 5 In method 1, simulator 3 simultaneously simulates at least a portion of sub-simulation steps a, b, and c by implementing the sub-simulation steps a, b, and c of circuit model 5 on a separately executable hardware unit 4, and executing sub-simulation steps a, b, and c multiple times within a simulation step duration T using the corresponding current input parameters u and g, thereby calculating the current average output parameter y multiple times within a simulation step duration T. - Compared to following Figure 4 Method 1 does not require multiple instances of circuit model 5, but rather a single circuit model (in Figure 5 (I) is sufficient to implement, at least partially simultaneously, the sub-simulation steps a, b, and c of the unique circuit model on independently operable hardware units. The independently executable hardware units here refer to multiple successive stages of an FPGA implementation. Figure 5 The diagram illustrates simulation steps i, j, and k, as well as three time-staggered sub-simulation steps a, b, and c. The computational unit responsible for calculating sub-simulation step a is never actually idle. Once at time t... k-1 The computation of sub-simulation step a, which has already begun, has ended. Then, the computation unit that initiates sub-simulation step a at time t... j-1 Further calculations are performed, in which the current input parameters u and g of circuit model 5 are obtained in real time, that is, the actual active switching signal g of switching element 7 is also considered. In this sense, this also applies to other sub-simulation steps b and c, which, compared to those calculated according to... Figure 3 The existing technology is also not idle. In order to implement according to... Figure 5 Method 1 requires increased hardware consumption because the sub-simulation steps that should be executed in overlapping time must be implemented on independently executable hardware units. According to Figure 5 The advantages of the method are corresponding to those of following Figure 4 Method 1 has advantages, such as, on the one hand, based on the time curve of the actual active switching signal g of the semiconductor switching element and the switching signal g detected in the simulation by sub-simulation steps a, b, and c of circuit model 5. I,1 g I,2 g I,3 The time curve is clearly visible.

[0049] In accordance with Figure 5 In this method, the calculations of sub-simulation steps a, b, and c are performed as quickly and sequentially as possible, thereby obtaining as much of the current average output parameter y as possible within the duration T of a simulation step. - As previously stated... Figure 4The average output parameter y is described. - The calculation.

[0050] Figure 6 Showing according to Figure 2 Simulation of a buck converter and time curves of some electrical parameters of the buck converter, namely the capacitor voltage V. C Input current i in Coil current i L The time curves are shown. Furthermore, the input current and coil current are displayed in detail over time. The curve referred to as the "reference" curve shows the actual, error-free curves for the corresponding parameters, while the dotted curves representing the "single model" show the simulation results with only one unique model, i.e., calculations without overlapping sub-simulation steps. If significant deviations can be identified between the curves, then the controller 2's simulation-based test does not agree well with actual physical facts. Using the... Figure 4 and 5 Method 1 achieves significant improvements, with the corresponding curves of the circuit parameters shown as "average values". The test implemented using Method 1 with controller 2 better reflects the actual physical facts compared to the test using "Single Models", thus the test with "average values" has higher quality and reliability.

[0051] List of reference numerals

[0052] 1 Method

[0053] 2 controllers

[0054] 3 simulator

[0055] 4 arithmetic units

[0056] 5 Mathematical Circuit Model

[0057] 6 Electrical Circuits

[0058] 7 Switching Components

[0059] 8 simulator interface

[0060] 9 controller interfaces

[0061] 10 Computer Programs

[0062] i, j, k Simulation steps (subscripts)

[0063] T Simulation step duration

[0064] a, b, c Sub-simulation steps

[0065] Q1, Q2 Active and passive semiconductor switching elements

[0066] The actual active switching signal of a semiconductor switching element

[0067] Switching signals detected in analog form for gi semiconductor switching elements

[0068] z sw Switching parameters of switching elements

[0069] Output parameters of the y-circuit model

[0070] y - Average output parameters of the circuit model

[0071] Examples of mathematical circuit models I, II, and III

Claims

1. A computer-implemented method (1) for testing an electronic controller (2) using a simulator (3), wherein, The simulator (3) uses at least one arithmetic unit (4) to numerically simulate the mathematical circuit model (5) of the electrical circuit (6). The calculation of the circuit model (5) is carried out in successive simulation steps (k) with a simulation step duration (T). One simulation step (k) includes multiple time-sequential sub-simulation steps (a, b, c). The circuit (6) includes at least one switching element (7) which can be either in an on or off switching state. Within one simulation step (k), the current switching state of the switching element (7) of the circuit (6) is obtained and the circuit model (5) is matched to the switching state of the switching element (7). Within one simulation step (k), the input parameters (u, g) of the circuit model (5) are detected, the output parameters (y) of the circuit model (5) are calculated, and the output parameters (y) are transmitted at least partially to the controller (2) to be tested through the simulator interface (8). Its features are, The simulator (3) simultaneously simulates at least a portion of the sub-simulation steps (a, b, c), thereby calculating multiple time-staggered input parameters (u, g) based on the circuit model (5) and multiple time-staggered switching states based on the switching elements (7) of the circuit model (5) within the simulation step duration (T), as well as multiple time-staggered output parameters (y) of the circuit model (5). n-1 y n y n+1 ), and the output parameters (y) calculated at staggered times for the multiple times. n-1 y n y n+1 ) Calculate the average to obtain the average output parameter (y) - n-1 y - n y - n+1 ), and the average output parameter (y) - n-1 y - n y - n+1 ) at least in part as an output parameter (y n-1 y n y n+1 The data is transmitted to the controller (2) to be tested through the controller interface (8).

2. The method (1) according to claim 1, characterized in that, The output parameters (y) calculated at multiple staggered times n-1 y n y n+1 At least partially, the moving average is used to calculate the average output parameter (y). - n-1 y - n y - n+1 ).

3. The method (1) according to claim 1 or 2, characterized in that, The simulator (3) simultaneously simulates at least a portion of the sub-simulation steps (a, b, c) in such a way that the simulator (3) simultaneously simulates multiple independent instances (I, II, III) of the mathematical circuit model (5) with corresponding independent instances of the sub-simulation steps (a, b, c), wherein the calculation of the instances (I, II, III) of the circuit model (5) is performed in simulation steps (i, j, k) respectively, and the simulation steps (i, j, k) are implemented at time staggered from each other by a small fraction of the duration (T) of the simulation steps.

4. The method (1) according to claim 3, characterized in that, The time dislocations between simulation steps (i, j, k) of successive instances (I, II, III) of the circuit model (5) are the same, especially in the case of N instances (I, II, III) of the circuit model (5), the time dislocation is the duration (T) of the simulation step divided by N.

5. The method (1) according to claim 3, characterized in that, The time dislocations between simulation steps (i, j, k) of the successively executed instances (I, II, III) of the circuit model (5) are different, in particular the sum of the time dislocations is less than the duration (T) of the simulation step, and / or in particular the time dislocations between simulation steps (i, j, k) of the successively executed instances (I, II, III) of the circuit model (5) are changed during simulation.

6. The method (1) according to any one of claims 3 to 5, characterized in that, In order to determine the output parameters (y) of the instances (I, II, III) of the circuit model (5), i y j y k ) to calculate the sliding arithmetic mean, in particular, where the output parameters (y) of all instances (I, II, III) of the circuit model (5) are considered in order to calculate the average. i y j y k Preferably, in the case of N instances (I, II, III) of the circuit model (5), the output parameter (y) of the last N calculated instances (I, II, III) of the circuit model (5) is... i y j y k Find the average.

7. The method (1) according to claim 1 or 2, characterized in that, The simulator (3) simultaneously simulates at least a portion of the sub-simulation steps (a, b, c) by implementing the sub-simulation steps (a, b, c) of the circuit model (5) on a separately executable hardware unit (4) and executing the sub-simulation steps (a, b, c) multiple times within the simulation step duration (T) using the corresponding current input parameters (u, g), thereby calculating the current average output parameter (y) multiple times within the simulation step duration (T). - ).

8. The method (1) according to claim 1, characterized in that, The sub-simulation steps (a, b, c) are performed sequentially as quickly as possible to obtain the largest possible amount of the current average output parameter (y) within the duration (T) of one simulation step. - ).

9. The method (1) according to any one of claims 1 to 8, characterized in that, The frequency of the simulation step, that is, the reciprocal of the duration (T) of the simulation step, is selected to be greater than the maximum switching frequency of the switching element (7) of the electrical circuit (6).

10. A simulator (3), the simulator having a computing unit (4) for numerically simulating an electrical circuit (6) having a mathematical circuit model (5), wherein, During the operation of the simulator (3), the calculation of the circuit model (5) is performed in successive simulation steps (k) with simulation step durations, one simulation step (k) comprising multiple temporally successive sub-simulation steps (a, b, c), the circuit (6) comprising at least one switching element (7) capable of being either on or off, the current switching state of the switching element (7) of the circuit (6) being detected within simulation step (k) and the circuit model (5) being matched to the switching state of the switching element (7), the input parameters (u, g) of the circuit model (5) being detected within simulation step (k), the output parameter (y) of the circuit model (5) being obtained, and the simulator (3) having a simulator interface (8) for connecting to the controller (2) to be tested, the simulator (3) transmitting the output parameter (y) at least partially through the simulator interface (8) to the controller (2) to be tested during operation when the controller (2) to be tested is connected. The feature is that the arithmetic unit (4) is programmed such that the arithmetic unit executes the method (1) according to any one of claims 1 to 9 during operation.

11. A computer program (10) comprising commands that, when executed by the arithmetic unit (4) of the simulator (3), cause the simulator to perform the method (1) according to any one of claims 1 to 9.

12. The computer program (10) according to claim 11, characterized in that, The computer program (10) relates to executable machine code for a processor, provided that the arithmetic unit is based on an application processor, and / or the computer program (10) relates to a hardware description for programmable logic gates, particularly a hardware description for a field-programmable gate array (FPGA), provided that the arithmetic unit (4) is based on an application-programmable logic gate.

Images