Power management engine in a semiconductor system

Abstract

Methods, systems, and devices are described for providing power management using a power management engine of a semiconductor system. Power management can refer to power management techniques associated with a semiconductor component (e.g., a chiplet). The power management engine supports monitoring power usage and dynamically adjusting power-related parameters to meet performance requirements of the chiplet. In particular, the power management engine supports asynchronous voltage drop detection among chiplets in an integrated circuit, where asynchronous detection means that drop events are detected by individual chiplets at different times or rates, without being synchronized. In operation, a voltage level associated with a shared power supply of a first chiplet and a second chiplet is monitored at a first voltage drop detector of the first chiplet. A first voltage drop that triggers a first clock modulation enable signal is detected. The first clock modulation enable signal is communicated to the second chiplet having a second voltage drop detector.

Description

Background Technology

[0001] Users rely on electronic devices (e.g., computing devices with applications and services) to perform different types of tasks. Computing devices, and other types of electronic devices, can include semiconductor components or systems that perform specific functions within integrated circuits (ICs) or system-on-a-chip (SoCs). For example, a graphics processing unit (GPU) can contain chiplets for high computational throughput and memory bandwidth. Semiconductors employ power management systems to provide optimal performance, reliability, and energy efficiency across a wide range of applications. Effective power management strategies can enhance the functionality, lifespan, and sustainability of devices incorporating semiconductors. Summary of the Invention

[0002] The various aspects of the technology described herein generally relate to systems, methods, and apparatus for providing power management, etc., using a power management engine for semiconductor systems. Power management can refer to power management techniques associated with semiconductor components (e.g., chiplets), where these techniques and mechanisms are employed to regulate and optimize power consumption. The power management engine supports monitoring power usage, detecting changes in operating conditions, and dynamically adjusting power-related parameters to meet the performance requirements of the chiplets. In particular, the power management engine supports asynchronous voltage drop detection within chiplets in integrated circuits, where asynchronous detection means that a drop event is detected by individual chiplets at different times or rates, and is not synchronized or aligned with each other.

[0003] Semiconductor systems can refer to 3D integrated circuit packaging (“3D-IC packaging”). 3D-IC packaging is a semiconductor packaging technology that enables the vertical stacking of multiple integrated circuit (IC) dies or chiplets within a single package. Vertical integration of ICs results in higher performance, increased functionality, and a reduced form factor. In 3D-IC packaging, computing chiplets (“chiplets”) can be configured to share a power source. Chipslets are associated with power management mechanisms or engines to mitigate voltage drops.

[0004] Traditional power management systems lack the logic and infrastructure for efficient dynamic power management of chiplets. For example, power management techniques limit voltage drop sensing and clock modulation to a single chiplet. They do not include shared clock modulation or shared sensing for drop modulation. In a 3D-IC package with multiple chiplets, the chiplets can have different impedance characteristics, resulting in varying drop responses due to differences in impedance levels. Impedance mismatch leads to different voltage drop behaviors among the chiplets during transient load conditions. For example, during operation, the first chiplet from the chiplet group may experience a voltage drop faster than the others in the group. In particular, chiplets with lower impedance will observe higher and faster drops than those with higher impedance. Therefore, power management schemes can be developed to account for worst-case drop scenarios among the chiplets in a chiplet group.

[0005] Technical solutions addressing the limitations of traditional email systems may include providing power management resources via a power management system that supports power management in semiconductor systems. The power management resources may include monitoring voltage levels at multiple chiplets of an integrated circuit and using a clock modulation enable signal from a first chiplet to control clock modulation operations on a second chiplet. The second chiplet may also detect a voltage drop and generate a second clock modulation enable signal; however, a bypass mode exists at each chiplet to bypass the second clock modulation signal. Thus, the power management engine includes multiple chiplets with corresponding dropout detectors; however, only one dropout detector is used to control clock modulation for these chiplets. Therefore, the power management system and power management resources can identify dropout detectors with superior performance metrics (e.g., response time, noise filtering, error margin) to send clock modulation enable signals for the chiplets in the semiconductor system using the identified dropout detector.

[0006] During operation, the voltage level associated with the shared power supply of the first and second chips is monitored at a first voltage drop detector of the first chip. A first voltage drop is detected, triggering a first clock modulation enable signal. The first clock modulation enables the signal to be transmitted to the second chip, which has a second voltage drop detector.

[0007] In the second embodiment, voltage levels associated with a shared power supply of the first and second chiplets are independently monitored at a first voltage drop detector of the first chiplet and a second voltage drop detector of the second chiplet. A first voltage drop is detected, triggering a first clock modulation enable signal. The first clock modulation allows a signal to be transmitted from the first chiplet to the second chiplet. A second voltage drop is detected at the second voltage drop detector of the second chiplet, triggering a second clock modulation enable signal, which is detected after the first voltage drop. The second clock modulation allows a signal to be transmitted to the first chiplet. A bypass mode is used at the first chiplet, and the second clock modulation enable signal from the second chiplet is bypassed.

[0008] In a third embodiment, a semiconductor system is provided having a shared power supply coupled to two or more chiplets; a first chiplet coupled to a first voltage drop detector, the first chiplet supporting a bypass mode including control logic for overriding a clock modulation enable signal from a second chiplet; and a second chiplet coupled to a second voltage drop detector, the second chiplet supporting a bypass mode including control logic for overriding a clock modulation enable signal from the second chiplet.

[0009] The present invention is provided to introduce, in a simplified form, the selection of concepts further described in the following detailed description. The present invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter. Attached Figure Description

[0010] The technology described herein is described in detail below with reference to the accompanying drawings, wherein:

[0011] Figure 1 This is a schematic diagram of an exemplary cross-section of a 3D-IC having shared power among chiplets, based on various aspects of the described technology.

[0012] Figure 2 This is a schematic diagram of an exemplary motherboard plane for an artificial intelligence hardware system based on various aspects of the technology described herein;

[0013] Figure 3 This is a schematic diagram of an exemplary power transfer model for sharing power between chiplets based on various aspects of the technology described herein;

[0014] Figure 4 This is a schematic diagram of an exemplary clock modulation scheme with a power delivery network according to various aspects of the technology described herein;

[0015] Figure 5This is an exemplary chart comparing different parameters with and without clock modulation based on various aspects of the techniques described herein;

[0016] Figure 6 This is a schematic diagram of an exemplary clock modulation in a 3D-IC having a shared power supply in two small chips, according to various aspects of the technology described herein;

[0017] Figure 7 This is an exemplary graph showing the delay of drop detection between small chips with different impedances according to various aspects of the techniques described herein;

[0018] Figure 8 This is an exemplary graph of the power delivery network impedance profile of a chiplet according to various aspects of the technology described herein;

[0019] Figure 9 This is a schematic diagram of an exemplary clock modulation scheme for a single dropout detector that drives clock modulation of other chips, according to various aspects of the technology described herein;

[0020] Figure 10 A first exemplary method is provided for providing power management using a power management engine of a semiconductor system according to various aspects of the technology described herein; and

[0021] Figure 11 A second exemplary method for providing power management using a power management engine of a semiconductor system, based on various aspects of the technology described herein, is provided. Detailed Implementation

[0022] Overview

[0023] Semiconductor systems can refer to 3D integrated circuit packaging (“3D-IC packaging”). 3D-IC packaging is a semiconductor packaging technology that enables the vertical stacking of multiple integrated circuit (IC) dies or chips within a single package. Unlike traditional 2D IC packaging, where dies are arranged side-by-side on a substrate, 3D-IC packaging allows for the compact integration of heterogeneous functional blocks such as processors, memory, and sensors by vertically stacking them. This vertical integration is achieved using through-silicon vias (TSVs) or microbumps for inter-die connections and typically involves silicon interposers or substrates to facilitate wiring and interconnections between the stacked dies. 3D-IC packaging offers advantages such as reduced footprint, improved performance, increased functionality, and enhanced thermal management, making it ideal for a wide range of applications, including high-performance computing, mobile devices, and Internet of Things (IoT) devices.

[0024] Traditional power management schemes in semiconductor systems lack the logic and infrastructure for efficient dynamic power management of chiplets. For example, power management techniques limit voltage drop sensing and clock modulation to a single chiplet. They do not include shared clock modulation or shared sensing for drop modulation. In a 3D-IC package with multiple chiplets, the chiplets can have different impedance characteristics, resulting in different drop responses due to differences in impedance levels. Impedance mismatch leads to different voltage drop behaviors among the chiplets during transient load conditions. For example, during operation, the first chiplet from a chiplet group in a semiconductor system may experience a voltage drop faster than the other chiplets in that group. In particular, chiplets with poor impedance will observe a higher and faster drop than chiplets with better impedance. Therefore, power management schemes can be developed to account for the worst-case drop scenarios among the chiplets in a chiplet group.

[0025] Embodiments of this technical solution relate to systems, methods, and computer storage media for providing power management, etc., using a power management engine for semiconductor systems. Power management can refer to power management technologies associated with semiconductor components (e.g., chiplets), wherein these technologies and mechanisms are employed to regulate and optimize power consumption. The power management engine supports monitoring power usage, detecting changes in operating conditions, and dynamically adjusting power-related parameters to meet the performance requirements of the chiplets. In particular, the power management engine supports asynchronous voltage drop detection among chiplets in integrated circuits, where asynchronous detection means that a drop event is detected by each chiplet at different times or rates, and is not synchronized or aligned with each other.

[0026] At a high level, power management solutions use drop detection on one chip to control clock modulation on another chip within an integrated circuit package. Specifically, the integrated circuit includes multiple chips with corresponding drop detectors, and the chip with the superior performance metrics (e.g., response time, noise filtering, error margin) can be identified. For illustration, a semiconductor system (e.g., a 3D-IC package) may include a first and second chip sharing a power supply, and corresponding drop detectors that independently monitor voltage levels associated with the power supply. Each chip may also be independently coupled to other power management components (e.g., phase-locked loops (PLLs), frequency dividers, and clock modulation units). An event at one chip (e.g., a di / dt event) can cause a voltage drop at another chip. The first chip is identified as the chip that detected the voltage drop. If the voltage drop triggers clock modulation (e.g., the voltage level exceeds a voltage limit), a clock modulation signal (e.g., a clock modulation enable signal) is transmitted to the second chip to initiate clock modulation. Furthermore, if more than two chips are present, this signal is transmitted to all other chips. The second chiplet can also detect a voltage drop and generate a second clock modulation enable signal; however, each chiplet in the chiplet has a bypass mode to support bypassing the second clock modulation enable signal.

[0027] Advantageously, embodiments of this technical solution include several inventive features associated with a semiconductor system (e.g., operation, chiplets, dropout detectors). The power management engine of the semiconductor system includes multiple chiplets with corresponding dropout detectors; however, only one dropout detector is used to control clock modulation for these chiplets. Therefore, the power management engine and power management resources can identify dropout detectors with superior performance metrics (e.g., response time, noise filtering, error margin) so that clock modulation enable signals can be sent for the chiplets in the semiconductor system using the identified dropout detector.

[0028] Example systems and resources

[0029] Various aspects of this technical solution can be seen through examples and references. Figures 1 to 8 Described.

[0030] refer to Figure 1 , Figure 1 The illustration shows a cross-section of a 3D-IC package 100 characterized by a shared chiplet power supply. Figure 1The diagram depicts a power delivery network (PDN) 110 within a 3D-IC package 100. The PDN 110 connects internal components to an external power source via BGA (Ball Grid Array) balls. These BGA balls (BGA 120A and BGA 120B) are soldered to the package substrate and serve as electrical connections between the package and the printed circuit board (PCB) or substrate on which the package is mounted. A package plane 130, typically a substrate or interposer within the package structure, also interconnects with the BGA balls. The PDN 100 extends from the BGA balls to the dielets (dielets 140A and 140B). Current flows through the package plane 130, through C4 bumps (C4 bump 150) to the bottom die 160, then through through-silicon vias (TSVs) 170, and finally reaches the dielets via microbumps (microbumps 180) located between dielets 140A and 140B and the bottom die 160. It is worth noting that the bottom die 160 can act as a passive interposer. Chiplets 140A and 140B can be the same dies that are typically located adjacent to each other on top of the bottom die 160 or the interposer die, and they are also depicted in the figure.

[0031] Power management in chiplets involves implementing strategies to efficiently regulate and distribute power within a single chiplet and across an assembly of chiplets within a larger integrated circuit or system. This includes dynamic voltage regulation to ensure a stable supply voltage, clock modulation techniques to adjust the operating frequency based on workload demands, and sophisticated power gating mechanisms to selectively shut down or reduce the power of inactive or low-power components. Additionally, chiplets may include drop detection and mitigation mechanisms to address transient voltage drop events, and advanced thermal management techniques to manage heat dissipation and ensure reliable operation under varying operating conditions. In summary, power management in chiplets aims to optimize energy efficiency, maximize performance, and enhance reliability while minimizing power consumption and thermal issues.

[0032] In heterogeneous chiplet-based systems, differences in silicon manufacturing and design complexity can manifest as functional variations or failures in critical components such as dropout detectors. For example, a dropout detector located on a chiplet may malfunction or fail due to silicon variations or manufacturing defects. Due to manufacturing variations, chiplets can exhibit different silicon behaviors. One chiplet may exhibit a superior error margin in detecting voltage drops compared to another. Alternatively, a chiplet may suffer from suboptimal dropout detection functionality due to localized noise interference.

[0033] refer to Figure 2The motherboard layout 200 for an artificial intelligence hardware system includes key components such as voltage regulation modules (VRMs) (left VRM 210B and right VRM 210B) and packages 220 soldered to board 230. Within package 220, components include a bottom die 240, chiplets (numbered 1 to 4), a SerDes (IO) die 250, and high-bandwidth memory (HBM) dies—top HBM die 260A and bottom HBM die 260B. Connections to the board are facilitated by BGA (Ball Grid Array) balls. The VRMs on the motherboard power the chiplets, with each power type potentially supported by one or more VRMs.

[0034] The placement of voltage regulators on the motherboard and the routing of power traces at both the board and package levels can lead to differences in the PDN (Power Distribution Network) of individual chipsets in a heterogeneous chiplet-based system. Differences in PDN impedance between chipsets can cause asynchronous detection of voltage drop events. In this scenario, one chiplet might detect a drop and initiate clock frequency modulation to compensate, while another chiplet with higher impedance continues to operate at an increased frequency, thus exacerbating the drop before it is detected internally. Insufficient protection bands to account for these drop detection differences can lead to functional failures. Implementing additional voltage protection bands incurs additional power costs to ensure reliable operation. In severe cases, drop detectors may fail entirely due to silicon manufacturing defects. These differences can cause asynchronous drop detection and clock modulation within chiplets sharing a power supply, thus hindering the effectiveness of the overall drop mitigation scheme.

[0035] refer to Figure 3 , Figure 3 The diagram illustrates a PDN 300 originating from the motherboard voltage regulator (MBVR) and extending to the chiplets—chiplet 1310A and chiplet 1310B (only two chiplets are considered in this example). Assuming the MBVR phase is on the right—associated with MBVR 320A—and on the left—associated with MBVR 320B—the PDN impedances from the left side of the board and package are represented as Zi. brd_left and Z pkg_left Similarly, the PDN impedances from the right side of the board and package are represented as Z. brd_rgt and Z pkg_rgt It is worth noting that, due to the different PDN implementation methods on the board, Z brd_left and Z brd_rgt They can be different. Similarly, Z pkg_rgt It is also different from Z pkg_left Z tsv1 This indicates the effective TSV impedance when connecting the bottom die to the small chip 1 310A, while Z... tsv2This indicates the effective TSV impedance for connecting the bottom die 330 to the chip 2 310B. It is important to note that Z... tsv1 and Z tsv2 They don't have to be equal.

[0036] refer to Figure 4 , Figure 4 The diagram illustrates a clock modulation scheme 400 used to mitigate voltage drops. Clock modulation is used as a technique to address voltage drops during dynamic current change events (e.g., di / dt). Failure to mitigate voltage drops necessitates a guard band, resulting in increased power consumption. The guard band provides a safety margin or buffer to account for uncertainties, variability, or unexpected events in the voltage. A typical voltage (Vdie) on the PDN network can be monitored by a dropout detector 420 of chiplet 410, which also receives a voltage threshold (Vlimit) 430 as input. If Vdie drops below Vlimit 430, the dropout detector 420 activates a divider block 440, thereby reducing the clock frequency by a factor (e.g., 2, 3, or more). The chiplet is operatively coupled to a PLL 450 and communicatively coupled to a global clock via a global clock communication path 460.

[0037] As an illustration, the chiplet utilizes a clock modulation enable signal to dynamically adjust its internal clock frequency (e.g., via a global clock communication path) in response to a voltage drop event or power management command. Upon detecting a voltage drop or receiving a power management command, the chiplet generates a clock modulation enable signal, activating its internal clock modulation mechanism (e.g., a clock modulation unit—not shown). This mechanism adjusts the chiplet's operating frequency, typically by reducing the frequency of the internal clock signal, to mitigate the effects of the voltage drop or meet power constraints.

[0038] Throughout the process, the chiplet continuously monitors the system status and can provide feedback to the system controller regarding the effectiveness of clock modulation. Once the voltage drop event subsides or the power management objective is achieved, the chiplet disables the clock modulation mechanism by disabling the clock modulation enable signal, thus returning to its normal operating frequency. This adaptive clock modulation method ensures efficient operation and reliable performance of the chiplet under varying system conditions.

[0039] refer to Figure 5 , Figure 5Figure 500 illustrates a comparison of different parameters with and without clock modulation. These figures include die current di / dt events 510, voltage drops 520, and clock frequency curves 530, both with and without clock modulation. Notably, the observed voltage drop with clock modulation is significantly lower than the voltage drop experienced without clock modulation. This highlights the effectiveness of clock modulation in mitigating voltage drops under varying current di / dt conditions. As an illustration, the graphical levels depicting the parameters associated with voltage drops without clock modulation (e.g., 512, 522, and 532) are based on the initial stable voltage level. As a sudden increase in current demand occurs, the voltage begins to drop rapidly and linearly over time. In contrast, the graphical levels depicting the parameters associated with drops with clock modulation (e.g., 515, 524, and 534) show a smoother and more controlled voltage level drop based on the voltage drop curves compared to the case without clock modulation. When a di / dt event occurs, triggering the voltage drop detector, clock modulation is initiated to reduce the system clock frequency. A decrease in clock frequency causes a reduction in the rate of current consumption, thus mitigating the voltage drop. Therefore, the voltage drop curve with clock modulation shows a shallower slope and a potentially smaller drop in voltage level compared to the case without clock modulation. The duration of the drop is also shorter due to the faster response of the clock modulation mechanism.

[0040] refer to Figure 6 , Figure 6 The diagram illustrates a typical clock modulation scheme used in a 3D integrated circuit (3DIC). In this scheme, the power supply (VCC) 600 is shared among chiplets (chiplet 620A and chiplet 620B), each chiplet having its own dedicated phase-locked loop (PLL) (PLL1 650A and PLL2 650B), voltage drop detectors (voltage drop detectors 630A and 630), frequency dividers (frequency divider 640A and 640B), signal paths (EN1 670A and EN2 670B), and global clock paths (global clock 1 680A and global clock 2 680B). Notably, the voltage drop detector threshold Vlimit (Vlimit660) is shared across all chiplets. While it would be possible to assign different voltage drop detector thresholds (e.g., Vlimit1 and Vlimit2) to each voltage drop detector, doing so would incur post-silicon calibration overhead. Therefore, for practicality and efficiency, a single Vlimit is typically utilized across all chiplets.

[0041] When each chiplet has a dedicated voltage drop detector, there are several potential problems, including silicon variation, local power supply noise and PDN impedance. With respect to silicon variation, due to inherent variation in silicon processing technology, transistors within a chiplet die may operate at different speeds. This can cause slower response time or loss of resolution of the voltage drop detector IP, leading to delayed triggering of clock modulation and may increase the voltage guard band. Additionally, silicon variation can increase the error margin of the voltage drop detector, causing it to mark an output signal at a voltage slightly different from the set threshold due to variation in the manufacturing process.

[0042] Various factors can cause local power supply noise within a chiplet. For example, high-speed IO operations such as SerDes, PCIE or HBM can generate switching noise, which is coupled to one chiplet to a more significant extent than other chiplets. Furthermore, at the server blade level, where multiple AI motherboards are interconnected, system-level noise coupling from other components may occur. Such noise can impair the optimal function of the voltage drop detector, especially if it is analog IP, and may cause unnecessary triggering of the voltage drop detector.

[0043] as Figure 2 and Figure 3 illustrated, due to the asymmetry of metal routing, the PDN impedance observed by each chiplet may be different. For example, chiplet 1 may experience a peak impedance (Z1) (in mΩ) at a frequency (f1) (in MHz), while chiplet 2 may encounter a peak impedance (Z2) at a different frequency (f2) (in MHz), where Z1<Z2 and f1<f2. During a di / dt event, the voltage at chiplet 2 may drop faster and with a larger amplitude than that at chiplet 1. Therefore, when chiplet 2 detects the drop earlier, it initiates clock modulation, while chiplet 1 has not yet experienced the drop. This delay in clock modulation hinders drop recovery, thereby causing an extended voltage drop.

[0044] reference Figure 7 and Figure 8When the second chiplet detects a voltage drop, it initiates clock modulation because the voltage drop is faster, while the first chiplet remains unaware of the voltage drop and continues to operate at a high frequency. Chiplets 1 (710) and 2 (720) experience different impedance levels (Z1 and Z2) and frequencies (f1 and f2) due to differences in their power delivery networks (PDNs). During the di / dt event, chiplet 2 can experience a faster and more significant voltage drop than chiplet 1 due to its higher impedance and / or frequency. Therefore, chiplet 2 detects the drop earlier and initiates clock modulation to mitigate it. However, chiplet 1, which has not yet experienced a drop, continues to operate at its normal frequency without initiating clock modulation. This delay in clock modulation by chiplet 1 hinders recovery from the voltage drop, resulting in a prolonged voltage drop phase. In summary, impedance and frequency asymmetry among the chipsets can lead to different responses to voltage drop events, potentially prolonging the recovery process and affecting the overall system performance. Thus, this difference hinders drop recovery, such as... Figure 7 As shown.

[0045] Chip 2 begins clock modulation at time t1, causing its di / dt to decrease, while chip 1 maintains the same di / dt rate. Subsequently, chip 1 begins clock modulation at time t2, thus decreasing its di / dt rate. Therefore, the combined di / dt of chip 1 and chip 2 decreases only after time t2. During the interval between t1 and t2, the voltage continues to decrease, as... Figure 8 As shown.

[0046] As an illustration, during the di / dt event, chiplet 2 810 responds rapidly by initiating clock modulation at time t1 814, effectively reducing its current change rate (di / dt) and mitigating the experienced voltage drop 816. This action results in stable power consumption for chiplet 2 and helps prevent further voltage drop. However, chiplet 1 820, which has not yet detected a voltage drop, maintains its original di / dt rate during this initial phase. Until after time t2 824, chiplet 1 also participates in clock modulation, subsequently reducing its di / dt rate without adequately mitigating the voltage drop experience 826. Therefore, the combined di / dt of chiplets 1 and 2 only begins to decrease after time t2. Meanwhile, during the time interval between t1 and t2, while chiplet 2 is actively mitigating the voltage drop, chiplet 1 continues to operate at its standard di / dt rate, resulting in an extended voltage drop. This delay in clock modulation by chiplet 1 prolongs the duration of the recovery process, allowing the voltage drop to persist until both chiplets have successfully adjusted their di / dt rates.

[0047] Regarding voltage 830, even after chip 2 initiates clock modulation (also known as "clock compression"), effectively reducing its current change rate (di / dt) and mitigating the voltage drop 832, the drop continues 834. The voltage drop only begins to recover when chip 1 also begins its clock modulation. This indicates that the drop persists when only chip 2 actively mitigates it. Recovery of the voltage drop is only observed after both chips participate in clock modulation. Chip 2's mitigation efforts alone are insufficient to completely resolve the voltage drop, and combined action from both chips is required to effectively stabilize the voltage level.

[0048] refer to Figure 9 , Figure 9 The illustration depicts a power management scheme in which a single dropout detector drives clock modulation on other chiplets. The power management scheme is associated with a semiconductor system 900 having a power management engine. The semiconductor system 900 includes a base die 910, chiplets 1 920A and 2 920B, dropout detectors 930A and 930B, frequency dividers 940A and 940B, PLL1 950A and 2 950B, Vlimit 960A and 2 960B, EN1 970A and EN2 970B, bypass DD1 972A, bypass DD2 972B, bypass EN2 974A, and bypass EN1 974B. This technical scheme is illustrated with reference to a 3D-IC that uses the dropout detector of one chiplet to control clock modulation on another chiplet within a 3D-IC package. In particular, in a 3D-IC with multiple small chips and corresponding dropout detectors, dropout detectors with superior performance metrics (e.g., response time, noise filtering, error margin) can be identified and used to send clock modulation enable signals.

[0049] As an illustration, a semiconductor system (e.g., a 3D-IC package) may include a first chiplet (e.g., chiplet 920A) and a second chiplet (e.g., chiplet 920B) sharing a power supply (e.g., VCC 902). Each chiplet may also be independently coupled to other power management components (e.g., phase-locked loops (PLLs), frequency dividers, and clock modulation units). An event at one chiplet (e.g., a di / dt event) may cause a voltage drop at the other chiplet.

[0050] Chip 920A is identified as the chip that detects a voltage drop. If the voltage drop triggers clock modulation (e.g., the voltage level exceeds a voltage limit), a clock modulation enable signal is transmitted to the second chip to initiate clock modulation. Furthermore, if more than two chips exist, this signal is transmitted to all other chips. Chip 920B can also detect a voltage drop and generate a second clock modulation enable signal; however, a bypass mode (e.g., bypassing EN2 974A and bypassing EN1 974B) exists at each chip to bypass the second clock modulation signal. The bypass mode includes control logic to override the clock modulation enable signal, where overriding the clock modulation enable signal can refer to selectively overriding, discarding, or ignoring the clock modulation enable signal. In other words, the clock modulation enable signal is not used to control the corresponding clock modulation unit of the chip.

[0051] For AI products, the propagation delay of the clock modulation enable signal from one chip to another should ideally be less than a few nanoseconds. This can be ensured by implementing large input / output drivers at the transmitting end and routing the signal using metal layers that provide minimal resistance and capacitance within the chiplets and the bottom die (or interposer).

[0052] Example Method

[0053] refer to Figure 10 and Figure 11 The document provides flowcharts illustrating methods for providing power management using a power management engine of a semiconductor system. These methods can be executed using the semiconductor system described herein. In embodiments, one or more computer storage media have computer-executable or computer-usable instructions contained thereon that, when executed by one or more processors, can cause one or more processors to perform these methods (e.g., computer-implemented methods) within a semiconductor system (e.g., a computerized system).

[0054] Turning Figure 10 A flowchart is provided illustrating a method 1000 for providing power management in a semiconductor system using a power management engine. At block 1002, a voltage level associated with a shared power supply between the first and second chiplets is monitored at a first voltage drop detector on a first chiplet. At block 1004, a first voltage drop triggering a first clock modulation enable signal is detected. At block 1006, the first clock modulation enable signal is transmitted to a second chiplet having a second voltage drop detector. At block 1008, the first clock modulation enable signal is accessed at the second chiplet. At block 1010, a second clock modulation unit on the second chiplet is activated based on the first clock modulation enable signal.

[0055] Turning Figure 11A flowchart is provided illustrating method 1100 for providing power management in a semiconductor system using a power management engine. At block 1102, independent monitoring is performed at a first voltage drop detector on a first chiplet and a second voltage drop detector on a second chiplet. At block 1104, the detection of a first voltage drop triggers a first clock modulation enable signal. At block 1106, a second voltage drop is detected at the second voltage drop detector on the second chiplet. At block 1108, a second clock modulation enable signal destined for the first chiplet is transmitted from the second chiplet back to the first chiplet. At block 1110, a bypass mode is used at the first chiplet to bypass the second clock modulation enable signal from the second chiplet.

[0056] Literal support of the claims and embodiments

[0057] In some embodiments, a method is provided. The method includes: monitoring a voltage level associated with a shared power supply of a first chiplet and a second chiplet at a first voltage drop detector; detecting a first voltage drop that triggers a first clock modulation enable signal; transmitting the first clock modulation enable signal to a second chiplet having a second voltage drop detector; accessing the first clock modulation enable signal at the second chiplet; and activating a second clock modulation unit of the second chiplet based on the first clock modulation enable signal.

[0058] In any combination of the above embodiments of the method, the method further includes: detecting a second voltage drop at a second voltage drop detector of the second chiplet, the second voltage drop triggering a second clock modulation enable signal, wherein the second voltage drop is detected after the first voltage drop; transmitting the clock modulation enable signal to the first chiplet; and using a bypass mode at the first chiplet to bypass the second clock modulation enable signal from the second chiplet.

[0059] In any combination of the above embodiments of the method, a first clock modulation enable signal is transmitted to a first divider of the first chip and a second divider of the second chip.

[0060] In any combination of the above embodiments of the method, the first chiplet supports a bypass mode that includes control logic for overriding the clock modulation enable signal from the second chiplet.

[0061] In any combination of the above embodiments of the method, the second chiplet supports a bypass mode that includes control logic for overriding the clock modulation enable signal from the first chiplet.

[0062] In any combination of the above embodiments of the method, the first chiplet supports a bypass mode that includes control logic for overriding the dropout detector signal from the first dropout detector.

[0063] In any combination of the above embodiments of the method, the second chiplet supports a bypass mode that includes control logic for overriding the voltage drop detector signal from the second voltage drop detector.

[0064] In any combination of the above embodiments of the method, the first chiplet is coupled to the first phase-locked loop (PLL) and the first clock modulation unit, and the second chiplet is coupled to the second PLL and the second clock modulation unit.

[0065] In any combination of the above embodiments of the method, the method further includes: activating the first clock modulation unit of the first chip based on the first clock modulation enable signal.

[0066] In some embodiments, a method is provided. The method includes: monitoring voltage levels associated with a shared power supply of the first chiplet and the second chiplet at a first voltage drop detector and a second voltage drop detector of the second chiplet; detecting a first voltage drop that triggers a first clock modulation enable signal; transmitting the first clock modulation enable signal from the first chiplet to the second chiplet; detecting a second voltage drop at the second voltage drop detector of the second chiplet, the second voltage drop triggering a second clock modulation enable signal, wherein the second voltage drop is detected after the first voltage drop; transmitting the second clock modulation enable signal destined for the first chiplet from the second chiplet to the first chiplet; and using a bypass mode at the first chiplet to bypass the second clock modulation enable signal from the second chiplet.

[0067] In any combination of the above embodiments of the method, the method further includes: accessing a first clock modulation enable signal at the second chiplet; and activating a second clock modulation unit of the second chiplet based on the first clock modulation enable signal.

[0068] In any combination of the above embodiments of the method, the method further includes: a first clock modulation enable signal being transmitted to a first divider of a first chiplet and a second divider of a second chiplet, and the first chiplet being coupled to a first phase-locked loop (PLL) and a first clock modulation unit, and the second chiplet being coupled to a second PLL and a second clock modulation unit.

[0069] In any combination of the above embodiments of the method, the clock modulation enable signal is triggered based on the detection of a voltage level exceeding a threshold limit.

[0070] In any combination of the above embodiments of the method, the clock modulation enable signal is transmitted across the chiplet based on an input / output driver that utilizes metal layers to route the clock modulation enable signal, which provide reduced resistance and capacitance within the bottom die of the chiplet and integrated circuit.

[0071] In some embodiments, a semiconductor system is provided. The semiconductor system includes a shared power supply coupled to two or more chiplets; a first chiplet coupled to a first dropout detector, the first chiplet supporting a bypass mode including control logic for overriding a clock modulation enable signal from a second chiplet; and a second chiplet coupled to a second dropout detector, the second chiplet supporting a bypass mode including control logic for overriding a clock modulation enable signal from the second chiplet.

[0072] In any combination of the above embodiments of the system, the second dropout detector of the second chiplet is disabled, and the clock modulation enable signal from the first chiplet is used for clock modulation on the second chiplet.

[0073] In any combination of the above embodiments of the system, the first chiplet supports a bypass mode that includes control logic for overriding the dropout detector signal from the first dropout detector.

[0074] In any combination of the above embodiments of the system, the second chiplet supports a bypass mode that includes control logic for overriding the dropout detector signal from the second dropout detector.

[0075] In any combination of the above embodiments of the system, the first chiplet is configured to: monitor a voltage level associated with a shared power supply of the first and second chipslets at a first voltage drop detector of the first chiplet; detect a first voltage drop that triggers a first clock modulation enable signal; and transmit the first clock modulation enable signal to a second chiplet having a second voltage drop detector to cause activation of a second clock modulation unit of the second chiplet.

[0076] In any combination of the above embodiments of the system, the second chiplet is configured to: monitor a voltage level associated with a shared power supply of the first and second chipslets at a second dropout detector of the second chiplet; detect a second voltage drop at the second dropout detector of the second chiplet, the second voltage drop triggering a second clock modulation enable signal, wherein the second voltage drop is detected after the first voltage drop; and transmit the second clock modulation enable signal to the first chiplet, wherein the first chiplet uses a bypass mode to bypass the second clock modulation enable signal.

[0077] Additional structural and functional features of embodiments of this technical solution

[0078] Having identified the various components utilized herein, it should be understood that any number of components and arrangements can be employed to achieve the desired functionality within the scope of this disclosure. For example, for clarity of concept, components in the embodiments depicted in the figures are shown as lines. Other arrangements of these and other components can also be implemented. For example, although some components are depicted as single components, many of the elements described herein can be implemented as discrete or distributed components, or combined with other components, and can be implemented in any suitable combination and location. Some elements can be omitted entirely. Furthermore, the various functions described herein as being performed by one or more entities can be performed by hardware, firmware, and / or software, as described below. For example, various functions can be performed by a processor executing instructions stored in memory. Therefore, other arrangements and elements (e.g., machines, interfaces, functions, sequences, and functional groups) can be used in addition to or in lieu of those arrangements and elements shown.

[0079] The embodiments described in the following paragraphs can be combined with one or more of the specific alternatives described. In particular, the claimed embodiments may include alternative references to more than one other embodiment. The claimed embodiments may specify further limitations on the claimed subject matter.

[0080] The subject matter of this technical solution embodiment has been specifically described herein to satisfy legal requirements. However, the description itself is not intended to limit the scope of this patent. Rather, the inventors have envisioned that the claimed subject matter may also be embodied in other ways to include steps or combinations of steps different from those described herein, and in combination with other existing or future techniques. Furthermore, although the terms “step” and / or “box” may be used herein to mean different elements of the method employed, these terms should not be construed as implying any particular order between or among the various steps disclosed herein, unless and only if the order of the various steps is explicitly described.

[0081] For the purposes of this disclosure, the word "including" has the same broad meaning as the word "comprising," and the word "access" includes "receiving," "quoting," or "retrieval." Furthermore, the word "communication" has the same broad meaning as "receiving" or "transmitting," facilitated by software or hardware-based buses, receivers, or transmitters using the communication medium described herein. Additionally, words such as "a" and "a" include both plural and singular forms unless otherwise indicated. Thus, for example, the constraint of "feature" is satisfied where one or more features are present. Furthermore, the term "or" includes connective relations, disjunctive relations, and both (a or b therefore includes a or b, and a and b).

[0082] For the purposes of the detailed discussion above, the embodiments of this technical solution are described with reference to a distributed computing environment; however, the distributed computing environment depicted herein is merely exemplary. Components may be configured to perform novel aspects of the embodiments, wherein the term "configured for" may mean "programmed to" perform a specific task or implement a specific abstract data type using code. Furthermore, while embodiments of this technical solution generally refer to the technical solution environment and schematic diagrams described herein, it should be understood that the technology can be extended to other implementation contexts.

[0083] For the purposes of this disclosure, the term "support" refers to the provision of functionality, services, or assistance by a computing component or through computing operations within a broader computing system. When a computing component or set of operations supports a specific function, it means that it plays a role in enabling or performing that specific aspect of the computing system. This support can manifest in various ways, including processing data, performing operations, managing resources, and ensuring compatibility or interoperability with other components. Additionally, support can involve providing interfaces, APIs (Application Programming Interfaces), or protocols that allow seamless interaction and integration with other elements of the computing system. The concept of support is not limited to the provision of functionality but also encompasses maintenance, troubleshooting, and overall optimization of computing resources to ensure the robust and efficient operation of the computing system.

[0084] Embodiments of this technical solution have been described with respect to specific embodiments, which are intended in all respects to be illustrative and not restrictive. Alternative embodiments will be apparent to those skilled in the art without departing from the scope of this technical solution.

[0085] As can be seen from the foregoing, this technical solution is very suitable for achieving all the purposes and objectives described above, as well as other obvious and inherent advantages of the structure.

[0086] It should be understood that certain features and sub-combinations are useful and can be employed without reference to other features or sub-combinations. This is conceivable and within the scope of the claims.

Claims

1. A method, the method comprising: The voltage level associated with the shared power supply of the first chip and the second chip is monitored at the first voltage drop detector of the first chip; The detection (1004) triggers a first voltage drop in the first clock modulation enable signal; The first clock modulation enable signal is transmitted (1006) to the second chip having a second voltage drop detector; Access the first clock modulation enable signal (1008) at the second chip; as well as Based on the first clock modulation enable signal, the second clock modulation unit of the second chip is activated (1010).

2. The method according to claim 1, further comprising: A second voltage drop is detected at the second voltage drop detector of the second chip, and the second voltage drop triggers a second clock modulation enable signal, wherein the second voltage drop is detected after the first voltage drop; The clock modulation enable signal is transmitted to the first chip. as well as A bypass mode is used at the first chip to bypass the second clock modulation enable signal from the second chip.

3. The method according to claim 1, wherein the first clock modulation enable signal is transmitted to the first divider of the first chip and the second divider of the second chip.

4. The method of claim 1, wherein the first chiplet supports a bypass mode, the bypass mode including control logic for overriding a clock modulation enable signal from the second chiplet.

5. The method of claim 1, wherein the second chiplet supports a bypass mode, the bypass mode including control logic for overriding a clock modulation enable signal from the first chiplet.

6. The method of claim 1, wherein the first chiplet supports a bypass mode, the bypass mode including control logic for overriding a voltage drop detector signal from the first voltage drop detector.

7. The method of claim 1, wherein the second chip supports a bypass mode, the bypass mode including control logic for overriding the voltage drop detector signal from the second voltage drop detector.

8. The method according to claim 1, wherein the first chip is coupled to the first phase-locked loop (PLL) and the first clock modulation unit, and the second chip is coupled to the second PLL and the second clock modulation unit.

9. The method according to claim 1, further comprising: Based on the first clock modulation enable signal, the first clock modulation unit of the first chip is activated.

10. A method, the method comprising: The voltage level associated with the shared power supply of the first chip and the second chip is monitored (1102) at the first voltage drop detector of the first chip and the second voltage drop detector of the second chip; The detection (1104) triggers a first voltage drop in the first clock modulation enable signal; The first clock modulation enable signal is transmitted from the first chip to the second chip; A second voltage drop is detected (1106) at the second voltage drop detector of the second chip, and the second voltage drop triggers a second clock modulation enable signal, wherein the second voltage drop is detected after the first voltage drop; The second clock modulation enable signal destined for the first chip is transmitted from the second chip to the first chip (1108); as well as A bypass mode is used at the first chip, bypassing (1110) the second clock modulation enable signal from the second chip.

11. The method of claim 10, further comprising: Access the first clock modulation enable signal at the second chip; as well as Based on the first clock modulation enable signal, the second clock modulation unit of the second chip is activated.

12. The method of claim 10, wherein the clock modulation enable signal is transmitted across the chiplet based on an input / output driver that utilizes a metal layer to route the clock modulation enable signal, the metal layer providing reduced resistance and capacitance within the bottom die of the chiplet and integrated circuit.

13. A semiconductor system, comprising: Shared power supply (320A), coupled to two or more small chips; A first chip (310A) is coupled to a first voltage drop detector. The first chip supports a bypass mode, which includes control logic to override a clock modulation enable signal from a second chip. as well as The second chip (320A) is coupled to the second voltage drop detector. The second chip supports a bypass mode, which includes control logic to override the clock modulation enable signal from the second chip.

14. The system of claim 13, wherein the second dropout detector of the second chiplet is disabled, and the clock modulation enable signal from the first chiplet is used for clock modulation on the second chiplet.

15. The system of claim 13, wherein the first chiplet is configured to: The voltage level associated with the shared power supply of the first chip and the second chip is monitored at the first voltage drop detector of the first chip; Detect the first voltage drop that triggers the first clock modulation enable signal; as well as The first clock modulation enable signal is transmitted to the second chip with a second voltage drop detector to activate the second clock modulation unit of the second chip; and The second small chip is configured as follows: The voltage level associated with the shared power supply of the first chip and the second chip is monitored at the second voltage drop detector of the second chip; A second voltage drop is detected at the second voltage drop detector of the second chip, and the second voltage drop triggers a second clock modulation enable signal, wherein the second voltage drop is detected after the first voltage drop; as well as The second clock modulation enable signal is transmitted to the first chip, wherein the first chip uses a bypass mode to bypass the second clock modulation enable signal.

Images