Read-modify-write manager with arithmetic circuitry

Abstract

In described examples, an apparatus includes a first memory (222) and a second memory, an arithmetic pipeline (212), a write pipeline (214), and a controller (202). An update request includes an ADD value and a memory location indicator for the second memory. The first memory (222) receives a first update request and stores the first update request at a tail memory location (228). A read of the second memory is controlled in response to reading a second memory location indicator of a second update request from an intermediate memory location (226) of the first memory (222), and responsive read data is stored at the intermediate memory location (226). A third update request and read data are read from a head memory location (224) of the first memory (222), and the third update request and read data are provided to the arithmetic pipeline (212). The arithmetic pipeline (212) adds the corresponding ADD value and read data to generate a result, which is provided to the write pipeline (214). The write pipeline (214) responsively generates a write transaction.

Description

Technical Field

[0001] This application generally relates to network accelerators, and more specifically, to a read-modify-write (RMW) manager for managing updates to stored network statistics. Background Technology

[0002] Integrated circuits connecting to a network (e.g., a system-on-a-chip (SoC)) may include network accelerators to accelerate the SoC's transceiver (transmit and receive) participation in the network. In turn, the network accelerator may include circuitry to improve transceiver performance by tracking network traffic statistics and responsively adjusting network transceiver behavior. In some instances, this circuitry may include an RMW manager to update stored network statistics in response to requests from various processor cores of the SoC. Network statistics include, for example, the number of packets received within a given time interval, the number of bytes received per packet thread, and the packet size and associated thread count position. Summary of the Invention

[0003] In the described example, an apparatus includes a first memory and a second memory, an arithmetic pipeline, a write pipeline, and a controller. An update request includes an ADD value for the second memory and a memory location indicator. The first memory receives a first update request and stores it at a tail memory location. Reading from the second memory is controlled in response to reading a second update request from an intermediate memory location of the first memory, and responsive read data is stored at the intermediate memory location. A third update request and read data are read from a head memory location of the first memory and provided to the arithmetic pipeline. The arithmetic pipeline adds a corresponding ADD value and read data to generate a result, which is provided to the write pipeline. The write pipeline responsively generates a write transaction. Attached Figure Description

[0004] Figure 1 This is a functional block diagram of an instance SoC that includes a network accelerator with an RMW manager.

[0005] Figure 2 for Figure 1 Example functional block diagram of RMW Manager.

[0006] Figure 3A For use Figure 2 The first flowchart of the process of updating statistics using the RMW manager.

[0007] Figure 3B To continue Figure 3A For use Figure 2The second flowchart shows the process of updating statistics using the RMW manager.

[0008] Figure 3C To continue Figure 3A and 3B For use Figure 2 The third flowchart shows the instance process of using the RMW manager to update statistics.

[0009] Figure 4 To show the use Figure 2 The flowchart shows an example of how the RMW manager forwards data.

[0010] Figure 5 For use Figure 2 The table of RMW target interface input / output (I / O) fields in the instance of the RMW manager.

[0011] Figure 6 For use Figure 2 The table of I / O fields of the RMW initiator interface of the RMW manager instance. Detailed Implementation

[0012] The instance network processing accelerator core (NPAC) circuitry tracks network statistics and responsively controls system network interactions, for example, by limiting the number of received packets allowed to be processed within a given time interval in response to a threshold. The threshold is stored in shared memory, such as a data store. In one instance, the threshold is implemented by decrementing a count from the threshold in response to received packets. When a packet is received, the processor in the SoC checks if it meets the corresponding threshold of the SoC. If so, the received packet is discarded. Otherwise, the packet is forwarded, for example, to the application host processor on the SoC or to a network port, such as an Ethernet or Controller Area Network (CAN) port. After the threshold comparison, if the threshold is not equal to zero, the processor uses a statistics function block to decrement the threshold. The threshold is periodically reset to a default value in response to a timer or other clock control circuitry. In some instances, the NPAC or other network controller tracks network statistics that supplement or replace the admission packet threshold.

[0013] Some SoCs have multiple processors or processor cores that can independently request updates to statistical values ​​such as the thresholds mentioned above. These types of statistics are instances of shared data values ​​that can be frequently accessed (e.g., read or written) by several different entities with a high probability of conflict. The RMW manager described herein enables the updating of such shared data values ​​without locking shared memory (or with reduced locking of shared memory), while maintaining consistency. Avoiding memory lock requirements and associated locking circuitry achieves some or all of the following benefits, such as reduced device area cost, increased memory and processing efficiency, reduced power cost, reduced firmware or software program size and / or complexity, and faster data updates.

[0014] Use the same reference numerals or other reference designations in the drawings to indicate structurally and / or functionally related features.

[0015] Figure 1 This is a functional block diagram of an example SoC 100 containing network accelerator 102. SoC 100 also includes another processor 104 (in addition to the processor of network accelerator 102) and other circuitry 106 communicating via network accelerator 102. Network accelerator 102 includes a bus 108, a processor 110, a processor controller 112, a scheduler 114, a statistics block 116, a configuration interface 118, data memory 120, other memory 122, a semaphore block 124, and other functional blocks 126. In some instances, the other memory 122 contains instruction memory or one or more lookup tables. In some instances, only the processor within the SoC can access network statistics tracked in response to statistics block 116.

[0016] Bus 108 includes a bus mesh architecture 128 and a bus controller 130. The bus mesh architecture 128 corresponds to the interconnection between or within various functional blocks of the network accelerator 102. The bus controller 130 determines the priority of messages requesting transmission using the bus mesh architecture 128 to a specified functional block within or outside the network accelerator 102. Processor 110 includes a first processor core 132 and a second processor core 134. In some instances, processor 110 is a Reduced Instruction Set Computing (RISC) processor. Statistics block 116 includes an RMW manager 136.

[0017] Other processors 104 are communicatively connected to network accelerator 102 and to other circuitry 106. In some instances, other circuitry 106 is communicatively connected to network accelerator 102. Statistics block 116 is communicatively connected to configuration interface 118. Each of processor 110, processor controller 112, scheduler 114, configuration interface 118, data memory 120, other memory 122, semaphore block 124, and other functional blocks 126 is communicatively connected to bus 108. Specifically, processor 110 and other processors 104 are connected to communicate with statistics block 116 via configuration interface 118. Statistics block 116 is connected to output to bus 108 (in some instances, via configuration interface 118). In some instances, for RMW manager 136, configuration interface 118 corresponds to a single-publishing port where users write statistical updates to it via memory-mapped registers. In some instances, configuration interface 118 is part of statistics block 116. In some instances, data memory 120 is shared memory. In some instances, bus 108 is referred to as the Switch Central Resource (SCR).

[0018] The first processor core 132, the second processor core 134, and other processors 104 are referred to herein as users and components of network accelerator 102. In some instances, users use semaphore block 124 or other functional block 126 (e.g., locking circuitry dedicated to statistically related memory access functionality) to lock access to data memory 120 or other memory 122 (or a portion thereof). While performing a user-requested data access (e.g., a read or write operation), the memory access is locked to the requesting user on a first-come, first-served basis. The access lock prevents other users from accessing the locked memory (or a portion thereof) when the data access is complete. Therefore, the memory access blocked by the lock stops when the memory access performed by the user holding the lock is completed. After the memory access initiated by the locking user is completed, the locking user communicates with semaphore block 124 to unlock the locked memory. In some instances, memory locking is used to maintain the ordering and / or consistency of memory operations. In some instances, different device functionalities use different circuitry to implement locking, such as different memories and / or different logic circuits.

[0019] As described above, the memory locking process is time-consuming and consumes device area, power, and other device resources. The RMW manager 136 enables ordered RMW operations on memory (e.g., data memory 120) used to store network statistics without locking. These network statistics are only one type of shared data values ​​frequently accessed by several different entities (e.g., processor 110, processor 104, etc.) with a high probability of conflict, and the RMW manager 136 is equally suitable for managing access to other types of shared data.

[0020] Figure 2 for Figure 1 An example functional block diagram of the RMW manager 136 is provided. The RMW manager 136 includes an RMW controller 202 and an RMW pipeline 204. The RMW pipeline 204 includes a decoding circuit 205, a working first-in-first-out (FIFO) memory 206, a holding memory 208, a read FIFO 210, an arithmetic pipeline 212, a write pipeline 214, a data interface register 216, and a data forwarding block 218. The data interface refers to the physical bus that connects the RMW manager 136 to the data memory 120 in which statistical values ​​are stored. The read FIFO 210 includes a FIFO memory controller 220 and a read FIFO memory 222. The read FIFO memory 222 uses circular addressing, such that repeatedly incrementing the pointer that initially indicates a memory location in the read FIFO memory 222 will cause the pointer to loop back and eventually indicate the initially indicated memory location. In this document, incrementing the pointer means adjusting the pointer to indicate the next memory location in sequence. It should be noted that in many instances, the tail pointer 228 is used to write (add) data to the tail of the FIFO queue, and the head pointer 224 is used to read (remove) data from the head of the FIFO queue.

[0021] RMW controller 202 is connected to control RMW pipeline 204. Decoding circuitry 205 receives messages referred to herein as statistics update requests from configuration interface 118 (via bus 108). A statistics update request corresponds to a request from a user to modify statistics values. In one instance, the statistics value is a threshold corresponding to the number of received packets that can be admitted within a specified time interval.

[0022] A statistics update request may include a pointer to a target memory location and / or an ADD value. The target memory location stores the statistics to be modified, and the ADD value is a signed value to be added to the statistics to generate the updated statistics. For example, an ADD value of +1 (positive one) or -1 (negative one) corresponds to an increment or decrement operation, respectively. In some instances, users who may send statistics update requests include processor cores within network accelerator 102 (e.g., first processor core 132 and second processor core 134), as well as other processors 104 outside network accelerator 102 that implement software performing network-related functionalities.

[0023] If the statistics update request contains both an ADD value and a memory pointer, then the decoding circuit 205 passes the statistics update request to the working FIFO memory 206. If the statistics update request contains only one of an ADD value or a memory pointer, then the decoding circuit 205 passes the statistics update request to the holding memory 208. This allows the ADD value and memory pointer to be specified in separate requests. For example, the first request can specify an ADD value, and the second request can specify the corresponding memory pointer, or vice versa.

[0024] The hold memory 208 outputs to the working FIFO memory 206. The working FIFO memory 206 outputs to the read FIFO 210. The read FIFO 210 communicates with the data forwarding block 218 and outputs to the arithmetic pipeline 212 and the data interface register 216. The arithmetic pipeline 212 outputs to the data forwarding block 218 and the write pipeline 214. The write pipeline 214 outputs to the data forwarding block 218 and the data interface register 216. The data forwarding block 218 outputs to the data interface register 216. The data interface register 216 outputs to the data interface.

[0025] The statistics update request includes either an ADD value or a pointer (memory pointer) to a location in the shared memory of network accelerator 102, which stores network statistics, such as data memory 120. In some instances, RMW controller 202 controls reads and writes to memory within RMW pipeline 204 and comparisons of actions and other data movements within RMW pipeline 204. In some instances, a memory controller within RMW pipeline 204 (including FIFO memory controller 220) may be described as part of or operated in response to RMW controller 202.

[0026] RMW pipeline 204 receives statistics update requests from requesting users via configuration interface 118. In some instances, holding memory 208 contains memory locations corresponding to each user for whom statistics update requests can be provided to RMW manager 136. If a statistics update request contains either an ADD value or a memory pointer, then the statistics update request is written to the location in holding memory 208 corresponding to the requesting user.

[0027] In some instances, one or more status bits are used to indicate whether and / or which locations in the holding memory 208 contain both an ADD value and a memory pointer. Once the ADD value and the memory pointer corresponding to the requesting user have been written to a location in the holding memory 208, the ADD value and memory pointer are read from the holding memory 208 and written to the tail memory location of the working FIFO memory 206. Alternatively, if the RMW pipeline 204 receives a statistics update request containing both an ADD value and a memory pointer, then the ADD value and memory pointer are written to the tail memory location of the working FIFO memory 206 instead of to the holding memory 208.

[0028] The RMW controller 202 tracks a head pointer 224, a read pointer 226, and a tail pointer 228, each indicating a different memory location within the read FIFO memory 222. The head pointer 224 indicates the head of the FIFO queue. The tail pointer 228 indicates the tail of the FIFO queue. The read pointer 226 indicates the location in the read FIFO memory 222 that stores a memory pointer, which in turn indicates the location in data memory 120 (or other memory 122) that stores a statistic that will be the next value updated (modified) using an ADD value corresponding to the memory pointer. Therefore, the read FIFO memory 222 is a wraparound window where the latest data is at the tail memory location, the oldest data is at the head memory location, and the read memory locations are in between.

[0029] Each memory location in the FIFO memory 222 may have several fields, such as a memory pointer field, an ADD value field, a read value field, and a status bit field. The memory pointer field stores a memory pointer indicating the memory location in the data memory 120 (or other shared memory) where the statistical value to be updated is stored. The ADD value field stores an ADD value corresponding to the memory pointer used to modify the statistical value stored at the memory location corresponding to the memory pointer. The read value field stores the statistical value (described below) to be modified after being read from the data memory 120. The status bit field stores a status bit indicating whether the read value field stores valid data to be modified.

[0030] The status bit can have a valid (VALID) value, indicating that valid data is stored in the read value field at the read FIFO memory location 222, or an invalid (INVALID) (or / valid ( / VALID)) value, indicating that valid data is not stored in the read value field at the read FIFO memory location 222. The status bit field has an invalid value when the memory pointer and ADD value are written to the read FIFO memory location 222 indicated by the tail pointer 228. The invalid value of the status field is set simultaneously with or before the initial write of the ADD value and memory pointer to the read FIFO memory location 222 indicated by the tail pointer 228.

[0031] RMW controller 202 controls working FIFO memory 206 to retrieve the ADD value and memory pointer stored at the head memory location of working FIFO memory 206, controls read FIFO memory 222 to store the ADD value and memory pointer into the corresponding field at the read FIFO memory 222 location indicated by tail pointer 228, and increments the tail pointer. (In Figure 2 In the illustrated example, incrementing the memory pointer of the read FIFO memory 222 corresponds to moving the pointer to the right. The RMW controller 202 controls the read FIFO memory 222 to retrieve the memory pointer stored at the location indicated by the read pointer 226 in the read FIFO memory 222, and generates a read transaction requesting a memory read from the data memory 120 at the location corresponding to the retrieved memory pointer. The read FIFO memory 222 provides the read transaction to the data interface register 216 to transmit the read transaction to the data memory 120 via the bus 108. After the data memory 120 returns responsive read data, the read data is stored in the read value field corresponding to the location of the read FIFO memory 222 at the memory pointer, and the status bit field at said location is set to a valid value indicating the presence of valid read data. The RMW controller also increments the read pointer 226.

[0032] RMW controller 202 controls the reading of the ADD value, read data, and memory pointer from the read FIFO memory 222 at the location indicated by head pointer 224 and provides them to arithmetic pipeline 212, and increments head pointer 224. Arithmetic pipeline 212 performs a mathematical function (e.g., addition or subtraction) on the ADD value and read data to generate a modified value. Write pipeline 214 generates a write transaction requesting the modified value to be written to the location in data memory 120 corresponding to the memory pointer. Write pipeline 214 provides the write transaction containing the modified value and memory pointer to data interface register 216. The write transaction is then read from data interface register 216 and transmitted to data memory 120 via bus 108. In response to the write transaction, the modified value is written to the location in data memory 120 indicated by the memory pointer.

[0033] In this document, a reference to information stored in the read FIFO memory 222 refers to information stored between the memory location indicated by the head pointer 224 and the memory location indicated by the tail pointer 228 (in terms of modulo addressing) and containing the memory locations indicated by the head pointer 224 and the tail pointer 228. The data forwarding block 218 compares the memory pointer stored in the read FIFO memory 222 with the memory pointer associated with the ADD value and corresponding read value forwarded through the arithmetic pipeline 212 or the write pipeline 214. If the memory pointer in the read FIFO memory 222 matches the memory pointer in the arithmetic pipeline 212 or the write pipeline 214 due to a first request and subsequent requests modifying the same value, then the following actions can be performed. First, the modified value associated with the first request and corresponding to the matching memory pointer in the arithmetic pipeline 212 or the write pipeline 214 is copied to the read FIFO memory 222 location corresponding to the matching memory pointer and associated with the subsequent request. Second, the status bit in the read FIFO memory location 222 corresponding to the matching memory pointer is set to valid. The status bit is set to valid because the modified value pulled from the arithmetic pipeline 212 or the write pipeline 214 already contains the read value previously read from the data memory location 120 corresponding to the memory pointer. Third, the matching memory pointer and the corresponding modified value associated with the first request in the arithmetic pipeline 212 or the write pipeline 214 are discarded.

[0034] It should be noted that it is unnecessary to perform a read of the data memory 120 corresponding to the matching memory pointer again, because the read is performed to generate a modified value associated with the first request while still in flight. It should also be noted that the modified value will be added to the ADD value corresponding to the matching memory pointer read from the FIFO memory 222 to generate a new modified value, which will be written back to the location in the data memory 120 where the corresponding statistics are stored. Therefore, the use of the data forwarding block 218 improves the operational efficiency of the RMW manager 136.

[0035] In some instances, data forwarding block 218 invalidates (discards) the matching memory pointer and the corresponding modified value associated with the first request by sending a command to data interface register 216 to overwrite the corresponding write transaction with a null value, or by setting the status flag that makes the write transaction eligible for transmission to an invalid value. In some instances, data forwarding block 218 invalidates the matching memory pointer and the corresponding modified value by sending a command to arithmetic pipeline 212 or write pipeline 214.

[0036] Figure 3A For use Figure 2 The first flowchart of the RMW Manager 136 update statistics information instance process 300. Figure 3A exist Figure 3B and 3C Continued. Figure 3A The first part 300a of process 300 is shown. Figure 3B The second part 300b of process 300 is shown, and Figure 3C The third part, 300c, of process 300 is shown. In some instances, process 300 describes a procedure for handling a specific statistical update request. Other statistical update requests can be handled by other iterations of process 300, which is executed in parallel with the specific statistical update request, using the RMW pipeline 204.

[0037] In step 302, the requesting user provides a statistics update request to statistics block 116. In one instance, the requesting user writes to the statistics memory-mapped register (MMR) associated with statistics block 116. The statistics update request contains either an ADD value or a pointer to a location in data memory 120 (or other shared memory), or both. In some instances, the statistics MMR resides in the processor or processor core corresponding to the requesting user. The presence of the statistics update request in the statistics MMR indicates a request to bus controller 130 to control the transfer of the statistics update request to statistics block 116.

[0038] In step 304, bus controller 130 arbitrates statistical update requests with other user requests to determine which statistical update request or other user request will be transmitted next via bus mesh architecture 128. In some instances, a round-robin, fixed-priority, or other priority determination system is used to determine request priority. Arbitration by bus controller 130 can impose an ordering on statistical update requests from various users, such that RMW manager 136 receives one statistical update request message at a time. In some instances, arbitration is used when multiple users simultaneously attempt to use the same physical bus interface.

[0039] In step 306, the bus mesh architecture 128 provides a statistics update request to the configuration interface 118 corresponding to statistics block 116. As described above, the configuration interface 118 corresponding to statistics block 116 is a single-publishing port. Therefore, the bus mesh architecture 128 sends one request to the RMW manager 136 at a time, and the configuration interface 118 receives one request at a time in the RMW manager 136. This enforcement of serial request behavior helps the RMW manager 136 maintain the ordering and / or consistency of statistics-related memory operations as described.

[0040] In step 308, configuration interface 118 accepts a statistics update request. In some instances, configuration interface 118 may reject the statistics update request if the working FIFO memory 206 is full and the statistics update request contains both an ADD value and a memory pointer, and / or if the read FIFO memory 222 is full. The statistics update request remains on bus 108 until configuration interface 118 accepts it. In some instances, the working FIFO memory 206 becomes full after the read FIFO memory 222 has become full. In some instances, if the working FIFO memory 206 is full, the RMW controller 202 sends a request to configuration interface 118 to set the READY flag to a NOT_READY value. Once the working FIFO memory 206 and / or the read FIFO memory 222 have been cleared to a specified threshold level, the RMW controller 202 sends a request to configuration interface 118 to set the READY flag to a READY value. If the ready flag has a ready value, then the configuration interface 118 accepts the statistics update request, and if the ready flag has a not ready value, then the statistics update request is rejected. As described above, once the ready flag changes from a not ready value to a ready value, the statistics update requests on bus 108 are arbitrated through bus 108 and accepted serially (one at a time) by the configuration interface 118.

[0041] In step 310, the RMW controller 202 determines whether the statistics update request contains an ADD value, a memory pointer, or both. In one example, this determination is performed by the decoding circuit 205. If the statistics update request contains both an ADD value and a memory pointer, then process 300 continues to step 312. If the statistics update request contains only one of an ADD value or a memory pointer, then process 300 continues to step 314.

[0042] In step 312, the RMW controller 202 controls the ADD value and memory pointer in the statistical update request written to the tail memory location of the working FIFO memory 206, and increments the tail pointer of the working FIFO memory 206. Process 300 then continues in step 320.

[0043] In step 314, the ADD value or memory pointer is written to the corresponding field (ADD value field or memory pointer field) of the holding memory 208 at the memory location corresponding to the requesting user. In step 316, the RMW controller 202 determines whether the memory location corresponding to the requesting user contains both an ADD value and a memory pointer, based on, for example, the first request providing an ADD value and the second request providing a corresponding memory pointer, or vice versa. If both are present, then process 300 proceeds to step 318. Otherwise, process 300 returns to step 302.

[0044] In step 318, the RMW controller 202 controls the retrieval of the ADD value and memory pointer corresponding to the requesting user from the holding memory 208 and writes them to the tail memory location of the working FIFO memory 206, and increments the tail pointer of the working FIFO memory 206.

[0045] Figure 3B To continue Figure 3A For use Figure 2 The second flowchart of the instance process 300 for updating statistics using the RMW manager 136 is as described above. Figure 3B The second part 300b of process 300 is shown.

[0046] In step 320, the RMW controller 202 retrieves the ADD value and memory pointer from the head of the working FIFO memory 206, increments the pointer to the head of the working FIFO memory 206, and stores the retrieved ADD value and memory pointer in the read FIFO memory 222 at the memory location pointed to by the tail pointer 228. In some instances, the RMW controller 202 waits until the read FIFO memory 222 becomes available; therefore, the read FIFO memory 222 is not read from or written to until a write to the read FIFO memory 222 is controlled. In some instances, the RMW controller 202 maintains a queued list of read and write operations performed on the read FIFO memory 222.

[0047] In step 322, the RMW controller 202 determines whether a status bit corresponding to the read FIFO memory location 222 of the read pointer 226 is set to valid, indicating that valid read data is stored at the read FIFO memory location 222 corresponding to the read pointer 226. If that status bit is set to valid, then in step 324, the RMW controller 202 increments the read pointer 226 to the next memory location of the read FIFO memory 222, and process 300 continues to step 334. In response to process 400 for data forwarding determining that the memory pointer in the arithmetic pipeline 212 or the write pipeline 214 matches the memory pointer stored at the read FIFO memory location 222, the status bit at the read FIFO memory location 222 may be set to valid before step 322. Regarding Figure 4 The process 400 for data forwarding is further described. If the status bit is set to invalid (indicating that no valid read data has been stored at the read FIFO memory 222 location corresponding to read pointer 226), then process 300 continues in step 326.

[0048] In step 326, the RMW controller 202 controls the read FIFO memory 222 to read at the memory location corresponding to the read pointer 226 to retrieve the stored memory pointer. In step 328, when the data port is available, the RMW controller 202 provides the retrieved memory pointer to the data port of the statistics block 116 as a read request. In some instances, a single such read request is pending at a time. In some instances, this constraint is imposed by the single-issue nature of the data port of the RMW manager 136.

[0049] In step 330, a read request is received by bus 108 and data memory 120 and provided to data memory 120 via bus 108. Data is read from the data memory 120 at the location corresponding to the memory pointer, and the read data is returned to the data port via bus 108. In step 332, RMW controller 202 controls the read data to be stored in the read data field at the read FIFO memory 222 location from which the memory pointer is read, sets the status bit to a valid value, and increments the read pointer 226 to the next memory location in the read FIFO memory 222.

[0050] Figure 3C To continue Figure 3A and 3B For use Figure 2 The third flowchart of the instance process 300 for updating statistics using the RMW manager 136. As described above, Figure 3C The third part 300c of process 300 is shown.

[0051] In step 334, the RMW controller 202 determines whether the status bit corresponding to the read FIFO memory 222 position of the head pointer 224 is set to a valid value. If yes, then process 300 continues to step 336. Otherwise, the check in step 334 is repeated until a valid value is detected. In some instances, the check in step 334 may return an invalid value in response to a delay in steps 330 and / or 332, such as a delay in accessing the data memory 120 in step 330. In some instances, the operation of the RMW manager 136 may continue, allowing other steps of process 300 to be performed on other statistical update requests, while process 300 waits for step 330 to detect a valid value.

[0052] In step 336, the RMW controller 202 controls the reading of the FIFO memory 222 position corresponding to the head pointer 224, provides the retrieved read data, ADD value, and memory pointer to the arithmetic pipeline 212, and increments the head pointer 224 to indicate the next read FIFO memory 222 position in sequence. Recall that the retrieved memory pointer is used to retrieve the read data and corresponds to the statistics being updated.

[0053] In step 338, the arithmetic pipeline 212 performs a signed addition on the ADD value and the read data to generate an updated (result) value. In step 340, the RMW controller 202 provides the updated value, along with the corresponding retrieved memory pointer, to the write pipeline 214.

[0054] In step 342, write pipeline 214 generates a write transaction requesting the updated value to be written to the memory location in data memory 120 indicated by the retrieved memory pointer. When the data port of the statistics block becomes available, RMW controller 202 moves the write transaction from write pipeline 214 to the data port. In step 344, the write transaction is accepted on the data port, bus 108 transmits the write transaction to data memory 120, and the updated value is written to the memory location corresponding to the retrieved memory pointer. The described data forwarding enables more efficient memory use, reduces the number of required bus transactions, reduces power consumption of the statistics-related RMW process, reduces memory and / or bus mesh contention, and enables network accelerators to handle greater capacity and / or throughput.

[0055] Figure 4 To show the use Figure 2 The flowchart illustrates an instance of data forwarding process 400 performed by the RMW manager 136. In step 402, the data forwarding block 218 compares the memory pointer stored in the read FIFO memory 222 with the memory pointer corresponding to the modified value passed through the arithmetic pipeline 212 or the write pipeline 214. If the memory pointer in the read FIFO memory 222 matches the memory pointer in the arithmetic pipeline 212 or the write pipeline 214, then process 400 continues to step 406. Otherwise, in step 404, process 400 waits until another entry (memory pointer and ADD value) is stored in the read FIFO memory 222, or another entry (memory pointer, ADD value, and read value) is provided to the arithmetic pipeline 212, and then returns to step 402.

[0056] In step 406, data forwarding block 218 provides the modified value corresponding to the match memory pointer from arithmetic pipeline 212 or write pipeline 214 to read FIFO 210. In step 408, RMW controller 202 controls read FIFO memory 222 to store the modified value in the read data field at the location of read FIFO memory 222 corresponding to the match memory pointer, and sets the corresponding status bit to valid. In step 410, the match memory pointer and the corresponding modified value in arithmetic pipeline 212 or write pipeline 214 are discarded.

[0057] Figure 5 For use Figure 2Table 500 lists the RMW target interface I / O fields of the RMW manager 136. These interface I / O fields correspond to the hardware I / O interfaces of the corresponding function blocks for the network accelerator 102. Regarding the interface I / O fields listed in Table 500, the configuration interface 118 of the RMW manager 136 is the target, and the user is the initiator. Therefore, the interface I / O fields listed in Table 500 are used to generate I / O requests issued by the user and executed by the configuration interface 118 of the RMW manager 136. In one instance, the user uses the RMW target interface I / O fields described in Table 500 to generate a statistical update request that is sent to the RMW manager 136 (via the configuration interface 118) for execution.

[0058] The first column 502 indicates the instance interface I / O field name, the second column 504 indicates the input or output direction, the third column 506 indicates the instance interface I / O field width, and the fourth column 508 provides a description of the corresponding interface I / O field. The request (req) field is related to input, has a one-bit width, and indicates an interface bus request. The direction (dir) field is related to input, has a one-bit width, and indicates the interface bus direction. In one instance, zero indicates a write, and one indicates a read. The address field is related to input, has an eight-bit width, and indicates the interface bus address. The byten field is related to input, has an eight-bit width, and indicates that the interface bus byte is enabled. The routeid field is related to input, has a twelve-bit width, and indicates the interface bus initiator identifier (ID). The wdata field is related to input, has a 64-bit width, and indicates that data is being written to the interface bus. The wready field is related to output, has a one-bit width, and indicates that the interface bus is ready to write. The rdatap field is related to output, has a 64-bit width, and indicates that data is being read from the interface bus. The rready field is related to the output, has a bit width of one, and indicates that the interface bus is ready to read.

[0059] Figure 6 For use Figure 2Table 600 lists the RMW initiator interface I / O fields of the RMW manager 136. These interface I / O fields correspond to the hardware I / O interfaces of the corresponding function blocks for the network accelerator 102. Regarding the interface I / O fields listed in Table 600, the RMW manager 136 or statistics block 116 is the initiator, and the data storage 120 is the target. Therefore, the interface I / O fields listed in Table 600 are issued by the RMW manager 136 or statistics block 116 for execution by the data storage 120 (e.g., by the memory controller of the data storage 120). In some instances, the RMW manager 136 uses the RMW initiator interface I / O fields described in Table 600 to generate read requests to retrieve updated statistics from the data storage 120, or to generate write requests (write transactions) to write updated statistics to the data storage 120.

[0060] The first column 602 indicates the instance interface I / O field name, the second column 604 indicates the input or output direction, the third column 606 indicates the instance interface I / O field width, and the fourth column 608 provides a description of the corresponding interface I / O field. The `req` field is output-related, has a one-bit width, and indicates an interface bus request. The `dir` field is output-related, has a one-bit width, and indicates the interface bus direction. In one instance, zero indicates a write, and one indicates a read. The `address` field is output-related, has an eight-bit width, and indicates the interface bus address. The `byten` field is output-related, has an eight-bit width, and indicates that the interface bus byte is enabled. The `wdata` field is output-related, has a 64-bit width, and indicates that data is being written to the interface bus. The `wready` field is input-related, has a one-bit width, and indicates that the interface bus is ready to write. The `rdatap` field is input-related, has a 64-bit width, and indicates that data is being read from the interface bus. The `rready` field is input-related, has a one-bit width, and indicates that the interface bus is ready to read.

[0061] As described above, when multiple different users simultaneously request updates to statistical values, the following applies: Figure 2 The RMW manager 136 enables consistency. The RMW manager 136 maintains a temporal order of statistical updates, ensuring that the correct value is written at the write time. This is achieved by controlling the execution of single statistical update data accesses to the data storage 120 at a time and by temporally ordering these accesses.

[0062] In some instances, integrated circuits other than the SoC include an RMW manager, such as RMW manager 136.

[0063] In some instances, the functional blocks other than network accelerator 102 include RMW managers, such as RMW manager 136.

[0064] In some instances, the processor is a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller unit (MCU).

[0065] In some instances, the processes described herein may be implemented as hardware, software, or a combination thereof.

[0066] In some instances, the status bit is set to invalid when there is a write to the read FIFO memory location 222 indicated by the tail pointer 228. In some instances, the status bit is set to invalid when an ADD value and a memory pointer are read from the read FIFO memory location 222 indicated by the head pointer 224 to be provided to the arithmetic pipeline 212.

[0067] The circuits or devices described herein as containing certain components may be practically adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may instead contain semiconductor elements only within a single physical device (e.g., a semiconductor die and / or IC package) and may be adapted to be coupled at least some of the passive elements and / or sources during or after manufacturing, for example, by an end user and / or a third party, to form the described structure.

[0068] The techniques described in this disclosure may also be embodied or encoded in articles of art comprising non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media may include random access memory (RAM), read-only memory (ROM), programmable ROM, erasable programmable ROM, electronically erasable programmable ROM, flash memory, solid-state drive, hard disk, magnetic media, optical media, or any other computer-readable storage device or tangible computer-readable medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. In some instances, non-transitory storage media may store data that may change over time (e.g., in RAM or cache memory).

[0069] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with minimal or no alteration to the remaining circuitry. For example, metal-oxide-semiconductor FETs (“MOSFETs”) (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs, such as NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices disclosed herein. The transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a silicon-germanium (SiGe) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0070] The circuits described herein may be reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0071] While some elements of the described examples may be contained within the IC and others external to the IC, in other example embodiments, additional or fewer features may be incorporated into the IC. Additionally, some or all features shown as external to the IC may be contained within the IC, and / or some features shown as internal to the IC may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0072] The use of the phrase “ground” in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding connection applicable to or suited to the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means + / - 10% of said value, or, if the value is zero, then means a reasonable range of values ​​near zero.

[0073] Although this disclosure has been described with reference to illustrative embodiments, this specification is not restrictive. Those skilled in the art will understand, upon referring to this specification, various modifications and combinations of the illustrative embodiments and other embodiments.

Claims

1. An apparatus comprising: First memory; Second memory; An arithmetic pipeline coupled to the first memory; The write pipeline is coupled to the arithmetic pipeline; as well as A controller, coupled to the arithmetic pipeline and the write pipeline, wherein: The first memory is configured as follows: Receive a first value and a first indicator of the memory location of the second memory; Store the first value and the first indicator; Receive a first read value associated with the memory location; and Store the first read value; The arithmetic pipeline is configured to perform arithmetic operations on the first value and the first read value to produce a first result; and The write pipeline is configured to store the first result in the second memory.

2. The apparatus according to claim 1, The controller is configured to maintain a first pointer indicating a first memory location of the first memory, a second pointer indicating a second memory location of the first memory, and a third pointer indicating a third memory location of the first memory; The first memory is configured to store the first value and the first indicator at the first memory location, and the controller is configured to responsively increment the first pointer; The first memory is configured to store the first read value at the second memory location, and the controller is configured to responsively increment the second pointer; and The first memory is configured to read the first value and the first read value from the third memory location and provide the first value and the first read value to the arithmetic pipeline, and the controller is configured to responsively increment the third pointer.

3. The apparatus according to claim 1, further comprising: Third memory; as well as Decoding circuit; The decoding circuit is configured to: Receive either the first value or the first indicator, or both, in the message; In response to receiving both the first value and the first indicator in the message, the first value and the first indicator are provided to the first memory; as well as In response to receiving either the first value or the first indicator in the message, the received value or the first indicator is provided to the third memory.

4. The apparatus of claim 3, wherein the third memory is configured to provide the first value and the first indicator to the first memory in response to the third memory storing both the first value and the first indicator.

5. The apparatus according to claim 1, The value or result, along with the corresponding indicator of the location in the second memory, corresponds to the update request; and If the first memory is not full, the first pending update request is not stopped in response to the second pending update request.

6. The apparatus according to claim 1, It further includes data forwarding blocks; The first memory, the arithmetic pipeline, and the write pipeline are configured to provide an indicator to the data forwarding block; The data forwarding block is configured to compare an indicator provided from a memory location of the first memory with an indicator provided from the arithmetic pipeline or the write pipeline to determine whether a matching indicator exists; The data forwarding block is configured to provide a read value or result corresponding to the matching indicator to the first memory in response to the matching indicator; and The first memory is configured to store the corresponding read value or corresponding result in the memory location of the first memory.

7. The apparatus of claim 6, wherein the controller is configured to invalidate the write transaction corresponding to the matching indicator.

8. The apparatus of claim 1, wherein the first memory is configured to be addressed in a cyclic manner.

9. An apparatus comprising: The first memory is configured to store instructions; A processor, coupled to the first memory, is configured to execute the instructions and to provide a first update request containing a first value and a first indicator of a memory location in the first memory; as well as Read-Modify-Write (RMW) manager, which includes: Second memory; Arithmetic pipeline; Write to the pipeline; as well as The controller is configured to: The system controls the second memory to receive the first update request and stores the first update request in the second memory. This causes the system to read a first read value from the first memory based on the first indicator and store the first read value in the second memory; This causes the arithmetic pipeline to perform operations on the first value and the first read value to produce a first result; as well as This causes the write pipeline to store the first result in the first memory.

10. The apparatus according to claim 9, The controller is configured to maintain a first pointer indicating a first memory location of the second memory, a second pointer indicating a second memory location of the second memory, and a third pointer indicating a third memory location of the second memory; The second memory is configured to store the first value and the first indicator at the first memory location, and the controller is configured to responsively increment the first pointer; The second memory is configured to store the first read value at a location in the second memory, and the controller is configured to responsively increment the second pointer. and The second memory is configured to read the first value and the first read value from the third memory location and provide the first value and the first read value to the arithmetic pipeline, and the controller is configured to responsively increment the third pointer.

11. The apparatus of claim 9, further comprising: Third memory; as well as Decoding circuit; The decoding circuit is configured to: Receive either the first value or the first indicator, or both, in the message; In response to receiving both the first value and the first indicator in the message, the first value and the first indicator are provided to the second memory; as well as In response to receiving either the first value or the first indicator in the message, the received value or the first indicator is provided to the third memory.

12. The apparatus according to claim 11, The message contains an identifier for the processor; and The third memory is configured to store the first value or the first indicator in a memory location corresponding to the identifier.

13. The apparatus of claim 11, wherein the third memory is configured to provide the first value and the first indicator to the second memory in response to the third memory storing both the first value and the first indicator.

14. The apparatus of claim 9, wherein the first update request is not stopped in response to a second pending update received from the second memory.

15. The apparatus according to claim 9, It further includes data forwarding blocks; The second memory, the arithmetic pipeline, and the write pipeline are configured to provide an indicator to the data forwarding block; The data forwarding block is configured to compare an indicator provided from a memory location of the second memory with an indicator provided from the arithmetic pipeline or the write pipeline to determine whether a matching indicator exists; The data forwarding block is configured to provide the second memory with a read value or result corresponding to the matching indicator in response to the matching indicator; and The second memory is configured to store the corresponding read value or corresponding result in the memory location of the second memory.

16. The apparatus of claim 15, wherein the controller is configured to invalidate a write transaction containing the matching indicator.

17. The apparatus of claim 9, wherein the second memory is configured to be addressed in a cyclic manner.

18. A method comprising: The first memory receives the first value and the first indicator of the memory location of the second memory; Store the first value and the first indicator in the first memory; Provide the first indicator from the first memory to the second memory; The first memory receives a first read value from the second memory in response to the first indicator; Store the first read value in the first memory; The first value and the first read value are provided from the first memory to the arithmetic pipeline; The arithmetic pipeline is used to perform arithmetic operations on the first value and the first read value to generate a result; as well as The result is stored in the second memory in response to the first indicator.

19. The method of claim 18, further comprising: Storing the first value and the first indicator in the first memory is responsive to incrementing the first pointer in response to a first pointer pointing to a first memory location in the first memory; The provision of the first indicator from the first memory to the second memory is in response to a second pointer pointing to a second memory location in the first memory, thereby incrementing the second pointer in response to the first memory receiving the first read value; and The provision of the first value and the first read value from the first memory to the arithmetic pipeline is achieved by responsively incrementing the third pointer, which points to a third memory location in the first memory.

20. The method of claim 19, wherein the storage is performed in response to the arithmetic pipeline providing the result and the first indicator to the write pipeline, the method further comprising: Indicators from the first memory, the arithmetic pipeline, and the write pipeline are provided to the data forwarding block; The data forwarding block compares the indicator provided from the memory location of the first memory with the indicator provided from the arithmetic pipeline or the write pipeline to determine whether a matching indicator exists. In response to the matching indicator, the read value or result corresponding to the matching indicator is provided to the first memory; as well as The corresponding read value or corresponding result is stored in the memory location of the first memory.

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