Semiconductor memory device and power supply method to semiconductor memory device

Abstract

A semiconductor storage device (10) is provided with: a memory cell array (24) divided into a plurality of sectors (20-23) that are sequentially accessed; and a power supply control circuit (30) that performs control for supplying a power supply voltage VDD to the plurality of sectors (20-23) individually, the power supply control circuit (30) performing control so that, when a first sector (for example, sector (20)) among the plurality of sectors (20-23) is accessed, a first power supply voltage VDD required for a second sector (for example, sector (21)) that is accessed next to the first sector performs data read and write is supplied.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices and methods for supplying power to semiconductor memory devices, and particularly to techniques for suppressing rush currents generated during startup of semiconductor memory devices. Background Technology

[0002] With the large-scale deployment of semiconductor memory devices, when power is supplied to the device or when power is restored (collectively referred to as "startup"), a surge current is generated in the power lines supplying the power voltage to the semiconductor memory device. This surge current is a rapid inrush current that flows rapidly during startup. Large surge currents can cause power supply noise and become a cause of malfunctions in semiconductor memory devices.

[0003] Previously, various techniques have been proposed as a means to suppress inrush currents generated during the startup of semiconductor memory devices (see, for example, Patent Document 1). In Patent Document 1, a semiconductor memory device is composed of multiple functional blocks, and these multiple functional blocks are started sequentially, thereby dispersing and suppressing the inrush current.

[0004] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2007-267162 Summary of the Invention

[0005] The problem that the invention aims to solve However, the technology in Patent Document 1 requires complex timing control to sequentially start multiple functional blocks. Furthermore, it also requires waiting for the power supply voltage supplied to the functional block to stabilize after the switching of the functional block (i.e., "power supply stabilization wait").

[0006] Therefore, the purpose of this disclosure is to provide a semiconductor memory device that can suppress inrush currents generated during startup without complex timing control and power stabilization waiting, as well as a method for supplying power to the semiconductor memory device.

[0007] Methods for solving problems To achieve the above objectives, one aspect of the present disclosure provides a semiconductor memory device comprising: a memory cell array divided into a plurality of sectors that are accessed sequentially; and a power control circuit for controlling the supply of power voltages to the plurality of sectors respectively, the power control circuit performing the control such that: when a first sector of the plurality of sectors is accessed, a first power voltage required for reading and writing data is supplied to a second sector that is subsequently accessed by the first sector.

[0008] To achieve the above objectives, one aspect of the present invention provides a method for supplying power to a semiconductor memory device, which is a method for supplying power to a semiconductor memory device having a memory cell array divided into a plurality of sectors that are accessed sequentially. The method includes a power control step for controlling the supply of power voltage to the plurality of sectors respectively. The control is performed in the power control step such that when a first sector of the plurality of sectors is accessed, a first power voltage required for reading and writing data is supplied to a second sector that is subsequently accessed by the first sector.

[0009] Invention Effects According to this disclosure, a semiconductor memory device that can suppress inrush currents generated during startup without complex timing control and power stabilization waiting is provided, as well as a method for supplying power to the semiconductor memory device. Attached Figure Description

[0010] Figure 1 This is a circuit diagram of a semiconductor memory device according to an implementation method.

[0011] Figure 2 This is a timing diagram illustrating the operation of a semiconductor memory device according to an implementation method.

[0012] Figure 3 This is a flowchart illustrating the operation of a semiconductor memory device according to an implementation method.

[0013] Figure 4 This is a circuit diagram of a semiconductor memory device according to a first variation of the implementation method.

[0014] Figure 5 This is a timing diagram illustrating the operation of a semiconductor memory device according to a first variation of the implementation method.

[0015] Figure 6 This is a circuit diagram of a semiconductor memory device according to a second variation of the implementation method.

[0016] Figure 7 This is a timing diagram illustrating the operation of a semiconductor memory device according to a second variation of the implementation method.

[0017] Figure 8 This is a circuit diagram of a semiconductor memory device according to a third variation of the implementation method.

[0018] Figure 9 This is a timing diagram illustrating the operation of a semiconductor memory device according to a third variation of the implementation method. Detailed Implementation

[0019] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, the embodiments described below represent specific examples of the present disclosure. The values, addresses, circuit elements, configuration positions of circuit elements, connection methods, steps, and order of steps shown in the following embodiments are examples and are not intended to limit the present disclosure. Additionally, the figures are not necessarily strictly illustrative. In the figures, substantially identical structures are labeled with the same reference numerals, and repeated descriptions are omitted or simplified. Furthermore, "connection" refers to electrical connection, which includes not only the case of two circuit elements being directly connected, but also the case of two circuit elements being indirectly connected when another circuit element is inserted between them.

[0020] Figure 1 This is a circuit diagram of the semiconductor memory device 10 according to the embodiment. The semiconductor memory device 10 is a memory device that can suppress the inrush current generated during startup without complex timing control and power stabilization waiting, and includes a memory cell array 24 and a power control circuit 30. In addition, only the circuit elements required for the operation of this disclosure are shown in this figure. As a semiconductor memory device 10, peripheral circuits (e.g., address decoder, readout amplifier circuit, etc.) not shown may also be included.

[0021] The memory cell array 24 is a memory cell array consisting of multiple sectors 20 to 23 accessed sequentially, such as an SRAM memory cell array or a DRAM memory cell array. In this embodiment, access is performed starting from sector 20, in the order of sector 21, sector 22, and sector 23.

[0022] Sectors 20-23 are connected to 10 address lines RA0-RA9 respectively. Sector 20 has memory cells corresponding to addresses 0-255 (i.e., word lines WL0-255) (also called "memory cell array 0" or "array 0"). Sector 21 has memory cells corresponding to addresses 256-511 (i.e., word lines WL 256-511) (also called "memory cell array 1" or "array 1"). Sector 22 has memory cells corresponding to addresses 512-767 (i.e., word lines WL 512-767) (also called "memory cell array 2" or "array 2"). Sector 23 has memory cells corresponding to addresses 768-1023 (i.e., word lines WL 768-1023) (also called "memory cell array 3" or "array 3").

[0023] Furthermore, VDD0~VDD3 in the diagram (the four terminals located to the left of each of VDD0~VDD3) are power supply terminals for receiving the first power supply voltage, i.e., the power supply voltage VDD, required for sectors 20~23 to read and write data. Additionally, "access" refers to inputting a specific address into the memory cell array 24 via address lines RA0~RA9 in order to read or write data to the memory cell array 24.

[0024] The power control circuit 30 is a circuit that controls the supply of power voltage VDD to the multiple sectors 20-23 constituting the memory cell array 24. It consists of inverters 31a, 31b and 40b, AND gates 40a, 41a, 42a and 43a, OR gates 41b, 42b and 43b, buffer circuits 40c, 41c, 42c and 43c, and transistors 40d-40g, 41d-41g, 42d-42g and 43d-43g.

[0025] When one of the multiple sectors 20 to 23 (referred to as the "first sector" (e.g., sector 20)) is accessed, the power control circuit 30 controls the accessed sector adjacent to the first sector (referred to as the "second sector" (e.g., sector 21)) to be supplied with the power supply voltage VDD.

[0026] In addition, in this specification, the “accessed sector” is referred to as the “first sector” or “current sector”, the next sector accessed is referred to as the “second sector” or “subordinate sector”, and the sector accessed after that is referred to as the “third sector” or “subordinate sector”.

[0027] Additionally, the power control circuit 30 controls the transition from a state where the first sector is accessed to a state where the second sector is accessed, thereby stopping the supply of the power voltage VDD, an example of the first power supply voltage, to the first sector. Furthermore, in this specification, "when transitioning to a certain state" can be simultaneous with the timing of the transition to that state, or it can occur after or immediately following the transition to that state.

[0028] Figure 2 This is a timing diagram illustrating the operation of the semiconductor memory device 10 according to an embodiment. Here, the timing of supplying the power supply voltage VDD to the power supply terminals VDD0 to VDD3 of the sequentially accessed sectors 20 to 23 is shown. In the timing diagram, a high level indicates the state of supplying the power supply voltage VDD, and a low level indicates the state of the power supply voltage VDD being cut off (in this case, grounded (0V)).

[0029] As shown in the figure, when the power supply voltage VDD is supplied to the power supply terminal VDD0 of sector 20 (i.e., array 0) and sector 20 (i.e., array 0) is accessed, the power supply voltage VDD required for reading and writing data is supplied to the power supply terminal VDD1 of sector 21 (i.e. array 1) that is subsequently accessed by sector 20.

[0030] Specifically, in Figure 1 In the process, when the address of sector 20 (i.e., array 0) is input to the power control circuit 30 via address lines RA0~RA9, the address of the high two address lines RA8 and RA9 is decoded by inverters 31a and 31b and AND gates 40a~43a. As a result, only AND gate 40a is activated (output becomes high level) among AND gates 40a~43a. According to its output signal, transistors 40d~40g are turned on via inverter 40b and buffer circuit 40c, and the power supply voltage VDD is supplied to the power supply terminal VDD0 of sector 20 (i.e., array 0). Furthermore, transistors 41d~41g are turned on via OR gate 41b and buffer circuit 41c, and the power supply voltage VDD is also supplied to the power supply terminal VDD1 of sector 21 (i.e., array 1).

[0031] Next, as Figure 2 As shown, when the state changes from sector 20 (i.e. array 0) being accessed to sector 21 (i.e. array 1) being accessed, the power supply voltage VDD to the power supply terminal VDD0 of sector 20 is stopped, and the power supply voltage VDD required for reading and writing data is supplied to the power supply terminal VDD2 of sector 22 (i.e. array 2) which is then accessed by sector 21.

[0032] Specifically, in Figure 1 In the process, when the address of sector 21 (i.e. array 1) is input to the power control circuit 30 via address lines RA0~RA9, the address of the high two address lines RA8 and RA9 is decoded by inverters 31a and 31b and AND gates 40a~43a. As a result, only AND gate 41a among AND gates 40a~43a is activated (the output becomes high level). According to its output signal, the conduction of transistors 41d~41g is maintained through OR gate 41b and buffer circuit 41c, maintaining the supply of power voltage VDD to sector 21 (i.e. array 1). Furthermore, transistors 42d~42g are turned on through OR gate 42b and buffer circuit 42c, and the power voltage VDD is also supplied to the power terminal VDD2 of sector 22 (i.e. array 2). Furthermore, by deactivating AND gate 40a (making its output low), transistors 40d to 40g are turned off via inverter 40b and buffer circuit 40c according to its output signal, thus stopping the supply of power voltage VDD to the power supply terminal VDD0 of sector 20.

[0033] Similarly, when the access state changes from sector 21 (i.e. array 1) to sector 22 (i.e. array 2) being accessed, the power supply voltage VDD to the power terminal VDD1 of sector 21 is stopped, and the power supply voltage VDD required for reading and writing data is supplied to the power terminal VDD3 of sector 23 (i.e. array 3) which is then accessed by sector 22.

[0034] Similarly, when the state changes from sector 22 (i.e. array 2) being accessed to sector 23 (i.e. array 3) being accessed, the power supply voltage VDD is stopped from being supplied to the power supply terminal VDD2 of sector 22.

[0035] Figure 3 This is a flowchart illustrating the operation of the semiconductor memory device 10 according to the embodiment (i.e., the method of supplying power to the semiconductor memory device). Here, details are shown of the power control steps performed by the power control circuit 30 of the semiconductor memory device 10 to control the supply of power supply voltage VDD to the plurality of sectors 20-23 respectively.

[0036] Figure 3 (a) is a flowchart related to the start of power supply to the next sector after the accessed sector in the power control step. The power control circuit 30 determines whether one of the multiple sectors 20-23 (i.e., the first sector) has been accessed (S10). If it determines that it has not been accessed ("No" in S10), the determination is repeated. On the other hand, if it determines that it has been accessed ("Yes" in S10), control is performed to supply the power voltage VDD required for starting data reading and writing in the sector following the first sector (i.e., the second sector) (S11). In this embodiment, as... Figure 2 As shown in the timing diagram, when a sector is accessed for the first time, control is performed to start supplying power to the sectors to be accessed next.

[0037] Figure 3 (b) is a flowchart related to stopping the power supply to the sector where the access has ended in the power control step. The power control circuit 30 determines whether the state of accessing a sector (i.e., the first sector) has changed to accessing the next sector to be accessed (i.e., the second sector) (S20). If it is determined that the state has not changed ("No" in S20), the determination is repeated. On the other hand, if it is determined that the state has changed ("Yes" in S20), the control to stop the supply of power voltage VDD to the first sector is performed (S21).

[0038] Thus, in the semiconductor memory device 10 according to the embodiment, the memory cell array 24 controls the on / off switching of the power supply on a sector-by-sector basis and stops the power supply after the access is completed. Therefore, compared with the case of controlling the on / off switching of the power supply to the entire memory cell array (i.e., on a macro basis), low power consumption is achieved, and the inrush current during startup is suppressed by being distributed on a sector-by-sector basis.

[0039] Furthermore, according to the semiconductor memory device 10 of this embodiment, power supply to the next accessed sector is started based on the address information of the accessed sector, so there is no need for the complex timing control used to start multiple functional blocks sequentially as in the prior art.

[0040] Furthermore, according to the semiconductor memory device 10 of this embodiment, when the first sector is accessed (in this embodiment, when the first sector is initially accessed), the power supply to the second sector to be accessed next is started, so there is no need to wait for the power supply voltage supplied to the function block to stabilize after the function block is switched, as in the prior art.

[0041] Figure 4 This is a circuit diagram of the semiconductor memory device 10a according to the first variation of the embodiment. The difference from the embodiment is that, in this variation, for the unaccessed sectors 20-23, instead of supplying ground (0V), a holding voltage VRE, an example of a second power supply voltage, is supplied as the power supply voltage required to retain data in the sectors. The holding voltage VRE is a voltage lower than the power supply voltage VDD required to read and write data.

[0042] To achieve this, the power control circuit 30a of the semiconductor memory device 10a in this modified example, in addition to the structure of the power control circuit 30 of the embodiment, also includes inverters 40h to 43h connected between the gates of transistors 40d to 43d and 40e to 43e that turn the supply of power voltage VDD on and off, and the gates of transistors 40f to 43f and 40g to 43g that turn the supply of holding voltage VRE on and off. With this circuit structure, the holding voltage VRE is supplied even when the power supply voltage VDD is not supplied to the power terminals VDD0 to VDD3 of sectors 20 to 23.

[0043] Figure 5 This is a timing diagram illustrating the operation of the semiconductor memory device 10a according to the first variation of the embodiment. (Compared to the embodiment...) Figure 2 Unlike other voltage sources, the power supply voltage supplied to unaccessed sectors (arrays) is called the holding voltage VRE.

[0044] Thus, according to this modified example, the semiconductor memory device 10a, in addition to the features of the semiconductor memory device 10 of the embodiment, also has the feature that data in unaccessed sectors is not deleted but retained. Furthermore, the power supply voltage supplied to the unaccessed sectors is maintained at a holding voltage VRE lower than the power supply voltage VDD, thereby achieving lower power consumption and suppressing leakage compared to the case where the power supply voltage VDD is supplied.

[0045] Figure 6 This is a circuit diagram of a semiconductor memory device 10b according to a second variation of the embodiment. The difference from the embodiment is that, in this variation, when changing from accessing the first sector to accessing the second sector, the charge accumulated on the power line of the first sector is distributed to the power line of the third sector by connecting the power line of the first sector to the power line of the third sector accessed next to the second sector.

[0046] To achieve this, the power control circuit 30b of the semiconductor memory device 10b in this variant, in addition to the structure of the power control circuit 30 of the embodiment, also includes: a transistor 44a for switching the connection between the power line 20a of sector 20 and the power line 22a of sector 22; a transistor 44b for switching the connection between the power line 21a of sector 21 and the power line 23a of sector 23; and a circuit (not shown) for controlling these transistors 44a and 44b. Furthermore, in Figure 6 In the figure, most of the components of the power control circuit 30b that are the same as those of the power control circuit 30 in the embodiment are omitted.

[0047] According to this circuit structure, when transitioning from accessing sector 20 to accessing sector 21, by connecting the power line 20a of sector 20 to the power line 22a of sector 22, the charge accumulated on the power line 20a of sector 20 can be distributed to the power line 22a of sector 22. More specifically, at this time, the power control circuit 30b first disconnects the power supply voltage VDD to sector 20 by setting the signal POW_SW0 to a high level, then turns on the transistor 44a by setting the signal Con0 to a low level, connecting the power line 20a of sector 20 to the power line 22a of sector 22 to perform charge distribution. Then, by setting the signal Con0 to a high level, the transistor 44a is turned off, disconnecting the connection between the power line 20a of sector 20 and the power line 22a of sector 22. Finally, the power supply voltage VDD to sector 22 is turned on by setting the signal POW_SW2 to a low level. Thus, the supply of power voltage VDD to sector 22 achieves low power consumption.

[0048] Similarly, when transitioning from accessing sector 21 to accessing sector 22, by connecting the power line 21a of sector 21 to the power line 23a of sector 23, the charge accumulated on the power line 21a of sector 21 can be distributed to the power line 23a of sector 23. More specifically, at this time, the power control circuit 30b first disconnects the power supply voltage VDD to sector 21 by setting the signal POW_SW1 to a high level, then turns on the transistor 44b by setting the signal Con1 to a low level to connect the power line 21a of sector 21 to the power line 23a of sector 23 for charge distribution. Then, by setting the signal Con1 to a high level to turn off the transistor 44b to disconnect the connection between the power line 21a of sector 21 and the power line 23a of sector 23, finally turns on the power supply voltage VDD to sector 23 by setting the signal POW_SW3 to a low level. Thus, the supply of power voltage VDD to sector 23 achieves low power consumption.

[0049] Figure 7 This is a timing diagram illustrating the operation of the semiconductor memory device 10b according to the second variation of the embodiment. (Compared to the embodiment...) Figure 2 In contrast, when the state changes from accessing sector 20 to accessing sector 21, a stepped waveform is generated due to charge distribution caused by the connection of power line 20a of sector 20 and power line 22a of sector 22. Furthermore, when the state changes from accessing sector 21 to accessing sector 22, a stepped waveform is generated due to charge distribution caused by the connection of power line 21a of sector 21 and power line 23a of sector 23.

[0050] Thus, according to the semiconductor memory device 10b of this modified example, in addition to the features of the semiconductor memory device 10 of the embodiment, when the state changes from accessing the first sector to accessing the second sector, the power line of the first sector is connected to the power line of the third sector that is then accessed by the second sector, and the charge accumulated in the power line of the first sector is distributed to the power line of the third sector, thereby achieving low power consumption in the supply of power voltage VDD to the third sector.

[0051] Figure 8 This is a circuit diagram of the semiconductor memory device 10c according to the third variation of the embodiment. The difference from the embodiment is that, in this variation, in addition to the switching on and off of the power supply on a sector-by-sector basis as in the embodiment, the power supply to the word line drive circuit of that sector is also switched on and off.

[0052] The figure also illustrates the word lines 60a-60b, 61a-61b, 62a-62b and 63a-63b of each sector 20-23 of the semiconductor memory device 10c, and the corresponding word line driving circuits 50a-50b, 51a-51b, 52a-52b and 53a-53b.

[0053] Furthermore, in this modified example, the power control circuit 30c of the semiconductor memory device 10c changes from a connection configuration that switches the power supply voltage VDD on and off in units of sectors to a connection configuration that switches the power supply voltage VDD on and off in units that combine sectors and word line drive circuits. Specifically, the connection destinations of the drains of transistors 40d, 41d, 42d, and 43d are changed from the power supply terminals VDD0, VDD1, VDD2, and VDD3 of sectors 20, 21, 22, and 23 to the power supply terminals of word line drive circuits 50a-50b, 51a-51b, 52a-52b, and 53a-53b, respectively.

[0054] Figure 9 This is a timing diagram illustrating the operation of the semiconductor memory device 10c according to the third variation of the embodiment. (Compared to the embodiment...) Figure 2 In comparison, the timing diagram itself is the same, but in the names of the parts shown on the left side of the timing diagram, in addition to the power supply terminals, word line drive circuits (word line drive circuits 50a to 50b, etc.) are added.

[0055] Thus, according to this modified example of the semiconductor memory device 10c, in addition to the features of the semiconductor memory device 10 of the embodiment, not only is the power supply to the sector switched on and off, but the power supply to the word line drive circuit of that sector is also switched on and off. Therefore, while stopping the power supply to unaccessed sectors, the power supply to the word line drive circuit of those sectors is also stopped, thus achieving lower power consumption compared to the embodiment.

[0056] As described above, the semiconductor memory device 10 of this embodiment includes: a memory cell array 24 divided into a plurality of sectors 20 to 23 that are accessed sequentially; and a power control circuit 30, etc., for controlling the supply of a power supply voltage VDD to the plurality of sectors 20 to 23 respectively; the power control circuit 30, etc., controls the supply of a first power supply voltage VDD required for reading and writing data to a second sector (e.g., sector 21) that is subsequently accessed when the first sector (e.g., sector 20) of the plurality of sectors 20 to 23 is accessed.

[0057] As a result, the power supply to the memory cell array 24 is controlled on and off at the sector level, thus achieving lower power consumption compared to controlling the power supply to the entire memory cell array (i.e., at the macro level), and the inrush current during startup is suppressed by being distributed at the sector level.

[0058] Furthermore, power supply to the next accessed sector begins based on the address information of the accessed sector, thus eliminating the need for complex timing control required to sequentially start multiple function blocks, as in existing technologies. Moreover, power supply to the next accessed sector begins when the first sector is accessed (in this embodiment, when the first sector is initially accessed), eliminating the need for power stabilization waiting after a function block switch, as in existing technologies.

[0059] Furthermore, the power control circuit 30 and the like control the flow of power to stop supplying the first power supply voltage VDD to the first sector when the state transitions from accessing the first sector to accessing the second sector. Thus, the memory cell array 24 controls the on / off switching of power supply on a sector-by-sector basis, and further, stops power supply after access is completed, thereby achieving low power consumption and suppressing leakage.

[0060] Furthermore, the power control circuit 30a of the first modification controls the data flow so that when the state changes from accessing the first sector to accessing the second sector, a second power supply voltage VRE, which is lower than the first power supply voltage VDD and required for the second sector to retain data, is supplied to the first sector. Therefore, data in unaccessed sectors is retained without being deleted. Moreover, the power supply voltage supplied to unaccessed sectors is maintained at a retention voltage VRE, which is lower than the power supply voltage VDD, thus achieving lower power consumption and suppressing leakage compared to the case where the power supply voltage VDD is supplied.

[0061] Furthermore, in the second variation, the power control circuit 30b connects the power line 20a of the first sector to the power line 22a of the third sector (e.g., sector 22) that is subsequently accessed after the second sector is accessed. This allows for charge distribution from the power line of the current sector (after access has ended) to the power line of the next lower-level sector, achieving low power consumption in the supply of the power voltage VDD to the third sector.

[0062] Furthermore, the semiconductor memory device 10c in the third modification also includes multiple word line driving circuits 50a to 50b, which correspond to multiple sectors 20 to 23 respectively, and drive word lines 60a to 60b corresponding to the sectors 20 to 23 respectively. The power control circuit 30c, when changing from accessing the first sector to accessing the second sector, controls the supply of power voltage VDD to the word line driving circuits 50a to 50b corresponding to the first sector. Thus, by stopping the power supply to the unaccessed sector, the power supply to the word line driving circuit of that sector is also stopped, thereby achieving lower power consumption.

[0063] Furthermore, the power supply method for a semiconductor memory device in this embodiment is a power supply method for a semiconductor memory device 10, etc., equipped with a memory cell array 24, which is divided into a plurality of sectors 20 to 23 that are accessed sequentially. This power supply method includes a power control step, which controls the supply of a power voltage VDD to each of the plurality of sectors 20 to 23. In the power control step, when a first sector (e.g., sector 20) of the plurality of sectors 20 to 23 is accessed, control is performed to supply a first power voltage VDD (VDD required for reading and writing data to a second sector (e.g., sector 21) that is subsequently accessed by the first sector. Figure 3 (a) of S10~S11).

[0064] Therefore, the power supply to the memory cell array 24 is controlled on and off at the sector level, thus achieving lower power consumption compared to controlling the power supply to the entire memory cell array. Furthermore, the inrush current during startup is suppressed by distributing it at the sector level.

[0065] Furthermore, power supply to the next accessed sector begins based on the address information of the accessed sector, thus eliminating the need for complex timing control required to sequentially start multiple function blocks, as in existing technologies. Moreover, power supply to the next accessed sector begins when the first sector is accessed (in this embodiment, when the first sector is initially accessed), eliminating the need for power stabilization waiting after a function block switch, as in existing technologies.

[0066] The semiconductor memory device and the power supply method to the semiconductor memory device of this disclosure have been described above based on embodiments and modifications, but this disclosure is not limited to these embodiments and modifications. Various modifications conceived by those skilled in the art to these embodiments and modifications, as well as other methods constructed by combining some of the constituent elements of the embodiments and modifications, are also included within the scope of this disclosure, provided they do not depart from its spirit.

[0067] For example, by combining the first and second variations of the implementation, it is also possible to maintain data by supplying a holding voltage to a sector where access has ended (first variation) and to reduce power consumption by distributing the power supply voltage VDD to the next lower sector of the current sector (second variation).

[0068] Similarly, by combining the second and third variations of the implementation, it is possible to reduce the power consumption of the power supply voltage VDD to both the next lower sector (second variation) and its word line drive circuit (third variation) of the current sector through charge distribution.

[0069] Furthermore, in the above embodiments, the memory cell array 24 is accessed in ascending order from address 0 to 1023, but it is also possible to access it in descending order from address 1023 to 0. In this case, the power control of sectors 20 to 23 is replaced with power control of sectors 23 to 20, respectively.

[0070] Furthermore, in the above embodiments, an example is shown in which all sectors 20 to 23 constituting the memory cell array 24 are accessed sequentially, but the invention is not limited to such access. For example, the features of the present invention can also be applied when accessing sectors 21 sequentially in the order of sectors 22 and 23.

[0071] Furthermore, in the above embodiments, power supply to the second sector is started when the first sector is initially accessed. However, the timing of starting power supply to the second sector is not limited to this timing. For example, power supply to the second sector may be started when a specified address within the address range of the first sector (e.g., the central address, or an address 100 addresses lower than the highest address) is accessed.

[0072] Furthermore, the method for supplying power to a semiconductor storage device disclosed herein can be implemented by a program executed by a processor, or by a non-transitory computer-readable recording medium such as a DVD containing the program, or as a program product.

[0073] Industrial applicability This disclosure provides a semiconductor memory device capable of suppressing inrush current during startup, and can be used, for example, as SRAM, DRAM, etc.

[0074] Explanation of reference numerals in the attached figures 10. 10a-10c semiconductor memory devices Sectors 20-23 20A, 21A, 22A, 23A power cords 24-cell array 30, 30a~30c power control circuit Inverters 31a, 31b, 40b, 40h, 41h, 42h, 43h 40a, 41a, 42a, 43a AND gate 41b, 42b, 43b OR gate 40C, 41C, 42C, 43C buffer circuits 40d-40g, 41d-41g, 42d-42g, 43d-43g, 44a, 44b transistors Word line drive circuits for 50a~50b, 51a~51b, 52a~52b, and 53a~53b

Claims

1. A semiconductor memory device, have: The storage cell array is divided into multiple sectors that are accessed sequentially; and The power control circuit controls the supply of power voltage to the multiple sectors respectively. The power control circuit performs the control such that: when the first sector of the plurality of sectors is accessed, a first power supply voltage required for reading and writing data is supplied to the second sector that is subsequently accessed by the first sector.

2. The semiconductor memory device according to claim 1, The power control circuit performs the control such that: when the state changes from accessing the first sector to accessing the second sector, the supply of the first power voltage to the first sector is stopped.

3. The semiconductor memory device according to claim 2, The power control circuit performs the control such that: when the state changes from accessing the first sector to accessing the second sector, a second power supply voltage lower than the first power supply voltage and required for the second sector to retain data is supplied to the first sector.

4. The semiconductor memory device according to claim 1, The power control circuit connects the power line of the first sector to the power line of the third sector, which is accessed next, when it changes from accessing the first sector to accessing the second sector.

5. The semiconductor memory device according to claim 2, It also includes multiple word line driving circuits corresponding to the plurality of sectors, which drive the word lines corresponding to the plurality of sectors. When the power control circuit changes from accessing the first sector to accessing the second sector, it controls the supply of power voltage to the word line driving circuit corresponding to the first sector.

6. A method for supplying power to a semiconductor memory device, the semiconductor memory device comprising a memory cell array divided into a plurality of sectors that are accessed sequentially. The method for supplying power to a semiconductor memory device includes a power control step of controlling the supply of power voltage to the plurality of sectors respectively. The control is performed in the power control step such that: when the first sector of the plurality of sectors is accessed, a first power supply voltage required for reading and writing data is supplied to the second sector for which the first sector is subsequently accessed.

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