Creating a layout of a printed circuit board (PCB) including electrical components using a model for assigning components to locations on a PCB array
Patent Information
- Application Number
- CN202480088942.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2026-09-25
Smart Images
Figure CN122826569A_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to electronic design automation (EDA), and more specifically to creating the layout of printed circuit boards (PCBs) including electrical components using models for assigning components to locations on an array of PCBs. Such electronic design automation systems and PCB layout systems are collectively referred to herein as product systems. Background Technology
[0002] The development of electronic devices with printed circuit boards typically involves a series of steps known as the design flow. This design flow usually begins with the specification of the new electronic device to be implemented on a printed circuit board. The specification of the electronic device can be translated into an electronic device design (e.g., a netlist), for example, through schematic capture tools or through logic design synthesis (sometimes referred to as register-transfer-level (RTL) description of the electronic device). The netlist can be specified using Electronic Design Exchange Format (EDIF) or a similar format, which describes the nets or connectivity between various components or parts in the electronic device design.
[0003] The design process can continue by validating the functionality of the electronic device design, for example, by simulating, modeling, or prototyping the electronic device design and verifying that the simulation or modeling results correspond to the expected output of the electronic device design. This functionality can also be validated through formal verification using one or more solvers, or by performing static checks on the electronic device design to examine various properties that may be problematic during the operation of an electronic device built using that design.
[0004] Once the electronic device design is functionally validated, the design flow can leverage the logic design to generate a layout design for the electronic device. This process can be implemented in various ways, but is typically achieved using a layout tool that arranges and interconnects various components or parts into a representation of a printed circuit board. For example, layout tools implemented in computing systems can present a graphical view of a printed circuit board and allow designers to use the tool to place components from a library onto the printed circuit board in the graphical view.
[0005] In this context, the task of creating a PCB layout can sometimes be roughly divided into three parts: component selection, which involves selecting hardware components that interact to meet the functional requirements associated with the PCB and connecting the selected components to each other accordingly; component placement (i.e., PCB layout planning), which involves selecting the physical location of each selected component on the PCB; and component routing, which involves outlining how the copper traces used to connect the components will be applied to the PCB.
[0006] In some respects, this patent application primarily focuses on the second task in the PCB layout process: component placement. Given a list of components and their connections (netlist), engineers need to determine the board layout, i.e., the placement of the physical components on the PCB.
[0007] Currently, there are product systems and solutions that support the creation of PCB layouts that include electrical components. These product systems can benefit from improvements. Summary of the Invention
[0008] Various disclosed implementations include methods and computer systems that can be used to facilitate the creation of PCB layouts that include electrical components.
[0009] According to a first aspect of the present invention, a computer-implemented method for creating a layout of a PCB comprising a plurality of electrical components electrically connected thereto, the method comprising: providing an array of PCB board canvases; providing a list of components and electrical connections thereof; providing characteristic information of corresponding components and corresponding connections thereof; providing a model combining the array, the list, and the characteristic information thereof, wherein the model describes a series of successive actions for assigning a component from the list to a corresponding position in the array; using the model to determine a corresponding probability distribution for assigning one of the components to the corresponding position in the array; using the corresponding assignment action with the highest corresponding probability in the corresponding probability distribution to form a layout of the component on the array; and outputting the formed layout.
[0010] According to a second aspect of the invention, a computer system can be arranged and configured to perform the steps of such a computer implementation method according to the first aspect.
[0011] According to a third aspect, a computer program product can include computer program code that, when executed by a computer system according to a second aspect, causes the computer system to perform the method according to a first aspect.
[0012] According to the fourth aspect, a computer-readable medium (e.g., a non-transitory computer-readable storage medium) can include a computer program product according to the third aspect. For example, the described computer-readable medium can be non-transitory and can also be a software component on a storage device.
[0013] The features and technical advantages of this disclosure have been outlined quite broadly above to enable those skilled in the art to better understand the following detailed description. Additional features and advantages of this disclosure that form the subject matter of the claims will be described below. Those skilled in the art will understand that they can readily utilize the disclosed concepts and specific embodiments as a basis for modifying or creating layouts for other structures that achieve the same purpose as this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure in its broadest form.
[0014] Furthermore, before proceeding with the following detailed description, it should be understood that various definitions of certain words and phrases are provided in this patent document, and those skilled in the art will understand that such definitions apply in many (if not most) cases to the prior and future uses of such defined words and phrases. While some terms may encompass various embodiments, the appended claims are designed to explicitly define these terms as specific embodiments.
[0015] The implementation method will be described in more detail below. Attached Figure Description
[0016] Figure 1 A functional block diagram of a first example system is shown to facilitate the creation of a PCB layout that includes electrical components in a product system.
[0017] Figures 2-4 Flowcharts of the first to third aspects of an example PCB layout process that can be performed by, for example, the first example system are shown.
[0018] Figure 5 A functional block diagram of a second example system is shown to facilitate the creation of a PCB layout that includes electrical components in a product system.
[0019] Figure 6 A flowchart of a training process associated with an example PCB layout process is shown, which can be performed by, for example, a first example system or a second example system.
[0020] Figure 7 A flowchart illustrates an example method for facilitating the creation of PCB layouts that include electrical components in a product system.
[0021] Figure 8 A block diagram of the data processing system in which the implementation method is located is shown. Detailed Implementation
[0022] Various techniques relating to systems and methods for creating layouts of printed circuit boards (PCBs) including electrical components in a product system will now be described with reference to the accompanying drawings, wherein the same reference numerals consistently denote the same elements. The drawings discussed below, and the various embodiments used to describe the principles of this disclosure in this patent document, are merely exemplary and should not be construed in any way as limiting the scope of this disclosure. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged device. It should be understood that functions described as being performed by certain system elements can be performed by multiple elements. Similarly, for example, an element can be configured to perform functions described as being performed by a component. Numerous innovative teachings of this patent document will be described with reference to exemplary, non-limiting embodiments.
[0023] Reference Figure 1 This document depicts a functional block diagram of an exemplary computer system or data processing system 100. The exemplary computer system or processing system 100 facilitates the creation of a layout 140 of a PCB 120 including electrical components 122. The processing system 100 may include a PCB layout system 118, which in some examples may include at least one processor 102 (e.g., a processor) configured to execute at least one application software component 106 in memory 104 accessed by the processor 102. The application software component 106 may be configured (e.g., programmed) to cause the processor 102 to perform various actions and functions described herein. For example, the application software component 106 may include and / or correspond to one or more components of an application for creating a layout 140 of the PCB 120 including electrical components 122, wherein the application software component 106 may, for example, be configured to generate and store product data in a data storage device 108 (such as a database).
[0024] For example, PCB layout system 118 can be cloud-based, internet-based, and / or operated by a provider offering support for layout 140 for creating PCB 120. In some examples, a user can be located near or away from PCB layout system 118 (e.g., in any other location, such as using a mobile device connected to PCB layout system 118 via the internet, where the mobile device can include input device 110 and display device 112). In some examples, PCB layout system 118 can be mounted on and run on a user's device, such as a computer, laptop, tablet, local computing facility, etc.
[0025] It should be understood that creating a layout 140 for a PCB 120 can be a challenging and time-consuming process, potentially requiring highly skilled engineers with years of training. For example, it may require advanced knowledge in electronics, physics, and other scientific fields, or it may require intentionally choosing from many options, each involving numerous manual steps, making it a lengthy and inefficient process.
[0026] To enable enhanced creation of the layout 140 of PCB 120, the product system or processing system 100 may include at least one input device 110 and at least one display device 112 (such as a display screen). The processor 102 may be configured to generate a graphical user interface (GUI) 114 via the display device 112. Such a GUI 114 may include GUI elements such as buttons, links, search boxes, lists, text boxes, images, and scrollbars, which a user can use to provide input via the input device 110, resulting in the creation of the layout 140 of PCB 120. For example, GUI 114 may include a PCB layout user interface (UI) 116 provided to the user.
[0027] In one exemplary embodiment, in order to create a layout 140 of a PCB 120 including multiple electrically connected electrical components 122, the application software component 106 and / or processor 102 can be configured to provide an array 124 of board canvas for the PCB 120.
[0028] Here, the creation of layout 140 can be understood as the determination or derivation of layout 140 using input data, which will be described in more detail below. Furthermore, PCB 120 (i.e., printed circuit board (PWB)) is the medium used in a circuit to connect or “wire” components to each other. In some examples, component 122 can include resistors, capacitors, transistors, batteries, etc. Component 122 can also include net nodes of the following types: ground, power supply (e.g., 24 volts), etc., where a network can be understood as electrically connected components 122 and their connections 128. In some examples, a network can correspond to wires or connections 128 between two components 122 (such as direct pins of connected components 122 or conductor paths between connected components 122) and other components 122 optionally electrically arranged between connected components 122.
[0029] In some examples, PCB 120 and components 122 arranged on PCB 120 can also be understood as integrated circuits (ICs) (e.g., microchips). An IC is a small electronic device made up of multiple interconnected electronic components, such as transistors, resistors, and capacitors. These components can be etched onto small pieces of semiconductor material (typically silicon).
[0030] Furthermore, the area on PCB 120 where components 122 can be arranged and electrically connected can be described by a board canvas, which in turn can be described by an array 124. Here, array 124 can be, for example, two-dimensional and subdivided into specific locations 136 where components can be arranged in columns and rows. Furthermore, array 124 can be understood as a geometric structure that can be used for the purpose of determining the layout 140 of PCB 120 as described above. In some examples, three-dimensional arrays 124 can also be used, for example by staggering two or more two-dimensional arrays 124. Such three-dimensional arrays 124 may be useful for more complex PCBs 120 that provide two or more layers on which components 122 can be arranged or connected.
[0031] In some examples, providing array 124 may involve the user or engineer determining an area on PCB 120 where components 122 can be placed and electrically connected. Array 124 can be provided and stored in data storage device 108 of PCB layout system 118 (e.g., by the user using PCB layout UI 116 and / or input device 110). In some examples, array 124 can be received, for example, from another data source 108' via application programming interface (API). Similar methods can also be used to provide other input information, which will be described in more detail below.
[0032] In some examples, the electrical components 122 with multiple electrical connections include millions or even billions of such components 122.
[0033] In some examples, application software component 106 and / or processor 102 can also be configured to provide component 122 and a list 126 of electrical connections 128 of component 122.
[0034] This list 124 can be determined or provided, for example, after the component selection task described above (which can be part of the design flow described above). List 124 includes components 122 of PCB 120 and connections 128 connecting components 122. In the context of EDA or design flow, list 124 can also be referred to as a netlist.
[0035] For example, application software component 106 and / or processor 102 can also be configured to provide characteristic information 130 of the corresponding component 122 and the corresponding connection 128.
[0036] The feature information 130 can include information about the type, shape, or other characteristics of the corresponding component 122 or the corresponding connection 128. For example, for component 122, the feature information 130 can indicate whether the corresponding component 122 is a resistor, capacitor, transistor, or battery, and can also be a ground potential or an electrical potential with a certain voltage (e.g., 24 volts). For connection 128, the feature information 130 can indicate whether the corresponding connection 128 is a signal connection or a power connection, wherein a power connection is suitable for a larger current or voltage than a signal connection. Optionally, in some examples, the feature information 130 can also include information about the placement of the component 122 that has already been placed (i.e., the feature information 130 can include a location 136 that a particular component 122 or connection 128 has been pre-assigned).
[0037] In other examples, application software component 106 and / or processor 102 can also be configured to provide a model 132 that combines array 124, list 126, and feature information 130. Model 132 describes a series of sequential actions 134, namely, assigning a component 122 from list 126 to a corresponding position 136 on array 124.
[0038] PCB 120 can be manufactured by placing individual components 122 on PCB 120 (e.g., placing them on the surface of PCB 120). Similarly, the layout 140 of PCB 120 can be configured by “placing” or assigning the components 122 to corresponding positions 136 in array 124. Positions 136 can be given, for example, in x, y, and optionally z coordinates, where other coordinate systems can also be used. Here, components 122 can be positioned individually (i.e., positioned one after another in a series of successive assignment actions 134, during which components 122 are “placed” or assigned one after another to corresponding positions 136 in array 124 until all components 122 have been assigned to array 124). The sequence of successive assignment actions 134 can be described or characterized by model 132, which combines the array 124, list 126, and corresponding feature information 130 provided above. Model 132 can be understood, for example, as a policy network that models the action of placing the components 122 in list 126 onto array 124.
[0039] In some examples, model 132 may be quite simple and, for example, could involve clustering components 122 by first assigning them to (e.g., directly) electrically connected components 122 that are adjacent to these (e.g., directly) electrically connected components 122, and then locating the connections 128 of these (e.g., directly) electrically connected components 122. For example, model 132 could consider electrically connected components 122 by assigning certain preference values to adjacent, electrically connected components 122. Since competing requirements need to be met in many examples, model 132 can help with selection using preference values and, for example, satisfying the most important of the competing requirements when creating layout 140. More advanced models 132 and how to obtain these models will be described in more detail below.
[0040] For example, application software component 106 and / or processor 102 can also be configured to use model 132 to determine a corresponding probability distribution 138 for assigning one of components 122 to a corresponding location 136 on array 124.
[0041] Model 132 can then be used to determine the corresponding probability distribution 138 for assigning one of the components 122 to the corresponding position 136 of the array 124. Here, in some examples, the probability distribution 138 can be understood as implementing a normalization for values between 0 and 1. Therefore, for a single assignment action 134 that assigns one of the components 122 to the corresponding position 136 of the array 124, a corresponding assignment probability can be determined for each position 136 of the array 124. Thus, the probability distribution 138 can be determined for each assignment action 134 covering the entire array 124, such that a probability of assigning the corresponding component 122 is determined for each position 136 of the array 124.
[0042] Here, in some examples, the corresponding probability distribution 138 can be represented using the aforementioned board canvas: the sequence of consecutively assigned components 122 on array 124 can be represented by a corresponding step canvas sequence, wherein a corresponding step canvas can be provided for each assignment action 134 (and previously assigned components 122). The corresponding canvas has an array 124, wherein probabilities from the corresponding probability distribution 138 are assigned to each position of array 124 of the corresponding canvas. Therefore, for each assignment action 134, a separate board canvas with a separate array 124 can exist. The probability distribution 138 for this assignment action 134 is mapped to position 136 of array 124.
[0043] For example, there may be locations 136 in array 124 with relatively low allocation probabilities (e.g., because the allocated component 122 should be far from the electrically connected component 122), and there may be locations 136 in array 124 with relatively high allocation probabilities (e.g., because the allocated component 122 should be near the electrically connected component 122). The probability distribution 138 can be understood, for example, as a heat map, where “hot” areas of array 124 indicate locations 136 with relatively high allocation probabilities relative to the corresponding component 122, and “cold” areas of array 124 indicate locations 136 with relatively low allocation probabilities relative to the corresponding component 122. In this context, the corresponding heat map for a single allocation action 134 or component 122 can be represented using the corresponding canvas and corresponding array 124 described above.
[0044] In some examples, application software component 106 and / or processor 102 can also be configured to form the layout 140 of component 122 on array 124 using the corresponding allocation action 134 with the highest corresponding probability in the corresponding probability distribution 138.
[0045] The layout 140 of components 122 can be obtained by performing a series of successive allocation actions 134 until all components 122 are allocated to their respective positions 136 in the array 124. To determine the corresponding individual allocation action 134, a determined probability distribution 138 can be used, as follows: for each action 134 that allocates one of the components 122 to its corresponding position 136 in the array 124, the allocation action 134 with the highest probability in the probability distribution 138 can be used. Therefore, for example, each component 122 can be allocated to one of the positions 136 in the array 124 based on the allocation action 134 with the highest probability. This can be understood, for example, as constructing the layout 140 of the PCB 120 stepwise or from one layout state to the next, wherein for each step only the most likely next state of the layout 140 is considered.
[0046] In some examples, the process can be executed sequentially for each component 122 to determine the appropriate position 136 of the array 124 to which the corresponding component 122 should be assigned. In other examples, the process can be executed sequentially for each position 136 of the array 124 to determine the appropriate component 122 to be assigned to the corresponding position 136.
[0047] After determining a series of consecutive allocation actions 134 and assigning components 122 to their corresponding positions 136 in array 124, the layout 140 of PCB 120 is completed. Since only the highest response probability is considered when assigning the corresponding component 122 to its corresponding position 136 in array 124, only one layout 140 is obtained. If, in some examples, for a particular allocation action 134, there are two positions 136 in the response probability distribution 138 with the highest response probability, then one of these two positions 136 can be selected randomly or according to a preconfigurable allocation rule (e.g., physical characteristics described below).
[0048] In some examples, the layout 140 of both components 122 and connections 128 on array 124 can be determined using the corresponding allocation action 134 with the highest corresponding probability in the corresponding probability distribution 138.
[0049] For example, application software component 106 and / or processor 102 can also be configured to output the layout 140.
[0050] The constructed layout 140 can then be output to a user or engineer, for example (e.g., via PCB layout UI 116, which can be displayed to the user on display device 112). In other examples, the constructed layout 140 can be additionally or alternatively output to another device communicatively connected to the PCB layout system 118. These other examples will be described in more detail below.
[0051] In other examples, application software component 106 and / or processor 102 can also be configured to: use the provided array 124 as a step canvas of height H and width W, on which component 122 can be arranged; and update the step canvas after assigning a corresponding assignment action 134 in one of component 122.
[0052] As mentioned above, the sequence of consecutively assigned components 122 on array 124 can be represented by a corresponding sequence of step canvases, wherein a corresponding step canvas can be provided for each assignment action 134 (and for each previously assigned component 122). Array 124 and the corresponding step canvas can have a height H and a width W that can be used to position or assign components 122. In some examples, the step canvas can also reflect other geometries (i.e., shapes other than rectangular shapes). In other examples, a three-dimensional array 124 can be used, which includes thickness in addition to height H and width W.
[0053] After each action 134 (based on the highest corresponding probability in the corresponding probability distribution 138) assigning one of the components 122 to the corresponding position 136 of the array 124 or the step canvas, the step canvas can be updated so that the updated step canvas correctly reflects the assigned components 122.
[0054] In more mathematical terms, array 124 and the corresponding step canvas can be a two-dimensional array with height H and width W. ,in, Each step represents a canvas. Here, This indicates the quantity of component 122. (Cell) The storage occupies the type identifier (ID) number of component 122, or if the coordinates If no component 122 is placed at a location, the value is 0, and the coordinates correspond to position 136. For the three-dimensional array 124, the corresponding array 124 expression can be used.
[0055] For example, application software component 106 and / or processor 102 can also be configured to provide list 126 as a graph representing the respective component 122 and the respective connection 128 of the respective component 122.
[0056] Here, a graph can be understood as a structure consisting of a set of objects, where some pairs of objects are "related" in some sense. These objects correspond to mathematical abstractions called vertices (i.e., nodes or points), and each related pair of vertices is called an edge (i.e., a link or line). A graph can be graphically depicted as a set of points or dots for vertices, which are connected by lines or curves for edges.
[0057] In the context of this invention, the nodes of the graph can correspond to component 122 or optionally to network or network nodes. As mentioned above, network nodes can be of the following types: ground, power supply (e.g., 24 volts), etc., wherein the network can be understood as the electrically connected component 122 and its connection 128. Furthermore, the edges of the graph can correspond to the connections 128 that electrically connect component 122 (and optionally connect network or network nodes). Therefore, the elements of List 126 can be represented by the graph.
[0058] As mentioned above, list 126 can be referred to as a netlist in the EDA context. A netlist can, for example, include a design schematic of all electrical components connected via the net. Here, the schematic should not be confused with the layout 140 of PCB 120. List 126 or the netlist can be represented as an undirected graph. ,in, It is a collection of all necessary components 122 and the network, and It is a set of 128 connections between components and networks. Although a netlist can naturally correspond to a hypergraph, in many examples it can be transformed into a bipartite graph between component nodes and network nodes.
[0059] In some examples, the feature information 130 may include information about the type, shape, or characteristics of the respective component 122 and / or the respective connection 128.
[0060] The aforementioned types can, for example, indicate whether the corresponding component 122 is a resistor, capacitor, transistor, battery, network node, ground potential, or a potential with a certain voltage (e.g., 24 volts), as mentioned above. Furthermore, the type can, for example, indicate whether the corresponding connection 128 is a signal connection or a power connection suitable for a larger current or voltage than a signal connection. The corresponding shape can indicate the size of the corresponding component 122 or the corresponding connection 128, for example, expressed in geometric dimensions. The characteristics can, for example, include the electrical, thermal, physical, or chemical properties of the corresponding component 122 or the corresponding connection 128, such as heat dissipation or electromagnetic radiation or interference generated during the operation of the corresponding component 122 or the corresponding connection 128. It should be understood that in some examples, the network node can have a type, such as ground, 24-volt power supply, etc., but no placement or shape.
[0061] In addition, as mentioned above, in some examples, feature information 130 may optionally include information about the placement of the already placed component 122 (i.e., feature information 130 may include a position 136 that a component 122 or connection 128 has been pre-assigned).
[0062] Application software component 106 and / or processor 102 may also be configured to provide feature information 130 as a two-dimensional feature array, wherein corresponding vectors of the feature array are assigned to corresponding nodes of the graph, and wherein the corresponding vectors include corresponding information about the type, shape, or characteristics of the corresponding component 122.
[0063] Two-dimensional feature arrays, for example, can have In the form of, V is the set of all the necessary components 122 and networks mentioned above. For each node in graph G, there is a d-dimensional vector containing values that further characterize the elements and networks, particularly their shape (such as height and width) and their (appropriately encoded) type (such as resistor, capacitor, battery, etc.), optional placement (position 136 if component 122 has been placed), and other characteristics. Here, d can be one if feature information 130 is directly assigned to the corresponding node in graph G, or, for example, three if feature information 130 is subdivided into its potential contribution type, shape, and other characteristics.
[0064] In other examples, application software component 106 and / or processor 102 can also be configured to transform model 132 into a factored probability distribution 138, wherein the factored probability distribution 138 includes, for each assignment action 134: a factor for the corresponding component 122, a factor for the x-coordinate in array 124, and a factor for the y-coordinate in array 124. Application software component 106 and / or processor 102 can also be configured to recognize the factored probability distribution 138 as a corresponding probability distribution 138 for assigning one of the components 122 to a corresponding position 136 in array 124.
[0065] In some examples, model 132 can be represented as a policy network that models the assignment action 134 of placing components 122 from list 126 onto array 124. If the policy expressed by model 132 is used... This indicates that action 134 is assigned. The representation, and the state of the canvas or array 124 at a given step t, are used. The strategy is indicated. It can first be represented as a state or step. The corresponding probability distribution 138, denoted by P, is shown below: Then, this strategy can be simplified to a factorized (e.g., autoregressive) probability distribution 138: .
[0066] Here, This represents the factor used for the corresponding component 122 (or node, as explained above). The factor representing the x-coordinate in array 124, and This represents the factor used for the y-coordinate in array 124, for the assignment action 134 or state of the canvas or array 124 at a given step t. If a three-dimensional array 124 is used, this strategy can be simplified, for example, to include an additional factor for the z-coordinate in array 124. Factorization (e.g., autoregressive) probability distribution 138: .
[0067] It should be understood that, in some examples, factorization of the corresponding probability distribution 138 can allow for a significant reduction in the dimensionality of the space involved, thereby contributing to increased efficiency in creating a layout 140 of a PCB 120 including electrical components 122. Here, the factorization of the corresponding probability distribution 138 can, for example, benefit from assigning components 122 and connections 128 to array 124 in sequential groups, rather than assigning all components 122 and connections 128 to array 124 in one step. However, the ordering of the assignments does not necessarily have disadvantages, as in practice (e.g., in PCB manufacturing) such ordering is not necessary and is not actually performed. Rather, the ordering of the assignments is a tool that allows for the factorization and benefits from the reduction in the dimensionality of the space involved. Furthermore, for example, the factorization enables the introduction of action masking. This improved efficiency can be achieved, for example, because the computational and memory resources required for processor 102 to execute the proposed method are significantly less. In some examples, particularly for large arrays with many components 122 or complex connections 128, layout 140 can be created for the first time ever, for example, without the need for human expert engineers.
[0068] For example, each factor can depend on array 124, the graph, and the feature array, respectively.
[0069] Therefore, the strategy (which model 132 uses to express it), the corresponding probability distribution 138, and the factorized (e.g., autoregressive) probability distribution 138 can be represented as follows:
[0070] Here, C represents the aforementioned two-dimensional array 124, G represents the graph, and X represents the two-dimensional feature array. Therefore, thanks to the factorization of the corresponding probability distribution 138, the size of the action space is drastically reduced from N×H×W to N+H+W. Here, as mentioned above, N=|V|, where V is the set of all the necessary components 122 and networks, and H and W are the height H and width W of the array 124 or step canvas on which the components 122 can be arranged. This drastic reduction in space size enables a significant efficiency improvement in creating the layout 140 of the PCB 120, which includes the electrical components 122. If a three-dimensional array 124 is used, the factorization of the corresponding probability distribution 138 can, for example, reduce the size of the action space from N×H×W×T to N+H+W+T, where T represents the thickness of the aforementioned array 124.
[0071] In some examples, if an artificial intelligence (AI) model is used in this context, and if θ represents the number of parameters to be trained for the corresponding AI model, then the policy (e.g., model 132 uses it to express), the corresponding probability distribution 138, and the factorized (e.g., autoregressive) probability distribution 138 can be represented as follows:
[0072] For example, this architecture can include several neural networks, some of which can... Figures 2 to 4 The description is as follows: For the input graph G and the 2D array X: A GNN encoder (e.g., a graph neural network) is used to encode the netlist and component (node) features into the latent space. This may involve a transformation from the graph space to a vector space, which is a reduced state space with appropriately adjusted GNN weights. For the input 2D array 124"C": "Conv" (e.g., a convolutional neural network) is used to encode the spatial information of the placed elements into the latent space. This may involve transforming the 2D input into a vector space, which is a reduced state space with appropriately adjusted CNN weights. "De-convolution": This is also a type of CNN, but uses transposed convolution (deconvolution) to recover the original canvas shape in the latent space. This may involve a corresponding inverse or backward transformation. Node action layer: This can be a simple feedforward multilayer perceptron (MLP) or a dot product between node embeddings and pooled canvas representations. Node mask is assigned to placed elements or other non-placeable elements. Probability. X-action layer: feedforward MLP, or the dot product between the sampled node embedding and the y-pooled canvas representation. The X-mask assigns the X coordinates of those sampled nodes (elements) that can never be accommodated regardless of their y-position. Probability. Y-action layer: Feedforward MLP, or a dot product of sampled node embeddings, sampled x-canvas embeddings, and X-pooled canvas representations as inputs. The Y-mask assigns Y coordinates to those that cannot accommodate sampled nodes (elements) and sampled x. Probability.
[0073] If a 3D array 124 is used in some examples, a corresponding Z-action layer can be added.
[0074] In some examples, application software component 106 and / or processor 102 can also be configured to: provide a training layout 144 including a training array 124 of a training board canvas, a training list 126 of components 122 and electrical connections 128 of components 122 of the training layout 144, and training feature information 130 of the corresponding components 122 and corresponding connections 128 of the training layout 144; determine a corresponding training probability distribution 138 for assigning one of the components 122 to a corresponding position 136 of the training array 124 using model 132; construct a test layout 140 of the components 122 on the training array 124 using the corresponding assignment action 134 with the highest corresponding probability in the corresponding training probability distribution 138; and assign a reward 142 to the determined corresponding assignment action 134 if the determined corresponding assignment action 134 meets preconfigurable boundary conditions; and update model 132 using the assigned reward 142.
[0075] The proposed update of model 132 can be understood, for example, as a training process for model 132. For this purpose, a training layout 144 (e.g., a layout 140 of a PCB 120 that has already been developed or manufactured) can be provided. The training layout 144 can, for example, be developed by an experienced engineer with or without other EDA tools. The training layout 144 can explicitly or implicitly include training array 124, training list 126, and training feature information 130. If the training layout 144 does not explicitly include this information, analysis can be performed to derive this information from the provided training layout 144.
[0076] In order to perform the training process, the training array 124, the training list 126 and the training feature information 130 can be used together with the model 132 to be trained, wherein the corresponding training probability distribution 138 can be determined, and the test layout 140 can be constructed in a manner similar to the method steps described above for creating the proposed PCB 120 layout 140.
[0077] The constructed test layout 140 can then be compared with the training layout 144, wherein if the corresponding allocation action 134 meets the preconfigurable boundary conditions, a reward 142 can be assigned to the corresponding allocation action 134 determined during the training process. Here, the preconfigurable boundary conditions can, for example, incentivize favorable allocation actions 134, or incentivize favorable test layouts 140 determined or constructed during the training process. Therefore, the reward 142 can be assigned to individual allocation actions 134 or placed as a whole (i.e., the resulting test layout 140) to further guide the agent's policy.
[0078] The corresponding reward can then be used to improve and update model 132, such that the updated model 132 makes the corresponding, rewarded allocation action 134 more likely to occur (e.g., by attributing the increased probability to the allocation action 134).
[0079] In some examples, the provided training layout 144 may consist only of the final training layout 144, while in other examples, the provided training layout 144 may also include sequences of assignment actions 134 that lead to the provided training layout 144. In the latter example, the training data may consist of a set of observed sequences (e.g., rounds), where each sequence may correspond to a chain of component placements over a period of time. Each round can then be modeled in the form of a Markov decision process, starting from the initial observation, which includes an empty step canvas (e.g., step 0) and given netlist and component features (e.g., feature information 130). At each step, an action can be sampled from the policy until a maximum number of steps is reached or no more components 122 can be placed.
[0080] The training process mentioned can focus on learning expert behavior from existing layouts 144 (e.g., PCB layout design (placement)), but can be extended to other forms of feedback, such as simulation key performance indicators (KPIs), without modifying the strategy.
[0081] As an example, the preconfigurable boundary conditions can involve the physical characteristics of the corresponding assigned component 122 and / or the plurality of assigned components 122, and / or the preconfigurable boundary conditions can involve the consistency between the constructed test layout 140 and the training layout 144.
[0082] Here, physical characteristics can include the electrical, thermal, or other physical characteristics of the corresponding component 122 or the plurality of assigned components 122, such that the complete physical characteristics of the constituted layout 140 may also be relevant to the decision to assign the mentioned reward 142 in some examples. As an example, favorable thermal characteristics, reduced heat dissipation during operation, or reduced electromagnetic radiation or interference during operation can be included in the mentioned physical characteristics, allowing model 132 to be trained and improved in this regard. Thus, for example, reward 142 can be calculated based on the electrical and thermal conductivity of the placement.
[0083] In some examples, model 132 can be trained and improved to achieve optimal consistency between the test layout 140 constructed during the training process and the provided training layout 144. Here, training layout 144 can be understood, for example, as a (e.g., artificial) truth design or layout 144 of PCB 120.
[0084] In yet another example, component 122 may include at least one network node, wherein preconfigurable boundary conditions may relate to the distance between components 122 connected to the same network node.
[0085] According to this aspect of the invention, a simple alternative reward for optimal placement is proposed: for example, the Euclidean distance between all components 122 connected to the same network. In optimal placement, this distance should be minimized. Given a list of all network nodes... For each Firstly, it is able to connect to Create a fully connected graph between all components. Each edge in the graph can be weighted using the Euclidean distance of the component placement. Then... It can be used to find its minimum spanning tree (MST). The reward of 142 can then be the sum of the edge weights of all edges in the MST, for example... The reward of 142 will be calculated as:
[0086] It should be understood that training can be performed using any policy optimization algorithm (such as Trust Region Policy Optimization (TRPO) or Proximity Policy Optimization (PPO)).
[0087] In some examples, application software component 106 and / or processor 102 can also be configured to transfer the constructed layout 140 to PCB manufacturing machine 150 (e.g., for manufacturing one or more PCBs 120 based on the transferred constructed layout 140, or for preparing for such manufacturing).
[0088] In another example, application software component 106 and / or processor 102 can also be configured to cause PCB manufacturing machine 150 to manufacture one or more PCBs 120 according to the transmitted and constructed layout 140.
[0089] It should be understood that the described application software component 106 and / or processor 102 are capable of performing similar methods to create a layout 140 of a PCB 120 including electrical components 122. Furthermore, Figure 1 The illustration shows a computer-readable medium 160 capable of including a computer program product 162, wherein the computer program product 162 can be encoded with executable instructions that, when executed, cause a computer system 100 and / or an application development platform 118 to perform the described methods.
[0090] It should also be understood that this patent document proposes a reinforcement learning-based PCB component placement system that can be trained to mimic placement by human experts, and also trained with additional reward signals indicating placement quality (e.g., KPIs derived from thermal or electrical characteristics listed above). The system can include a novel policy network architecture and training process.
[0091] Key aspects may include, for example, trainable policies that encode PCB netlists, board canvases, and component features; efficient policy learning through factorized action space, reducing the amount of exploration and enabling scaling to large board sizes and large numbers of components; efficient policy learning through action masks (e.g., easily incorporating unavailable or constrained placements); and the possibility of learning from expert placements, wherein the method can also be extended to other forms of feedback / rewards, such as temperature, routing KPIs, etc.
[0092] These aspects can lead to, for example, a more efficient PCB layout and design process, improved efficiency in disseminating product engineering knowledge throughout the organization (due to the use of design examples created by experienced engineers as training data), and potentially reduced costs associated with PCB design trial-and-error methods, in which design iterations need to be physically fabricated for testing purposes.
[0093] In another example, the architecture (e.g., model 132) is also open for further incorporation constraints (e.g., the minimum distance between certain types of components 122).
[0094] Figures 2 to 4 A flowchart illustrating the first to third aspects of an exemplary PCB layout process is provided, which can be performed, for example, by a first exemplary system 100.
[0095] A list 126 of components 122 and their electrical connections 128 is provided, along with characteristic information 130 for each component 122 and its corresponding connection 128. Additionally, a suitable array 124 or step canvas (e.g., in...) is provided. Figures 2 to 4 It is described in the text as a "Step Canvas".
[0096] This information can be input into the policy network or model 132, which includes the GNN encoder, convolutions (Conv), and deconvolutions (De-Conv), such as... Figures 2 to 4 As described above, this architecture can include several neural networks, parts of which can be described in [the text]. Figures 2 to 4For the input graph G and the 2D array X: a GNN encoder, such as a graph neural network (GNN), is used to encode the netlist and component (node) features into the latent space. This may involve a transformation from the graph space to a vector space, which is a reduced state space with appropriately adjusted GNN weights. For the input 2D array 124 "C": "Convolution (Conv)," such as a convolutional neural network (CNN), is used to encode the spatial information of the placed elements into the latent space. This may involve transforming the 2D input to a vector space, which is a reduced state space with appropriately adjusted CNN weights. "De-conv": also a CNN, but using transpose (deconvolution) to recover the original canvas shape in the latent space. This may involve a corresponding inverse or reverse transformation.
[0097] The model can then be transformed into a factorized probability distribution 138, wherein the factorized probability distribution 138 includes factors for the corresponding component 122 or node for each assignment action 134. Figure 2 Described as a "NodeAction Layer," it makes the first contribution to the assignment of action 134. The NodeAction Layer can be, for example, a simple feedforward multilayer perceptron (MLP) or a dot product between node embeddings and pooled canvas representations. The node mask assigns a probability of 0 to placed components 122 or other non-placeable components 122. The factor used for the x-coordinate in array 124... Figure 3 Described as the "X Action Layer", it makes a second contribution to the allocation of action 134.
[0098] The X-action layer could be, for example, a feedforward MLP or a dot product between the sampled node embedding and the y-pooled canvas representation. The X-mask assigns a probability of 0 to the X-coordinates of sampled nodes (e.g., component 122) that can never fit regardless of their y-position. The factor used for the y-coordinates in array 124... Figure 4 Described as the "Y Action Layer," it makes a third contribution to the assignment of action 134. The Y Action Layer can be, for example, a feedforward MLP or a dot product of the sampled node embedding, the sampled x canvas embedding, and the X-pooled canvas representation as input. The Y mask assigns a probability of 0 to the Y coordinates of samples that cannot fit the sampled node (e.g., component 122) and the sampled x.
[0099] If a 3D array 124 is used in some examples, it is possible to add a corresponding Z-action layer.
[0100] Figure 5 A functional block diagram of a second example system 100 is depicted, which facilitates the creation of a layout 140 of a PCB 120 including electrical components 122 in a product system 100.
[0101] In the second example system 100, model 132 can be trained using training layout 144, wherein a reward 142 can be assigned to action 134 if the determined corresponding assigned action 134 meets preconfigurable boundary conditions. Model 132 can then be updated using the assigned reward 142, as described in more detail above. Figure 6 This will be illustrated in another example within the context of that example.
[0102] Figure 6 A flowchart depicts a training process involving an example PCB layout process, which can be performed, for example, by a first example system 100 or a second example system 100.
[0103] For the training process, a training layout 144 is provided, which includes a training list 126 of components 122 and electrical connections 128 of the training layout 144, and training feature information 130 of the corresponding components 122 and corresponding connections 128 of the training layout 144. Additionally, a suitable training array 124 or step canvas (in...) is provided. Figure 6 It is described in the text as "Step0 Canvas".
[0104] In step 1, this information can be input into a policy network or model 132, which can then use model 132 to determine a training probability distribution 138 for assigning one of the components 122 to the corresponding position 136 of the training array 124. The assignment action 134 with the highest probability in the probability distribution 138 is selected, and the canvas or array 124 is updated accordingly by assigning the corresponding component 122 to the determined position 136 to obtain, as shown... Figure 6 The “Step 1 Canvas” or array 124’ is depicted in the text.
[0105] In addition, it can be used with training layout 144 (in Figure 6 The description of "Ground-truth Placement" is compared to derive a reward of 142, where... Figure 6 In this context, "IOU" stands for "Intersection over Union". Bonus 142 can be used to update model 132.
[0106] In step 2 and subsequent steps, until the final canvas (e.g., in step T) has been constructed, the canvas or array from the previous step (e.g., for step 2: 124') is input into the policy network or model 132, which is then able to use model 132 to determine a training probability distribution (e.g., for step 2: 138') on the corresponding position (e.g., in step 2: 136') for assigning one of the components 122 to the training array 124. The assignment action 134 with the highest probability in probability distribution 138 is selected again, and the canvas or array (for step 2: 124') is updated accordingly by assigning the corresponding component 122 to the determined position (e.g., in step 2: 136') to obtain (e.g., for step 2) as shown in step 2. Figure 6 The “Step 2 Canvas” or array 124'' depicted in the text.
[0107] See now Figure 6 Method M facilitates the creation of a PCB layout that includes electrical components within a product system. The method can be initiated at M02 and can include several actions performed via the operation of at least one processor.
[0108] These actions can include: action M04 providing an array of PCB board canvases; action M06 providing a list of components and their electrical connections; action M08 providing characteristic information for the corresponding components and connections; action M10 providing a model combining the array, list, and characteristic information, wherein the model describes a series of consecutive actions to assign one of the components in the list to a corresponding position in the array; action M12 using the model to determine a corresponding probability distribution for assigning one of the components to the corresponding position in the array; action M14 using the corresponding assignment action with the highest probability in the corresponding probability distribution to form a layout of the components on the array; and action M16 outputting the formed layout. The method can end at M18.
[0109] It should also be understood that method M can include other actions and features previously discussed regarding computer implementation methods for creating layouts of PCBs including electrical components.
[0110] Figure 8A block diagram depicts a data processing system 1000 (e.g., a computer system) capable of implementing embodiments, such as as part of a product system, and / or other systems operatively configured via software or other means to perform the processes described herein. The data processing system 1000 may include, for example, the computer or IT system or data processing system 100 mentioned above. The depicted data processing system includes at least one processor 1002 (e.g., a CPU) capable of being connected to one or more bridges / controllers / buses 1004 (e.g., a northbridge, a southbridge). Exemplarily, one of the buses 1004 may include one or more I / O buses, such as a PCI Express bus. Also connected to various buses in the depicted example may be main memory 1006 (RAM) and a graphics controller 1008. The graphics controller 1008 may be connected to one or more display devices 1010. It should also be noted that in some embodiments, one or more controllers (e.g., a graphics controller, a southbridge) may be integrated with the CPU (on the same chip or die). Examples of CPU architectures include IA-32, x86-64, and ARM processor architectures.
[0111] Other peripheral devices connected to one or more buses may include a communication controller 1012 (Ethernet controller, WiFi controller, cellular controller) operable to connect to a local area network (LAN), wide area network (WAN), cellular network and / or other wired or wireless network 1014 or communication devices.
[0112] Other components connected to various buses can include one or more I / O controllers 1016, such as USB controllers, Bluetooth controllers, and / or dedicated audio controllers (e.g., connected to speakers and / or microphones). It should also be understood that various peripheral devices can be connected to the I / O controller (e.g., via various ports and connections), including input devices 1018 (e.g., keyboards, mice, pointing devices, touchscreens, touchpads, drawing tablets, trackballs, buttons, keypads, game controllers, gamepads, cameras, microphones, scanners, motion sensing devices capturing motion gestures), output devices 1020 (e.g., printers, speakers), or any other type of device operable to provide input to or receive output from the data processing system. Furthermore, it should be understood that many devices referred to as input or output devices are capable of both providing input and receiving communication output with the data processing system. For example, processor 1002 can be integrated into a housing (e.g., a tablet computer) that includes a touchscreen serving as both an input and display device. Additionally, it should be understood that some input devices (such as laptops) can include multiple different types of input devices (e.g., touchscreens, touchpads, keyboards). Furthermore, it should be understood that other peripheral hardware 1022 connected to the I / O controller 1016 can include any type of device, machine, or component configured to communicate with the data processing system.
[0113] Additional components connected to various buses can include one or more storage controllers 1024 (e.g., SATA). The storage controller can connect to storage devices 1026, such as one or more storage drives and / or any associated removable media, which can be any suitable non-transitory machine-usable or machine-readable storage medium. Examples include non-volatile devices, volatile devices, read-only devices, writable devices, ROM, EPROM, magnetic tape storage, floppy disk drives, hard disk drives, solid-state drives (SSDs), flash memory, optical disc drives (CD, DVD, Blu-ray), and other known optical, electrical, or magnetic storage devices, drives, and / or computer media. Furthermore, in some examples, storage devices such as SSDs can be directly connected to I / O buses 1004, such as the PCI Express bus.
[0114] The data processing system according to embodiments of this disclosure can include an operating system 1028, software / firmware 1030, and a data storage device 1032 (e.g., the data storage device can be stored on storage device 1026 and / or memory 1006). Such an operating system can employ a command-line interface (CLI) shell and / or a graphical user interface (GUI) shell. A GUI shell allows multiple display windows to be presented simultaneously in the graphical user interface, each providing an interface for a different application or different instances of the same application. A cursor or pointing device in the graphical user interface can be operated by a user via a pointing device such as a mouse or a touchscreen. The position of the cursor / pointing device can be changed and / or events (such as clicking a mouse button or touching a touchscreen) can be generated to trigger a desired response. Examples of operating systems that can be used in the data processing system include Microsoft Windows, Linux, UNIX, iOS, and Android operating systems. Furthermore, examples of data storage devices include data files, data tables, relational databases (e.g., Oracle, Microsoft SQL Server), database servers, or any other structure and / or device capable of storing data and retrieving it by a processor.
[0115] The communication controller 1012 is capable of connecting to a network 1014 (not part of the data processing system 1000), which can be any public or private data processing system network or network configuration known to those skilled in the art, including the Internet. The data processing system 1000 is capable of communicating via network 1014 with one or more other data processing systems (e.g., server 1034, which is also not part of the data processing system 1000). However, alternative data processing systems can correspond to multiple data processing systems implemented as part of a distributed system in which processors associated with several data processing systems can communicate via one or more network connections and collectively perform tasks described as being performed by a single data processing system. Therefore, it should be understood that, when referring to a data processing system, such a system can be implemented across several data processing systems organized in a distributed system that communicates with each other via a network.
[0116] Furthermore, the term "controller" refers to any device, system, or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software, or at least a combination of both. It should be noted that the functionality associated with any particular controller can be centralized or distributed, whether local or remote.
[0117] Furthermore, it should be understood that the data processing system can be implemented as a virtual machine architecture or a virtual machine in a cloud environment. For example, processor 1002 and associated components can correspond to a virtual machine running in a virtual machine environment on one or more servers. Examples of virtual machine architectures include VMware ESXi, Microsoft Hyper-V, Xen, and KVM.
[0118] Those skilled in the art will understand that the hardware described for a data processing system can vary for a particular implementation. For example, the data processing system 1000 in this example can correspond to a computer, workstation, server, PC, laptop, tablet, mobile phone, and / or any other type of device / system operable to process data and perform the functions and features described herein associated with the operation of a data processing system, computer, processor, and / or controller. The examples depicted are provided for illustrative purposes only and are not intended to imply any architectural limitations of this disclosure.
[0119] Furthermore, it should be noted that the processor described herein can reside in a server located remotely from the display and input devices described herein. In such an example, the described display and input devices can be included in a client device that communicates with the server (and / or a virtual machine running on the server) via a wired or wireless network (potentially including the Internet). In some implementations, for example, such a client device can execute a remote desktop application or correspond to a portal device that utilizes the server to execute a remote desktop protocol in order to send input from the input device to the server and receive visual information from the server for display via the display device. Examples of such remote desktop protocols include Teradici's PCoIP, Microsoft's RDP and RFB protocols. In such an example, the processor described herein can correspond to a virtual processor of a virtual machine running in the physical processor of the server.
[0120] As used herein, the terms “component” and “system” are intended to encompass hardware, software, or a combination of hardware and software. Thus, for example, a system or component can be a process, a process executing on a processor, or a processor itself. Furthermore, a component or system can be localized on a single device or distributed across several devices.
[0121] Furthermore, as used herein, a processor corresponds to any electronic device configured to process data via hardware circuitry, software, and / or firmware. For example, the processor described herein can correspond to one or more (or configurations) of a microprocessor, CPU, FPGA, ASIC, or any other integrated circuit (IC) or other type of circuit capable of processing data in a data processing system that can take the form of a controller board, computer, server, mobile phone, and / or any other type of electronic device.
[0122] Those skilled in the art will recognize that, for simplicity and clarity, this document does not depict or describe the complete structure and operation of all data processing systems applicable to this disclosure. Rather, only the parts of a data processing system that are unique to this disclosure or necessary for understanding this disclosure are depicted and described. The remaining construction and operation of the data processing system 1000 can conform to various current implementations and practices known in the art.
[0123] Furthermore, it should be understood that, unless explicitly limited in some examples, the words or phrases used herein should be interpreted broadly. For example, the term “comprise” and its derivatives mean unrestricted inclusion. The singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context explicitly indicates otherwise. Additionally, the term “and / or” as used herein refers to and covers any and all possible components of one or more of the associated listed items. The term “or” is inclusive, meaning and / or unless the context explicitly indicates otherwise. The phrases “associated with” and “associated therewith” and their derivatives can mean including, being included, interconnected, containing, being contained within, connected to or linked to, coupled to or coupled to, able to communicate with, cooperate with, intertwined, parallel, adjacent, bound to or limited to, having, having the nature of, etc.
[0124] Furthermore, while the terms “first,” “second,” “third,” etc., can be used herein to describe various elements, functions, or actions, these elements, functions, or actions should not be limited by these terms. Rather, these ordinal adjectives are used to distinguish different elements, functions, or actions from one another. For example, without departing from the scope of this disclosure, a first element, function, or action can be referred to as a second element, function, or action, and similarly, a second element, function, or action can be referred to as a first element, function, or action.
[0125] Furthermore, phrases such as "the processor is configured to" perform one or more functions or processes can mean that the processor is operatively configured or operablely configured to perform these functions or processes via software, firmware, and / or wired circuitry. For example, a processor configured to perform a function / process can correspond to a processor executing software / firmware programmed to cause the processor to perform that function / process, and / or can correspond to a processor having software / firmware in memory or a storage device that can be executed by the processor to perform that function / process. It should also be noted that a processor "configured to" perform one or more functions or processes can also correspond to processor circuitry (e.g., an ASIC or FPGA design) specifically manufactured or "wired" to perform these functions or processes. Additionally, the phrase "at least one" preceding an element (e.g., processor) is configured to perform more than one function, and can correspond to one or more elements (e.g., processors) that each perform those functions, and can also correspond to two or more elements (e.g., processors) that each perform a different function among one or more different functions.
[0126] In addition, the term "adjacent to" can mean: an element is relatively close to but does not touch another element; or an element touches another part, unless the context clearly indicates otherwise.
[0127] Although exemplary embodiments of this disclosure have been described in detail, those skilled in the art will understand that various changes, substitutions, variations and modifications can be made to this disclosure without departing from the spirit and scope of this disclosure in its broadest form.
[0128] The descriptions in this patent document should not be construed as implying that any particular element, step, action, or function is a necessary element that must be included within the scope of the claims: the scope of the patented subject matter is limited only by the permitted claims.
[0129] The elements and features recited in the appended claims can be configured in different ways to produce new claims that also fall within the scope of this invention. Therefore, although the dependent claims appended below refer only to a single independent or dependent claim, it should be understood that these dependent claims can be alternatively modified to selectively refer to any of the preceding or subsequent claims, whether independent or dependent. Such new configurations should be understood as forming part of this specification.
[0130] Although the invention has been described above with reference to various embodiments, it should be understood that many changes and modifications can be made to the described embodiments. Therefore, the foregoing description is intended to be illustrative rather than restrictive, and it should be understood that all equivalents and / or configurations of the embodiments are intended to be included in this specification.
[0131] List of reference numerals
[0132] 100 processing system
[0133] 102 processor
[0134] 104 Memory
[0135] 106 Application Software Components
[0136] 108 Internal Data Memory
[0137] 110 Input Devices
[0138] 112 Display devices
[0139] 114 Graphical User Interface (GUI)
[0140] 116 PCB Layout User Interface
[0141] 118 PCB Layout System
[0142] 120 PCB
[0143] 122 Electrical Components
[0144] 124 array
[0145] 126 List
[0146] 128 Electrical Connections
[0147] 130 Feature Information
[0148] Model 132
[0149] 134 Assignment Actions
[0150] 136 Location
[0151] 138 Probability Distribution
[0152] 140 layout
[0153] 142 Rewards
[0154] 144 Realistic Layout
[0155] 150 PCB manufacturing machines
[0156] 160 Computer-readable media
[0157] 162 Computer program products.
Claims
1. A computer-implemented method for creating a layout of a printed circuit board (PCB) comprising a plurality of electrical components electrically connected, the computer-implemented method comprising: Provides an array of PCB board canvases; Provide a list of components and their electrical connections; Provide characteristic information of the corresponding components in the components and the corresponding electrical connections in the electrical connections; A model is provided that combines the array, the list, and the feature information, wherein the model describes a sequence of consecutive actions that assign one of the components of the list to a corresponding position in the array; The model is used to determine the corresponding probability distribution for assigning one of the components to the corresponding position in the array; The layout of the components on the array is constructed using the corresponding allocation action with the highest corresponding probability in the corresponding probability distribution; and The layout formed by the output.
2. The computer-implemented method according to claim 1 further includes: The provided array is used as a step canvas with height H and width W, and the components can be arranged on the step canvas; and The step canvas is updated after the corresponding assignment action in one of the components.
3. The computer-implemented method according to any one of the preceding claims further includes: The list is provided as a diagram representing the respective components and their respective electrical connections.
4. The computer-implemented method according to any one of the preceding claims, wherein, The feature information includes information about the type, shape, or characteristics of the corresponding component, the corresponding connection, or the corresponding component and the corresponding connection.
5. The computer-implemented method according to claims 3 and 4, further comprising: The feature information is provided as a two-dimensional feature array. Wherein, the corresponding vectors of the two-dimensional feature array are assigned to the corresponding nodes of the graph, and The corresponding vector includes information about the type, shape, or characteristics of the corresponding component.
6. The computer-implemented method according to any one of the preceding claims further includes: The model is transformed into a factorized probability distribution, wherein, for each allocation action, the factorized probability distribution includes: Factors used for the corresponding components; Factors for the x-coordinates in the array; and Factors for the y-coordinates in the array; and The factorized probability distribution is identified as a corresponding probability distribution for assigning one of the components to a corresponding position on the array.
7. The computer-implemented method according to claim 6, wherein, Each factor depends on the array, the graph, and the feature array, respectively.
8. The computer-implemented method according to any one of the preceding claims further includes: A training layout is provided, the training layout including a training array of a training board canvas, a training list of components of the training layout and electrical connections of the components, and training feature information of the corresponding components and corresponding connections of the training layout. The model is used to determine the corresponding training probability distribution for assigning one of the components to the corresponding position in the training array; The test layout of the component is constructed on the training array using the corresponding assignment action with the highest corresponding probability in the corresponding training probability distribution. When the determined corresponding allocation action meets the preconfigurable boundary conditions, a reward is allocated to the determined corresponding allocation action; and Update the model using the allocated rewards.
9. The computer-implemented method according to claim 8, wherein, The preconfigurable boundary conditions relate to the physical characteristics of the corresponding assigned components, the physical characteristics of the assigned components, or the physical characteristics of the corresponding assigned components and the assigned components, and / or the preconfigurable boundary conditions relate to the consistency between the constructed test layout and the training layout.
10. The computer-implemented method according to claim 8 or 9, wherein, The component includes at least one network node, and The preconfigurable boundary conditions relate to the distance between components connected to the same network node in the at least one network node.
11. The computer-implemented method according to any one of the preceding claims further includes: The resulting layout is then transferred to the PCB manufacturing machine.
12. The computer-implemented method according to claim 11, further comprising: The PCB manufacturing machine manufactures one or more PCBs according to the layout formed by the transmission.
13. A computer system arranged and configured to perform the steps of a computer-implemented method as described in any of the preceding claims.
14. A computer program product comprising computer program code, which, when executed by a computer system, causes the computer system to perform the method of any one of claims 1 to 12.
15. A computer-readable medium comprising a computer program product, the computer program product including computer program code, which, when executed by a computer system, causes the computer system to perform the method of any one of claims 1 to 12.