Semiconductor device, arithmetic device, and electronic apparatus

Abstract

A semiconductor device capable of long-term retention of data for operation is provided. The semiconductor device includes an operation unit and a driving unit, each of which includes first to third transistors, a first capacitor, a second capacitor, and a first amplification circuit. A first terminal of the first transistor is electrically connected to a gate of the third transistor, an input terminal of the first amplification circuit, and a first terminal of the first capacitor, and a second terminal of the first transistor is electrically connected to a first terminal of the second transistor, an output terminal of the first amplification circuit, and a first terminal of the second capacitor. The first amplification circuit is used as a buffer circuit that outputs an analog potential, and the first amplification circuit supplements electric charges to the first terminal of the second capacitor in accordance with a potential of the first terminal of the first capacitor, whereby a leakage current between a source and a drain in each of the first transistor and the second transistor can be prevented.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a computing device, and an electronic device.

[0002] Furthermore, one aspect of the present invention is not limited to the aforementioned technical fields. The technical fields of the invention disclosed in this specification relate to an object, a method of operation, or a method of manufacturing. Additionally, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, specifically, examples of the technical fields of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, storage devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for inspecting them. Background Technology

[0003] The development of integrated circuits that mimic the structure of the human brain is currently booming. These integrated circuits assemble electronic circuitry that serves as the brain's structure and include circuits that mimic the "neurons" and "synapses" of the human brain. Therefore, such integrated circuits are sometimes referred to as "neuro-morphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, which, compared to the von Neumann architecture where power consumption increases with processing speed, promises to enable parallel processing with extremely low power consumption.

[0004] Information processing models that mimic neural networks, including "neurons" and "synapses," are called artificial neural networks (ANNs). For example, Non-Patent Documents 1 and 2 disclose computing devices that use SRAM (Static Random Access Memory) to construct artificial neural networks.

[0005] In addition, there is research on using computing devices constituting artificial neural networks, for example, for the correction of images displayed on display devices. For example, Patent Document 1 discloses a display device that uses computing devices constituting artificial neural networks to adjust the brightness, hue, etc. of the displayed image according to the preferences of the person viewing the image.

[0006] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Patent Application Publication No. 2018-36639.

[0007] [Non-patent literature] [Non-Patent Literature 1] M. Kang et al., “IEEE Journal of Solid-State Circuits”, 2018, Volume 53, No.2, pp.642-655. [Non-Patent Literature 2] J. Zhang et al., “IEEE Journal of Solid-State Circuits”, 2017, Volume 52, No.4, pp.915-924. [Non-patent document 3] H.Baba et al., "Novel analog in-memory compute with>1 nAcurrent / cell and 143.9 TOPS / W enabled by monolithic normally-off Zn-richCAAC-IGZO FET-on-Si CMOS technology," IEEE International Electron Devices Meeting (IEDM), pp. 21.2.1-21.2.4, 2021. Summary of the Invention

[0008] The technical problem that the invention aims to solve Artificial neural networks also have various models. For example, a model used for image analysis is called a Convolutional Neural Network (CNN). CNNs are among the neural networks that perform exceptionally well in image recognition, but their computational complexity depends on factors such as image resolution and filter size. Specifically, for example, higher image resolution, larger filter size, or smaller stride result in greater computational complexity in the CNN, thus increasing the processing time of the computing device. Furthermore, higher computational complexity also leads to higher power consumption of the computing device.

[0009] Furthermore, in CNNs, feature extraction is performed on each of the multiple partitioned images using the same filter. Therefore, since the filter is used repeatedly in each operation, there is a significant amount of work involved in reading out the filter from storage circuitry. Because the power consumption of reading out the filter and transmitting data such as the filter is high, the computational circuitry performing the operations of the convolutional neural network is expected to not only perform computational functions known as in-memory computing (CiM) or in-memory computing (iMC), but also to retain the filter value used as the multiplier for extended periods.

[0010] One objective of this invention is to provide a computing circuit with reduced power consumption. Another objective of this invention is to provide a computing circuit capable of retaining data for extended periods. Another objective of this invention is to provide a novel computing circuit. Another objective of this invention is to provide a computing device including the aforementioned computing circuit. Another objective of this invention is to provide an electronic device including the aforementioned computing device.

[0011] Note that the purpose of one aspect of the present invention is not limited to the objectives described above. The above objectives do not preclude the existence of other objectives. Furthermore, other objectives are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract objectives not mentioned above from the description, drawings, etc. Additionally, one aspect of the present invention achieves at least one of the above and other objectives without necessarily achieving all of them.

[0012] means of solving technical problems In convolution processing used in convolutional neural networks, each of the multiple partitioned images is used as input data and multiplied with the same filter value. Therefore, in one aspect of the present invention, in order to perform multiplication with each input data, a holding node is needed that maintains the same filter value as its potential. Furthermore, by inputting a potential corresponding to the input data to this holding node through a capacitor, the potential of the holding node is the sum of the potential of the filter value and the potential corresponding to the input data due to capacitive coupling.

[0013] Furthermore, when an n-channel transistor operates in the subthreshold region, the current between its source and drain (sometimes referred to as the subthreshold current in this case) is approximately equal to the gate-source voltage V. GS And with exp[V GS -V th Proportional. Note that V th This is the threshold voltage of the transistor. At this time, the gate potential is the potential V of the filter value. F With respect to the potential V corresponding to the input data IN The sum of and the source potential is V GNDWhen, exp[V GS -V th This can be rewritten as exp[V] F ]exp[V IN ]exp[V GND -V th From this, we can see that the subthreshold current is related to exp[V]. F ] and exp[V IN The product of ] is proportional.

[0014] Therefore, one embodiment of the operational circuit of the present invention includes a circuit in which one of the electrodes of a capacitor is connected to the gate of a transistor. Note that this connection point is a holding node. Furthermore, since the input data is multiplied by the same filtered value, the circuit preferably maintains the filtered value for a long period. For example, it is preferable to provide two or more switches connected in series between the holding node and the wiring that transmits the filtered value written to the holding node. Moreover, it is preferable to supply a potential corresponding to the holding node's potential between each switch to reduce leakage current caused by the switches. Specifically, this structure is preferably used, for example, as a buffer circuit for the output analog potential. This prevents the holding node's potential from fluctuating due to leakage current through the switches, etc.

[0015] The following describes the specific structure of one embodiment of the present invention. (1) One aspect of the present invention is a semiconductor device comprising a first unit and a second unit. The first unit includes a first transistor to a third transistor, a first capacitor, a second capacitor, and a first amplifier circuit, and the second unit includes a fourth transistor to a sixth transistor, a third capacitor, a fourth capacitor, and a second amplifier circuit.

[0017] The first terminal of the first transistor is electrically connected to the gate of the third transistor, the input terminal of the first amplifier circuit, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the output terminal of the first amplifier circuit, and the first terminal of the second capacitor. Furthermore, the first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the input terminal of the second amplifier circuit, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the output terminal of the second amplifier circuit, and the first terminal of the fourth capacitor. Additionally, the second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first wiring. Furthermore, the second terminal of the fifth transistor, the first terminal of the sixth transistor, the second terminal of the first capacitor, and the second terminal of the third capacitor are electrically connected to the second wiring. Finally, the gates of the first transistor, the second transistor, the fourth transistor, and the fifth transistor are electrically connected to the third wiring.

[0018] In addition, the first and second amplifier circuits are used as buffer circuits for the output analog potential. (2) In addition, in one embodiment of the invention described in (1) above, the first to sixth transistors may also contain oxide semiconductors in the channel forming region, and the transistors in the first amplifier circuit and the second amplifier circuit may also contain oxide semiconductors or silicon in the channel forming region. In particular, the oxide semiconductor preferably contains one or more elements selected from indium, zinc, and element M.

[0020] Element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (3) In addition, in one aspect of the present invention described in (2) above, the channel length of the switching transistor may be greater than the channel length of the amplifying transistor, and the channel width of the amplifying transistor may be greater than the channel width of the switching transistor.

[0022] Note that, here, the switching transistors refer to the first transistor, the second transistor, the fourth transistor, and the fifth transistor, and the amplifying transistors refer to the third transistor and the sixth transistor. (4) One aspect of the present invention is an operational circuit that includes a first unit and a second unit, and is different from (1) above. The first unit includes a first transistor to a third transistor, a seventh transistor, a first capacitor, a second capacitor, and a first amplifier circuit, and the second unit includes a fifth transistor to a sixth transistor, an eighth transistor, a third capacitor, a fourth capacitor, and a second amplifier circuit.

[0024] Furthermore, the first terminal of the first transistor is electrically connected to the gate of the third transistor, the input terminal of the first amplifier circuit, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the output terminal of the first amplifier circuit, and the first terminal of the second capacitor. Additionally, the first terminal of the third transistor is electrically connected to the first terminal of the seventh transistor. The first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the input terminal of the second amplifier circuit, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the output terminal of the second amplifier circuit, and the first terminal of the fourth capacitor. Furthermore, the first terminal of the sixth transistor is electrically connected to the first terminal of the eighth transistor. The second terminals of the second transistor and the seventh transistor are electrically connected to the first wiring. Additionally, the second terminals of the sixth transistor, the eighth transistor, the first capacitor, and the third capacitor are electrically connected to the second wiring. Finally, the gates of the first transistor, the second transistor, the fourth transistor, and the fifth transistor are electrically connected to the third wiring.

[0025] In addition, the first and second amplifier circuits are used as buffer circuits for the output analog potential. (5) In addition, in one embodiment of the invention described in (4) above, the first to eighth transistors may also contain oxide semiconductors in the channel forming region, and the transistors in the first amplifier circuit and the second amplifier circuit may also contain oxide semiconductors or silicon in the channel forming region. In particular, the oxide semiconductor preferably contains one or more selected from indium, zinc, and element M.

[0027] Element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (6) In addition, in one aspect of the present invention described in (5) above, the channel length of the switching transistor may be greater than the channel length of the amplifying transistor, and the channel width of the amplifying transistor may be greater than the channel width of the switching transistor.

[0029] Note that, here, the switching transistors refer to the first transistor, the second transistor, the fourth transistor, and the fifth transistor, and the amplifying transistors refer to the third transistor and the sixth transistor. (7) One aspect of the present invention is a semiconductor device comprising a first unit and a second unit, which is different from (1) and (4) above. The first unit includes a first transistor to a third transistor, a seventh transistor, a ninth transistor, a tenth transistor, a first capacitor, and a second capacitor, and the second unit includes a fourth transistor to a sixth transistor, an eighth transistor, an eleventh transistor, a twelfth transistor, a third capacitor, and a fourth capacitor.

[0031] The first terminal of the first transistor is electrically connected to the gate of the third transistor, the gate of the ninth transistor, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminals of the second transistor, the ninth transistor, the tenth transistor, and the second capacitor. Additionally, the first terminal of the third transistor is electrically connected to the first terminal of the seventh transistor. Furthermore, the first terminal of the fourth transistor is electrically connected to the gates of the fifth and eleventh transistors and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminals of the fifth, eleventh, and twelfth transistors and the fourth capacitor. Additionally, the first terminal of the sixth transistor is electrically connected to the first terminal of the eighth transistor. Furthermore, the second terminals of the second and seventh transistors are electrically connected to the first wiring. Additionally, the second terminals of the fifth and eighth transistors, the second terminals of the first and third capacitors are electrically connected to the second wiring. Finally, the gates of the first, second, fourth, and fifth transistors are electrically connected to the third wiring. (8) In addition, in one aspect of the invention described in (7) above, the first to eighth transistors may also contain an oxide semiconductor in the channel forming region, and the ninth to twelfth transistors may also contain an oxide semiconductor or silicon in the channel forming region. In particular, the oxide semiconductor preferably contains one or more selected from indium, zinc, and element M.

[0033] Element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (9) In addition, in one aspect of the present invention described in (8) above, the channel length of the switching transistor may be greater than the channel length of the amplifying transistor, and the channel width of the amplifying transistor may be greater than the channel width of the switching transistor.

[0035] Note that, here, the switching transistors refer to the first, second, fourth, and fifth transistors, and the amplifying transistors refer to the third, sixth, and ninth through twelfth transistors. (10) One aspect of the present invention is a semiconductor device comprising a first unit and a second unit, which is different from (1), (4) and (7) above. The first unit includes a first transistor to a third transistor, a ninth transistor, a tenth transistor, a first capacitor and a second capacitor, and the second unit includes a fourth transistor to a sixth transistor, an eleventh transistor, a twelfth transistor, a third capacitor and a fourth capacitor.

[0037] The first terminal of the first transistor is electrically connected to the gate of the third transistor, the gate of the ninth transistor, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminals of the second transistor, the ninth transistor, the tenth transistor, and the second capacitor. Furthermore, the first terminal of the fourth transistor is electrically connected to the gates of the sixth and eleventh transistors and the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminals of the fifth, eleventh, and twelfth transistors and the fourth capacitor. Additionally, the second terminals of the second and third transistors are electrically connected to the first wiring. Furthermore, the second terminals of the fifth and sixth transistors, the second terminals of the first and third capacitors are electrically connected to the second wiring. Finally, the gates of the first, second, fourth, and fifth transistors are electrically connected to the third wiring. (11) In another embodiment of the invention described in (10) above, the first to sixth transistors may also contain an oxide semiconductor in the channel forming region, and the ninth to twelfth transistors may also contain an oxide semiconductor or silicon in the channel forming region. In particular, the oxide semiconductor preferably contains one or more selected from indium, zinc, and element M.

[0039] Element M is selected from one or more of the following: aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (12) In addition, in one aspect of the present invention described in (11) above, the channel length of the switching transistor may be greater than the channel length of the amplifying transistor, and the channel width of the amplifying transistor may be greater than the channel width of the switching transistor.

[0041] Note that, here, the switching transistors refer to the first, second, fourth, and fifth transistors, and the amplifying transistors refer to the third, sixth, and ninth through twelfth transistors. (13) Furthermore, in any of the embodiments of the present invention described in (1) to (12) above, one or more selected from the first capacitor to the fourth capacitor may also include a first conductive layer and a second conductive layer serving as a pair of electrodes, and a first insulating layer serving as a dielectric. In particular, the first conductive layer is preferably disposed at the bottom and side of the opening in the second insulating layer leading to the third conductive layer. In addition, the first insulating layer is preferably disposed on the top surface of the first conductive layer, the side of the opening, and the top surface of the second insulating layer. In addition, the second conductive layer is preferably disposed in the region including the opening on the first insulating layer. (14) In another aspect, the present invention is a computing device comprising the computing circuit described in (13) above and a first driving circuit to a fourth driving circuit. The first driving circuit and the fourth driving circuit are electrically connected to a first wiring, the second driving circuit is electrically connected to a second wiring, and the third driving circuit is electrically connected to a third wiring.

[0044] The first driving circuit has the function of generating a first current corresponding to the first data and causing it to flow through the first wiring. Furthermore, the second driving circuit has the function of generating a second current corresponding to the second data and causing it to flow through the second wiring. Additionally, the third driving circuit has the function of supplying a high-level potential or a low-level potential to the third wiring. The fourth driving circuit has the function of obtaining a third current generated in the first unit from the first wiring, performing a function calculation with the value corresponding to the third current as input, and outputting the calculation result, wherein the third current corresponds to the product of the first data and the second data.

[0045] In addition, the current quantities of the first to the third currents are the current quantities of the third and sixth transistors within the range of their operation in the subthreshold region. (15) In addition, one aspect of the present invention is an electronic device that includes the computing device and the housing described in (14) above.

[0047] Invention Effects In the structure of the first unit in (1) above, the first terminal of the first capacitor is the first holding node, and the first terminal of the second capacitor is the second holding node. The first holding node can hold the filter value at a potential, can write the filter value when both the first transistor and the second transistor are in the on state, and can hold the filter value when both the first transistor and the second transistor are in the off state.

[0048] Furthermore, when the third transistor operates in the subthreshold region, by supplying a potential corresponding to the input data to the second terminal of the first capacitor while the filter value is held at the first holding node, a subthreshold current corresponding to the result of the multiplication of the input data and the filter value flows through the third transistor. Thus, with the structure described in (1), the multiplication of the filter value and the input data can be performed simultaneously.

[0049] Furthermore, since the first holding node is electrically connected to the input terminal of the first amplifier circuit, the potential corresponding to the filtered value held by the first holding node is input to the input terminal of the first amplifier circuit. Since the first amplifier circuit is used as a buffer circuit for the output analog potential, ideally, the same potential as the input terminal is output to the output terminal of the first amplifier circuit. Therefore, the second holding node is also supplied with a potential corresponding to the filtered value. Additionally, when the potential of the second holding node fluctuates due to a fault, charge is replenished through the output analog potential buffer circuit, thus maintaining the potential of the second holding node. Consequently, the voltage between the first and second terminals of the first transistor becomes 0V, thereby reducing the leakage current between the source and drain of the first transistor. Therefore, the potential corresponding to the filtered value of the first cell can be maintained for a long period.

[0050] In addition, the above explanation also applies to Unit 2.

[0051] Furthermore, the first and second amplifier circuits are used as voltage followers or source followers in the buffer circuit for the output analog potential. In particular, the source follower has fewer transistors than the voltage follower, so by using both the first and second amplifier circuits as source followers, the circuit area of ​​the operational circuit can be reduced.

[0052] Furthermore, as shown in (4) above, by providing the fourth and eighth transistors, drain-induced barrier lowering (DIBL) in the third and sixth transistors can be prevented, thereby preventing the threshold voltage of the third and sixth transistors from decreasing. Additionally, as shown in (7) above, by providing the fourth and tenth transistors, DIBL in the third and ninth transistors can be prevented, thereby preventing the threshold voltage of the third and ninth transistors from decreasing.

[0053] Furthermore, as shown in (2), (5), (8), and (11) above, by including oxide semiconductors in the channel forming regions of the plurality of transistors included in the first and second units, all transistors can be manufactured in the same process, thus shortening the cycle time required to manufacture the operational circuit. Additionally, in (2), (5), (8), and (11) above, the first, second, fourth, and fifth transistors are all used as switching transistors; therefore, by including oxide semiconductors in the channel forming regions of these transistors, the off-state current can be reduced. Thus, the potential of the first terminals of the first to fourth capacitors can be maintained for a long period.

[0054] Furthermore, as shown in (2) and (5) above, by using silicon in the channel forming regions of the transistors included in the first and second amplifier circuits, the on-state current of these transistors can be increased. This improves the driving speed of the first and second amplifier circuits and allows for rapid charge replenishment. Additionally, as shown in (8) above, by using silicon in the channel forming regions of the fifth, sixth, eleventh, and twelfth transistors, the on-state current of these transistors can be increased. This improves the operating speed of the source follower included in the structure of (8) and allows for rapid charge replenishment. Furthermore, as shown in (11) above, by using silicon in the channel forming regions of the fourth, fifth, ninth, and tenth transistors, the on-state current of these transistors can be increased. This improves the speed of the source follower included in the structure of (11) and allows for rapid charge replenishment.

[0055] According to one aspect of the present invention, a computing circuit with reduced power consumption can be provided. Furthermore, according to one aspect of the present invention, a computing circuit capable of retaining data for extended periods can be provided. Additionally, according to one aspect of the present invention, a novel computing circuit can be provided. Furthermore, according to one aspect of the present invention, a computing device including the aforementioned computing circuit can be provided. Furthermore, according to one aspect of the present invention, an electronic device including the aforementioned computing device can be provided.

[0056] Note that the effects of one aspect of the present invention are not limited to those described above. The above-described effects do not preclude the existence of other effects. Furthermore, other effects are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description, drawings, etc. Additionally, one aspect of the present invention has at least one of the above-described effects and other effects. Therefore, one aspect of the present invention may sometimes lack the effects listed above, depending on the circumstances. Attached Figure Description

[0057] Figure 1This is a circuit diagram showing an example of the structure of an arithmetic device including arithmetic circuits and drive circuits. Figures 2A to 2C This is a circuit diagram showing an example of the structure of the circuits included in the drive circuit. Figures 3A to 3D This is a circuit diagram showing an example of the structure of the circuits included in the drive circuit. Figure 4 This is a circuit diagram showing an example of the structure of the circuits included in the drive circuit. Figures 5A to 5C This is a circuit diagram showing an example of the structure of the circuits included in the drive circuit. Figure 6 This is a circuit diagram showing an example of the structure of the circuits included in the drive circuit. Figure 7 This is a timing diagram illustrating an example of the operation of a computing device. Figures 8A to 8C This is a circuit diagram showing an example of the structure of an operational circuit. Figure 9 This is a circuit diagram showing an example of the structure of an operational circuit. Figure 10A and Figure 10B This is a circuit diagram showing an example of the structure of an operational circuit. Figure 11 This is a circuit diagram showing an example of the structure of an operational circuit. Figure 12 This is a planar schematic diagram illustrating an example of the structure of an operational circuit. Figure 13 This is a planar schematic diagram illustrating an example of the structure of an operational circuit. Figure 14 This is a planar schematic diagram illustrating an example of the structure of an operational circuit. Figure 15 This is a circuit diagram showing an example of the structure of an arithmetic device including arithmetic circuits and drive circuits. Figure 16 This is a circuit diagram showing an example of the structure of an arithmetic device including arithmetic circuits and drive circuits. Figure 17 This is a circuit diagram showing an example of the structure of the circuits included in the drive circuit. Figure 18 This is a circuit diagram showing an example of the structure of the circuits included in the drive circuit. Figure 19 This is a timing diagram illustrating an example of the operation of the circuitry included in the drive circuit. Figure 20 This is a diagram illustrating an example of a convolutional neural network. Figure 21 This is a diagram illustrating an example of convolution processing. Figure 22 This is a diagram illustrating an example of convolution processing. Figure 23 This is a block diagram illustrating a working example of convolution processing in a computing device. Figure 24 This is a block diagram illustrating a working example of convolution processing in a computing device. Figure 25A and Figure 25B This is a diagram illustrating an example of pooling processing. Figure 26 This is a three-dimensional schematic diagram showing an example of the structure of a computing device. Figure 27 This is a block diagram illustrating an example of the structure of a computing device. Figure 28 This is a cross-sectional schematic diagram showing an example of the structure of a computing device. Figure 29A and Figure 29B This is a cross-sectional schematic diagram showing an example of a transistor structure. Figure 30A This is a planar schematic diagram showing an example of a transistor structure. Figures 30B to 30D This is a cross-sectional schematic diagram showing an example of a transistor structure. Figures 31A to 31C This is a cross-sectional schematic diagram showing an example of a transistor structure. Figure 32 This is a cross-sectional schematic diagram showing an example of the structure of a computing device. Figure 33A This is a planar schematic diagram showing an example of a transistor structure. Figure 33B and Figure 33C This is a cross-sectional schematic diagram showing an example of a transistor structure. Figure 33D This is a three-dimensional schematic diagram showing an example of a transistor structure. Figure 34A This is a cross-sectional schematic diagram showing an example of the structure of a capacitor that can be used in a computing device. Figure 34B This is a plan view illustrating an example of the structure of a capacitor that can be used in a computing device. Figure 35 This is a schematic diagram illustrating the hierarchy of storage devices. Figures 36A to 36D This is a diagram showing an example of an electronic component. Figure 37A and Figure 37B This is a diagram illustrating an example of an electronic device. Figure 37C This is a diagram illustrating an example of a large computer. Figure 38 This is a diagram illustrating an example of a space device. Figure 39 This is a diagram illustrating an example of a storage system that can be used in a data center. Figure 40A and Figure 40B This is a circuit diagram illustrating the circuit structure of an operational circuit used for simulation according to an embodiment. Figures 41A to 41C This is a graph illustrating the retention characteristics of the operational circuit obtained through simulation according to an embodiment. Figure 42 This is a graph illustrating the multiplication characteristics of an arithmetic circuit obtained through simulation according to an embodiment. Figure 43 This is a graph illustrating the multiplication characteristics of the arithmetic circuit according to an embodiment. Figure 44 This is a graph illustrating the holding characteristics of the operational circuit according to an embodiment. Figure 45A It is taking photographs of a bare die including a semiconductor device according to an embodiment. Figure 45B It is a cross-sectional photograph of a semiconductor device. Figure 46 This is a block diagram illustrating a structural example of a semiconductor device according to an embodiment. Figure 47A and Figure 47B This is a circuit diagram illustrating an example of the structure of a circuit in a semiconductor device according to an embodiment. Figure 48A and Figure 48B This is a circuit diagram illustrating an example of the structure of a circuit in a semiconductor device according to an embodiment. Figure 49 This is a circuit diagram illustrating an example of the structure of a circuit in a semiconductor device according to an embodiment. Figure 50A This is a graph illustrating the input / output characteristics of the DAC according to an embodiment. Figure 50B This is a graph illustrating the input / output characteristics of the circuit according to an embodiment. Figure 51 This is a graph illustrating the input-output characteristics of a SAR-type ADC according to an embodiment. Figure 52 This is a graph illustrating the multiplication operation characteristics of the arithmetic unit according to an embodiment. Figure 53A A graph showing the relationship between the expected value of the current resulting from the multiplication operation of the arithmetic unit according to an embodiment and the difference between the expected value and the measured value. Figure 53B This is a graph showing the relationship between the expected value and the measured value of the current resulting from the multiplication operation of the arithmetic unit according to an embodiment. Figure 54 It is a histogram showing the distribution of the difference between the expected value and the measured value of the current resulting from the multiplication operation of the arithmetic unit. Figure 55This is a graph showing the deviation range of the current from the multiplication result of the arithmetic unit according to an embodiment. Figure 56A This is a graph showing the relationship between measured values ​​and expected values ​​of the computational results of the semiconductor device according to an embodiment. Additionally, Figure 56B It is a histogram showing the distribution of the difference between the measured value and the expected value of the computational result of the semiconductor device according to the embodiment. Figure 57A This is a graph showing the dependence of power consumption and inference accuracy on inference time when performing inference in a semiconductor device according to an embodiment. Figure 57B This is a graph showing the changing accuracy of inferences based on the embodiments. Figure 57C This is a graph showing the power consumption of a semiconductor device according to an embodiment. Figure 58 This is a graph showing the results of the computational accuracy of the semiconductor device according to an embodiment. Figures 59A1 to 59A7 and Figures 59B1 to 59B6 It is a circuit diagram used to illustrate electrical connections. Detailed Implementation

[0058] (Notes regarding this instruction manual) In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as a circuit that includes semiconductor elements (e.g., transistors, diodes, and photodiodes) and a device that includes such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. An integrated circuit can be cited as an example of a semiconductor device. A chip incorporating an integrated circuit can also be cited as an example of a semiconductor device. An electronic component housing a chip in a package can also be cited as an example of a semiconductor device. Additionally, for example, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are sometimes semiconductor devices themselves, or sometimes include semiconductor devices.

[0059] In this specification, “connection” includes, for example, “electrical connection”.

[0060] When the connection relationship of circuit elements is represented as an "electrical connection" to define an object, "electrical connection" includes, for example, "direct connection" and "indirect connection". "A and B directly connected" means, for example, that A and B are connected without passing through circuit elements (such as transistors or switches; note that wiring is not a circuit element). On the other hand, "A and B indirectly connected" means, for example, that A and B are connected through more than one circuit element. Note that A, B, and C (described later) represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0061] Here, the definition of "A and B are indirectly connected" refers to the following connection relationship: That is, when assuming the circuit is operating, if there is a sequence of electrical signal exchange or potential interaction between A and B during circuit operation, such a circuit can be defined as "A and B are indirectly connected." Furthermore, even if there is no sequence of electrical signal exchange or potential interaction between A and B, if there is a sequence of electrical signal exchange or potential interaction between A and B during circuit operation, it can still be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating due to the lack of a power supply voltage, the circuit can still be defined as "A and B are indirectly connected" (note that, as an example, this is limited to the case where electrical signal exchange or potential interaction occurs between A and B during circuit operation when the circuit is operating due to a power supply voltage).

[0062] The following are specific examples of "indirect connection". First, as an example of "A and B are indirectly connected", the following can be given: Figure 59A1 and Figure 59A2 Examples of "indirect connection between A and B" include cases where A and B are connected via the source and drain of one or more transistors. Other examples of "indirect connection between A and B" include cases where A and B are connected via one or more switches. In the case of "indirect connection between A and B," assuming the circuit is operational, at least once a transistor between A and B is in an on-state, a conducting state, or a state where current can flow. Additionally, the case of "indirect connection between A and B" includes cases where one transistor between A and B is in an off-state or a non-conducting state. In the case of "indirect connection between A and B," when multiple transistors are connected between A and B, assuming the circuit is operational, at least once each of the multiple transistors between A and B is in an on-state, a conducting state, or a state where current can flow. That is, in the case of "indirect connection between A and B," multiple transistors do not necessarily need to be in an on-state, a conducting state, or a state where current can flow simultaneously. Therefore, the case of "indirect connection between A and B" includes cases where multiple transistors between A and B are in an off-state or a non-conducting state simultaneously or at different times. As other examples, such as Figure 59A3As shown, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that, as described below, when a fixed potential V is supplied to C from the power supply or GND, etc., although it can be said that "A and C are indirectly connected" or "B and C are indirectly connected", it is not possible to say that "A and B are indirectly connected".

[0063] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples show situations where "indirect connection" cannot be described. Even when electrical signals are exchanged or potentials interact between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of this exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, "A and B are indirectly connected" cannot be described. Specific examples of A and B being connected through an insulator include... Figure 59A4 The case shown is where a capacitor is connected between A and B. Other examples of cases where A and B are connected through an insulator include... Figure 59A5 As shown, sometimes the gate insulating film of a transistor is sandwiched between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected".

[0064] As another example of why it's inappropriate to say "A and B are indirectly connected," cases where there is no timing sequence of electrical signal exchange or potential interaction between A and B. Examples include... Figure 59A6 and Figure 59A7 As shown, sometimes multiple transistors are connected through their source and drain along the path from A to B, and a fixed potential V is supplied to the nodes between the transistors from the power supply or GND. In this case, although it cannot be said that "A and B are indirectly connected," it can be said that "A and V are indirectly connected" or "B and V are indirectly connected." Figure 59A3 In the case where A and C are connected through the source and drain of transistor TrP, and B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from the power supply or GND, etc., it has the same characteristics as... Figure 59A6 and Figure 59A7 Since they have the same connection relationship, we cannot say "A is indirectly connected to B" but we can say "A is indirectly connected to C" or "B is indirectly connected to C".

[0065] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0066] Next, specific examples of the "direct connection" case are shown. As an example of the case where "A and B are directly connected," such as... Figure 59B1 , Figure 59B2 and Figure 59B3 In that case, sometimes A and B are not connected through circuit components. Additionally, as... Figure 59B4 and Figure 59B5 Therefore, when A and B are connected without circuit elements by a power supply of a fixed potential V or GND, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Additionally, as... Figure 59B6 As shown, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected". However, since A and V or B and V are connected through the source and drain of a transistor, it cannot be said that they are directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected".

[0067] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0068] Furthermore, even when independent components are connected to each other in a circuit diagram, sometimes one component can function as multiple components. For example, when a portion of a wiring is used as an electrode, a conductive film functions as both a wiring and an electrode. Therefore, the term "connection" in this specification also includes such cases where a conductive film functions as multiple components.

[0069] In this specification, etc., "resistor" can be, for example, a circuit element having a resistance value greater than 0Ω or a wiring having a resistance value greater than 0Ω. Therefore, in this specification, "resistor" includes wiring with a resistance value, a transistor, diode, or coil through which current flows between the source and drain. Therefore, "resistor" can sometimes be referred to as "resistor," "load," or "area with a resistance value." In contrast, "resistor," "load," or "area with a resistance value" can sometimes be referred to as "resistor." As for the resistance value, it is preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Alternatively, it can be, for example, 1Ω or more and 1×10⁻⁶. 9 Below Ω.

[0070] In this specification, etc., "capacitor" can refer to, for example, a circuit element having an electrostatic capacitance value higher than 0F, a wiring area having an electrostatic capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. Additionally, "capacitor," "parasitic capacitance," or "gate capacitance" can sometimes be referred to simply as "capacitor." Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) comprises an insulator and a pair of conductors clamping the insulator. Thus, the "pair of conductors" of a "capacitor" can be referred to as a "pair of electrodes," a "pair of conductive regions," a "pair of regions," or a "pair of terminals." Additionally, "one of the pair of terminals" and "the other of the pair of terminals" are sometimes referred to as the first terminal and the second terminal, respectively. Furthermore, the electrostatic capacitance value can be, for example, 0.05fF or more and 10pF or less. Additionally, for example, it can be 1pF or more and 10μF or less.

[0071] In addition, in this specification, a switch refers to a component that controls whether current flows by changing to an on or off state. Alternatively, a switch refers to a component that selects and switches the current path.

[0072] In this specification, "conducting state" refers to a state in which current may flow between the two input / output terminals, and "non-conducting state" refers to a state in which the two input / output terminals are electrically disconnected. Furthermore, in this specification, the open state of a switch falls within the category of "conducting state," and the closed state falls within the category of "non-conducting state." Therefore, in this specification, the "conducting state" and "open state" of the switch can be interchanged, as can the "non-conducting state" and "closed state."

[0073] Furthermore, switches sometimes include two or more terminals besides the control terminals, allowing current to flow through. As an example, electrical switches or mechanical switches can be used. In other words, a switch is not limited to a specific component as long as it has the function of controlling current.

[0074] Examples of electrical switches include transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, MIS (Metal-insulator-semiconductor) diodes, or diode-connected transistors), or logic circuits that combine these components. When a transistor is used as a switch, the "on state" or "turn-on state" of a transistor refers, for example, to the state where current can flow between the source and drain electrodes of the transistor. Conversely, the "off state" or "turn-off state" of a transistor refers to the state where the source and drain electrodes of the transistor are electrically disconnected. When a transistor is used solely as a switch, there are no particular restrictions on the transistor's polarity (conduction type).

[0075] As an example of a mechanical switch, a switch utilizing MEMS (microelectromechanical systems) technology can be cited. This switch has mechanically movable electrodes, and operates by controlling the on and off states through the movement of these electrodes.

[0076] In this specification, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the switching between the transistor's on and off states. The two terminals used as the source or drain are the transistor's input and output terminals. Depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to the three terminals, one of the two input / output terminals is used as the source and the other as the drain. Therefore, in this specification, the source and drain may sometimes be interchanged. In this specification, when describing the transistor's connection relationship, the terms "one of the source and drain" and "the other of the source and drain" are used. In this specification, sometimes one of the source and drain is referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other is referred to as the "second electrode of the transistor" or "second terminal of the transistor." Furthermore, depending on the transistor's structure, sometimes a back gate is included in addition to the three terminals mentioned above. In this case, in this specification, sometimes one of the transistor's gate and back gate is referred to as the first gate, and the other is referred to as the second gate. Furthermore, in the same transistor, the "gate" and "back gate" can sometimes be interchanged. Additionally, when a transistor includes three or more gates, in this specification and other materials, each gate is sometimes referred to as the first gate, the second gate, the third gate, etc.

[0077] For example, as described in this specification, a multi-gate transistor with two or more gate electrodes can be used as an example of a transistor. When a multi-gate structure is used, since the channel forming regions are connected in series, it becomes a structure in which multiple transistors are connected in series. Therefore, by utilizing a multi-gate structure, the off-state current can be reduced, and the transistor's voltage withstand capability (reliability) can be improved. Alternatively, by utilizing a multi-gate structure, when the transistor is operating in the saturation region, even if the voltage between the drain and source changes, the change in the drain and source current is not significant, thus obtaining a flat voltage-current characteristic. When a flat voltage-current characteristic is used, an ideal current source circuit or an active load with extremely high resistance can be realized. As a result, differential circuits or current mirror circuits with good characteristics can be realized.

[0078] Furthermore, a circuit diagram illustrating a single circuit element sometimes includes cases where that circuit element comprises multiple circuit elements. For example, a circuit diagram illustrating a resistor may include cases where two or more resistors are connected in series. Similarly, a circuit diagram illustrating a capacitor may include cases where two or more capacitors are connected in parallel. Likewise, a circuit diagram illustrating a transistor may include cases where two or more transistors are connected in series and their gates are connected to each other. Likewise, a circuit diagram illustrating a switch may include cases where the switch comprises two or more transistors connected in series or in parallel and their gates are connected to each other.

[0079] In addition, in this specification and other documents, nodes may also be referred to as terminals, wiring, electrodes, conductive layers, conductors, impurity regions, etc., depending on the circuit structure and device structure. Furthermore, terminals and wiring may also be referred to as nodes.

[0080] Furthermore, in this instruction manual and other documents, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference between the reference potential and a ground potential. For example, when the reference potential is ground potential (grounding potential), "voltage" may also be referred to as "potential." Ground potential does not necessarily mean 0V. Additionally, potential is relative; the potential supplied to wiring, the potential applied to circuits, and the potential output from circuits also change according to changes in the reference potential.

[0081] Furthermore, in this specification and other materials, "high-level potential" and "low-level potential" do not imply specific potentials. For example, when two wires are both labeled as "wires used to supply a high-level potential," the high-level potentials supplied to the two wires may sometimes be different. Similarly, when two wires are both labeled as "wires used to supply a low-level potential," the low-level potentials supplied to the two wires may sometimes be different.

[0082] Furthermore, "current" refers to the phenomenon of charge migration (conductivity). For example, the description "conductivity occurs in a positively charged body" can be replaced with the description "conductivity occurs in a negatively charged body in the opposite direction." Therefore, in this specification, unless otherwise stated, "current" refers to the phenomenon of charge migration (conductivity) during charge carrier migration. Here, examples of charge carriers include electrons, holes, anions, cations, and complex ions, depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). Additionally, the "direction of current" in wiring, etc., refers to the direction of migration of positively charged charge carriers and is described as a positive current quantity. In other words, the direction of migration of negatively charged charge carriers is opposite to the direction of current and is described as a negative current quantity. Therefore, in this specification, unless otherwise stated, regarding the positive or negative (or direction) of the current, the description "current flows from element A to element B" can be replaced with the description "current flows from element B to element A." Furthermore, the description "current is input to element A" can be replaced with the description "current is output from element A."

[0083] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Additionally, these ordinal numbers do not limit the order of the constituent elements. For example, in this specification and other documents, a "first" constituent element in one embodiment may be referred to as a "second" constituent element in other embodiments or claims. Furthermore, for example, in this specification and other documents, a constituent element referred to by "first" in one embodiment may be omitted in other embodiments or claims.

[0084] In this specification and other materials, for convenience, terms such as "upper" and "lower" are sometimes used to indicate the arrangement of components in conjunction with the accompanying drawings. Furthermore, the positional relationships of the components may be appropriately changed depending on the orientation in which each component is described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately changed as needed. For example, if the description is "an insulator located on the top surface of a conductor," it can be changed to "an insulator located on the bottom surface of a conductor" by rotating the orientation of the shown drawings by 180°.

[0085] Furthermore, terms like "above" or "below" are not limited to situations where the constituent elements are directly above or below each other and in direct contact. For example, if the expression is "electrode B on insulating layer A," it is not necessarily required that electrode B is formed directly in contact with insulating layer A; it could also include situations where other constituent elements are included between insulating layer A and electrode B. Similarly, for example, if the expression is "electrode B above insulating layer A," it is not necessarily required that electrode B is formed directly in contact with insulating layer A; it could also include situations where other constituent elements are included between insulating layer A and electrode B. Likewise, for example, if the expression is "electrode B below insulating layer A," it is not necessarily required that electrode B is formed directly in contact below insulating layer A; it could also include situations where other constituent elements are included between insulating layer A and electrode B.

[0086] Furthermore, in this specification and other materials, terms such as "row" and "column" are sometimes used to describe the matrix-like configuration of constituent elements and their positional relationships. Additionally, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately changed as needed. For example, by rotating the orientation of the accompanying drawings by 90°, the expression "row direction" may sometimes be replaced with "column direction."

[0087] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged depending on the context. For example, "conductive layer" may sometimes be replaced with "conductive film." Also, "insulating film" may sometimes be replaced with "insulating layer." Additionally, depending on the situation, other terms may be used instead of "film" and "layer." For example, "conductive layer" or "conductive film" may sometimes be replaced with "conductor." Also, for example, "insulating layer" or "insulating film" may sometimes be replaced with "insulator."

[0088] Note that in this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as one unit. Additionally, for example, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where one or more of "electrode," "wiring," and "terminal" are formed as one unit. Therefore, for example, an "electrode" can be part of "wiring" or "terminal," and vice versa. Furthermore, the terms "electrode," "wiring," or "terminal" are sometimes replaced with terms such as "area," depending on the context.

[0089] In this instruction manual, etc., depending on the circumstances or situation, "wiring," "signal line," or "power line," etc., can be interchanged. For example, sometimes "wiring" can be changed to "signal line." Also, sometimes "wiring" can be changed to "power line." Conversely, sometimes "signal line" or "power line," etc., can be changed to "wiring." Sometimes "power line," etc., can be changed to "signal line." Conversely, sometimes "signal line," etc., can be changed to "power line," etc. Furthermore, depending on the circumstances or situation, sometimes the "potential" applied to the wiring can be changed to "signal." Conversely, sometimes "signal" can be changed to "potential."

[0090] Furthermore, in this specification and other documents, timing diagrams are sometimes used to illustrate the operation of semiconductor devices. The timing diagrams used in this specification and other documents show ideal operating examples and, unless otherwise stated, are not limited to the periods, signal (e.g., potential or current) magnitudes, and timing shown in the timing diagram. In the timing diagrams of this specification and other documents, the magnitudes and timing of signals (e.g., potential or current) input to each wiring (including nodes) in the timing diagram can be changed depending on the situation. For example, even if two periods are shown at equal intervals in the timing diagram, the lengths of the two periods may sometimes be different. Also, for example, even if one period is shown to be longer than the other, the lengths of the two periods may sometimes be the same, or sometimes one period may be shorter than the other. Additionally, to clearly illustrate the timing diagram, sometimes overlapping signals are intentionally staggered in the illustration.

[0091] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form the channel formation region of a transistor that has at least one of amplification, rectification, and switching functions, the metal oxide can be called a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0092] In addition, in this specification and other materials, metal oxides containing nitrogen are sometimes referred to as metal oxides. Furthermore, metal oxides containing nitrogen are sometimes referred to as metal oxynitrides.

[0093] Furthermore, in this specification, impurities in a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 at.% are considered impurities. When impurities are present, one or more of the following may occur: increased defect state density, decreased carrier mobility, and decreased crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, particularly, for example, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0094] In this specification, "parallel" refers to two straight lines arranged at an angle of -10° to 10°. Therefore, it also includes situations where the angle is -5° to 5°. "Approximately parallel" refers to two straight lines arranged at an angle of -30° to 30°. Furthermore, "perpendicular" refers to two straight lines arranged at an angle of 80° to 100°. Therefore, it also includes situations where the angle is 85° to 95°. "Approximately perpendicular" or "approximately perpendicular" refers to two straight lines forming an angle of 60° to 120°.

[0095] Furthermore, the structures shown in each embodiment in this specification and other documents can be appropriately combined with structures shown in other embodiments to constitute a mode of the present invention. Additionally, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0096] Additionally, the content described in one embodiment can be applied / combined / replaced with other content described in that embodiment and at least one content described in other embodiments.

[0097] Note that the content described in the embodiments refers to the content illustrated using various accompanying drawings or the content described using the text in the specification.

[0098] Furthermore, more figures can be formed by combining the figures shown in one embodiment with other parts of the figures and at least one figure shown in one or more other embodiments.

[0099] The embodiments described in this specification are illustrated with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. In perspective views, etc., illustrations of some constituent elements are sometimes omitted for clarity.

[0100] In this specification and other materials, when multiple constituent elements use the same symbol and it is necessary to distinguish them, symbols such as "_1", "[n]", and "[m,n]" are sometimes added to the symbol for identification. Furthermore, in the accompanying drawings and other materials, when symbols such as "_1", "[n]", and "[m,n]" are added to the symbol for identification, if it is not necessary to distinguish them in this specification or other materials, these symbols are sometimes omitted.

[0101] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples and are not limited to the shapes or values ​​shown. For example, deviations in signals, voltages, or currents caused by noise or timing skew may be included.

[0102] (Implementation Method 1) In this embodiment, the operational circuit of a semiconductor device as one aspect of the present invention will be described.

[0103] <Example 1 of the structure of an arithmetic device> This operational circuit is capable of holding a multiplier and performing multiplication of the multiplier with the input multiplicands. In particular, the operational circuit can hold the multiplier for an extended period. Therefore, the operational circuit can sequentially perform multiplication of a multiplier with each of multiple multiplicands by sequentially inputting multiplicands while holding the multiplier.

[0104] As described above, a convolutional neural network (CNN) is an example of an artificial neural network that performs a multiplication operation between a multiplier and each of multiple multiplicands. The CNN will be described in detail in Embodiment 2, where, as an example, a multiplication operation is performed between a filter containing a certain feature and image data. In particular, since the CNN performs a multiplication operation between a filter feature (which is the multiplier) and multiple image data (which are the multiplicands), it is preferable to use the aforementioned operational unit to perform this multiplication operation.

[0105] Note that in this specification, the multiplier is referred to as the first number, and each of the multiple multiplicands is referred to as the second number. Note that the multiplier and multiplicands can be interchanged according to the commutative property of multiplication. For example, the multiplier can also be referred to as the second number, and each of the multiple multiplicands can be referred to as the first number.

[0106] Figure 1 An example of a computing device CDV as one aspect of the present invention is shown. The computing device CDV is a computing device capable of performing multiplication of first data and second data, wherein the first data and the second data are 0 or positive numbers. Additionally, as... Figure 1 As shown, the computing device CDV includes a computing circuit CC, a driving circuit WCD, a driving circuit XCD, a driving circuit WSD, and a driving circuit ITS.

[0107] The arithmetic circuit CC includes, for example, an arithmetic unit IM and a driving unit IMD. Furthermore, the arithmetic unit IM includes, for example, transistors M1 to M3, capacitors C1 and C2, and an amplifier circuit SF. Additionally, the driving unit IMD includes, for example, transistors M1d to M3d, capacitors C1d and C2d, and an amplifier circuit SFd.

[0108] In addition, both amplifier circuits SF and SFd include a terminal Sin used as an input terminal and a terminal Sout used as an output terminal.

[0109] In the arithmetic unit IM, transistors M1 and M2 are used as switching transistors, for example. Additionally, transistor M3 is used as a transistor that outputs the result of the multiplication operation between the multiplier and the multiplicand (sometimes referred to as an amplifying transistor).

[0110] Furthermore, in the drive unit IMD, transistors M1d and M2d are used as write transistors, for example. Also, like transistor M3, transistor M3d is used as an amplification transistor.

[0111] Note that in the operational circuit CC, transistors M1, M2, M1d, and M2d, which are sometimes used as switching transistors, are referred to as write transistors or hold transistors.

[0112] Especially in the operational circuit CC, unless otherwise stated, transistors M1, M2, M1d, and M2d operating in the saturation region when in the ON state include the case where they ultimately operate in the linear region. In other words, this includes situations where the gate, source, and drain voltages of the aforementioned transistors are appropriately biased so that the transistor operates in the linear region. Note that one aspect of the invention is not limited to this. For example, one or two of transistors M1, M2, M1d, and M2d may operate in the saturation region when in the ON state, or may sometimes operate in the linear region and sometimes in the saturation region.

[0113] Furthermore, in the operational circuit CC, unless otherwise stated, this includes the case where transistors M3 and M3d operate in the subthreshold region (in other words, in transistor M3 or M3d, the gate-source voltage is lower than the threshold voltage, and more preferably, the drain current increases exponentially with respect to the gate-source voltage). In other words, this includes the case where the gate, source, and drain voltages of each of the aforementioned transistors are appropriately biased so that the transistor operates in the subthreshold region. Therefore, this includes the case where transistors M3 and M3d operate with off-state current (sometimes called leakage current) flowing between the source and drain.

[0114] Note that in Figure 1 In the operational circuit CC, transistors M1 to M3 and transistors M1d to M3d are preferably, for example, OS transistors. In particular, the metal oxide used as the channel forming region of the OS transistor can be, for example, indium oxide, gallium oxide, and zinc oxide. Furthermore, the metal oxide preferably contains one or more selected from indium, element M, and zinc. Element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, element M is preferably selected from one or more of aluminum, gallium, yttrium, and tin.

[0115] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also denoted as IGZO) is preferred. Alternatively, an oxide containing indium, tin, and zinc (also denoted as ITZO (registered trademark)) is preferred. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferred. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also denoted as IAZO) is preferred. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also denoted as IAGZO) is preferred. Note that the OS transistor is described in detail in Embodiment 3.

[0116] Furthermore, the metal oxide contained in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer having a two-layer structure with a first layer and a second layer located directly above the first layer. The atomic ratio of element M, relative to the main component metal element, in the metal oxide used in the first layer is preferably greater than the atomic ratio of element M, relative to the main component metal element, in the metal oxide used in the second layer. Additionally, the atomic ratio of element M, relative to In, in the metal oxide used in the first layer is preferably greater than the atomic ratio of element M, relative to In, in the metal oxide used in the second layer. By employing this structure, the diffusion of impurities and oxygen from the structure formed beneath the first layer to the second layer can be suppressed.

[0117] Furthermore, the ratio of In atoms relative to element M in the metal oxide used in the second layer is preferably greater than the ratio of In atoms relative to element M in the metal oxide used in the first layer. By employing this structure, the OS transistor can achieve large on-state current and high-frequency characteristics.

[0118] Specifically, for example, as the metal oxide used for the first layer, metal oxides with an In:M:Zn ratio of 1:3:2 or similar, an In:M:Zn ratio of 1:3:4 or similar, or an In:M:Zn ratio of 1:1:0.5 or similar can be used. Furthermore, as the metal oxide used for the second layer, metal oxides with an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:2 or similar, or an In:M:Zn ratio of 4:2:3 or similar can be used. Note that "similar" includes a range of ±30% of the desired atomic ratio.

[0119] To reduce the off-state current of transistors, IGZO is preferably used as the metal oxide for the semiconductor layer. When the semiconductor layer of the transistor contains IGZO, the current flowing through each channel width of 1 μm between the source and drain when the gate-source voltage is 0V is 1 × 10⁻⁶ at room temperature (e.g., 25°C). -20 Below A, at 85℃, it is 1×10 -18 Below A, or 1×10 at 125℃ -16 Below A. Furthermore, as described above, in this specification, the condition where the current flowing between the source and drain of a transistor is extremely small when the voltage between the gate and source is 0V is referred to as normally off.

[0120] In particular, for example, by using transistors with the aforementioned oxide contained in the semiconductor layer as transistors M1, M2, M1d, and M2d, the off-state current of transistors M1, M2, M1d, and M2d can be made extremely small. As described above, transistors M1 and M2 are both used as write transistors in the arithmetic unit IM, and transistors M1d and M2d are both used as write transistors in the drive unit IMD. Therefore, it is preferable to use OS transistors with extremely small off-state currents as transistors M1, M2, M1d, and M2d.

[0121] Furthermore, for example, by using transistors with the aforementioned oxide contained in the semiconductor layer as transistors M3 and M3d, the subthreshold current can be reduced. This reduces the amount of current flowing between the source and drain of transistor M3 or M3d, thereby reducing the power consumption of the computing device CDV.

[0122] For example, when OS transistors are used as transistors M3 and M3d, the subthreshold current per channel width of 1 μm can be, for example, 1.0 × 10⁻⁶. -8 A (1.0×10 -2 μA and below, 1.0×10 -12 A (1.0 pA) or less or 1.0 × 10 -15 Below A (1.0fA). In particular, when the threshold voltage of these transistors is above 0V, the subthreshold current per 1μm channel width can, for example, range from 1.0 × 10⁻⁶. -20 A (10zA) or higher and 1.0 × 10 -8 A (1.0×10 -2 μA and below, 1.0×10 -20 A (10zA) or higher and 1.0 × 10 -12 A (1.0 pA) or less or 1.0 × 10 -20 A (10zA) or higher and 1.0 × 10 -15 Below A (1.0fA). Therefore, by using OS transistors as transistors M3 and M3d, the range of currents that can be output as the result of multiplication operations in the arithmetic circuit CC can be expanded. Strictly speaking, the range in which the drain current increases exponentially with respect to the gate-source voltage within the aforementioned subthreshold current range is the range of currents that can be output as the result of multiplication operations in the arithmetic circuit CC.

[0123] For example, if both the multiplier and multiplicand are set to 0 or higher and 64 or lower, and the current when the multiplier or multiplicand is 1 is set to 0.03 nA, the range of the output current of the multiplication result that the transistor should ensure is 0 or higher and 3.7 nA or lower, which can be included in the range of the subthreshold current mentioned above.

[0124] In addition to OS transistors, transistors M1 to M3 and M1d to M3d can also be transistors with silicon contained in the channel formation region (hereinafter referred to as Si transistors). Si transistors have a larger on-state current than OS transistors, so they are suitable for carrying large currents.

[0125] In addition, as transistors M1 to M3 and transistors M1d to M3d, besides OS transistors and Si transistors, transistors containing germanium in the channel forming region, transistors containing compound semiconductors such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in the channel forming region, transistors containing carbon nanotubes in the channel forming region, or transistors containing organic semiconductors in the channel forming region can be used.

[0126] Note that in Figure 1 In this specification, transistors M1 to M3 and transistors M1d to M3d are all n-channel transistors, but they can also be replaced with p-channel transistors depending on the situation. Furthermore, in this case, the potentials supplied to the operational circuit CC may differ from those when using n-channel transistors. In this specification, unless otherwise stated, it is assumed that transistors M1 to M3 and transistors M1d to M3d are all n-channel transistors.

[0127] In the operational unit IM, the first terminal of transistor M1 is connected to the gate of transistor M3, the Sin terminal of amplifier circuit SF, and the first terminal of capacitor C1. The second terminal of transistor M1 is connected to the first terminal of transistor M2, the Sout terminal of amplifier circuit SF, and the first terminal of capacitor C2. Furthermore, the first terminal of transistor M3 and the second terminal of transistor M2 are connected to wiring WCL, and the gates of transistors M1 and M2 are connected to wiring WSL. Additionally, the second terminal of capacitor C1 is connected to wiring XCL.

[0128] The second terminal of capacitor C2 is connected to wiring VEG. Additionally, the second terminal of transistor M3 is connected to wiring VEL.

[0129] In addition, in this specification, the connection point of the first terminal of transistor M1, the gate of transistor M3, the first terminal of capacitor C1 and the terminal Sin of amplifier circuit SF is called node N, and the connection point of the second terminal of transistor M1, the first terminal of transistor M2, the first terminal of capacitor C2 and the terminal Sout of amplifier circuit SF is called node Nm.

[0130] Furthermore, in the driving unit IMD, the first terminal of transistor M1d is connected to the gate of transistor M3d, the first terminal of capacitor C1d, and the Sin terminal of amplifier circuit SFd; the second terminal of transistor M1d is connected to the first terminal of transistor M2d, the first terminal of capacitor C2d, and the Sout terminal of amplifier circuit SFd. Additionally, the first terminal of transistor M3d, the second terminal of transistor M2d, and the second terminal of capacitor C1d are connected to wiring XCL, and the gates of transistors M1d and M2d are connected to wiring WSL.

[0131] The second terminal of capacitor C2d is connected to wiring VEG. Additionally, the second terminal of transistor M3d is connected to wiring VEL.

[0132] In addition, in this specification, the connection point of the first terminal of transistor M1d, the gate of transistor M3d, the first terminal of capacitor C1d, and the terminal Sin of amplifier circuit SFd is referred to as node Nd, and the connection point of the second terminal of transistor M1d, the first terminal of transistor M2d, the first terminal of capacitor C2d, and the terminal Sout of amplifier circuit SFd is referred to as node Nmd.

[0133] Both amplifier circuits SF and SFd have the function of outputting a potential to the terminal Sout that is approximately equal to the potential input to the terminal Sin. In other words, amplifier circuits SF and SFd are used as buffer circuits for the output analog potential. For example, a source follower or voltage follower can be used as a buffer circuit for the output analog potential.

[0134] The driver circuit WCD is connected to the wiring circuits WCL and IWL. Additionally, the driver circuit ITS is connected to the wiring circuits IWL and OL. Furthermore, the driver circuit XCD is connected to the wiring circuits XCL and IXL. Finally, the driver circuit WSD is connected to the wiring circuit WSL.

[0135] As an example, the wiring WCL is used to supply the current corresponding to the first data to the arithmetic unit IM. Note that this current is generated by the drive circuit WCD, which will be explained in detail later.

[0136] As an example, the wiring XCL is used to supply the current corresponding to the reference data or the current corresponding to the second data to the arithmetic unit IM and the drive unit IMD. Note that the aforementioned currents are all generated by the drive circuit XCD, which will be explained in detail later. Additionally, the reference data will be explained later.

[0137] As an example, the wiring WSL is used to transmit the selection signal for the arithmetic unit IM, which selects the object to be written with the first data. Additionally, this selection signal is also sent to the driver unit IMD. Note that the selection signal is generated by the driver circuit WSD, which will be explained in detail later.

[0138] The VEG wiring is used as a wiring to supply a fixed potential. Specifically, the VEG wiring is used to supply this fixed potential to the second terminals of capacitors C2 and C2d. Thus, when nodes Nm and Nmd are in a floating state, the potentials of nodes Nm and Nmd can be maintained. This fixed potential can be, for example, a low-level potential, a ground potential, a negative potential, etc.

[0139] As an example, wiring VEL is used as a wiring to supply a fixed potential. Specifically, wiring VEL is used as a wiring to supply the fixed potential to the second terminals of transistors M3 and M3d. In particular, the fixed potential is the potential within the range driven by transistors M3 and M3d in the subthreshold region. Specifically, the fixed potential can be, for example, a low-level potential, a ground potential, a negative potential, etc. Alternatively, depending on the situation, the fixed potential can be a high-level potential, a positive potential, etc.

[0140] The driver circuit WCD is used as a driver circuit to write first data to the arithmetic unit IM. Specifically, the driver circuit WCD, for example, has the function of acquiring the first data W and converting it into an analog potential for output to the wiring WCL. This first data W is digital data read from external circuits such as storage devices and control circuits. Note that in Figure 1 In the process, the first data W is sent by the wiring IWL.

[0141] like Figure 1 As shown, the drive circuit WCD includes, for example, a circuit WCDa and a switch SA. The output terminal of the circuit WCDa is connected to the first terminal of the switch SA, and the second terminal of the switch SA is connected to wiring WCL. Additionally, the control terminal of the switch SA is connected to wiring SWLA.

[0142] As the switch SA, analog switches and transistors can be used, for example. In particular, transistors are preferred as the switch SA, and OS transistors are especially preferred. Note that when using an electrical switch as the switch SA, in addition to OS transistors, Si transistors can also be used as the switch. Alternatively, mechanical switches can also be used as the switch SA, for example.

[0143] Note that in this instruction manual, etc., Figure 1 The switch SA shown is in the open state when a high-level potential is supplied to the control terminal and in the closed state when a low-level potential is supplied to the control terminal.

[0144] The SWLA wiring is used to transmit signals that control the switching between the on and off states of the switch SA. For example, the SWLA wiring is supplied with a high-level potential or a low-level potential.

[0145] As an example, the circuit WCDa has the function of converting digital data input to the input terminal into analog current and outputting the analog current to the output terminal. Therefore, the circuit WCDa preferably includes a digital potential-to-analog current conversion circuit.

[0146] In a digital potential-to-analog current conversion circuit, when the first digital data input to the input terminal is W and the current output to the output terminal is I... W At that time, W and I W Ideally, it should be proportional. Additionally, the analog current I output by circuit WCDa... W When I is the current driven by transistor M3 within the range of the subthreshold region, W It satisfies the following formula (1.1).

[0147] [Equation 1] .

[0148] Note that V g (W) is the potential of the gate of transistor M3 corresponding to the first data W.

[0149] When the first data W is written to the arithmetic unit IM, the circuit WCDa obtains the first data W as digital data from an external source and converts it into an analog current. Then, a high-level potential is supplied to the wiring SWLA, turning the switch SA on. Consequently, the analog current I is output as the first data W from the output terminal of the circuit WCDa. W The flow passes through the wiring WCL.

[0150] Note that nodes N and Nm of the computation unit IM correspond to the analog current I. WThe potential will be explained in detail later. Therefore, the first data W is written to the arithmetic unit IM. Furthermore, it is preferable to supply a low-level potential to the wiring SWLA after the writing is complete, thus turning off the switch SA. This increases the impedance of the output terminal of circuit WCDa, stopping the transmission of the first data W from the output terminal of circuit WCDa to wiring WCL, thereby reducing the power consumption of circuit WCDa.

[0151] The drive circuit XCD is used as a drive circuit to send second data X to the arithmetic unit IM. Specifically, for example, the drive circuit XCD has the function of acquiring second data X as digital data from an external source and converting X into analog current I. X The function is as follows. Additionally, the drive circuit XCD has the function of causing the analog current I to... X The function of the XCL wiring.

[0152] In addition, the drive circuit XCD has the function of supplying a reference current to the wiring XCL when the arithmetic unit IM is written with the first data W.

[0153] like Figure 1 As shown, the drive circuit XCD includes, for example, a circuit XCDa. Furthermore, the input terminals of circuit XCDa are connected to wiring IXL, and the output terminals of circuit XCDa are connected to wiring XCL.

[0154] As an example, circuit XCDa has the function of converting digital data input to the input terminal into analog current. Therefore, circuit XCDa preferably includes a digital potential-to-analog current conversion circuit.

[0155] When the arithmetic unit IM is written with the first data W, the circuit XCDa obtains reference data as digital data from the input terminal, causing an analog current (sometimes called the reference current) corresponding to this reference data to flow through the wiring XCL connected to the output terminal, which will be explained in detail later. At this time, the potential of the wiring XCL is V. r At that time, capacitor C1 of the arithmetic unit IM maintains the potential difference V between node N1 and wiring XCL. W -V r Note that, unless otherwise stated, this specification uses a base value of 1 for explanation.

[0156] After the arithmetic unit IM holds the first data W, the circuit XCDa obtains the second data X as digital data from the input terminal, causing the analog current I corresponding to X to... X The current flows through the wiring XCL connected to the output terminal. In circuit XCDa, the analog current I... XWhen the current flows through the wiring XCL, the potential of node N can be varied in the arithmetic unit IM through the capacitive coupling of capacitor C1. Specifically, the potential variation in node N1 due to the capacitive coupling of capacitor C1 is within the range driven by transistor M3 in the subthreshold region. Similarly, in the driving unit IMD, the potential of node Nd can be varied through the capacitive coupling of capacitor C1d. Specifically, the potential variation in node Nd due to the capacitive coupling of capacitor C1d is within the range driven by transistor M3d in the subthreshold region.

[0157] In other words, circuit XCDa has the following functions: during the period when the arithmetic unit IM is written with first data W, it obtains reference data from wiring IXL, causing a reference current corresponding to the reference data to flow through wiring XCL; and while the arithmetic unit IM holds the first data W, it obtains second data X from wiring IXL, causing the analog current I corresponding to X to... X The flow passes through the wiring XCL.

[0158] In the digital potential-to-analog current conversion circuit included in circuit XCDa, the second data X input to the input terminal and the current I output from the output terminal are... X Ideally, it should be proportional. Additionally, the analog current I output by circuit XCDa... X When the current driven by transistor M3d in the subthreshold region is within the range, I X The following formula (1.2) is satisfied.

[0159] [Equation 2] .

[0160] Note that V gm (X) is the gate potential of transistor M3d corresponding to the second data X.

[0161] The drive circuit WSD has the following functions: To ensure that transistors M1 and M2, which are the write transistors, are both turned on when the arithmetic unit IM, the target of writing the first data, is selected, a selection signal is supplied to the wiring WSL. Furthermore, when not writing the first data, the arithmetic unit IM has the following function: To ensure that transistors M1 and M2 are both turned off, a non-selection signal is supplied to the wiring WSL. Additionally, in Figure 1 In the circuit structure, it is preferable to set the selection signal to a high level and the non-selection signal to a low level.

[0162] Furthermore, since the driving unit IMD is also connected to the wiring WSL, the driving circuit WSD simultaneously sends a selection signal or a non-selection signal to both the arithmetic unit IM and the driving unit IMD. Therefore, when a selection signal is sent to the wiring WSL, transistors M1d and M2d, which act as write transistors for the driving unit IMD, are both turned on. Conversely, when a non-selection signal is sent to the wiring WSL, transistors M1d and M2d are both turned off.

[0163] As an example, the driving circuit ITS has the following function: obtains the current flowing through the wiring WCL corresponding to the multiplication of the first data W and the second data X output by the arithmetic unit IM, uses the current quantity as the input value as the function class (e.g., nonlinear function class) to perform the operation of the activation function F, and outputs the output data Z=F(W×X) as the result of the operation.

[0164] Furthermore, the activation function mentioned above can be a nonlinear function such as the sigmoid function, tanh function, softmax function, ReLU function, or threshold function. In particular, an example of the structure of the driver circuit ITS for performing the ReLU function operation will be described later.

[0165] Note that in the CDV (Computing Device for Digital Transmission), when the activation function calculation is not required using the ITS (Initial Activation Switch), the ITS can obtain the current corresponding to the multiplication of the first data W and the second data X and output Z=WX as the multiplication value. Alternatively, when the activation function calculation is not required using the ITS, the CDV may not need to include the ITS.

[0166] like Figure 1 As shown, the drive circuit ITS includes, for example, a circuit ITSa and a switch SB. Furthermore, the first terminal of switch SB is connected to wiring WCL, the second terminal of switch SB is connected to the input terminal of circuit ITSa, and the control terminal of switch SB is connected to wiring SWLB. Additionally, the output terminal of circuit ITSa is connected to wiring OL.

[0167] As for switch SB, for example, a switch that can also be used with switch SA can be used. Therefore, for information about switch SB, please refer to the description of switch SA.

[0168] The SWLB wiring is used to transmit signals that control the switching between the on and off states of the switch SB. Therefore, the SWLB wiring is supplied with a high-level or low-level potential.

[0169] As an example, the circuit ITSa has the function of performing function-like operations with the value corresponding to the current input to the input terminal as the input value. Furthermore, as an example, the circuit ITSa has the function of converting the operation result into any one of digital data, analog potential, and analog current, and outputting it to the output terminal.

[0170] Next, examples of the structures of the driving circuits WCD, XCD, and ITS used to drive the arithmetic unit IM and the driving unit IMD will be described.

[0171] <<Driver Circuit WCD>> Figure 1 The driving circuit WCD shown can, for example, employ... Figure 2A The structure shown. Note that in Figure 2A To illustrate the connection between the drive circuit WCD and its surrounding circuitry, wiring SWLA, wiring IWL, and wiring WCL are also shown. Additionally, for convenience, switch SA is included in circuit SWCA, and circuit SWCA is included in drive circuit WCD.

[0172] Circuit WCDa has the function of supplying a signal to wiring WCL, the signal quantity corresponding to the first data W. Note that in Figure 1 In the arithmetic device CDV, the signal is current. Therefore, the circuit WCDa preferably includes a digital potential-to-analog current conversion circuit.

[0173] As an example Figure 2A The circuit WCDa shown includes a switch SWW. The first terminal of switch SWW is connected to the second terminal of switch SA, and the second terminal of switch SWW is connected to wiring VINI1. Wiring VINI1 is used to supply an initialization potential to wiring WCL. This initialization potential can be negative, ground (GND), low, or high. Note that switch SWW is only in the on state when supplying an initialization potential to wiring WCL; otherwise, it is in the off state.

[0174] For example, a switch that can be used with a switch SA can be used with a switch SWW.

[0175] Additionally, as an example, Figure 2A The circuit WCDa includes multiple current sources CS. Specifically, the circuit WCDa has K-bit (2 K The first data W output is the current quantity function of the value (K is an integer greater than or equal to 1). In this case, the circuit WCDa includes 2 K-1 current source CS. Circuit WCDa, for example, includes one current source CS that outputs current corresponding to the value of bit 0, two current sources CS that output current corresponding to the value of bit 1, and 2... K-1 A current source CS outputs the information corresponding to the value of the (K-1)th bit as current.

[0176] exist Figure 2A In the circuit, each current source CS includes a terminal T1 and a terminal T2. The terminal T1 of each current source CS is connected to the second terminal of the switch SA included in the circuit SWCA. In addition, the terminal T2 of one current source CS is connected to the wiring DW[0], and the terminals T2 of the two current sources CS are respectively connected to the wiring DW[1]. K-1 Terminal T2 of each current source CS is connected to wiring DW[K-1].

[0177] In particular, routing DW[0] to routing DW[K-1] can be Figure 1 The wiring IWL shown is a group of wirings consisting of combined wirings DW[0] to wirings DW[K-1].

[0178] The multiple current sources CS in circuit WCDa have the same constant current I output from terminal T1. Wut The function. Note that, in reality, during the manufacturing stage of the CDV (Computing Device), errors sometimes occur due to variations in the electrical characteristics of the transistors in each current source CS. Therefore, the constant current I output from each terminal T1 of the multiple current sources CS... Wut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. Note that in this embodiment, it is assumed that the constant current I output from the terminal T1 of the plurality of current sources CS in the circuit WCDa is... Wut There is no error between them, so this is explained.

[0179] Wiring DW[0] to wiring DW[K-1] is used to transmit a constant current I from the current source CS connected to them. Wut The control signal is routed. Thus, circuit WCDa can allow a current corresponding to the amount of K bits of data sent from route DW[0] to route DW[K-1] to flow through route WCL. Specifically, for example, when route DW[0] is supplied with a high-level potential, the current source CS connected to route DW[0] acts as a constant current to make I... Wut When the circuit DW[0] is supplied with a low-level potential, the current source CS connected to the circuit DW[0] does not output I when the circuit flows through the second terminal of the switch SA. Wut For example, when wiring DW[1] is supplied with a high-level potential, the two current sources CS connected to wiring DW[1] make a total of 2I. WutA constant current flows through the second terminal of switch SA. When wiring DW[1] is supplied with a low-level potential, the current source CS connected to wiring DW[1] does not output a total of 2I. Wut The constant current. For example, when wiring DW[K-1] is supplied with a high-level potential, the 2 connected to wiring DW[K-1] K-1 The current source CS makes a total of 2 K-1 I Wut A constant current flows through the second terminal of switch SA. When wiring DW[K-1] is supplied with a low-level potential, the current source CS connected to wiring DW[K-1] does not output a total of 2. K-1 I Wut The constant current.

[0180] The current supplied by one current source CS connected to wiring DW[0] is equivalent to the value of bit 0, the current supplied by two current sources CS connected to wiring DW[1] is equivalent to the value of bit 1, and the current supplied by K current sources CS connected to wiring DW[K-1] is equivalent to the value of bit K-1. Here, consider the circuit WCDa when K is 2. For example, when the value of bit 0 is "1" and the value of bit 1 is "0", wiring DW[0] is supplied with a high level potential and wiring DW[1] is supplied with a low level potential. At this time, as a constant current, I Wut The current flows from circuit WCDa to the second terminal of switch SA in circuit SWCA. Additionally, for example, when the value of bit 0 is "1" and the value of bit 1 is "1", wiring DW[0] and wiring DW[1] are supplied with a high-level potential. At this time, as a constant current, 3I... Wut The current flows from circuit WCDa to the second terminal of switch SA in circuit SWCA. Additionally, for example, when the value of bit 0 is "0" and the value of bit 1 is "0", wiring DW[0] and wiring DW[1] are supplied with a low-level potential. At this time, the constant current does not flow from circuit WCDa to the second terminal of switch SA in circuit SWCA.

[0181] Notice, Figure 2A The circuit WCDa is shown when K is an integer greater than or equal to 3, but when K is 1, Figure 2A The circuit WCDa preferably adopts a structure that does not have a current source CS connected to wiring DW[1] to wiring DW[K-1]. Furthermore, when K is 2, Figure 2A The circuit WCDa preferably adopts a structure in which the current source CS is not connected to the wiring DW[2] to the wiring DW[K-1].

[0182] Next, a specific structural example of the current source CS will be described.

[0183] Figure 3A The current source CS1 shown is suitable for use Figure 2AThe circuit of the current source CS in the circuit WCDa, the current source CS1 includes transistor Tr1 and transistor Tr2.

[0184] The first terminal of transistor Tr1 is connected to wiring VEH. The second terminal of transistor Tr1 is connected to the gate and back gate of transistor Tr1, and the first terminal of transistor Tr2. The second terminal of transistor Tr2 is connected to terminal T1, and the gate of transistor Tr2 is connected to terminal T2. Additionally, terminal T2 is connected to wiring DW.

[0185] DW wiring is Figure 2A Any one of the wiring DW[0] to wiring DW[K-1].

[0186] The VEH wiring is used as a wiring to supply a fixed potential. This fixed potential can be, for example, a high-level potential.

[0187] When the fixed potential supplied by the wiring VEH is set to a high level, the first terminal of transistor Tr1 is input with a high level potential. Meanwhile, the potential of the second terminal of transistor Tr1 is set to a lower potential than this high level. At this time, the first terminal of transistor Tr1 is used as the drain, and the second terminal of transistor Tr1 is used as the source. Furthermore, the gate and second terminal of transistor Tr1 are connected, therefore the gate-source voltage of transistor Tr1 is 0V. Therefore, when the threshold voltage of transistor Tr1 is within an appropriate range, a subthreshold current (source-drain current) flows between the first and second terminals of transistor Tr1. When transistor Tr1 is an OS transistor, this current quantity per 1μm channel width is preferably, for example, 1.0 × 10⁻⁶. -8 A (1.0×10 -2 μA or less, more preferably 1.0 × 10 μA. -12 A (1.0 pA) or less, more preferably 1.0 × 10⁻⁶ -15 A (1.0fA) or less. Furthermore, this current is more preferably in the range where it increases exponentially with respect to the gate-source voltage. That is, transistor Tr1 is used as a current source to supply current when operating in the subthreshold region. Note that this current is equivalent to the aforementioned I. Wut Or the following I Xut .

[0188] Transistor Tr2 is used as a switching transistor. In transistor Tr2, when the potential of the first terminal is higher than the potential of the second terminal, the first terminal is used as the drain, and the second terminal is used as the source. Furthermore, the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2, therefore the voltage between the back gate and the source is 0V. Thus, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 is in the on state when a high-level potential is input to its gate, and in the off state when a low-level potential is input to its gate. Specifically, when transistor Tr2 is in the on state, the aforementioned subthreshold current flows from the second terminal of transistor Tr1 through terminal T1; when transistor Tr2 is in the off state, this current does not flow from the second terminal of transistor Tr1 through terminal T1.

[0189] Note that it can be used Figure 2A The circuit of the current source CS in the circuit WCDa is not limited to Figure 3A The current source CS1. For example, the current source CS1 has a structure in which the back gate of transistor Tr2 is connected to the second terminal, but it can also be a structure in which the back gate of transistor Tr2 is connected to other wiring. Figure 3B An example of such a structure is shown. Figure 3B The current source CS2 shown has a structure where the back gate of transistor Tr2 is connected to the wiring VTHL. In current source CS2, because the wiring VTHL is connected to external circuitry, a predetermined potential can be supplied to the back gate of transistor Tr2 by supplying a predetermined potential to the wiring VTHL using this external circuitry. This allows the threshold voltage of transistor Tr2 to be changed. By increasing the threshold voltage of transistor Tr2, the off-state current of transistor Tr2 can be reduced.

[0190] Alternatively, for example, current source CS1 has a structure in which the back gate of transistor Tr1 is connected to the second terminal, but it can also have a structure in which the voltage between the back gate of transistor Tr2 and the second terminal is maintained by a capacitor. Figure 3C An example of such a structure is shown. Figure 3CThe current source CS3 shown includes transistors Tr1 and Tr2, transistor Tr3, and capacitor C6. The difference between current source CS3 and current source CS1 is that capacitor C6 is placed between the second terminal of transistor Tr1 and its back gate in the former; and the back gate of transistor Tr1 is connected to the first terminal of transistor Tr3. Furthermore, current source CS3 employs a structure where the second terminal of transistor Tr3 is connected to wiring VTL, and the gate of transistor Tr3 is connected to wiring VWL. In current source CS3, supplying a high-level potential to wiring VWL turns transistor Tr3 on, thus conducting the connection between wiring VTL and the back gate of transistor Tr1. At this time, a predetermined potential can be input from wiring VTL to the back gate of transistor Tr1. Conversely, supplying a low-level potential to wiring VWL turns transistor Tr3 off, and capacitor C6 maintains the voltage between the second terminal of transistor Tr1 and its back gate. In other words, by determining the potential supplied by wiring VTL to the back gate of transistor Tr1, the threshold voltage of transistor Tr1 can be changed, and the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C6.

[0191] Additionally, for example, as can be used Figure 2A The circuit of current source CS in circuit WCDa can also be used. Figure 3D The current source CS4 is shown. Current source CS4 uses... Figure 3C The back gate of transistor Tr2, the current source CS3, is connected to the wiring VTHL but not to the second terminal of transistor Tr2. That is, with... Figure 3B Similarly, in current source CS4, the threshold voltage of transistor Tr2 can be changed according to the potential supplied by wiring VTHL.

[0192] When a large current flows through the first and second terminals of transistor Tr1 in current source CS4, the on-state current of transistor Tr2 needs to be increased in order for this current to flow from terminal T1 to the outside of current source CS4. At this time, by supplying a high-level potential to wiring VTHL in current source CS4, the threshold voltage of transistor Tr2 is reduced and the on-state current of transistor Tr2 is increased, allowing the large current flowing through the first and second terminals of transistor Tr1 to flow from terminal T1 to the outside of current source CS4.

[0193] By acting Figure 2A The current source CS in the circuit WCDa uses Figures 3A to 3DAny one of the current sources CS1 to CS4 shown can be used to output the current corresponding to the first data of the K bits. Furthermore, this current quantity can be, for example, the current flowing between the first and second terminals within the range where transistor M3 operates in the subthreshold region.

[0194] In addition, as Figure 2A The circuit WCDa can also be used Figure 2B The circuit shown is WCDa. Figure 2B The circuit WCDa uses wiring DW[0] to wiring DW[K-1] to connect to one of each. Figure 3A The structure of the current source CS. Furthermore, when the channel widths of transistors Tr1[0], Tr1[1], and Tr1[K-1] are w[0], w[1], and w[K-1] respectively, the ratio of each channel width is w[0]:w[1]:w[K-1]=1:2:2 K-1 The current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, and therefore... Figure 2A The circuit WCDa is the same. Figure 2B The circuit WCDa shown can output the current corresponding to the first data W at bit K.

[0195] Note that transistors Tr1 (including transistors Tr1[0] to Tr1[K-1]), Tr2 (including transistors Tr2[0] to Tr2[K-1]), and Tr3 can be transistors that can be used as transistors F1 or F2. In particular, OS transistors are preferably used as transistors Tr1 (including transistors Tr1[0] to Tr1[K-1]), Tr2 (including transistors Tr2[0] to Tr2[K-1]), and Tr3.

[0196] In particular, Figure 2A and Figure 2B The circuit shown is sometimes referred to as a K-bit current trapezoidal DAC (Digital to Analog Converter), one of the digital potential-to-analog current conversion circuits.

[0197] in addition, Figure 2B The circuit WCDa shown can also be modified to a CMOS (Complementary Metal-Oxide-Semiconductor) circuit structure that includes both n-channel and p-channel transistors. For example, Figure 2A The circuit WCDa can also be changed to Figure 4 The circuit structure shown is shown.

[0198] Figure 4The circuit WCDa shown employs a circuit structure including n-channel and p-channel transistors, and is an example of a K-bit current trapezoidal DAC. Circuit WCDa includes K current sources CS and a current mirror circuit CRM. Furthermore, Figure 4 The connection structure of the current source CS shown is... Figures 3A to 3D The difference between current sources CS1 to CS4 shown lies in their connection structure.

[0199] Next, the explanation Figure 4 The current sources CS are shown.

[0200] The first terminal of transistor Tr1[0] is electrically connected to wiring VSSL, the second terminal of transistor Tr1[0] is connected to the first terminal of transistor Tr2[0], and the gate of transistor Tr1[0] is connected to wiring BIS. In addition, the gate of transistor Tr2[0] is connected to wiring DW[0].

[0201] Similarly, the first terminal of transistor Tr1[1] is connected to wiring VSSL, the second terminal of transistor Tr1[1] is connected to the first terminal of transistor Tr2[2], and the gate of transistor Tr1[1] is connected to wiring BIS. In addition, the gate of transistor Tr2[1] is connected to wiring DW[1].

[0202] Similarly, the first terminal of transistor Tr1[K-1] is connected to wiring VSSL, the second terminal of transistor Tr1[K-1] is connected to the first terminal of transistor Tr2[K-1], and the gate of transistor Tr1[K-1] is connected to wiring BIS. In addition, the gate of transistor Tr2[K-1] is connected to wiring DW[K-1].

[0203] Furthermore, the second terminals of transistors Tr2[0] to Tr2[K-1] are connected to the terminal CTi of the current mirror circuit CRM described later.

[0204] exist Figure 4 In the diagram, the channel widths of transistors Tr1[0] to Tr1[K-1] can be referenced. Figure 2B Description of transistors Tr1[0] to Tr1[K-1].

[0205] In addition, Figure 4 In this configuration, transistors Tr2[0] to Tr2[K-1] are used as transistors capable of adjusting the current flowing between the source and drain of transistors Tr1[0] to Tr1[K-1]. Therefore, the wiring BIS is used as wiring to supply a fixed potential. This fixed potential can be, for example, a high-level potential, a positive potential, etc. Furthermore, depending on the situation, this fixed potential can also be a low-level potential, a ground potential, a negative potential, etc.

[0206] As an example, VSSL wiring is used to supply a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, a negative potential, etc. Furthermore, depending on the situation, this fixed potential can also be a high-level potential, etc.

[0207] Figure 4 Each current source CS shown has the above connection structure and is therefore used as a current inflow circuit, wherein current flows from the terminal T1 of the current source CS through transistors Tr1 and Tr2 through wiring VSSL.

[0208] Next, the current mirror circuit CRM will be explained.

[0209] A current mirror circuit CRM includes a terminal CTi used as an input terminal and a terminal CTo used as an output terminal. For example, the current mirror circuit CRM has the function of outputting a current equal to the amount of current flowing through terminal CTi to terminal CTo.

[0210] In addition, the current mirror circuit CRM includes transistors Tr5, Tr5m, Tr6, and Tr6m.

[0211] The first terminal of transistor Tr5 is connected to terminal CTi, the gate of transistor Tr6, and the gate of transistor Tr6m. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr6. The gate of transistor Tr5 is connected to the gate of transistor Tr5m and wiring CPE. The second terminal of transistor Tr6 is connected to wiring VEH. The first terminal of transistor Tr5m is connected to terminal CTo. The second terminal of transistor Tr5m is connected to the first terminal of transistor Tr6m. The second terminal of transistor Tr6m is connected to wiring VEH.

[0212] For information on VEH routing, please refer to [link / reference]. Figure 2A The wiring diagram for VEH is shown below.

[0213] As an example, a CPE (Cable Premises Equipment) is used to supply a fixed potential. This fixed potential can be a low-level potential, ground potential, negative potential, etc. Furthermore, depending on the situation, this fixed potential can also be a high-level potential, etc.

[0214] In the current mirror circuit CRM, the second terminals of transistors Tr6 and Tr6m are supplied with potential from wiring VDDL, and the gates of transistors Tr6 and Tr6m are supplied with the potential of terminal CTi. Therefore, ideally, equal amounts of current flow between the source and drain of transistors Tr6 and Tr6m.

[0215] Furthermore, transistor Tr5 is used as a transistor connected in a common-source, common-gate configuration with transistor Tr6. Similarly, transistor Tr5m is used as a transistor connected in a common-source, common-gate configuration with transistor Tr6m. This prevents the potential of terminal CTi from being directly input to the first terminal of transistor Tr6. In other words, it prevents drastic changes in the potential of the first terminal of transistor Tr6, thereby ensuring stable operation of the current mirror circuit CRM.

[0216] <<Driver Circuit XCD>> Figure 1 The driving circuit XCD shown may, for example, have Figure 2C The structure shown.

[0217] Circuit XCDa has the function of supplying a signal to wiring XCL, the signal quantity corresponding to the second data X. Note that in Figure 1 In the CDV (Computational Device), the signal is current.

[0218] As an example Figure 2C The circuit XCDa shown includes a switch SWX. The first terminal of switch SWX is connected to wiring XCL, and the second terminal of switch SWX is connected to wiring VINI2. Wiring VINI2 is used to supply an initialization potential to wiring XCL. This initialization potential can be negative, ground (GND), low, or high. Alternatively, the initialization potential supplied by wiring VINI2 can be made equal to the potential supplied by wiring VINI1. Note that switch SWX is only in the open state when supplying an initialization potential to wiring XCL; otherwise, it is in the closed state.

[0219] Switch SWX can be, for example, a switch that can be used with switch SA.

[0220] also, Figure 2C The circuit structure of XCDa can be adopted with Figure 2A The circuit WCDa has a roughly the same structure. Specifically, the circuit XCDa has the function of outputting reference data as a current quantity and outputting L-bit (2) current quantity. L The second data X output (where L is an integer greater than or equal to 1) functions as a current quantity. In this case, the circuit XCDa includes 2... L -1 current source CS. Circuit XCDa includes one current source CS that outputs current as information corresponding to the value of bit 0, two current sources CS that output current as information corresponding to the value of bit 1, and 2 L-1 A current source CS outputs the information corresponding to the value of the (L-1)th bit as current.

[0221] Furthermore, the reference data for the current output of the circuit XCDa can be, for example, information where the value of the 0th bit is "1" and the values ​​of the bits after the 1st bit are "0".

[0222] exist Figure 2C In the circuit, terminal T2 of one current source CS is connected to wiring DX[0], and terminal T2 of two current sources CS are respectively connected to wiring DX[1]. L-1 Terminal T2 of each current source CS is connected to wiring DX[L-1].

[0223] In particular, routing DX[0] to routing DX[L-1] can be Figure 1 The routing IXL is shown. That is, the routing IXL can be a group of routings that combine routings DX[0] to routings DX[L-1].

[0224] Multiple current sources CS in circuit XCDa have the same constant current output I from terminal T1. Xut The function is as follows. Furthermore, wiring DX[0] to wiring DX[L-1] is used to transmit the current source CS connected to them, I. Xut The control signal is routed. Thus, circuit XCDa can make a current corresponding to the amount of L bits of data sent from route DX[0] to route DX[L-1] flow through route XCL.

[0225] Specifically, consider circuit XCDa when L is 2. For example, when the value of bit 0 is "1" and the value of bit 1 is "0", wiring DX[0] is supplied with a high-level potential and wiring DX[1] is supplied with a low-level potential. At this time, as a constant current, I Xut The current flows from circuit XCDa through wiring XCL. Additionally, for example, when the value of bit 0 is "1" and the value of bit 1 is "1", wiring DX[0] and wiring DX[1] are supplied with a high-level potential. At this time, as a constant current, 3I... Xut The current flows from circuit XCDa through wiring XCL. Additionally, for example, when the value of bit 0 is "0" and the value of bit 1 is "0", wiring DX[0] and wiring DX[1] are supplied with a low-level potential. At this time, constant current does not flow from circuit XCDa through wiring XCL. Note that at this time, in this specification, etc., the current sometimes referred to as current quantity 0 flows from circuit XCDa through wiring XCL. Furthermore, the current quantity 0 and I output by circuit XCDa can be... Xut 2I Xut 3I Xut As the second data output by circuit XCDa, in particular, the current I output by circuit XCDa can be... Xut This serves as reference data output by the circuit XCDa.

[0226] When errors occur due to fluctuations in the electrical characteristics of the transistors in the current sources CS of circuit XCDa, the constant current I output from the terminals T1 of the multiple current sources CS will change. Xut The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. Note that in this embodiment, it is assumed that the constant current I output from the terminal T1 of the plurality of current sources CS in the circuit XCDa is... Xut The description is provided without error. Note that in this embodiment, it is assumed that the constant current I is output from terminal T1 of the multiple current sources CS in circuit WCDa. Xut Explanation without error.

[0227] In addition, similar to the current source CS in circuit WCDa, the current source CS in circuit XCDa also uses... Figures 3A to 3D Any one of the current sources CS1 to CS4. In this case, wiring DX can be used instead. Figures 3A to 3D The wiring DW is shown. Therefore, circuit XCDa can be used as reference data or the second data of the L-bit to allow subthreshold current to flow through wiring XCL.

[0228] in addition, Figure 2C The circuit XCDa can have the same characteristics as... Figure 2B The circuit shown, WCDa, has the same circuit structure. At this time, in Figure 2B In the symbols shown, circuit XCDa is used to replace circuit WCDa, wiring DX[0] is used to replace wiring DW[0], wiring DX[1] is used to replace wiring DW[1], wiring DX[L-1] is used to replace wiring DW[K-1], switch SWX is used to replace switch SWW, and wiring VINI2 is used to replace wiring VINI1.

[0229] also, Figure 2C The circuit XCDa can have the same characteristics as... Figure 4 The circuit shown, WCDa, has the same circuit structure. At this time, in Figure 4 In the symbols shown, circuit XCDa is used to replace circuit WCDa, wiring DX[0] is used to replace wiring DW[0], wiring DX[1] is used to replace wiring DW[1], and wiring DX[L-1] is used to replace wiring DW[K-1].

[0230] <<Driver Circuit WSD>> Figure 1The illustrated drive circuit WSD has the function of supplying a specified signal to the wiring WSL when writing first data W to the arithmetic unit IM, thereby turning on the write transistor in the arithmetic unit IM. In other words, the drive circuit WSD can be considered as a write word line for both the arithmetic unit IM and the drive unit IMD. For example, when the drive circuit WSD supplies a high-level potential to the wiring WSL as a selection signal, transistors M1 and M2 in the arithmetic unit IM, and transistors M1d and M2d in the drive unit IMD, can all be turned on. Furthermore, when the drive circuit WSD supplies a low-level potential to the wiring WSL as a non-selection signal, transistors M1 and M2 in the arithmetic unit IM, and transistors M1d and M2d in the drive unit IMD, can all be turned off. As described above, when the drive circuit WSD sends a selection signal or a non-selection signal to the wiring WSL, data can be written or held in each of the arithmetic unit IM and the drive unit IMD.

[0231] <<Driver Circuit ITS>> Figure 1 The driving circuit ITS shown can, for example, employ... Figure 5A The structure shown. Note that in Figure 5A To illustrate the connection between the drive circuit ITS and its surrounding circuitry, wiring SWLB, wiring WCL, and wiring OL are also shown. Additionally, for convenience, switch SB is included in circuit SWCB, and circuit SWCB is included in drive circuit ITS.

[0232] As mentioned above, Figure 5A The circuit ITSa shown includes a circuit that performs activation function operations as a function class (e.g., a nonlinear function class) and an analog-to-digital conversion circuit. In particular, the circuit that performs function operations preferably has the following function: it performs function operations with a value corresponding to the input current quantity as input value and outputs digital data (voltage) corresponding to the result of the operation.

[0233] Figure 5A The circuit ITSa may include, for example, a circuit RL that performs function-type operations and an analog-to-digital converter circuit ATDC. Additionally, the circuit RL may include, for example, terminals RTi and RTo.

[0234] The second terminal of switch SB is connected to the input terminal of circuit ITSa and the terminal RTi of circuit RL. Additionally, the terminal RTo of circuit RL is connected to the input terminal of analog-to-digital converter circuit ATDC, and the output terminal of analog-to-digital converter circuit ATDC is connected to wiring OL via the output terminal of circuit ITSa.

[0235] The wiring OL is used as wiring to output the results of the calculations performed by the computing device CDV as digital data to the outside.

[0236] The circuit RL can be the aforementioned function-type operational circuit. Furthermore, this function can be an activation function for an artificial neural network model. Additionally, as this activation function, for example, nonlinear functions such as the sigmoid function, tanh function, softmax function, ReLU function, or threshold function can be used. Alternatively, the circuit RL may not include function-type operational circuits but include a circuit for pooling processing. Furthermore, when employing... Figure 5A In the case of the structure, the circuit RL preferably outputs the potential from the terminal RTo.

[0237] Alternatively, circuit RL can also be a current-to-voltage conversion circuit.

[0238] When the circuit RL is a current-to-voltage conversion circuit, it is preferable that, for example, the circuit RL generates an analog potential corresponding to the current input from the wiring WCL through the switch SB to the terminal RTi of the circuit RL, and outputs it to the terminal RTo of the circuit RL.

[0239] In addition, the analog-to-digital converter circuit ATDC preferably converts the analog potential supplied from the terminal RTo of the circuit RL into a digital signal and outputs it to the wiring OL.

[0240] in addition, Figure 5B This shows an example of the structure of the drive circuit ITS when the circuit RL is a current-to-voltage conversion circuit. Figure 5B The circuit RL shown includes, for example, a load LE and an amplifier circuit OP.

[0241] An amplifier circuit (OP) is an amplifier circuit that includes inverting input terminals, non-inverting input terminals, and output terminals. Examples of OP amplifier circuits include operational amplifiers and differential amplifier circuits.

[0242] The inverting input terminal of amplifier circuit OP is connected to the first terminal of load LE and the second terminal of switch SB. The non-inverting input terminal of amplifier circuit OP is connected to wiring VRL. The output terminal of amplifier circuit OP is connected to the second terminal of load LE and terminal RTo.

[0243] VRL wiring is used to supply a fixed potential. This fixed potential can be, for example, ground potential (GND), low-level potential, etc.

[0244] In particular, when the fixed potential supplied by the wiring VRL is the ground potential (GND), the inverting input terminal of the amplifier circuit OP is virtually grounded, so the analog voltage output to the wiring OL can be a voltage based on the ground potential (GND).

[0245] When the drive circuit ITS has Figure 5B In this configuration, the value corresponding to the current flowing from wiring WCL through switch SB to terminal RTi of circuit RL can be output as an analog voltage to terminal RTo. Furthermore, this analog voltage can be converted into a digital signal by analog-to-digital converter (ATDC) and output to wiring OL.

[0246] Note that when the driver circuit ITS outputs an analog voltage instead of a digital signal to the wiring OL, such as Figure 5C As shown in the ITS drive circuit, the analog-to-digital converter (ATDC) circuit can also be omitted from the ITS circuit. Furthermore, in Figure 5C Preferably, the circuit RL performs a function-type operation with the value corresponding to the current flowing through terminal RTi as input, and outputs the result as an analog current to terminal RTo. Furthermore, by allowing the analog current from the operation result output from terminal RTo to flow through the wiring XCL of, for example, another computing device CDV, the result can be used for further operations. This corresponds to sending the operation result to the next fully connected layer in a multilayer perceptron, one type of artificial neural network. By directly using the analog current as the operation result for the next calculation, analog-to-digital and digital-to-analog current conversions are unnecessary, thus eliminating the need for these conversion circuits. This reduces the circuit area of ​​the computing device CDV and lowers the power consumption required by the conversion circuits.

[0247] Next, an example of the structure of circuit RL will be explained.

[0248] Next, the explanation Figure 5A or Figure 5C A specific structural example of circuit RL in the circuit ITSa.

[0249] As an example Figure 6 It is shown Figure 5A or Figure 5C The circuit diagram showing the specific structure of circuit RL in circuit ITSa. Figure 6 The circuit RL shown has the function of performing ReLU function operations.

[0250] As an example Figure 6 The circuit RL includes transistors MP1i, MP1o, MP2i, MP2o, MP3i, MP3o, MP4i, MP4o, MN1i, MN1o, MN2i, MN2o and current source CNI.

[0251] exist Figure 6In circuit RL, the first current mirror circuit is formed by p-channel transistors MP1i, MP2i, MP1o, and MP2o. The second current mirror circuit is formed by n-channel transistors MN1i, MN2i, MN1o, and MN2o. The third current mirror circuit is formed by p-channel transistors MP3i, MP4i, MP3o, and MP4o. Because circuit RL includes the first to third current mirror circuits, it is sometimes referred to as a three-stage current mirror circuit.

[0252] The drain of transistor MP1i is connected to terminal RTi, and the drain of transistor MP1o is connected to the input terminal of current source CNI and the drain of transistor MN2i. Additionally, the drain of transistor MN2o is connected to the drain of transistor MP3i. Furthermore, transistor MP3o is connected to the output terminal of circuit RL. Finally, the output terminal of current source CNI is connected to wiring VGE.

[0253] As an example, a VGE (Vehicle Gateway) is used to supply a fixed potential. This fixed potential can be, for example, a low-level potential, a negative potential, or a ground potential. Alternatively, depending on the situation, the fixed potential supplied by the VGE can be a high-level potential, a positive potential, or the like.

[0254] Ideally, the first current mirror circuit has the function of allowing a current of the same magnitude as the source-drain current corresponding to the gate-source potential of transistor MP2i to flow between the source and drain of transistor MP2o. Similarly, ideally, the second current mirror circuit has the function of allowing a current of the same magnitude as the source-drain current corresponding to the gate-source potential of transistor MN1i to flow between the source and drain of transistor MN1o. Likewise, ideally, the third current mirror circuit has the function of allowing a current of the same magnitude as the source-drain current corresponding to the gate-source potential of transistor MP4i to flow between the source and drain of transistor NP4o.

[0255] In the first current mirror circuit, transistor MP1i is used as a clamping transistor to prevent the threshold voltage of transistor MP2i from dropping due to DIBL. Similarly, transistor MP1o is also used as a clamping transistor to prevent the threshold voltage of transistor MP2o from dropping due to DIBL. Therefore, the gates of transistors MP1i and MP1o are connected to wiring RSWL1, which supplies the desired bias potential.

[0256] In the second and third current mirror circuits, transistors MN2i, MN2o, MP3i, and MP3o are all used as clamping transistors to reduce the threshold voltage of the series transistors caused by DIBL. At this time, wiring RSWL2 and wiring RSWL3 are used to supply the desired bias potential.

[0257] Furthermore, the bias potentials supplied by each of the wirings RSWL1 to RSWL3 can be equal. Therefore, wirings RSWL1 to RSWL3 can be identical wirings.

[0258] Furthermore, both transistors MP1i and MP1o can be used as switching transistors. In this case, wiring RSWL1 is preferably used to control the switching between the on and off states of transistors MP1i and MP1o. Additionally, by keeping both transistors MP1i and MP1o in the off state, the first current mirror circuit can be stopped, thereby reducing the power consumption of circuit RL.

[0259] Similarly, when both transistors MN2i and MN2o are used as switching transistors, the second current mirror circuit can be stopped at the desired timing. In this case, wiring RSWL2 is preferably used to control the switching between the on and off states of transistors MN2i and MN2o. Likewise, when both transistors MP3i and MP3o are used as switching transistors, the third current mirror circuit can be stopped at the desired timing. In this case, wiring RSWL3 is preferably used to control the switching between the on and off states of transistors MP3i and MP3o.

[0260] Furthermore, transistors MP1i and MP1o can be simultaneously turned on or off, just as transistors MP3i and MP3o can be turned off. Therefore, wiring RSWL1 and wiring RSWL3 can be the same wiring.

[0261] In the first current mirror circuit, the sources of transistors MP2i and MP2o are both connected to the wiring VDDL. Since the first current mirror circuit is composed of p-channel transistors, it also functions as a current pull-out circuit. Therefore, wiring VDDL is used as the wiring to supply a high-level potential for the high power supply potential of the first current mirror circuit. Similarly, the third current mirror is also used as a current pull-out circuit, and therefore the high-level potential supplied by wiring VDDL is also used as the high power supply potential for the third current mirror circuit.

[0262] In the second current mirror circuit, the sources of transistors MN1i and MN1o are both connected to wiring VSSL. Since the second current mirror circuit is composed of n-channel transistors, it also serves as a current sink circuit. Therefore, wiring VSSL is used to supply a low-level potential as the low power supply potential for the second current mirror circuit.

[0263] As an example, the current source CNI has the ability to transfer the quantity I IB The current flows from the drain of each of transistors MP1o and MN2i to the function of wiring VGE.

[0264] When the wiring SWLB is supplied with a high-level potential, the control terminal of switch SB is supplied with the same high-level potential, thus putting switch SB in the open state. At this time, the quantity I corresponding to the value of the multiplication operation performed by the arithmetic unit IM... IL The current flows through the wiring WCL. Therefore, the quantity I IL The current flows from wiring VDDL to wiring WCL. Therefore, due to the first current mirror circuit, the current between the source and drain of transistor MP2o is also I. IL .

[0265] In addition, when the current source CNI is working, according to Kirchhoff's current law, I... IL =I IB +I OL Established. OL This represents the amount of current flowing between the source and drain of transistor MN1i. Therefore, due to the second current mirror circuit, the amount of current between the source and drain of transistor MN1o is also I. OL .

[0266] Furthermore, since the current between the source and drain of transistor MN1o is also I... OL The current between the source and drain of transistor MP4i is also I. OL Therefore, due to the third current mirror circuit, the current between the source and drain of transistor MP4o is also I. OL , quantity I OL The current flows through the terminal RTo and through the wiring OL.

[0267] in I IL Greater than I B At that time, the circuit RL acts as its differential quantity I. OL The current flows through the terminal RTo and the wiring OL. Additionally, when I... IL For I B In the following case, the current between the input and output terminals of the current source CNI is I. IL And I OL =0. At this time, the current from the circuit RL does not flow through the wiring OL. That is to say, it can be obtained from... Figure 6 The circuit shown, RL, performs ReLU function operations.

[0268] <Example of how a computing device works> Next, the explanation Figure 1 The example shown is a working example of a computing device CDV.

[0269] Figure 7 This is a timing diagram illustrating an example of the operation of a computing device CDV. The timing diagram shows the potential variations of traces SWLA, SWLB, WSL, XCL, node N, and node Nd during and around periods T01 to T08. Additionally, the timing diagram also shows the source-drain current I flowing through transistor M3. M3 The quantity and the current I flowing between the source and drain of transistor M3d M3d The quantities of each change.

[0270] In addition, Figure 7 In the timing diagram, the left side lists the types of wiring, nodes, etc., and the right side lists the potential levels. In particular, "High" in this timing diagram refers to the high-level potential of the wiring, and "Low" refers to the low-level potential of the wiring.

[0271] Note that in this example, as Figure 1 The drive circuits WCD and XCD in the CDV computing device respectively use Figure 2A The driving circuit WCD and Figure 2C The XCD driving circuit will be explained in detail.

[0272] Additionally, the potential supplied by wiring VEL, wiring VINI1, and wiring VINI2 is set to V. N Additionally, V N It is ground potential (GND) or negative potential.

[0273] [Before T01] Prior to period T01, wiring SWLA, wiring SWLB, wiring WSL, and wiring XCL are supplied with a low-level potential. Additionally, the potential of node N in the arithmetic unit IM and node Nd in the driver unit IMD is V. N In addition, I M3 and I M3d All are 0.

[0274] Because wiring WSL is supplied with a low-level potential, the gates of transistors M1, M2, M1d, and M2d are also supplied with a low-level potential. As a result, these transistors are turned off.

[0275] Furthermore, assume that no second data X, as digital data, has been supplied from an external source before period T01. The current generated in circuit XCDa of the drive circuit XCD is 0. Additionally, assume that switch SWX is in the open state, and V is supplied from wiring VINI2 to wiring XCL through switch SWX. N .

[0276] [Period T01] During period T01, wiring SWLA is supplied with a high-level potential. As a result, the control terminal of switch SA is supplied with a high-level potential, and therefore switch SA is in the open state.

[0277] Furthermore, assume that during the period T01, the first data W, as digital data, has not yet been supplied from the outside. Therefore, the current generated in the circuit WCDa of the drive circuit WCD is 0. Additionally, assume that switch SWW is in the open state, and V is supplied from wiring VINI1 to wiring WCL through switch SWW and switch SA. N .

[0278] [Period T02] During period T02, wiring WSL is supplied with a high-level potential. Therefore, the gates of transistors M1, M2, M1d, and M2d are supplied with a high-level potential, and these transistors become turned on.

[0279] In the arithmetic unit IM, transistors M1 and M2 are turned on, thereby increasing the potential V from the wiring WCL. N The voltage is supplied to the gate of transistor M3, the first terminal of capacitor C1 (node ​​N), the first terminal of capacitor C2, and the terminal Sout (node ​​Nm) of amplifier circuit SF. At this time, the first terminal of transistor M3 is also supplied with a potential V from wiring WCL. N The second terminal of transistor M3 is supplied with a potential V from wiring VEL. N Therefore, current does not flow between the source and drain of transistor M3, thus I M3 Become 0.

[0280] Similarly, in the drive unit IMD, transistors M1d and M2d are turned on, thereby increasing the potential V from the wiring XCL. N The voltage is supplied to the gate of transistor M3d, the first terminal (node ​​Nd) of capacitor C1d, the first terminal of capacitor C2d, and the terminal Sout (node ​​Nmd) of amplifier circuit SFd. At this time, the first terminal of transistor M3d is also supplied with a potential V from wiring XCL. N The second terminal of transistor M3d is supplied with a potential V from wiring VEL. NTherefore, current does not flow between the source and drain of transistor M3d, thus I M3d It also becomes 0.

[0281] [Period T03] During period T03, reference data r is supplied from wiring IXL as digital data. Therefore, the current generated in circuit XCDa of the drive circuit XCD is the amount corresponding to r. Here, this current amount is rI. Xut Note that I Xut This is the current flowing when r=1. Additionally, when switch SWX is in the closed state, the quantity rI generated in circuit XCDa... Xut Current flows through the wiring XCL.

[0282] Furthermore, in the driving unit IMD, transistors M1d and M2d are in the on state, therefore the quantity rI Xut The current flows through the wiring VEL between the source and drain of transistor M3d. At this time, the potentials of the gate of transistor M3d, the first terminal (node ​​Nd) of capacitor C1d, the first terminal of capacitor C2d, and the terminal Sout (node ​​Nmd) of amplifier circuit SFd become the corresponding quantities rI. Xut The height of the current. At this time, set the potential to V. gm (r).

[0283] Additionally, during period T03, the first data W, as digital data, is supplied from wiring IWL. Therefore, the current generated in the circuit WCDa of the drive circuit WCD is the amount corresponding to W. Here, this current is WI. Wut Note that I Wut This is the current flowing when W=1. Additionally, switch SWW is in the closed state. Since switch SA is in the open state, the quantity WI generated in circuit WCDa is... Wut Current flows through the wiring WCL.

[0284] Furthermore, in the arithmetic unit IM, transistors M1 and M2 are in the ON state, therefore the quantity WI Wut The current flows through the wiring VEL between the source and drain of transistor M3. At this time, the potentials of the gate of transistor M3, the first terminal (node ​​N) of capacitor C1, the first terminal of capacitor C2, and the terminal Sout (node ​​Nm) of amplifier circuit SF become the corresponding quantities WI. Wut The height of the current. At this time, set the potential to V. g (W).

[0285] Note that I Xut Preferred and I Wut Equal. Here, I will be... Xut and IWut Each is defined as I0 for explanation.

[0286] Furthermore, since the current rI0 generated in circuit XCDa is the subthreshold current of transistor M3d and the gate-source voltage of transistor M3d is V gm (r)-V N Therefore, rI0 can be represented by the following formula (1.3).

[0287] [Equation 3] .

[0288] Note that V th This is the threshold voltage of transistor M3d, and J is a correction factor determined by temperature, device structure, etc. Additionally, I... a The gate-source voltage of transistor M3 is V. th The amount of current flowing through it.

[0289] Furthermore, since the current WI0 generated in circuit WCDa is the subthreshold current in transistor M3 and the gate-source voltage of transistor M3 is V g (W)-V N Therefore, WI0 can be represented by the following formula (1.4).

[0290] [Equation 4] .

[0291] Note that, for the sake of simplicity, the V of transistor M3... th J and I a The values ​​are respectively related to the V of transistor M3d th J and I a The values ​​are equal.

[0292] Here, I0 can be represented by the following formula (1.5).

[0293] [Equation 5] .

[0294] Therefore, by using formulas (1.4) and (1.5), W can be expressed as the following formula (1.6).

[0295] [Equation 6] .

[0296] [Period T04] During period T04, wiring WSL is supplied with a low-level potential. Therefore, the gates of transistors M1, M2, M1d, and M2d are each supplied with a low-level potential. Consequently, these transistors are turned off.

[0297] In the arithmetic unit IM, transistors M1 and M2 are turned off, thereby capacitor C1 maintains the potential V of node N. g (W). Thus, node N becomes a floating state. Furthermore, by maintaining the potential of node N, the voltage between the gate and source of transistor M3 is fixed, so the current of WI0 continues to flow between the source and drain of transistor M3.

[0298] Similarly, in the driving unit IMD, transistors M1d and M2d are turned off, thereby capacitor C1d maintains the potential V of node Nd. gm (r) is. Thus, node Nd becomes a floating state. Furthermore, by maintaining the potential of node Nd, the voltage between the gate and source of transistor M3d is fixed, so the current rI0 continues to flow between the source and drain of transistor M3d.

[0299] As with transistors M3 and M3d described above, by allowing a current of amount I to flow between the source and drain while maintaining a potential at the gate corresponding to that current, a current of amount I can subsequently flow between the source and drain as well. In this specification, this operation is referred to as "setting (programming) the amount of current flowing between the source and drain of the transistor to I," etc.

[0300] Furthermore, during period T04, in the arithmetic unit IM, transistors M1 and M2 are turned off, thereby capacitor C2 also maintains the potential V of node Nm. g (W). Furthermore, the Sin terminal of the amplifier circuit SF is connected to the input potential V. g (W), therefore the amplifier circuit outputs a potential V at terminal Sout. g (W). Therefore, even when transistor M2 is in the off state, the potential of node Nm fluctuates due to leakage current, etc., and the amplifier circuit SF can replenish the charge of node Nm. Thus, node Nm can maintain its potential V for a long time. g (W). At this time, the voltage between the source and drain of transistor M1 is 0V, thus reducing the leakage current of transistor M1. Therefore, node N can maintain a potential of V for a long time. g (W).

[0301] Similarly, in the driving unit IMD, transistors M1d and M2d are turned off, thus capacitor C2d also maintains the potential V of node Nmd. gm (r). Furthermore, the Sin terminal of the amplifier circuit SFd is connected to the input potential V.gm (r), therefore the amplifier circuit SFd outputs a potential V to terminal Sout. gm (r). Therefore, even when transistor M2d is in the off state, the potential of node Nmd fluctuates due to leakage current, etc., and the amplifier circuit SFd can replenish the charge of node Nmd. Thus, node Nmd can maintain its potential V for a long time. gm (r). At this time, the voltage between the source and drain of transistor M1 is 0V, thus reducing the leakage current of transistor M1. Therefore, node Nd can maintain a potential V for a long time. gm (r).

[0302] [Period T05] During period T05, the drive circuit XCDa stops, and the current generated in circuit XCDa is 0. Additionally, switch SWX becomes open, supplying potential V from wiring VINI2 to wiring XCL via switch SWX. N .

[0303] Therefore, the potential V from wiring VINI2 N The first terminal of transistor M3d is supplied to the drive unit IMD. Additionally, since node Nd is in a floating state, the potential of node Nd varies with the potential of wiring XCL due to the capacitive coupling of capacitor C1d. For example, the potential of wiring XCL changes from V... gm (r) becomes V N Therefore, the changing voltage is V. gm (r)-V N Furthermore, we assume V thereafter. gm (r)-V N =ΔV gm (r). Furthermore, when the capacitive coupling coefficient of capacitor C1d is p, the potential change at node Nd is pΔV. gm (r) = p(V) gm (r)-V N Therefore, the potential of node Nd during period T05 becomes V. gm (r)-pΔV gm (r).

[0304] At this time, the voltage between the gate and source of transistor M3d is V. gm (r)-pΔV gm (r)-V N Furthermore, in this example, the current flowing through transistor M3d caused by the gate-source voltage is 0.

[0305] Additionally, the potential V from wiring VINI2 NIt is also supplied to the second terminal of capacitor C1 of the arithmetic unit IM. Furthermore, since node N is also in a floating state, the potential of node N also varies with the potential change of wiring XCL due to the capacitive coupling of capacitor C1. For example, the potential change of wiring XCL is ΔV. gm (r), and when the capacitive coupling coefficient of capacitor C1 is the same as that of capacitor C1d, the potential change at node N is pΔV. gm (r) = p(V) gm (r)-V N Therefore, the potential of node N during period T05 becomes V. g (W)-pΔV gm (r).

[0306] At this time, the voltage between the gate and source of transistor M3 is V. g (r)-pΔV gm (r)-V N Furthermore, in this example, the current flowing through transistor M3 caused by the gate-source voltage is also 0.

[0307] Additionally, during period T05, the potential of node N in the computation unit IM becomes V. g (W)-pΔV gm (r), therefore, through the amplifier circuit SF, the potential of node Nm also becomes V. g (W)-pΔV gm (r). Similarly, the potential of node N in the driving unit IMD becomes V. gm (r)-pΔV gm (r), therefore, through the amplifier circuit SFd, the potential of node Nm also becomes V. gm (r)-pΔV gm (r).

[0308] [Period T06] During period T06, wiring SWLA is supplied with a low-level potential. Consequently, the control terminal of switch SA is supplied with a low-level potential, and therefore switch SA is in the closed state.

[0309] During period T05, the circuit WCDa of the drive circuit WCD stops, and the current generated in circuit WCDa is 0. Additionally, switch SWW can be in either the on or off state. In short, because switch SA is in the off state, the terminal connected to the wiring WCL of the drive circuit WCD has high impedance, therefore current or potential is not supplied from the drive circuit WCD to the wiring WCL.

[0310] [Period T07] During T07, wiring SWLB is supplied with a high-level voltage. Additionally, the control terminal of switch SB is supplied with a high-level potential, thus switch SB is in the ON state.

[0311] At this time, the input terminal of circuit ITSa and the first terminal of transistor M3 of arithmetic unit IM are in the conducting state.

[0312] [Period T08] During period T08, second data X, as digital data, is supplied from wiring IXL. Therefore, the current generated in circuit XCDa of the drive circuit XCD is the amount corresponding to X. Here, this current is XI0. Additionally, switch SWX is turned off, and the current XI0 generated in circuit XCDa flows through wiring XCL.

[0313] The current of XI0 flows through the transistor M3d of the drive unit IMD and through the wiring VEL. At this time, the potential of the wiring XCL changes from V... N Change to V gm (X). Furthermore, since node Nd is in a floating state, the potential of node Nd varies with the potential of the wiring XCL due to the capacitive coupling of capacitor C1d. For example, the potential of wiring XCL changes from V... N Change to V gm (X), therefore the changing voltage is V. gm (X)-V N Furthermore, we assume V thereafter. gm (X)-V N =ΔV gm (X). Furthermore, the capacitive coupling coefficient of capacitor C1d is p, therefore the potential change at node Nd is pΔV. gm (X) = p(V) gm (X)-V N Therefore, the potential of node Nd during period T08 becomes V. gm (r)-pΔV gm (r) + pΔV gm (X) = V gm (r) + p(ΔV) gm (X)-ΔV gm (r)).

[0314] At this time, the voltage between the gate and source of transistor M3d is V. gm (r) + p(ΔV) gm (X)-ΔV gm (r))-V N Therefore, the current I flowing between the source and drain of transistor M3d... M3d =XI0 becomes the following formula (1.7).

[0315] [Equation 7] .

[0316] Furthermore, in the computation unit IM, since node N is also in a floating state, the potential of node N changes according to the potential change of the routing XCL due to the capacitive coupling of capacitor C1. For example, the potential change of the routing XCL is ΔV. gm (X), the capacitive coupling coefficient of capacitor C1 is p, therefore the potential change at node N is also pΔV. gm (X) = p(V) gm (X)-V N Therefore, the potential of node N in T08 during this period becomes V. g (W)-pΔV gm (r) + pΔV gm (X) = V g (W)-p(ΔV) gm (X)-ΔV gm (r)).

[0317] At this time, the voltage between the gate and source of transistor M3 is V. g (W)-p(ΔV) gm (X)-ΔV gm (r))-V N Therefore, the current I flowing between the source and drain of transistor M3... M3 It becomes the following formula (1.8).

[0318] [Equation 8] .

[0319] Here, r and X are defined as formulas (1.9) and (1.10), respectively.

[0320] [Equation 9] .

[0321] By using equations (1.5), (1.6), (1.9), and (1.10), equation (1.8) becomes equation (1.11).

[0322] [Equation 10] .

[0323] As shown in equation (1.11), the current I flowing between the source and drain of transistor M3 M3 It is directly proportional to the product of W and X. Therefore, it can be determined from the current I... M3 Find the result of the multiplication of the first and second data points of W and X, respectively. Therefore, by using... Figure 1 The CDV (Computational Device for Data) can perform multiplication operations between the first data and the second data.

[0324] In particular, when performing the multiplication operation between the first data and the second data, the reference data r is preferably 1. That is, during periods T03 and T04, the amount of current flowing from the circuit XCDa through the wiring XCL is preferably I0.

[0325] In addition, according to the above explanation, in Figure 1 In the CDV (Computational Discrete Vault) arithmetic unit, by setting the reference data r to a positive number other than 1, division with r as the divisor and W / X as the dividend can be performed. In other words, multiplication of W / X / r can be performed. Therefore, the CDV arithmetic unit can improve the resolution of values ​​that can be used as second data inputs. Furthermore, when considering multiplication of W / r and X, it can also be said that the CDV arithmetic unit can improve the resolution of values ​​that can be used as first data inputs.

[0326] Since switch SA is in the closed state and switch SB is in the open state, the amount I flowing between the source and drain of transistor M3 is... M3 The current flows through the input terminal of the circuit ITS in the drive circuit ITS.

[0327] Circuit ITSa obtains quantity I M3 The current, corresponding to the quantity I M3 The value of I is substituted into the function as a variable for calculation, and the voltage or current corresponding to the calculation result is output from the output terminal. Specifically, refer to the description of the circuit ITSa above. For example, the function that substitutes I as a variable for the operation of the circuit ITSa is F(I), and the result of the operation is Z[j], which can be represented by the following formula (1.12).

[0328] [Equation 11] .

[0329] Additionally, during period T08, the potential of node N in the computation unit IM becomes V. g (W)-p(ΔV) gm (X)-ΔV gm (r)), therefore, through the amplifier circuit SF, the potential of node Nm also becomes V. g (W)-p(ΔV) gm (X)-ΔV gm (r)). Similarly, the potential of node N in the driving unit IMD becomes V. gm (r) + p(ΔV) gm (X)-ΔV gm (r)), therefore, through the amplifier circuit SFd, the potential of node Nm also becomes V.gm (r) + p(ΔV) gm (X)-ΔV gm (r)).

[0330] <Example 1 of operational circuit structure> Next, the explanation Figure 1 The example shown is a modified example of the arithmetic circuit CC in the arithmetic device CDV.

[0331] Figure 8A The operational circuit CC shown has the following characteristics: Figure 1 The circuit structure shown has transistor M4 in the arithmetic unit IM and transistor M4d in the driving unit IMD.

[0332] Specifically, transistor M4 is positioned between the first terminal of transistor M3 and wiring WCL, and transistor M4d is positioned between the first terminal of transistor M3d and wiring XCL. The first terminal of transistor M4 is connected to the first terminal of transistor M3, and the second terminal of transistor M4 is connected to wiring WCL. Furthermore, the first terminal of transistor M4d is connected to the first terminal of transistor M3d, and the second terminal of transistor M4d is connected to wiring XCL. Additionally, the gates of transistors M4 and M4d are connected to wiring VEB.

[0333] Transistor M4 is used as a clamping transistor to prevent DIBL in transistor M3. This prevents the threshold voltage of transistor M3 from dropping when a high-level potential is supplied to its first terminal. Similarly, transistor M4d is used as a clamping transistor to prevent DIBL in transistor M3d. This prevents the threshold voltage of transistor M3d from dropping when a high-level potential is supplied to its first terminal.

[0334] As an example, a VEB (Vessel Embedded Wire) is used to supply a fixed potential. This fixed potential can be, for example, a high level, a positive potential, etc. Alternatively, depending on the situation, the fixed potential supplied by the VEB can be a low level, a ground potential, a negative potential, etc.

[0335] <Example 2 of operational circuit structure> Figure 8B The operational circuit CC shown adopts a circuit structure in which both amplifier circuits SF and SFd are used as source followers.

[0336] Specifically, the amplifier circuit SF includes transistors M5 and M6, and the amplifier circuit SFd includes transistors M5d and M6d. Thus, these transistors are used as amplifying transistors.

[0337] The gate of transistor M5 is connected to the Sin terminal of amplifier circuit SF. The first terminal of transistor M5 is connected to the first terminal of transistor M6 and the Sout terminal of amplifier circuit SF. The second terminal of transistor M5 is connected to wiring VED. Additionally, the second terminal of transistor M6 is connected to wiring VES, and the gate of transistor M6 is connected to wiring VEI.

[0338] Furthermore, the gate of transistor M5d is connected to the Sin terminal of amplifier circuit SFd, the first terminal of transistor M5d is connected to the first terminal of transistor M6d and the Sout terminal of amplifier circuit SFd, and the second terminal of transistor M5d is connected to wiring VED. Additionally, the second terminal of transistor M6d is connected to wiring VES, and the gate of transistor M6d is connected to wiring VEI.

[0339] As an example, the wiring VED is used as a wiring to supply a fixed potential. Specifically, the wiring VED is used to supply a high-level potential as a high power supply potential to the source followers including transistors M5 and M6, and to the source followers including transistors M5d and M6d. Furthermore, depending on the situation, the fixed potential supplied by the wiring VED can be a low-level potential, ground potential, negative potential, etc., instead of a high-level potential.

[0340] As an example, the wiring VES is used as a wiring to supply a fixed potential. Specifically, the wiring VES is used to supply a low-level potential to the source followers including transistors M5 and M6, and to the source followers including transistors M5d and M6d, respectively, as a low power supply potential. Alternatively, depending on the situation, the fixed potential supplied by the wiring VES may be a high-level potential or something similar, rather than a low power supply potential.

[0341] As an example, wiring VEI is used as a wiring to supply a fixed potential. Specifically, wiring VEI is used to supply this fixed potential to the gates of transistors M6 and M6d. Furthermore, when the second terminals of transistors M6 and M6d are supplied with a low-level potential from wiring VES, transistors M6 and M6d are used as current sources. This fixed potential can be, for example, a potential higher than 0V, a potential higher than ground, etc.

[0342] Note that transistors M5 and M6 can be any of the transistors M1 through M3. Similarly, transistors M5d and M6d can be any of the transistors M1d through M3d.

[0343] As described above, in the operational unit IM, transistors M5 and M6 are both source followers. In particular, in transistors M5 and M6, to improve the operating speed of the source follower that can be used in the amplifier circuit SF, it is preferable to increase the current flowing between each source and drain. Similarly, as described above, in the driving unit IMD, transistors M5d and M6d are both source followers. In particular, in transistors M5d and M6d, to improve the operating speed of the source follower that can be used in the amplifier circuit SFd, it is preferable to increase the current flowing between each source and drain.

[0344] Therefore, Si transistors are preferably used as transistors M5, M6, and M6. Si transistors have a larger on-state current than OS transistors, thus improving the charging speed of nodes, terminals, capacitors, etc. In amplifier circuit SF, the increased current output to terminal Sout shortens the time required for potential change at node Nm. Similarly, in amplifier circuit SFd, the increased current output to terminal Sout shortens the time required for potential change at node Nmd. In other words, in each of amplifier circuits SF and SFd, the response speed from potential input to terminal Sin to potential output to terminal Sout can be improved.

[0345] Note that the structures described in this embodiment can be combined with each other. For example, they can also be combined... Figure 8A and Figure 8B The various operational circuits CC and so on Figure 9 The structure of the operational circuit CC shown is used as one aspect of this invention.

[0346] exist Figure 9 In the operational circuit CC shown, as Figure 8A The operational circuit CC uses the amplifier circuit SF and amplifier circuit SFd. Figure 8B The circuit structures of amplifier circuits SF and SFd are shown. Therefore, Figure 9 The amplifier circuits SF and SFd in the operational circuit CC can be referred to respectively. Figure 8B Explanation of the amplifier circuits SF and SFd shown.

[0347] <Example 3 of operational circuit structure> Figure 8C The operational circuit CC shown is Figure 1 The example shown is a variation of the operational circuit CC. Figure 8C The operational circuit CC and Figure 1 The difference between the operational circuit CC and the former is that the former does not include capacitor C2 and capacitor C2d.

[0348] exist Figure 8C In the operational circuit CC, there are no capacitors provided to maintain the potentials of nodes Nm and Nmd. Figure 8C In the operational circuit CC, nodes Nm and Nmd cannot be held charged by capacitors. However, when the charge supply of amplifier circuit SF is greater than the charge release of node Nm, the potential fluctuation of node Nm can be suppressed. Similarly, when the charge supply of amplifier circuit SFd is greater than the charge release of node Nmd, the potential fluctuation of node Nmd can be suppressed. Therefore, under the above conditions, the operational circuit CC can be structured without capacitors C2 and C2d.

[0349] In addition, by not including capacitor C2 (capacitor C2d) in the operational circuit CC, the time required for the amplifier circuit SF (amplifier circuit SFd) to store charge at node Nm (node ​​Nmd) can be reduced, thereby increasing the operating speed of the operational circuit CC.

[0350] Furthermore, by omitting capacitor C2 (capacitor C2d) in the arithmetic circuit CC, the circuit area of ​​the arithmetic unit IM (driving unit IMD) in the arithmetic circuit CC can be reduced. Additionally, since the wiring VEG connected to capacitor C2 (capacitor C2d) is not required, the circuit area of ​​the cell array CA can also be reduced. Thus, the circuit area of ​​the arithmetic device CDV can be reduced. Furthermore, the cell density of the cell array CA can be increased, thereby enabling larger-scale operations to be performed in the arithmetic device CDV.

[0351] <Example 4 of operational circuit structure> Figure 10A The operational circuit CC shown is Figure 1 The illustrated variation of the operational circuit CC shows that the second terminals of capacitors C2 and C2d are connected to wiring XCL instead of wiring VEG, which is different from... Figure 1 The operational circuits CC are different.

[0352] In the arithmetic unit IM, node Nm, in addition to node N, is also connected to the wiring XCL via the second terminals of capacitors C2 and C2d. Therefore, the potential of node Nm changes due to the capacitive coupling of capacitor C2 along with the potential changes in the wiring XCL. Furthermore, during write operations and hold operations, the potentials of nodes N and Nm are equal. Therefore, it is preferable that the potentials of nodes N and Nm are also equal after the capacitive coupling of capacitor C2 occurs due to the potential changes in the wiring XCL. Similarly, in the drive unit IMD, node Nmd, in addition to node Nd, is also connected to the wiring XCL. Therefore, the potential of node Nmd changes due to the capacitive coupling of capacitor C2d along with the potential changes in the wiring XCL. Furthermore, during write operations and hold operations, the potentials of nodes Nd and Nmd are equal. Therefore, it is preferable that the potentials of nodes Nd and Nmd are also equal after the capacitive coupling of capacitor C2d occurs due to the potential changes in the wiring XCL.

[0353] In the operational unit IM, the potential change of the wiring XCL causes changes in the potentials of nodes N and Nm, thereby reducing the amplification of the potential of node Nm by the amplifier circuit SF. As a result, the charge supply to the terminal Sout of the amplifier circuit SF can be reduced. Thus, the power consumption of the amplifier circuit SF can be reduced.

[0354] Similarly, in the driving unit IMD, the potential change of the wiring XCL causes changes in the potentials of nodes Nd and Nmd, thereby reducing the amplification of the potential of node Nmd by the amplifier circuit SFd. As a result, the charge supply to the terminal Sout of the amplifier circuit SFd can be reduced. Thus, the power consumption of the amplifier circuit SFd can be reduced.

[0355] In addition, for example, combinations are also possible. Figure 8A and Figure 10A The various operational circuits CC and so on Figure 10B The structure of the operational circuit CC shown is used as one aspect of this invention.

[0356] exist Figure 10B In the operational circuit CC shown, Figure 10A The arithmetic unit IM is equipped with transistor M4 to prevent DIBL of transistor M3. Figure 10A The driving unit IMD includes a transistor M4d to prevent the threshold voltage of transistor M3d from dropping. Therefore, the threshold voltage of transistor M3d can be prevented from dropping by utilizing the potential of wiring WCL, or the threshold voltage of transistor M3d can be prevented from dropping by utilizing the potential of wiring XCL.

[0357] <Example 5 of operational circuit structure> Figure 11 Showing with Figure 1 And the operational circuits CC with different structures shown in Figures 8 to 10. Figure 11 The operational circuit CC shown is Figure 1 A modified example of the arithmetic circuit CC can hold the first data in the arithmetic unit IM for a long time and hold the reference data in the driving unit IMD for a long time.

[0358] The arithmetic unit IM includes transistors M1, M2[1] to M2[K] (K is an integer greater than or equal to 3), transistor M3, capacitor C1, and capacitors C2[1] to C2[K]. Note that... Figure 11 The transistor M1 corresponds to Figure 1 transistor M1, Figure 11 Transistor M2[1] to transistor M2[K] correspond to Figure 1 transistor M2, Figure 11 The transistor M3 corresponds to Figure 1 The transistor M3. Additionally... Figure 11 The capacitor C1 corresponds to Figure 1 capacitor C1, Figure 11 The capacitor C2[1] to capacitor C2[K] corresponds to Figure 1 Capacitor C2. Additionally... Figure 11 The amplifier circuits SF[1] to SF[K] correspond to Figure 1 SF amplifier circuit.

[0359] Additionally, the driving unit IMD includes transistor M1d, transistors M2d[1] to M2d[K] (K is an integer greater than or equal to 3), transistor M3d, capacitor C1d, and capacitors C2d[1] to C2d[K]. Note that Figure 11 The transistor M1d corresponds to Figure 1 transistor M1d, Figure 11 The transistors M2d[1] to M2d[K] correspond to Figure 1 transistor M2d, Figure 11 The transistor M3d corresponds to Figure 1 The transistor M3d. Additionally... Figure 11 The capacitor C1 corresponds to Figure 1 The capacitor C1d, Figure 11 The capacitor C2d[1] to capacitor C2d[K] corresponds to Figure 1 The capacitor C2d. Additionally... Figure 11 The amplifier circuit SFd[1] to the amplifier circuit SFd[K] correspond to Figure 1 The amplifier circuit SFd.

[0360] In the arithmetic unit IM, the first terminal of transistor M1 is connected to the gate of transistor M3, the first terminal of capacitor C1, and the Sin terminals of amplifier circuits SF[1] to SF[K]. Furthermore, the second terminal of transistor M1 is connected to the first terminal of transistor M2[K], the first terminal of capacitor C2[K], and the Sout terminal of amplifier circuit SF[K]. Additionally, the first terminal of transistor M2[k] (where k is an integer greater than or equal to 1 and less than or equal to K-1) is connected to the second terminal of transistor M2[k+1], the first terminal of capacitor C2[k], and the Sout terminal of amplifier circuit SF[k].

[0361] The second terminal of transistor M2[1] and the first terminal of transistor M3 are connected to wiring WCL, and the second terminal of transistor M3 is connected to wiring VEL. In addition, the second terminal of capacitor C1 is connected to wiring XCL, and the second terminals of capacitors C2[1] to C2[K] are connected to wiring VEG. In addition, the gates of transistors M1 and M2[1] to M2[K] are connected to wiring WSL.

[0362] Furthermore, in the driving unit IMD, the first terminal of transistor M1d is connected to the gate of transistor M3d, the first terminal of capacitor C1d, and the Sin terminals of amplifier circuits SFd[1] to SFd[K]. Additionally, the second terminal of transistor M1d is connected to the first terminal of transistor M2d[K], the first terminal of capacitor C2d[K], and the Sout terminal of amplifier circuit SFd[K]. Furthermore, the first terminal of transistor M2d[k] (where k is an integer greater than or equal to 1 and less than or equal to K-1) is connected to the second terminal of transistor M2d[k+1], the first terminal of capacitor C2d[k], and the Sout terminal of amplifier circuit SFd[k].

[0363] The second terminal of transistor M2d[1], the first terminal of transistor M3d, and the second terminal of capacitor C1d are connected to wiring XCL, and the second terminal of transistor M3d is connected to wiring VEL. Additionally, the second terminals of capacitors C2[1] to C2[K] are connected to wiring VEG. Furthermore, the gates of transistors M1d and M2d[1] to M2d[K] are connected to wiring WSL.

[0364] Notice, Figure 11 Transistor M2[k], transistor M2[k+1], transistor M2d[k], transistor M2d[k+1], capacitor C1[k], capacitor C1d[k], amplifier circuit SF[k], and amplifier circuit SFd[k] are not shown.

[0365] In the arithmetic unit IM, the first terminals of capacitors C1 and C2[1] to C2[K] are holding nodes, and each holding node holds the same first data.

[0366] In addition, in the drive unit IMD, the first terminals of capacitors C1d and C2d[1] to C2d[K] are holding nodes, and each holding node holds the same reference data.

[0367] like Figure 11 As shown, in the arithmetic unit IM, by connecting transistor M1 and transistor M2[1] to transistor M2[K] in series, the channel length of transistor M1 can be considered to be substantially extended. By extending the channel length, the leakage current between the source and drain of transistors M1 and transistors M2[1] to M2[K] can be reduced, thereby maintaining the potential corresponding to the first data in the arithmetic unit IM for a long time.

[0368] Similarly, in the driving unit IMD, by connecting transistor M1d and transistor M2d[1] to transistor M2d[K] in series, the channel length of transistor M1 can be considered to be substantially extended. By extending the channel length, the leakage current between the source and drain of transistors M1d and transistors M2d[1] to M2d[K] can be reduced, thereby maintaining the potential corresponding to the reference data in the driving unit IMD for a long time.

[0369] <An example of the layout of an operational circuit> Next, an example of the layout of the aforementioned computing unit IM and driving unit IMD will be described.

[0370] Figure 12 It is shown Figure 9 A plan view illustrating an example layout of the computational unit IM. Figure 13 It is shown Figure 9 The diagram shows a plan view of an example layout of the drive unit IMD.

[0371] exist Figure 12 In the diagram, as an example, the computing unit IM includes a conductive layer GEM, a conductive layer SDM, a conductive layer WIR, a semiconductor layer SMC, and a conductive layer PLG. Similarly, as an example, the driving unit IMD also includes a conductive layer GEM, a conductive layer SDM, a conductive layer WIR, a semiconductor layer SMC, and a conductive layer PLG. Note that this is for clarity in showing a planar schematic. Figure 12 and Figure 13 The insulating layer included in the computing unit IM and the driving unit IMD is not shown.

[0372] As an example, the semiconductor layer SMC is located below the conductive layer SDM and the conductive layer GEM. As another example, the conductive layer PLG is located above the conductive layer SDM and the conductive layer GEM. As yet another example, the conductive layer WIR is located above the conductive layer PLG. Note that the formation sequence can be as follows: First, form the semiconductor layer SMC; second, form one of the conductive layers SDM and GEM; third, form the other of the conductive layers SDM and GEM; fourth, form the conductive layer PLG; fifth, form the conductive layer WIR.

[0373] In the arithmetic unit IM and the driving unit IMD, a portion of the conductive layer GEM is used, for example, as the gate of each of transistors M1 to M6 and transistors M1d to M6d. Additionally, a portion of the conductive layer GEM is used, for example, as one of a pair of electrodes of each of capacitors C1, C2, C1d, and C2d.

[0374] Additionally, a portion of the conductive layer GEM can be wiring extending near the computing unit IM or the driving unit IMD. For example, in Figure 12 and Figure 13 In this process, wiring XCL, wiring WSL, wiring VEI, wiring VED, wiring VES and wiring VEG extending near the computing unit IM or the driving unit IMD can be formed as part of the conductive layer GEM.

[0375] A portion of the conductive layer SDM is used, for example, as the source or drain of transistors M1 to M6 and transistors M1d to M6d respectively.

[0376] A portion of the conductive layer WIR is used, for example, as another of a pair of electrodes in capacitors C1, C2, C1d, and C2d.

[0377] Additionally, a portion of the conductive layer WIR can be wiring extending near the computing unit IM or the driving unit IMD. For example, in Figure 12 In this context, the wiring VEL, wiring WCL, and wiring VEB extending near the computing unit IM can be formed as part of the conductive layer WIR. Additionally, for example, in... Figure 13 In this process, the wiring VEL and wiring VEB extending near the drive unit IMD can be formed as part of the conductive layer WIR.

[0378] The conductive layer GEM, conductive layer SDM, conductive layer WIR, and semiconductor layer SMC can all be formed using photolithography, for example. Specifically, for example, when forming the conductive layer GEM, the conductive material to become the conductive layer GEM can be formed using one or more methods selected from sputtering, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition), and then the desired pattern can be formed using photolithography. Furthermore, the conductive layer SDM, conductive layer WIR, semiconductor layer SMC, and conductive layer PLG can also be formed using the same methods described above.

[0379] Additionally, insulating layers can be provided between the semiconductor layer SMC and the conductive layer GEM, between the conductive layer GEM and the conductive layer SDM, and between the conductive layer WIR and the conductive layer GEM. In particular, the insulating layer provided between the semiconductor layer SMC and the conductive layer GEM is sometimes used as a gate insulating film (sometimes referred to as a front gate insulating film, etc.). Furthermore, in the region where capacitors C1 and C2 are provided, it is preferable to provide an insulating layer serving as the dielectric for each of capacitors C1 and C2 between the conductive layer WIR and the conductive layer GEM. Similarly, in the region where capacitors C1d and C2d are provided, it is also preferable to provide an insulating layer serving as the dielectric for each of capacitors C1d and C2d between the conductive layer WIR and the conductive layer GEM.

[0380] like Figure 12 As shown, capacitor C1 is preferably disposed in the conductive layer GEM as part of the area where the wiring XCL extends. Similarly, as Figure 12 As shown, capacitor C2 is preferably disposed in a region of the conductive layer GEM that is an extension of the wiring VEG. In this way, by using a portion of the extended wiring as one of the two electrodes of the capacitor and the portion above it as the other of the two electrodes of the capacitor, the area where the capacitor is disposed can be easily secured, thereby reducing the circuit area of ​​the computing unit IM.

[0381] Alternatively, the width of the wiring XCL area where capacitor C1 is located can be made larger than the width of the wiring XCL area where capacitor C1 is not located to increase the electrostatic capacitance value. In this way, by increasing the electrostatic capacitance of capacitor C1, the lifespan can be extended. Figure 1 The holding time of the potential at node N is shown. Additionally, similarly to the above, the width of the wiring VEG with capacitor C2 can be made larger than the width of the wiring VEG without capacitor C2 to increase the electrostatic capacitance value of capacitor C2.

[0382] In addition, Figure 12 In this capacitor, the width d1 of the conductive layer WIR, which serves as one of the electrodes in a pair of capacitors C1, is smaller than the width d2 of the conductive layer GEM, which serves as one of the electrodes in the pair of electrodes C1. When an insulating layer serving as a dielectric is formed on the conductive layer GEM, poor formation of the insulating layer sometimes occurs at or near the edge of the conductive layer GEM. Specifically, the coverage of the insulating layer formed at or near the edge of the conductive layer GEM is sometimes reduced. In this case, if the width d1 of the conductive layer WIR is greater than the width d2 of the conductive layer GEM, the edge of the conductive layer GEM or its surrounding area and the area of ​​the conductive layer WIR overlapping with it may come into contact with each other and short-circuit. Therefore, the width d1 of the conductive layer WIR is preferably smaller than the width d2 of the conductive layer GEM.

[0383] Conversely, when it is possible to improve the coverage of the insulating layer formed on or near the edge of the conductive layer GEM, the width d1 is preferably greater than the width d2. Specifically, the electrostatic capacitance of a capacitor is proportional to the area of ​​the overlapping region of one of the electrodes, the dielectric, and the other of the electrodes; therefore, to increase the electrostatic capacitance, it is preferable to increase the area of ​​this region. Thus, by making the width d1 greater than the width d2, the width of this region can be increased from d1 to d2. Consequently, the conductive layer WIR is formed above the edge of the conductive layer GEM, thus increasing the area of ​​the other electrode of capacitor C1, thereby increasing the electrostatic capacitance of capacitor C1. Note that the same applies to capacitor C2.

[0384] Note that it can be said that... Figure 13 The capacitors C1d and C2d of the drive unit IMD are the same as those of the capacitors C1 and C2 mentioned above.

[0385] Furthermore, an opening is provided in the region where a portion of the conductive layer SDM overlaps with a portion of the conductive layer WIR, and a conductive layer PLG is embedded in this opening. This allows charge to move between the portion of the conductive layer SDM and the portion of the conductive layer WIR via the conductive layer PLG. Similarly, an opening is provided in the region where a portion of the conductive layer GEM overlaps with a portion of the conductive layer WIR, and another conductive layer PLG is embedded in this opening. This allows charge to move between the portion of the conductive layer GEM and the portion of the conductive layer WIR via the conductive layer PLG.

[0386] In addition, Figure 1 In the diagram, transistor M1 and transistor M2 are connected in series, therefore, as shown... Figure 12 As shown in the planar schematic diagram of the computing unit IM, transistors M1 and M2 can be formed by sharing an island-shaped semiconductor layer (SMC). Similarly, in Figure 1In the diagram, transistor M1 and transistor M2 are connected in series, therefore, as shown... Figure 12 As shown in the planar schematic diagram of the computing unit IM, transistors M3 and M4 can be formed by sharing an island-shaped semiconductor layer (SMC). Similarly, in Figure 1 In the diagram, transistors M5 and M6 are connected in series, therefore, as shown... Figure 12 As shown in the planar schematic of the arithmetic unit IM, transistors M5 and M6 can be formed using a shared island semiconductor layer (SMC). This reduces the transistor formation area of ​​the arithmetic unit IM, resulting in increased cell density and a smaller circuit area of ​​the arithmetic device CDV. Furthermore, as... Figure 12 As shown, by arranging three island-shaped semiconductor layers (SMCs) in parallel, the circuit area of ​​the computing unit (IM) can be reduced. Note that the above can also be said to apply to... Figure 13 A planar schematic diagram of the drive unit IMD.

[0387] In addition, such as Figure 12 As shown, by arranging three island-shaped semiconductor layers (SMCs) in parallel, each of the transistors M1 to M6 included in the arithmetic unit IM can be easily used as a back gate electrode wiring (back gate wiring). For example, as Figure 14 As shown, the conductive layer BGM used as wiring BGL1, which serves as the back gate wiring, can extend below the semiconductor layer SMC, which includes the channel formation regions of transistors M1, M3, and M5. Similarly, the conductive layer BGM used as wiring BGL2, which serves as the back gate wiring, can extend below the semiconductor layer SMC, which includes the channel formation regions of transistors M2, M4, and M6. This simplifies the winding of wiring BGL1 and BGL2, shortens the wiring distance, reduces parasitic resistance, and consequently lowers power consumption.

[0388] Note that the planar schematic diagram of the operational circuit of one embodiment of the present invention is not limited to... Figure 12 and Figure 13 The planar schematic diagram of the operational circuit as one embodiment of the present invention can also be appropriately modified. Figure 12 and Figure 13 Make changes. For example, in Figure 12 In this configuration, transistors M1 and M2 are formed using a shared island semiconductor layer (SMC), but they can also be arranged with separate island semiconductor layers (SMC). Additionally, for example, in... Figure 12 In the circuit diagram shown, transistors M1, M2, M4, and M3 are connected in series, so they can be formed using a common island semiconductor layer (SMC).

[0389] In addition, Figure 12 and Figure 13 In the planar schematic diagram, the dimensions (including channel length and channel width) of transistors M1 to M6 are equal to each other, and the dimensions of transistors M1d to M6d are equal to each other. However, the dimensions of transistors M1 to M6 can also be different from each other, and similarly, the dimensions of transistors M1d to M6d can also be different from each other.

[0390] For example, in Figure 12 In this configuration, the channel width d3 of transistors M1 and M2 is preferably smaller than the channel width d5 ​​of transistor M3 and the channel width d7 of transistors M5 and M6. In other words, it is preferable that the channel width of the switching transistor is smaller than the channel width of the amplifying transistor. By shortening the channel width d3 of transistors M1 and M2, the off-state current of transistors M1 and M2 can be reduced, thereby maintaining the potential of node N of the operational unit IM for a longer period. Furthermore, the channel length d4 of transistors M1 and M2 is preferably greater than the channel length d6 of transistor M3 and the channel length d7 of transistors M5 and M6. In other words, it is preferable that the channel length of the switching transistor is greater than the channel length of the amplifying transistor. By increasing the channel length d4 of transistors M1 and M2, the off-state current of transistors M1 and M2 can also be reduced, thereby maintaining the potential of node N of the operational unit IM for a longer period.

[0391] Furthermore, the channel length d6 of transistor M3 is preferably smaller than the channel length d4 of transistors M1 and M2. By shortening the channel length d6 of transistor M3, the on-state current of transistor M3 can be increased. Similarly, the channel length d8 of transistors M5 and M6 is preferably smaller than the channel length d4 of transistors M1 and M2. By shortening the channel length d8 of transistors M5 and M6, the on-state current of transistors M5 and M6 can be increased. In other words, the channel length of the amplifying transistors (transistors M3, M5, and M6 mentioned above) is preferably smaller than the channel length of the switching transistors (transistors M1 and M2 mentioned above).

[0392] Note that since transistor M4 is used as a clamping transistor, the channel length d10 of transistor M4 is preferably greater than the channel length d6 of transistor M3. By making the channel length d10 of transistor M4 greater than the channel length d6 of transistor M3, DIBL of transistor M3 can be prevented. Furthermore, even if the channel length d10 of transistor M4 is less than or equal to the channel length d6 of transistor M3, DIBL of transistor M3 can sometimes still be prevented. Additionally, in transistor M4, to prevent a decrease in the amount of current flowing between the source and drain of transistor M3, the channel width d9 of transistor M4 is preferably greater than the channel width d5 ​​of transistor M3. Furthermore, even if the channel width d9 of transistor M4 is less than or equal to the channel length d5 ​​of transistor M3, a decrease in the amount of current flowing between the source and drain of transistor M3 can sometimes still be prevented.

[0393] Note that the above also applies to transistors M1d to M6d of the drive unit IMD.

[0394] In addition, Figure 12 and Figure 13 In the planar schematic diagram, capacitors C1, C2, C1d, and C2d are all planar capacitors, but they can also be replaced with the latter. Figure 34A The cross-sectional schematic diagram shows a pair of electrodes and a dielectric capacitor embedded in the opening of the insulating layer.

[0395] In addition, Figure 12 and Figure 13 In the plan view, wiring XCL, wiring WSL, wiring VEI, wiring VED, wiring VES, and wiring VEG are placed below wiring WCL, wiring VEL, and wiring VEB, but there are no particular restrictions on the vertical relationship of the wiring. For example, one or more of wiring XCL, wiring WSL, wiring VEI, wiring VED, wiring VES, and wiring VEG can be placed above wiring WCL, wiring VEL, and wiring VEB. Furthermore, one or more of the above wirings can be placed vertically (approximately perpendicular to the direction shown in the plan view) instead of in the planar direction shown in the plan view. For example, in... Figure 12 or Figure 13 In this process, the aforementioned wiring can be formed using a conductive layer that can be formed in the longitudinal direction, such as a plug.

[0396] <Example 2 of the structure of an arithmetic device> Figure 1 The shown computing device CDV includes one computing circuit CC, but the number of computing circuits CC can also be two or more. Additionally, Figure 1 The arithmetic circuit CC shown includes one arithmetic unit IM, but the number of arithmetic units IM can also be two or more.

[0397] Figure 15 The shown computing device CDVA is Figure 1 A variant example of the CDV computing device, and Figure 1 The difference between the computing device CDV and the former is that the former includes a cell array CA in which multiple computing circuits CC are arranged in the column direction, and the computing circuit includes multiple computing units IM; etc.

[0398] exist Figure 15 In the array CA, the cell array includes arithmetic circuits CC_1 to CC_m (where m is an integer greater than or equal to 1). Furthermore, each of the arithmetic circuits CC_1 to CC_m includes a driver unit IMD and n (where n is an integer greater than or equal to 1) arithmetic units IM. As described above, in the cell array CA, m driver units IMD are arranged in the column direction, and the arithmetic units IM are arranged in an m×n matrix.

[0399] Note that in Figure 15 In the case of arithmetic units IM focusing only on the cell array CA, the sign of the arithmetic unit IM located at the address of row i, column j (where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) is appended with [i, j]. Furthermore, arithmetic units IM[1, 1] to IM[m, n] have the same characteristics as... Figure 1 The circuit structure of the arithmetic unit IM shown is the same. The circuit structures of arithmetic units IM[1,1] to IM[m,n] can be referred to. Figure 1 Description of the IM (Input / Output Unit).

[0400] In addition, Figure 15 In the case of focusing only on the driver unit IMD of the cell array CA, the symbol of the driver unit IMD located at the address of the i-th row is appended with _i. Furthermore, driver units IMD_1 to IMD_m have the same characteristics as... Figure 1 The circuit structure of the driving unit IMD shown is the same. The circuit structures of driving units IMD_1 to IMD_m can be referred to. Figure 1 Description of the drive unit IMD.

[0401] in addition, Figure 15 The drive circuit WCD in the computing device CDVA includes corresponding Figure 1 The circuits WCDa_1 to WCDa_n and the corresponding circuits WCDa_n Figure 1 Switches SA_1 to SA_n are the switches of SA.

[0402] in addition, Figure 15 The drive circuit XCD in the computing device CDVA includes corresponding to Figure 1The circuits XCDa_1 to XCDa_m.

[0403] in addition, Figure 15 The drive circuit WSD in the CDVA computing device corresponds to Figure 1 The driving circuit WSD. Therefore, the driving circuit WSD can send selection signals to the arithmetic unit IM and the driving unit IMD configured in one of the rows selected from the first row to the m-th row of the cell array CA, and can send non-selection signals to the arithmetic unit IM and the driving unit IMD configured in other rows.

[0404] in addition, Figure 15 The drive circuit ITS in the CDVA (Computational Device for Arithmetic Vehicles) includes corresponding to Figure 1 The circuits ITSa_1 to ITSa_n and the corresponding circuits ITSa_n Figure 1 Switches SB_1 to SB_n are the switches of SB_1.

[0405] Figure 15 The wiring WCL_1 to wiring WCL_n shown are corresponding to Figure 1 The wiring of the WCL extends along the column direction of the cell array CA. Additionally, Figure 15 The wiring IWL_1 to wiring IWL_n shown are corresponding to Figure 1 IWL wiring Figure 15 The wiring OL_1 to wiring OL_n shown are corresponding to Figure 1 The wiring of OL.

[0406] Wiring IWL_j is connected to the input terminal of circuit WCDa_j, the output terminal of circuit WCDa_j is connected to the first terminal of switch SA_j, and the second terminal of switch SA_j is connected to wiring WCL_j. Furthermore, wiring WCL_j is connected to each of the arithmetic units IM[1,j] to IM[m,j] arranged in column j of cell array CA, and to the first terminal of switch SB_j. Additionally, the second terminal of switch SB_j is connected to the input terminal of circuit ITSa_j, and the output terminal of circuit ITSa_j is connected to wiring OL_j. Furthermore, the control terminal of switch SA_j is connected to wiring SWLA, and the control terminal of switch SB_j is connected to wiring SWLB.

[0407] Figure 15 The wiring XCL_1 to wiring XCL_m shown are corresponding to Figure 1 The routing of the XCL extends in the row direction of the cell array CA. Additionally, Figure 15 The wiring IXL_1 to wiring IXL_m shown are corresponding to Figure 1 The routing of the IXL. Additionally... Figure 15 The wiring WSL_1 to wiring WSL_m shown are corresponding to Figure 1 The wiring of WSL extends in the row direction of the cell array CA.

[0408] The wiring IXL_i is connected to the input terminal of the circuit XCDa_i, and the output terminal of the circuit XCDa_i is connected to the wiring XCL_i. The wiring XCL_i is connected to each of the driving unit IMD_i, the arithmetic unit IM[i,1] to the arithmetic unit IM[i,n] configured in the i-th row of the cell array CA.

[0409] In the driving unit IMD_i (not shown), the gates of transistors M1d and M2d are connected to wiring WSL_i. Additionally, the second terminal of capacitor C1d, the second terminal of transistor M2d, and the first terminal of transistor M3d are connected to wiring XCL_i.

[0410] In the arithmetic unit IM[i,j] (not shown), the gates of transistors M1 and M2 are connected to wiring WSL_i. Additionally, the second terminal of capacitor C1 is connected to wiring XCL_i. Furthermore, the second terminal of transistor M2 and the first terminal of transistor M3 are connected to wiring WCL_j.

[0411] Next, explain the... Figure 15 The first data is written to the CDVA computing device, and the first data is multiplied by the second data.

[0412] exist Figure 15 In the arithmetic device CDVA, when writing first data to each of the arithmetic units IM[1,1] to IM[m,n], the current corresponding to the reference data r[i] flows from each of the circuits XCDa_1 to XCDa_m through the driving units IMD_1 to IMD_m.

[0413] Furthermore, during this period, each of the arithmetic units IM[1,1] to IM[m,n] is written as first data to W[1,1] to W[m,n]. Specifically, for example, the current corresponding to each of W[1,1] to W[m,1] generated by circuit WCDa_1 flows sequentially through each of the arithmetic units IM[1,1] to IM[m,1] arranged in the first column. Similarly, the current corresponding to each of W[1,n] to W[m,n] generated by circuit WCDa_n flows sequentially through each of the arithmetic units IM[1,n] to IM[m,n] arranged in the nth column. Note that the writing operation can be referred to Figure 1 Description of the CDV (Computing Device).

[0414] After each of the arithmetic units IM[1,1] to IM[m,n] is written as first data into W[1,1] to W[m,n], the second data X[1] to X[m] are sent to the driving units IMD and arithmetic units IM of each row by circuits XCDa_1 to XCDa_m. Thus, the multiplication operation between the held first data and the sent second data is performed in each of the arithmetic units IM[1,1] to IM[m,n]. For example, the multiplication operation between W[i,j] and X[i] is performed in the arithmetic unit IM[i,j].

[0415] Additionally, in the j-th column of the cell array CA, the current corresponding to the sum of the multiplication results obtained from operations performed on each of the arithmetic units IM[1,j] to IM[m,j] flows through the wiring WCL_j. Specifically, the current flowing through wiring WCL_j is I. S When [j], I S [j] can be represented by the following formula (1.13).

[0416] [Equation 12] .

[0417] Therefore, the current I flowing through wiring WCL_j S When [j] flows through circuit ITSa_j, circuit ITSa performs the operation corresponding to I. S The function [j] performs operations on the value Z[j] of the function and outputs Z[j] to the wiring OL_j.

[0418] Therefore, Z[j] can be expressed using the above formula (1.13) as the following formula (1.14). Thus, by configuring the operation unit IM as an m×n matrix, the product sum operation of the first data W[1,j] to W[m,j] and the second data X[1] to X[m] and the corresponding function calculation can be performed in the j-th column of the cell array CA. Furthermore, Figure 15 The CDVA's arithmetic unit IM is configured with n columns, thus enabling it to perform n product sum operations and corresponding function operations based on the results.

[0419] [Equation 13] .

[0420] In addition, Z[j] is output to the outside through wiring OL_j.

[0421] In particular, the computing device CDVA can appropriately perform operations on fully associative layer neural networks. For example, by using the values ​​of the input signals of neurons—which are first data (weight coefficients) and wiring XCL (second data inputs) in each of the computing units IM of the cell array CA of the computing device CDVA—the product of the weight coefficients and the input signals of the neurons can be performed. Furthermore, by using a computing circuit that employs the activation function for a fully associative layer neural network as the circuit ITSa_j, the value of the activation function, with the result of this product operation as its input value, can be output. This value can then be input to the next hidden layer, output layer, etc.

[0422] Furthermore, the computing device CDVA can also appropriately perform convolutional neural network operations. In particular, the computing unit IM of the cell array CA of the computing device CDVA can hold the first data for a long time, so the first data is preferably the filtered value used for convolution processing. In the convolution processing of a convolutional neural network, the same filtered value is multiplied by multiple image data, so it can be said that the computing unit IM of the computing device CDVA is suitable as a multiplication unit that can hold the filtered value for a long time.

[0423] <Example 3 of the structure of an arithmetic device> Next, a computing device according to one aspect of the present invention, which differs from computing devices CDV and CDVA, will be described.

[0424] Figure 16 This is a circuit diagram showing the circuit structure of an arithmetic device CDVB, which is different from arithmetic devices CDV and CDVA. The arithmetic device CDVB is an arithmetic device capable of performing multiplication of a first data and a second data, wherein the first data is 0, a negative number, or a positive number, and the second data is 0 or a positive number.

[0425] exist Figure 16 In the cell array CA, the driving unit IMD_i located in the i-th row and the arithmetic unit IM[i,j] located in the i-th row and j-th column are shown. However, in the description of the arithmetic device CDVB in this specification, unless otherwise stated, they are referred to as the driving unit IMD and the arithmetic unit IM respectively.

[0426] In the CDVB arithmetic unit, unlike the CDVA arithmetic unit, the arithmetic unit IM includes transistors M1p, M2p, M3p, capacitors C1p and C2p, amplifier circuit SF, transistors M1n, M2n, M3n, capacitors C1n and C2n, and amplifier circuit SFn. In other words, the number of circuit elements included in the arithmetic unit IM in the CDVB arithmetic unit is... Figure 1 The number of circuit elements included in the arithmetic unit IM in the arithmetic device CDV varies.

[0427] Transistor M1p and transistor M1n correspond to Figure 1 Transistors M1, M2p, and M2n in the CDV computing device correspond to Figure 1 Transistors M2, M3p, and M3n in the CDV computing device correspond to Figure 1 Transistor M3 in the CDV computing device. Additionally, capacitors C1p and C1n correspond to... Figure 1 The capacitors C1, C2p, and C2n in the CDV computing device correspond to Figure 1 The capacitor C2 in the CDV arithmetic unit. Additionally, the amplifier circuits SFp and SFn correspond to... Figure 1 The amplifier circuit SF in the CDV computing device.

[0428] Therefore, the arithmetic unit IM in the CDVB includes two Figure 1 The computing unit IM in the CDV computing device. Specifically, transistors M1p, M2p, and M3p, capacitors C1p and C2p, and amplifier circuit SF constitute a... Figure 1 The computing unit IM in the CDV computing device, and transistors M1n, M2n, M3n, capacitors C1n and C2n, and amplifier circuit SFn constitute a... Figure 1 The computing unit IM in the computing device CDV.

[0429] Therefore, the arithmetic unit IM in the arithmetic device CDVB can hold two data.

[0430] Here, the value of the first data held by the arithmetic unit IM is defined as follows.

[0431] When the arithmetic unit IM is written with a positive first data value α, the current flowing through the source and drain of transistor M3p in the arithmetic unit IM is set to |α|×I0. At this time, the potential between the first terminal of capacitor C1p and the gate of transistor M3p is determined according to the current flowing through the source and drain |α|×I0. Furthermore, the current flowing through the source and drain of transistor M3n in the arithmetic unit IM is set to 0. Note that I0 is the current flowing when the absolute value of the first data (which is α[i,j] in this case) is 1, and is the I0 described in the example of the operation of the arithmetic device CDV.

[0432] When the arithmetic unit IM is written with a negative first data value α, the current flowing through the source and drain of transistor M3n in the arithmetic unit IM is set to |α|×I0. At this time, the potential between the first terminal of capacitor C1n and the gate of transistor M3n is determined according to the current flowing through the source and drain |α|×I0. Furthermore, the current flowing through the source and drain of transistor M3p in the arithmetic unit IM is set to 0.

[0433] In addition, when the arithmetic unit IM is written with 0 as the first data, the current between the source and drain of transistors M3p and M3n flowing through the arithmetic unit IM is set to 0.

[0434] Note that when the current flowing through the source and drain of transistor M3p in the operational unit IM is set to 0, this specification sometimes states that 0 current flows between the source and drain of transistor M3p. Similarly, when the current flowing through the source and drain of transistor M3n in the operational unit IM is set to 0, this specification sometimes states that 0 current flows between the source and drain of transistor M3n.

[0435] As described above, the arithmetic unit IM in the arithmetic device CDVB can maintain the first data corresponding to the potentials of capacitor C1p and the first terminal of capacitor C1n, respectively. Because different potentials need to be written to the first terminals of capacitors C1p and C1n, the arithmetic unit IM requires two wirings for transmitting data (used as wiring WCL in the arithmetic device CDVB). The arithmetic device CDVB includes wiring WCLp and wiring WCLn as such wiring. Note that in... Figure 16 In the diagram, as a wiring extending into the j-th column, wiring WCLp is denoted as wiring WCLp_j, and wiring WCLn is denoted as wiring WCLn_j.

[0436] Wiring WCLp is connected to the first terminal of transistor M3p and the second terminal of transistor M2p, and wiring WCLn is connected to the first terminal of transistor M3p and the second terminal of transistor M2p.

[0437] Additionally, the drive circuit WCD of the arithmetic unit CDVB includes circuits WCDp and WCDn corresponding to circuit WCDa of the arithmetic unit CDV. Furthermore, the circuit SWCA included in the drive circuit WCD includes switches SAp and SAn corresponding to switch SA of the arithmetic unit CDV. Note that in Figure 16 In the diagram, switch SAp is configured as the switch in column j, and switch SAn is denoted as switch SAn_j.

[0438] Circuit WCDp has the function of allowing an analog current corresponding to the digital data input to wiring IWLp to flow through wiring VEL via the source and drain of wiring WCLp and transistor M3p. Similarly, circuit WCDn has the function of allowing an analog current corresponding to the digital data input to wiring IWLn to flow through wiring VEL via the source and drain of wiring WCLn and transistor M3n. Therefore, when α is a positive number as the first data, wiring IWLp is sent digital data of the value |α|, and wiring IWLn is sent 0 as digital data. Furthermore, when α is a negative number as the first data, wiring IWLp is sent 0 as digital data, and wiring IWLn is sent digital data of the value |α|. Additionally, when the first data is 0, both wiring IWLp and wiring IWLn are sent 0 as digital data.

[0439] In addition, when writing the first data to the arithmetic unit IM, the same as the operation method of the arithmetic device CDV, switches SAp and SAn are both in the on state, and switches SBp and SBn are both in the off state.

[0440] After holding the first data, the current corresponding to the second data flows through the wiring XCL, thereby enabling the arithmetic unit IM to perform a multiplication operation between the first and second data. In the arithmetic unit IM of the arithmetic device CDVB, the second terminals of capacitor C1p and capacitor C1n are input with potentials corresponding to the current. As a result, the current between the source and drain of transistor M3p increases due to the capacitive coupling of capacitor C1p, and the current between the source and drain of transistor M3n increases due to the capacitive coupling of capacitor C1n.

[0441] Here, the current corresponding to the second data is βI0. Furthermore, when the first data α is positive, the current Ip flowing between the source and drain of transistor M3p is αβI0, and the current In flowing between the source and drain of transistor M3n is 0. At this time, the current Ip flows from the terminal RTip of the circuit ITPn described later through the switch SBp and transistor M3p, through the wiring VEL.

[0442] Furthermore, when the first data α is negative, the current Ip flowing between the source and drain of transistor M3p is 0, and the current In flowing between the source and drain of transistor M3n is αβI0. At this time, the current In flows from the terminal RTin of the circuit ITSpn described later through the switch SBn and transistor M3n through the wiring VEL.

[0443] In addition, when sending multiplication data from the arithmetic unit IM to the drive circuit ITS, the switches SBp and SBn are in the open state, and the switches SAp and SAn are in the closed state, similar to the operation of the arithmetic device CDV.

[0444] The drive circuit ITS of the arithmetic unit CDVB includes circuit ITSpn corresponding to circuit ITSa of the arithmetic unit CDV. Additionally, the circuit SWCA included in the drive circuit ITS includes switch SBp and switch SBn corresponding to switch SB of the arithmetic unit CDV. Note that in... Figure 16 In the diagram, switch SBp is designated as switch SBp_j and switch SBn is designated as switch SBn_j, which are configured on the j-th column.

[0445] The circuit ITSpn includes terminals RTip, RTin, and RTo, and has the function of obtaining the difference between the current input to terminal RTip and the current input to terminal RTin, and outputting the data corresponding to the difference to terminal RTo.

[0446] Terminal RTip is connected to the second terminal of switch SBp, terminal RTin is connected to the second terminal of switch SBn, and terminal RTo is connected to wiring OL.

[0447] Here, when the cell array CA includes m rows of arithmetic circuits CC, the current corresponding to the product of a positive first data value and a second data value sent to each row flows through the terminal RTip of the circuit ITSpn, and the current corresponding to the product of a negative first data value and a second data value sent to each row flows through the terminal RTin of the circuit ITSpn. The circuit ITSpn can obtain the current corresponding to the product of the first and second data values ​​by taking the difference between the currents flowing through the wiring WCLp and the wiring WCLn, where the first data value is 0, negative, or positive, and the second data value is 0 or positive. Thus, the circuit ITSpn can convert or generate data based on this current and output it to the terminal RTo.

[0448] <<Circuit ITSpn>> Next, the circuit structure applicable to the circuit ITSpn will be described.

[0449] Figure 17 The circuit ITSpn shown has the function of obtaining the difference between the current flowing through wiring WCLp and wiring WCLn, and outputting this differential current as an analog current. Note that, as an example, Figure 17 The circuit shown, ITSpn, is a change Figure 6 The circuit structure of the circuit RL shown is described here. Figure 6 The differences between the circuit RL and the circuit RL.

[0450] Figure 17 The circuit ITSpn and Figure 6The difference between the circuit RL and the previous one is that the former does not have a current source CNI. Additionally, the terminal RTip of the circuit ITSpn corresponds to... Figure 6 The terminal RTi is shown. In addition, the first terminal of transistor Mp1o, the first terminal of transistor MN2i, the gate of transistor MN1i, and the gate of transistor MN1o are connected to the terminal RTi.

[0451] In the cell array CA, the current I is the product of the first data corresponding to a positive number and the second data sent to each row. Sp The current flows through terminal RTip. Note that this current flows through wiring WCLp. Furthermore, in the cell array CA, the current I is the sum of the product of the first data corresponding to a negative number and the second data sent to each row. Sn The current flows through terminal RTi. Note that this current flows through wiring WCLn.

[0452] Since transistors MP1i, MP2i, MP1o, and MP2o form a current mirror circuit, ideally, the current I flowing through terminal RTip should be... Sp This is equal to the current flowing between the sources and drains of transistors MP2o and MP1o. Furthermore, according to Kirchhoff's laws, I flows between the sources and drains of transistors MN2i and MN1i. Sp -I Sn (=I) S The amount of current. Note that in I Sp Less than I Sn At that time, Figure 17 In the circuit structure shown, I S It is 0.

[0453] Since transistors MN1i, MN2i, MN1o, and MN2o also constitute a current mirror circuit, ideally, the current I flowing through the source and drain of transistors MN2i and MN1i should be... S This is equal to the amount of current I flowing between the source and drain of transistors MN1o and MN2o. S .

[0454] Since transistors MP3i, MP4i, MP3o, and MP4o also constitute a current mirror circuit, ideally, the current I flowing between the source and drain of transistors MN3i and MN4i should be... S This is equal to the current I flowing between the source and drain of transistors MN3o and MN4o. S .

[0455] The result is that Figure 17 The circuit ITSpn outputs from terminal RTo as ISp with I Sn The differential current I S Therefore, the circuit ITSpn can output the product and sum of the cell array CA as an analog current.

[0456] Next, an explanation and Figure 17 The circuits ITSpn can be used for different purposes Figure 16 Example of the circuit structure of the CDV (Computational Device) circuit and the ITSpn circuit.

[0457] Figure 18 The circuit ITSpn shown has the function of obtaining the difference between the current flowing through wiring WCLp and wiring WCLn and outputting the value corresponding to that difference as digital data. Furthermore, Figure 18 The circuit ITSpn shown is sometimes referred to as a successive approximation register (SAR) type ADC (Analog to Digital Converter).

[0458] As an example Figure 18 The circuit ITSpn shown includes transistors MP5i, MP6i, MP5o and MP6o in the first current mirror circuit, and transistors MP7i, MP8i, MP7o and MP8o in the second current mirror circuit.

[0459] In addition, Figure 18 The circuit ITPn includes a first digital potential-to-analog current conversion circuit and a second digital potential-to-analog current conversion circuit. The first digital potential-to-analog current conversion circuit includes transistors Tp1[1] to Tp1[M] (M is an integer greater than or equal to 1) and transistors Tp2[1] to Tp2[M]. In addition, the second digital potential-to-analog current conversion circuit includes transistors Tn1[1] to Tn1[M] and transistors Tn2[1] to Tn2[M].

[0460] Note that transistor Tp1[s] (where s is an integer greater than 1 and less than M) and transistor Tp2[s] correspond to respectively Figure 4 The current source CS shown includes transistors Tr1 and Tr2. Additionally, transistors Tn1[s] and Tn2[s] correspond to... Figure 4Transistors Tr1 and Tr2 are shown in the current source CS. Therefore, transistors Tp1[1] to Tp1[M] and transistors Tn1[1] to Tn1[M] are used as transistors to allow a constant current corresponding to the channel width to flow. In addition, transistors Tp2[1] to Tp2[M] and transistors Tn2[1] to Tn2[M] are used as switching transistors.

[0461] Here, the channel widths of transistors Tp1[1] and Tn1[1] are w[1], the channel widths of transistors Tp1[2] and Tn1[2] are w[2], and the channel widths of transistors Tp1[M] and Tn1[M] are w[M]. The ratio of the channel widths is w[1]:w[2]:w[M] = 1:2:2 M-1 .

[0462] in addition, Figure 18 The circuit ITSpn includes a comparator CPR and a logic circuit LGC. The logic circuit LGC includes terminals LTi, LFTp, LFTn, and LTo.

[0463] The first terminal of transistor MP5i is connected to terminal RTip, the gate of transistor MP6i, the gate of transistor MP6o, and the first terminals of transistors Tp2[1] to Tp2[M]. The second terminal of transistor MP5i is connected to the first terminal of transistor MP6i, and the gate of transistor MP5i is connected to the gate of transistor MP5o and wiring RSWLp.

[0464] The first terminal of transistor MP7i is connected to terminal RTin, the gate of transistor MP8i, the gate of transistor MP8o, and the first terminals of transistors Tn2[1] to Tn2[M]. The second terminal of transistor MP7i is connected to the first terminal of transistor MP8i, and the gate of transistor MP7i is connected to the gate of transistor MP7o and wiring RSWLn.

[0465] For information on wiring RSWLp and RSWLn, please refer to [link / reference]. Figure 6 Description of wiring RSWL1 to wiring RSWL3 shown.

[0466] The first terminal of transistor MP5o is connected to the first terminal of comparator CPR, and the second terminal of transistor MP5o is connected to the first terminal of transistor MP6o. The first terminal of transistor MP7o is connected to the second terminal of comparator CPR, and the second terminal of transistor MP7o is connected to the first terminal of transistor MP8o. Additionally, the second terminals of transistors MP6i, MP6o, MP8i, and MP8o are each connected to wiring VDDL.

[0467] For information on routing VDDL, please refer to... Figure 6 The wiring VDDL shown is an explanation.

[0468] The second terminal of transistor Tp2[s] is connected to the first terminal of transistor Tp1[s]. Additionally, the gates of transistors Tp2[1] to Tp2[M] are connected to the terminal LFTp of the logic circuit LGC. Furthermore, the second terminals of transistors Tp1[1] to Tp1[M] are connected to wiring VSSL. Additionally, the gates of transistors Tp1[1] to Tp1[M] are connected to wiring VFE.

[0469] The second terminal of transistor Tn2[s] is connected to the first terminal of transistor Tn1[s]. Additionally, the gates of transistors Tn2[1] to Tn2[M] are connected to the terminal LFTn of the logic circuit LGC. Furthermore, the second terminals of transistors Tn1[1] to Tn1[M] are connected to wiring VSSL. Additionally, the gates of transistors Tn1[1] to Tn1[M] are connected to wiring VFE.

[0470] For information on VSSL cabling, please refer to [link / reference]. Figure 6 The diagram shows the VSSL wiring configuration. Additionally, for information on VFE wiring, please refer to... Figure 4 The diagram shows the wiring BIS.

[0471] The output terminal of comparator CPR is connected to terminal LTi of logic circuit LGC, and terminal LTo of logic circuit LGC is connected to terminal RTo. Additionally, the current I input to the second input terminal... FSn Less than the current I input to the first input terminal FSp In the case of and the current I input to the first input terminal FSp With the current I input to the second input terminal FSn When the values ​​are equal, the comparator CPR has the function of outputting a high-level potential to the output terminal, or when the current I input to the second input terminal is equal. FSn Greater than the current I input to the first input terminal FSp In this case, the comparator CPR has the function of outputting a low-level potential to the output terminal.

[0472] The logic circuit LGC has the following functions: obtaining the comparison result of comparator CPR from terminal LTi, outputting digital signal Q to terminals LFTp and LFTn according to the comparison result; and outputting digital data to terminal LTo according to the comparison result.

[0473] Next, the detailed operation of the logic circuit LGC will be explained. Figure 18 Example of the operation of the circuit ITSpn.

[0474] Figure 19 It is shown Figure 18 Timing diagram of an example of the operation of the circuit ITSpn. Figure 19 The timing diagram shows the current I input to terminal RTip. Sp The current I is greater than the current input to terminal RTi. Sn This is an example of operation, and the timing diagram shows the current I during the period from T0 to T9. FSp and current I FSn The current, the potential change at terminal LTi in the logic circuit LGC, and the logic change of the signal Q output from terminal LFTp. Note that the current I... FSp It is the amount of current input to the first input terminal of the comparator CPR, the current I. FSn It is the amount of current input to the second input terminal of the comparator CPR.

[0475] Note that in Figure 19 In the timing diagram, Figure 18 The ordinal number M recorded in the circuit ITSpn is set to 8. In this case, the resolution of the first digital potential-to-analog current conversion circuit and the second digital potential-to-analog current conversion circuit is 8 bits. In addition, the current output by the first digital potential-to-analog current conversion circuit and the second digital potential-to-analog current conversion circuit is, for example, in the range of 0nA to 255nA in steps of 1nA.

[0476] Additionally, the b-th bit (b is an integer greater than 0 and less than 7) of the digital signal Q output from the logic circuit LGC to terminals LFTp and LFTn is logically represented as Q[b].

[0477] During period T0, the logic circuit LGC outputs (00000000)2 as 8-bit digital signals Qp and Qn to terminals LFTp and LFTn. Consequently, the gates of transistors Tp2[1] to Tp2[8] in the first digital-to-analog current conversion circuit are input with a low-level potential, and these transistors become off. Similarly, the gates of transistors Tn2[1] to Tn2[8] in the second digital-to-analog current conversion circuit are input with a low-level potential, and these transistors become off.

[0478] At this time, the quantity I from the cell array CA Sp The current flowing through the terminal RTip, the amount I from the cell array CA Sn The current flows through terminal RTi. Note that here, I... Sp =203nA, I Sp =150nA. At this time, the quantity I SpThe current flows through the first input terminal of the comparator CPR, and the quantity I Sn The current flows through the second input terminal of the comparator CPR. At this time, due to I... FSp Greater than I FSn Therefore, the comparator CPR outputs a high-level potential to its output terminal. Consequently, the LTi terminal of the logic circuit LGC receives this high-level potential.

[0479] During period T1, the logic circuit LGC outputs (10000000)2 as an 8-bit digital signal Qp to terminal LFTp. That is, the logic of the 7th bit of the digital signal Qp changes from "0" to "1". As a result, only the gate of transistor Tp2[8] of the first digital potential-analog current conversion circuit is input with a high level potential, and a current of 128nA flows from the first terminal of transistor MP5i through the source and drain of transistors Tp1[8] and Tp2[8] through the wiring VSSL. As a result, I FSp =203-128=75nA, which is lower than I FSn =150nA, therefore the output terminal of comparator CPR outputs a low-level potential. Consequently, the terminal LTi of logic circuit LGC is input with this low-level potential.

[0480] During period T1, when the potential of terminal LTi changes from its initial potential, the logic of bit 7 of digital signal Qp, Q[7], is set to "0" after period T1. Conversely, when the potential of terminal LTi does not change from its initial potential, the logic of bit 7 of digital signal Qp, Q[7], is set to "1" after period T1. In this example, the logic of Q[7] after period T1 is "0".

[0481] During period T2, the logic circuit LGC outputs an 8-bit digital signal Qp ((01000000)2) to terminal LFTp. That is, in the digital signal Qp, the logic of the 7th bit changes from "1" to "0", and the logic of the 6th bit changes from "0" to "1". As a result, only the gate of transistor Tp2[7] of the first digital potential-analog current conversion circuit is input with a high level potential, and a current of 64nA flows from the first terminal of transistor MP5i through the source and drain of transistors Tp1[7] and Tp2[7] through the wiring VSSL. As a result, I FSp =203-64=139nA, which is lower than I FSn =150nA, therefore the output terminal of comparator CPR outputs a low-level potential. Consequently, the terminal LTi of logic circuit LGC is input with this low-level potential.

[0482] During period T2, when the potential of terminal LTi changes from its initial potential, the logic of bit 6 of digital signal Qp, Q[6], is set to "0" after period T2. Conversely, when the potential of terminal LTi does not change from its initial potential, the logic of bit 6 of digital signal Qp, Q[6], is set to "1" after period T2. In this example, the logic of Q[6] after period T2 is "0".

[0483] During period T3, the logic circuit LGC outputs (00100000)2 as an 8-bit digital signal Qp to terminal LFTp. That is, in the digital signal Qp, the logic of the 6th bit changes from "1" to "0", and the logic of the 5th bit changes from "0" to "1". As a result, only the gate of transistor Tp2[6] of the first digital potential-analog current conversion circuit is input with a high level potential, and a current of 32nA flows from the first terminal of transistor MP5i through the source and drain of transistors Tp1[6] and Tp2[6] through the wiring VSSL. As a result, I FSp =203-32=171nA, which is higher than I FSn =150nA, therefore the output terminal of comparator CPR outputs a high-level potential. Consequently, the terminal LTi of logic circuit LGC is input with this high-level potential.

[0484] During period T3, when the potential of terminal LTi changes from its initial state, the digital signal Q is then... p The logic of the 5th bit Q[5] is set to "0". Additionally, when the potential of terminal LTi remains unchanged from its initial state, after period T3, the digital signal Q is... p The logic of the 5th bit Q[5] is set to "1". In this working example, the logic of Q[5] after period T3 is "1".

[0485] During period T4, the logic circuit LGC outputs (00110000)2 as an 8-bit digital signal Qp to terminal LFTp. That is, in the digital signal Qp, the logic of the 4th bit changes from "0" to "1". As a result, only the gates of transistors Tp2[6] and Tp2[5] of the first digital potential-analog current conversion circuit are input with a high level potential, and a current of 32+16=48nA flows from the first terminal of transistor MP5i through wiring VSSL. As a result, I FSp =203-48=155nA, which is higher than I FSn =150nA, therefore the output terminal of comparator CPR outputs a high-level potential. Consequently, the terminal LTi of logic circuit LGC is input with this high-level potential.

[0486] During period T4, when the potential of terminal LTi changes from its initial state, the digital signal Q is then... p The logic of the 4th bit Q[4] is set to "0". In addition, when the potential of terminal LTi does not change from the initial potential, the logic of the 4th bit Q[4] of digital signal Q is set to "1" after period T4. In this working example, the logic of Q[4] after period T4 is "1".

[0487] During T5, the logic circuit LGC outputs (00111000)2 as an 8-bit digital signal Qp to terminal LFTp. That is, in the digital signal Qp, the logic of the 3rd bit changes from "0" to "1". As a result, only the gates of transistors Tp2[4] to Tp2[6] of the first digital potential-analog current conversion circuit are input with a high level potential, and a current of 32+16+8=56nA flows from the first terminal of transistor MP5i through wiring VSSL. As a result, I FSp =203-56=147nA, which is lower than I FSn =150nA, therefore the output terminal of comparator CPR outputs a low-level potential. Consequently, the terminal LTi of logic circuit LGC is input with this low-level potential.

[0488] During period T5, when the potential of terminal LTi changes from its initial state, the digital signal Q is then... p The logic of the third bit Q[3] is set to "0". In addition, when the potential of terminal LTi does not change from the initial potential, the logic of the third bit Q[3] of digital signal Q is set to "1" after period T5. In this working example, the logic of Q[3] after period T5 is "0".

[0489] During T6, the logic circuit LGC outputs (00110100)2 as an 8-bit digital signal Qp to terminal LFTp. That is, in the digital signal Qp, the logic of the 3rd bit changes from "1" to "0", and the logic of the 2nd bit changes from "0" to "1". As a result, only the gates of transistors Tp2[6], Tp2[5] and Tp2[3] of the first digital potential-analog current conversion circuit are input with a high level potential, and a current of 32+16+4=52nA flows from the first terminal of transistor MP5i through wiring VSSL. As a result, I FSp =203-52=151nA, which is higher than I FSn =150nA, therefore the output terminal of comparator CPR outputs a high-level potential. Consequently, the terminal LTi of logic circuit LGC is input with this high-level potential.

[0490] During period T6, when the potential of terminal LTi changes from its initial state, the digital signal Q is then... p The logic of the second bit Q[2] is set to "0". In addition, when the potential of terminal LTi does not change from the initial potential, the logic of the second bit Q[2] of digital signal Q is set to "1" after period T6. In this working example, the logic of Q[2] after period T6 is "1".

[0491] During T7, the logic circuit LGC outputs (00110110)2 as an 8-bit digital signal Qp to terminal LFTp. That is, in the digital signal Qp, the logic of the first bit changes from "0" to "1". As a result, only the gates of transistors Tp2[6], Tp2[5], Tp2[3] and Tp2[2] of the first digital potential-analog current conversion circuit are input with a high level potential, and a current of 32+16+4+2=54nA flows from the first terminal of transistor MP5i through wiring VSSL. As a result, I FSp =203-54=149nA, which is lower than I FSn =150nA, therefore the output terminal of comparator CPR outputs a low-level potential. Consequently, the terminal LTi of logic circuit LGC is input with this low-level potential.

[0492] During period T7, when the potential of terminal LTi changes from its initial state, the digital signal Q is then... p The logic of the first bit Q[1] is set to "0". In addition, when the potential of terminal LTi does not change from the initial potential, the logic of the first bit Q[1] of digital signal Q is set to "1" after period T7. In this example, the logic of Q[1] after period T7 is "0".

[0493] During T8, the logic circuit LGC outputs (00110101)2 as an 8-bit digital signal Qp to terminal LFTp. That is, in the digital signal Qp, the logic of the 0th bit changes from "0" to "1". As a result, only the gates of transistors Tp2[6], Tp2[5], Tp2[3] and Tp2[1] of the first digital potential-analog current conversion circuit are input with a high level potential, and a current of 32+16+4+1=53nA flows from the first terminal of transistor MP5i through wiring VSSL. As a result, I FSp =203-53=150nA, which is the same as I FSn =150nA, therefore the output terminal of comparator CPR outputs a high level potential. As a result, the terminal LTi of logic circuit LGC is input with this high level potential.

[0494] During period T8, when the potential of terminal LTi changes from its initial state, the digital signal Q is then... p The logic of bit 0, Q[0], is set to "0". Additionally, when the potential of terminal LTi remains unchanged from its initial state, the logic of bit 0, Q[0], of the digital signal Q is set to "1" after period T8. In this example, the logic of Q[0] after period T8 is "1".

[0495] During period T9, the logic circuit LGC outputs an 8-bit digital signal Qp (00000000) 2 at terminal LFTp. Therefore, there is no current supply from the first digital potential-to-analog current conversion circuit, and thus I... FSp =203nA. This result is higher than I. FSn =150nA, therefore the output terminal of comparator CPR outputs a high-level potential.

[0496] Additionally, during period T9, the LTo terminal of the logic circuit LGC outputs the digital signal Qp (00110101)2. This is to... Sp =203nA and I Sn The 53nA of the differential current of 150nA is obtained by converting it into digital data.

[0497] As described above, by making Figure 18 When the circuit ITSpn is working, it can output I. Sp with I Sn The differential current is used as digital data. It can be converted.

[0498] Note that the above working example assumes I Sp Greater than I Sn In the case of I Sn Greater than I Sp In such cases, the meaning can be understood by appropriately replacing the wording.

[0499] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0500] (Implementation Method 2) In this embodiment, a convolutional neural network, one type of artificial neural network, is described. Furthermore, by using the computing device described in the above embodiment, it is possible to perform operations on a convolutional neural network.

[0501] As an example of a convolutional neural network, let's illustrate AlexNet. AlexNet is... Figure 20 The artificial neural network model shown, AlexNet, includes an input layer INLY, convolutional layers CNV1 to CNV5, pooling layers PL1, PL2, PL5, and fully connected layers FC6 to FC8. Additionally, as... Figure 20 As shown, AlexNet consists of an input layer INLY, a convolutional layer CNV1, a pooling layer PL1, a convolutional layer CNV2, a pooling layer PL2, a convolutional layer CNV3, a convolutional layer CNV4, a convolutional layer CNV5, a pooling layer PL5, a fully connected layer FC6, a fully connected layer FC7, and a fully connected layer FC8.

[0502] [Input Layer INLY] As input to AlexNet, the input layer INLY is, for example, fed a 224×224 pixel image P. in Note that a pixel includes red, green, and blue subpixels, and the total number of subpixels is three colors (red, green, and blue) × 224 × 224. Additionally, image P... in The image has three channels: red, green, and blue. Therefore, image P... in The amount of image data included in the INLY input layer is 3×224×224.

[0503] Note that in this example, image P in The input value in the x-th row and y-th column of the z-th input channel (where z is an integer greater than 1 and less than 3) is recorded as p. in [x, y, z]. Note that x represents the image P. in The line address, y represents the image P in The column address. In other words, in the input layer INLY, x is an integer greater than 1 and less than 2^24, and y is an integer greater than 1 and less than 2^24.

[0504] [Convolutional layer CNV1] In the convolutional layer CNV1, for image P in Convolution processing is performed. Specifically, a filter (also called a convolution kernel) for the convolution process CNV1 is applied to the image P. in Region A in in The product and sum operation of the included image data.

[0505] In the convolutional layer CNV1, the filter size (also known as the kernel size) is set to 11, the number of output channels (also known as the number of kernels) is set to 96, and the stride is set to 4. This applies to images selected from P. inThe region within the data is subjected to convolution processing. Furthermore, the number of filtered values ​​in a single convolution kernel is (filter size). 2 × (Number of input channels). Due to image P in The number of input channels is 3, and the number of filtered values ​​in one convolutional kernel of the convolutional layer CNV1 is 11×11×3=363.

[0506] Here, the s-th convolutional kernel in the CNV1 convolutional layer (where s is an integer greater than 1 and less than 96) is denoted as K. C1 （s） Additionally, the convolution kernel K... C1 The included filter values ​​are recorded as k. C1 （s） [p, q, r]. Note that p represents the row address of the convolution kernel, q represents the column address of the convolution kernel, and r represents the ordinal number of the input channel. In other words, in the convolutional layer CNV1, p is an integer greater than or equal to 1 and less than 11, q is an integer greater than or equal to 1 and less than 11, and r is an integer greater than or equal to 1 and less than 3.

[0507] For example, Figure 21 The image P is shown as being selected from the image. in Region A in in (1) with convolution kernel K C1 （1） Perform a product sum operation and output the data p as the result. C1 （1） Example of (1). Region A in (x) where x represents the image selected from P. in The ordinal number of the region in the data. Additionally, data p... C1 （s） In (x), s represents the ordinal number of the output channel. Additionally, the data p... C1 （s） x in (x) corresponds to region A in The ordinal number x of (x).

[0508] Additionally, since the step size is 4, it will start from region A. in (1) The region that drifts 4 in the direction of movement is called region A. in (2). For example, Figure 22 The image P is shown as being selected from the image. in Region A in in (2) with convolution kernel K C1 （1） Perform a product sum operation and output the data p as the result. C1 （1） (2) is an example.

[0509] Note that in image P in Given an image P with a pixel count of 224×224 and a step size of 4, the image selected is...in The number of regions is 3025 (=55) 2 In this embodiment, they will be referred to as region A. in (1) To region A in (3025).

[0510] As described above, the selection from image P is sequentially made according to the step size. in In the context of region drift, whenever a region drift is caused, the region is compared with the convolution kernel K. C1 （1） The product and sum operations yield a matrix-like output data of 55 rows and 55 columns. Furthermore, the convolution kernel in the CNV1 convolutional layer is kernel K. C1 （1） To convolution kernel K C1 （96） (The number of kernels in convolutional layer CNV1 is 96), therefore the result is P, which is the output data of convolutional layer CNV1 as 55×55×96. C1 .

[0511] Here, in the convolution process of the CNV1 convolution layer, a convolution kernel is used to perform a convolution with the kernel selected from the image P. in The product and sum operation is performed on each of the multiple regions in the image P. Therefore, as a structure of the arithmetic circuit, it is preferable to perform the filtering values ​​included in a convolution kernel together with those selected from the image P. in The operation of the product of each of the data included in the middle region.

[0512] For example, in Figure 15 In the structure of the computing device CDVA shown, the preferred first data is the convolution kernel K. C1 （1） The 11×11×3=363 filter values ​​are written into the first column of the cell array CA, specifically into the operation units IM[1,1] to IM[m,1] (where m is an integer greater than or equal to 11×11×3=363). Furthermore, it is preferable to input the values ​​from image P into circuits XCDa_1 to XCDa_m respectively. in Selected area A in (1). Therefore, convolution kernel K can be performed. C1 （1） With region A in (1) Product and sum operation. At this time, circuits ITSa_1 to ITSa_n of the drive circuit ITS preferably perform identity function operations as activation functions. In other words, circuit ITSa preferably has the function of outputting a value that is the same as the value input to the input terminal to the output terminal. In addition, circuit ITSa can output this value as current or voltage to the output terminal.

[0513] Furthermore, the above description focuses on the computational units IM[1,1] to IM[m,1] of the first column of the cell array CA, but filter values ​​from other convolutional kernels can be written to columns other than the first column. For example, in Figure 15 In the structure of the shown computing device CDVB, the kernel K is preferably the one corresponding to the convolution kernel. C1 （j） (Here, j is an integer greater than 1 and less than 96) The filtered value is written to each of the operation units IM[1, j] to IM[m, j] configured in the j-th column of the cell array CA. That is to say, it can be used Figure 15 The shown computing device CDVB writes filtered values ​​of different convolution kernels column-by-column. Therefore, the number of columns n of the cell array CA is preferably 96 or more. Thus, for example, it is possible to simultaneously process region A, which is input as second data. in (1) Convolution kernel K that is preserved by column C1 （1） To K C1 （96） The product and sum of the filtered values ​​are calculated.

[0514] In addition, Figure 15 In the arithmetic unit CDVA, each of the circuits XCDa_1 to XCDa_m is sequentially input into region A. in (1) To region A in (3025) allows for convolution kernel K. C1 （1） To K C1 （96） The product and summation operation of each with each region.

[0515] For example, consider Figure 23 The shown arithmetic units IM are configured as a 363×96 matrix array CA. For each arithmetic unit IM[1,1] to arithmetic unit IM[363,1] located in the first column of the array CA, k is written respectively. C1 （1） [1, 1, 1] to k C1 （1） [11, 1, 3] is used as the convolution kernel K C1 （1） The filtered value. Additionally, k is written to each of the arithmetic units IM[1, 96] to IM[363, 96] configured in the 96th column of the cell array CA. C1 （96） [1, 1, 1] to k C1 （96） [11, 1, 3] is used as the convolution kernel K C1 （96）The filtered value. Note that each of the second through 95th columns of the cell array CA is also written into the convolution kernel K in the same way. C1 （2） To K C1 （96） .

[0516] Then, by inputting a for each of routing XCL_1 to routing XCL_363 respectively. in (1) [1, 1, 1] to a in (1) [11, 11, 3] as region A in (1) values ​​are used to output the convolution kernel K from the wiring WCL_1. C1 （1） With region A in The product sum result p of (1) c1 （1） (1), and output convolution kernel K from wiring WCL_96. C1 （96） With region A in The product sum result p of (1) c1 （96） (1).

[0517] Next, input the data into area A, from wiring XCL_1 to wiring XCL_363. in (1) Change to region A in (2). Specifically, such as Figure 24 As shown, input a for each of routing XCL_1 to routing XCL_363 respectively. in (2) [1, 1, 1] to a in (2) [11, 11, 3] as region A in (2) values. Therefore, the output from wiring WCL_1 is used as the convolution kernel K. C1 （1） With region A in (2) The product sum operation result p c1 （1） (2), and the output from the wiring WCL_96 is used as the convolution kernel K. C1 （96） With region A in (2) The product sum operation result p c1 （96） (2).

[0518] The same applies below, by using region A in (3) to A in (3025) Input sequentially to routing XCL_1 to routing XCL_363, and p can be output sequentially. c1 （1） (3) to p c1（96） (3) group to p c1 （1） (3025) to p c1 （96） The result of the product and operation of the group (3025).

[0519] As described above, by using a computing device according to one aspect of the present invention, region A can be... in (1) To region A in (3025), Kernel K C1 （1） To K C1 （96） The filtered value is used as the input value to obtain the output data P from the convolutional layer CNV1. C1 .

[0520] [Pooling layer PL1] In pooling layer PL1, P, which is the output data from convolutional layer CNV1, C1 Pooling is performed. Pooling refers to the following process: sequentially selecting specified regions from the data output from convolutional layers, performing specified processing in each region to extract features, and then configuring these features into a matrix.

[0521] like Figure 20 As shown, in pooling layer PL1, the kernel size is set to 3, and the kernel size is selected from data P. C1 Pooling is performed on each region within the pool. Note that the step size is 2, and this pooling process is max pooling.

[0522] For example, Figure 25A This is shown in the data P C1 The first input channel selects region A. C1in （1） (1) Perform max pooling and output the data p as the processing result. p1 （1） (1) is an example. Additionally, because the kernel size is 3, region A... C1in （1） (1) Includes 3×3 data.

[0523] Area A C1in （s） (a) s represents data P C1 The ordinal number of the input channel, region A C1in （s） (a) where 'a' represents data selected from P. C1 The ordinal number of the region in the data p p1 （s） (a) where s represents the ordinal number of the output channel and p represents the data. p1 （s）(a) where 'a' corresponds to region A C1in （s） The ordinal number a of (a).

[0524] Additionally, since the step size is 2, from region A... C1in （1） (1) The region that drifts 2 in the direction of movement is region A. C1in （1） (2). For example, Figure 25B Showing the selection of data P C1 Region A in C1in （1） (2) Perform max pooling and output the data p as the processing result. p1 （1） (2) is an example.

[0525] Note that in data P C1 Given a quantity of 55×55×96 and a step size of 2, select from data P C1 The number of regions is 729 (=27) 2 ).

[0526] As described above, by sequentially processing the data selected from P according to the step size... C1 Pooling the region in the data yields a 27x27 matrix output. Additionally, although the data P was explained above... C1 The first input channel, but by similarly pooling the second to 96th input channels, the result is that the output from the pooling layer PL1 is P as 27×27×96 output data. P1 .

[0527] [Convolutional Layer CNV2] In the convolutional layer CNV2, the data P output by the pooling layer PL1 is... P1 Convolution processing is performed. Specifically, a convolution kernel selected from P is used for the CNV2 convolution processing. P1 The product and sum of data included in the region.

[0528] like Figure 20 As shown, in the convolutional layer CNV2, the kernel size is set to 5 and the number of kernels is set to 256. For kernels selected from P... P1 The region in the image is processed by convolution. Note that the stride is 1.

[0529] Similar to the description of convolutional layer CNV1, convolution processing is performed in convolutional layer CNV2, and P is output from convolutional layer CNV2 as 27×27×256 output data. C2 .

[0530] Furthermore, similar to convolutional layer CNV1, the operation of convolutional layer CNV2 can be performed using a computing device according to one aspect of the present invention. For example, 256 convolutional kernels of convolutional layer CNV2 are written according to each column of cell array CA and input selected from P using drive circuit XCD. P1 From each region in the equation, P can be obtained as the result of each product sum operation. C2 .

[0531] [Pooling layer PL2] In pooling layer PL2, P, which is the output data from convolutional layer CNV2, C2 Perform pooling processing.

[0532] like Figure 20 As shown, in pooling layer PL2, the kernel size is set to 3, and the kernel selected from data P... C2 Pooling is performed on each region within the pool. Note that the step size is 2, and this pooling process is max pooling.

[0533] Similar to the description of pooling layer PL1, by performing pooling processing in pooling layer PL2, P is output from pooling layer PL2 as 13×13×256 output data. P2 .

[0534] [Convolutional layer CNV3] In the convolutional layer CNV3, the data P output by the pooling layer PL2 is... P2 Convolution processing is performed. Specifically, a convolution kernel selected from P is used for the CNV3 convolution processing. P2 The product and sum of data included in the region.

[0535] like Figure 20 As shown, in convolutional layer CNV3, the kernel size is set to 3 and the number of kernels is set to 384. For kernels selected from P... P2 The region in the image is processed by convolution. Note that the stride is 1.

[0536] Similar to the description of convolutional layer CNV1, convolution processing is performed in convolutional layer CNV3, and P is output from convolutional layer CNV3 as 13×13×384 output data. C3 .

[0537] Furthermore, the operation of the computing device in convolutional layer CNV3 can be referenced from that in convolutional layer CNV1. Figure 15 Explanation of the operation of the CDVA computing device.

[0538] [Convolutional layer CNV4] In convolutional layer CNV4, the data P output by convolutional layer CNV3 is processed. C3Convolution processing is performed. Specifically, a convolution kernel selected from P is used for the CNV4 convolution processing. C3 The product and sum of data included in the region.

[0539] like Figure 20 As shown, in convolutional layer CNV4, the kernel size is set to 3 and the number of kernels is set to 384. For kernels selected from P... C3 The region in the image is processed by convolution. Note that the stride is 1.

[0540] Similar to the description of convolutional layer CNV1, convolution processing is performed in convolutional layer CNV4, and P is output from convolutional layer CNV4 as 13×13×384 output data. C4 .

[0541] Furthermore, the operation of the computing device in convolutional layer CNV4 can be referenced from that in convolutional layer CNV1. Figure 15 Explanation of the operation of the CDVA computing device.

[0542] [Convolutional layer CNV5] In convolutional layer CNV5, the data P output by convolutional layer CNV4 is processed. C4 Convolution processing is performed. Specifically, a convolution kernel of CNV5 and a kernel selected from P are used for convolution processing. C4 The product and sum of data included in the region.

[0543] like Figure 20 As shown, in convolutional layer CNV5, the kernel size is set to 3 and the number of kernels is set to 256. For kernels selected from P... C4 The region in the image is processed by convolution. Note that the stride is 1.

[0544] Similar to the description of convolutional layer CNV1, convolution processing is performed in convolutional layer CNV5, and P is output from convolutional layer CNV5 as 13×13×256 output data. C5 .

[0545] Furthermore, the operation of the computing device in convolutional layer CNV5 can be referenced from that in convolutional layer CNV1. Figure 15 Explanation of the operation of the CDVA computing device.

[0546] [Pooling layer PL5] In pooling layer PL5, P, which is the output data from convolutional layer CNV5, C5 Perform pooling processing.

[0547] like Figure 20 As shown, in pooling layer PL5, the kernel size is set to 3, and the kernel size is selected from data P. C5Pooling is performed on each region within the pool. Note that the step size is 2, and this pooling process is max pooling.

[0548] Similar to the description of pooling layer PL1, pooling is performed in pooling layer PL5, and P is output from pooling layer PL5 as 6×6×256 output data. P5 .

[0549] [Fully Connected Layer FC6] In the fully connected layer FC6, P is the output data from the pooling layer PL5. P5 Perform operations on the fully connected layer.

[0550] like Figure 20 As shown, in the fully connected layer FC6, the number of input channels is 9126 (=6×6×256), and the number of output channels is 4096. In the fully connected layer, for each output channel, the product of all input channel data and its corresponding weight coefficient (first data) is performed to calculate the value of the activation function, which is then used as the input value. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC6 is 4096×9126.

[0551] The data for the Nth output channel (where N is an integer greater than 1 and less than 4096) of the fully connected layer FC6 is z. FC6 When (N), z FC6 (N) can be represented by the following formula (2.1).

[0552] [Equation 14] .

[0553] Note that f is the activation function of the fully connected layer FC6. Furthermore, the activation function can be, for example, an activation function operable in the circuit RL described in Embodiment 1. Specific examples include the sigmoid function, tanh function, softmax function, ReLU function, or threshold function. Additionally, u FC6 (N) is represented by the following formula (2.2).

[0554] [Equation 15] .

[0555] In addition, p p5 （s） (A) is the A-th data of the s-th output channel in the pooling layer PL5. Additionally, w FC6（N） （s） (A) corresponds to the Nth channel and p in the fully connected layer FC6. p5 （s） (A) weighting coefficients (first data).

[0556] By using the above formulas (2.1) and (2.2), the z-values ​​of the data from the first to the 4096th output channels of the fully connected layer FC6 can be obtained. FC6 (1) to z FC6 (4096).

[0557] Note that the operations of the fully connected layer FC6 described above are preferably performed in, for example, in Figure 15 The computational device CDVA shown is used. At this time, the computation in the fully connected layer FC6 is performed... Figure 15 In the case of the shown arithmetic device CDVA, it is preferable that the number of rows m of the cell array CA is equal to 9126 of the number of input channels, and the number of columns n of the cell array CA is equal to 4096 of the number of output channels. Therefore, the first data w in the arithmetic device CDVA can be... FC6（N） （s） (A) Write to the arithmetic units IM[1, 1] to IM[9126, 4096] respectively.

[0558] Additionally, the second data in the computing device CDVA is p p5 （s） (A), therefore, for example, it is preferable to input p to the input terminal of each of circuits XCDa_1 to XCDa_m. p5 （s） The values ​​of each component of (A). Therefore, each of the operation units IM[1, 1] to IM[m, n] performs p... p5 （s） The values ​​of each component in (A) and their corresponding weighting coefficients w FC6（N） （s） The multiplication operation of (A) results in the operational circuit being able to output u from each of the wirings WCL_1 to WCL_4096. FC6 (1) to u FC6 (4096).

[0559] In addition, through Figure 15 The driving circuit ITS shown performs u FC6 (1) to u FC6 Each of (4096) is an activation function operation for the input value, from which z is obtained. FC6 (1) to z FC6 (4096). Thus, z is output from the fully bonded layer FC6. FC6 (1) to z FC6 The output signal of (4096).

[0560] Therefore, the cell array CA executes the first data (weight coefficients) and the second data (P). P5 u is obtained by performing a product and sum operation on ) FC6(1) to u FC6 (4096). Additionally, using the ITS drive circuit, it is possible to achieve u FC6 (1) to u FC6 For each input value in (4096), the result of the activation function is z. FC6 (1) to z FC6 (4096).

[0561] [Fully Connected Layer FC7] In the fully connected layer FC7, the z-axis of the data, which is the output channel from the fully connected layer FC6, is... FC6 (1) to z FC6 (4096) Perform the operation of the fully connected layer.

[0562] like Figure 20 As shown, in the fully connected layer FC7, there are 4096 input channels and 4096 output channels. Similar to the fully connected layer FC6, in the fully connected layer FC7, for each output channel, the product of all input channel data and its corresponding weight coefficient (first data) is performed to calculate the value of the activation function, using the result as the input value. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC7 is 4096 × 4096.

[0563] Note that the product sum operation and activation function operation in the fully connected layer FC7 can be found in the description of the fully connected layer FC6.

[0564] In the fully connected layer FC7, the z-axis is input as the data from the output channel of the fully connected layer FC6. FC6 (1) to z FC6 At (4096), the z-values ​​of the data output as the first to the 4096th output channels of the fully connected layer FC7 are used. FC7 (1) to z FC7 (4096).

[0565] [Fully Connected Layer FC8] In the fully connected layer FC8, the z-axis of the data as the output channel from the fully connected layer FC7... FC7 (1) to z FC7 (4096) Perform the operation of the fully connected layer.

[0566] like Figure 20As shown, in the fully connected layer FC8, there are 4096 input channels and 1000 output channels. Similar to the fully connected layer FC6, in the fully connected layer FC8, for each output channel, the product of all input channel data and its corresponding weight coefficient (first data) is performed to calculate the value of the activation function, using the result as the input value. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC8 is 1000 × 4096.

[0567] Note that the product summation and activation function operations in the fully connected layer FC8 can be found in the documentation for the fully connected layer FC6.

[0568] In the fully connected layer FC8, the z-axis is input as the output channel of the fully connected layer FC7. FC7 (1) to z FC7 (4096) When the z-axis is output as the data of the first to the 1000th output channels of the fully connected layer FC8, it is used as the output of the fully connected layer FC8. FC8 (1) to z FC8 (1000).

[0569] In addition, the working description of the fully connected layer FC8 can be referred to the above description of the fully connected layer FC7.

[0570] As described above, by using a computing device according to one aspect of the present invention, it is possible to perform... Figure 20 The operation of AlexNet is shown.

[0571] Note that in this example, the computing device described in Implementation 1 is used to perform... Figure 20 The diagram illustrates the operation of AlexNet, but the computational model performed by this device is not limited to AlexNet. For example, in the input layer INLY, a 224×224 pixel image P... in The image is input to the processing unit, but the image size can also be arbitrarily determined. Furthermore, the number of convolution kernels used for convolutional layers CNV1 to CNV5 and the filter values ​​they include can also be arbitrarily determined. Additionally, the processing unit can also... Figure 20 The operational model of AlexNet is different from that of convolutional neural networks.

[0572] Note that this example uses max pooling as the underlying principle, but average pooling, Lp pooling, etc., can also be used depending on the situation.

[0573] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. In addition, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with configurations, structures, methods, etc. shown in other embodiments, etc.

[0574] (Implementation Method 3) In this embodiment, an example of the structure of the computing device described in the above embodiment will be explained.

[0575] Figure 26 This is a schematic perspective view of the computing device CDVA described in Embodiment 1. As an example, Figure 26 The shown computing device CDVS includes a circuit layer PHRL and a computing layer OMAL. The circuit layer PHRL is located below the computing layer OMAL.

[0576] Figure 27 It is shown Figure 26 The block diagrams show examples of the circuit layer PHRL and the operational layer OMAL.

[0577] exist Figure 27 In this configuration, the circuit layer PHRL includes, for example, the drive circuit WCD, drive circuit XCD, drive circuit ITS, and drive circuit WSD described in Embodiment 1. Additionally, the computation layer OMAL includes, for example, the cell array CA described in Embodiment 1.

[0578] In addition, one or more of the drive circuits WCD, XCD, ITS and WSD described in Embodiment 1 may also be included in the operation layer OMAL.

[0579] The circuit layer PHRL can be constructed, for example, by placing circuit elements such as transistors and capacitors on a substrate. Alternatively, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium) can be used as the substrate. Other substrates besides semiconductor substrates include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates containing stainless steel foil, tungsten substrates, substrates containing tungsten foil, flexible substrates, laminated films, and paper or substrate films containing fibrous materials. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, or substrate films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Other examples include synthetic resins such as acrylic resins. Other examples include polypropylene, polyester, ethylene fluoride, or polyvinyl chloride. Other examples include polyamides, polyimides, aromatic polyamides, epoxy resins, inorganic vapor-deposited films, or paper. Furthermore, when the manufacturing process of the CDV (Computing Device for Display) includes heat treatment, a material with high heat resistance is preferably selected as the substrate.

[0580] Note that in this embodiment, the description is based on the premise that the substrate included in the circuit layer PHRL is a semiconductor substrate containing silicon.

[0581] By using a semiconductor substrate, such as silicon, as the substrate included in the circuit layer PHRL, transistors included in each of the drive circuits WCD, XCD, ITS, and WSD can be formed on the semiconductor substrate. In this case, the transistor is a Si transistor. Because Si transistors have high field-effect mobility, large on-state currents can flow through them. Therefore, the driving speed of the aforementioned drive circuits can be increased, and the signal range can be expanded, etc.

[0582] Alternatively, a stacked structure of the circuit layer PHRL and the operational layer OMAL can be fabricated by forming the operational layer OMAL directly on top of the circuit layer PHRL. Alternatively, the operational layer OMAL can be fabricated by placing circuit elements such as transistors and capacitors on a substrate and mounting that substrate on top of the circuit layer PHRL.

[0583] When the operational layer OMAL is formed directly on top of the circuit layer PHRL, the operational layer OMAL preferably includes OS transistors. Because OS transistors can be formed not only on semiconductor substrates, but also on insulating substrates, conductive substrates, conductive films, insulating films, and semiconductor films, they are easy to place on semiconductor substrates on which Si transistors are formed (on the circuit layer PHRL).

[0584] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the operational layer OMAL and the substrate is mounted on the circuit layer PHRL, flip-chip bonding or wire bonding methods can be used. Alternatively, a first bonding layer can be provided on one side of the circuit layer PHRL, and a second bonding layer can be provided on the substrate of the operational layer OMAL. The first bonding layer and the second bonding layer can be bonded together using one or both of surface activation bonding and hydrophilic bonding methods, thereby mounting the operational layer OMAL on the circuit layer PHRL. In particular, the bonding of copper (Cu) in the conductors included in the first and second bonding layers and bonding the copper to each other is called Cu-Cu (copper-copper) direct bonding.

[0585] <Example 1 of the cross-sectional structure of a computing device> Next, the explanation Figure 26 and Figure 27 The diagram shows a specific structural example of the CDVS computing device. Figure 28 yes Figure 26 and Figure 27 A cross-sectional schematic diagram of an example of a computing device CDVS is shown.

[0586] Figure 28 A cross-sectional schematic diagram of the circuit layer PHRL and the operational layer OMAL is shown. Note that in... Figure 28 In the CDV computing device, the OMAL computing layer is directly formed on the PHRL circuit layer.

[0587] Figure 28 An example of a transistor 400 included in the circuit layer PHRL is shown. The transistor 400 is disposed on a substrate 311 and includes: a conductive layer 316 serving as a gate; insulating layers 315 and 317 serving as gate insulating films; a semiconductor region 313 including a portion of the substrate 311; and low-resistance regions 314a and 314b, including a portion of the substrate, serving as source or drain regions. The transistor 400 can be a p-channel transistor or an n-channel transistor. Furthermore, the substrate 311 can be, for example, a single-crystal substrate made of silicon.

[0588] Here, in Figure 28In the transistor 400 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. Alternatively, the conductive layer 316 can be made of a material with adjustable work function. Because it utilizes the convex portion of the semiconductor substrate, this transistor 400 is also referred to as a finned transistor. Alternatively, an insulating layer for forming the convex portion can be included in such a way that it contacts the top of the convex portion. Although the case shown here is of forming the convex portion by processing a portion of the semiconductor substrate, a semiconductor film with a convex shape can also be formed by processing an SOI substrate.

[0589] Notice, Figure 28 The structure of transistor 400 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0590] A wiring layer, including interlayer membranes, wiring, and connectors, can also be provided between the various structures. Furthermore, multiple wiring layers can be configured according to the design. Additionally, in this specification, wiring and connectors connecting to the wiring can also be considered as components. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a connector.

[0591] For example, insulating layers 320, 324, and 326 are sequentially stacked as interlayer films on transistor 400. A conductive layer 328 or the like is embedded in the insulating layer 320. A conductive layer 330 or the like is embedded in the insulating layers 324 and 326. Furthermore, the conductive layers 328 and 330 are used as contact plugs or wiring.

[0592] Alternatively, the insulating layer used as an interlayer film can also be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulating layer 320, its top surface can also be planarized by a planarization process using chemical mechanical polishing (CMP).

[0593] Wiring layers can also be disposed on the insulating layer 326 and the conductive layer 330. For example, in Figure 28 In this structure, insulating layers 350, 357, 352, and 354 are sequentially stacked on insulating layer 326 and conductive layer 330. Conductive layer 356 is formed in insulating layers 350, 357, and 352. Conductive layer 356 is used as a contact plug or wiring.

[0594] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. The insulating layer 354 preferably has a contact plug or wiring embedded therein for connecting to the circuit above (e.g., the circuit included in the circuit of the operational layer OMAL).

[0595] in addition, Figure 28 This example illustrates a portion of the computational units included in the OMAL computational layer. Specifically, Figure 28 Show Figure 1 The arithmetic unit IM of the arithmetic circuit CC shown includes transistors M1, M2, M3, M5, capacitor C1, and capacitor C2.

[0596] exist Figure 28 In the operational layer OMAL of the CDVS arithmetic device, transistors M3 and M5 are formed on insulating layer STJ1. Transistors M1 and M2 are formed on insulating layer STJ2. Capacitors C1 and C2 are formed on insulating layer STJ3. Insulating layer STJ2 is located above insulating layer STJ1, and insulating layer STJ3 is located above insulating layer STJ2. Therefore, capacitors C1 and C2 are located above transistors M1 and M2, and transistors M1 and M2 are located above transistors M3 and M5.

[0597] Furthermore, insulating layers STJ1 to STJ3 are preferably used as barrier insulating films to suppress the permeation of impurities such as water and hydrogen. Therefore, insulating materials that suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, or NO2), and copper atoms (making it difficult for these impurities to permeate) are preferably used as insulating layers STJ1 to STJ3. Alternatively, insulating materials that suppress the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (making it difficult for the aforementioned oxygen to permeate) are preferably used. Note that the materials that can be used for each of insulating layers STJ1 to STJ3 can be referred to the description of the insulating layers of the transistor's constituent materials.

[0598] Additionally, one of the source and drain electrodes of transistor M3 is connected to a conductive layer used as wiring WCL via a connector, and the other of the source and drain electrodes of transistor M3 is connected to a conductive layer used as wiring VEL via a connector. Furthermore, one of the source and drain electrodes of transistor M5 is connected to a conductive layer used as wiring VED via a connector. Also, although not shown, the other of the source and drain electrodes of transistor M5 is connected to one of the source and drain electrodes of transistor M6, one of the source and drain electrodes of transistor M1, one of the source and drain electrodes of transistor M2, and one of the pair of electrodes of capacitor C2. Furthermore, wiring WCL, wiring VEL, and wiring VED extend, for example, in the channel width direction of transistor M3 or transistor M5.

[0599] In addition, the gate electrode of transistor M3 is connected to a conductive layer that serves as one of the pair of electrodes used as capacitor C1 via a plug.

[0600] Additionally, one of the source and drain electrodes of transistor M1 is connected via a connector to a conductive layer of one of the electrodes used as capacitor C1, and the other of the source and drain electrodes of transistor M1 is connected via a connector to a conductive layer of one of the electrodes used as capacitor C2. Similarly, one of the source and drain electrodes of transistor M2 is connected via a connector to a conductive layer of one of the electrodes used as capacitor C2, and the other of the source and drain electrodes of transistor M2 is connected via a connector to a conductive layer used as wiring WCL.

[0601] Furthermore, each gate electrode of transistor M1 and transistor M2 is connected to a conductive layer used as a wiring WSL. Additionally, the conductive layer serving as the gate electrode of transistors M1 and M2 extends in the channel width direction.

[0602] An insulating layer serving as an interlayer film is formed between transistors M3 and M5 and transistors M1 and M2. Furthermore, an opening is provided in the region of this insulating layer that overlaps with the gate electrode of transistor M3, and a conductive layer serving as a plug is embedded in this opening. Similarly, an opening is also provided in the region that overlaps with the source or drain electrodes of transistors M3 and M5, and a conductive layer serving as a plug is embedded in this opening.

[0603] Furthermore, an insulating layer serving as an interlayer film is formed between transistors M1 and M2 and capacitors C1 and C2. Additionally, an opening is provided in the region of this insulating layer overlapping with the gate electrodes of transistors M1 and M2, and a conductive layer serving as a plug is embedded in this opening. Similarly, an opening is also provided in the region overlapping with the source or drain electrodes of transistors M1 and M2, and a conductive layer serving as a plug is embedded in this opening.

[0604] The conductive layer used as one of the pairs of electrodes in capacitor C1 is formed in a manner that embeds it within the insulating layer STJ4 on the insulating layer STJ3. Similarly, the conductive layer used as one of the pairs of electrodes in capacitor C2 is also formed in a manner that embeds it within the insulating layer STJ4.

[0605] Additionally, a conductive layer, serving as the other electrode of capacitor C1, is disposed above one of the pairs of electrodes of capacitor C1 and a portion of the insulating layer STJ4, separated from the insulating layer used as a dielectric. This conductive layer also serves as wiring XCL.

[0606] Similarly, one of the electrodes of capacitor C2 is separated from the other part of the insulating layer STJ4 by a conductive layer that serves as the dielectric material, and is disposed thereon as the other electrode of capacitor C2. Additionally, this conductive layer is also used as wiring VEG.

[0607] By embedding the conductive layer, which serves as one of the electrodes of capacitor C1, into the insulating layer STJ4, the conductive layer and the insulating layer STJ4 can be flush with each other and planarized. This allows for the high flatness of the insulating layer (serving as a dielectric) and the conductive layer (serving as the other electrode of capacitor C1) on the top surfaces of both the conductive layer (serving as one electrode of capacitor C1) and the insulating layer STJ4, which already possess good flatness. By improving the flatness of both electrodes of capacitor C1 and the insulating layer (serving as a dielectric), localized electric field concentration can be suppressed, thereby preventing leakage current between the electrodes of capacitor C1. Furthermore, the area of ​​one electrode of capacitor C1 (the lower electrode in this case) is smaller than that of the other electrode (the upper electrode in this case). By employing this structure, potential localized electric field concentration in the dielectric film (the insulating film sandwiched between the electrodes) of capacitor C1 can be suppressed, thus enabling a highly reliable semiconductor device. Note that the same applies to capacitor C2.

[0608] For example, in Figure 1In the arithmetic unit IM, by employing the above structure as capacitor C1, leakage current between the pair of electrodes of capacitor C1 generated between node N and wiring XCL can be prevented. Therefore, in the arithmetic unit IM, potential fluctuations at node N caused by this leakage current can be prevented, thereby maintaining the potential of node N for a long period. Similarly, by employing the above structure as capacitor C2, leakage current between the pair of electrodes of capacitor C2 generated between node Nm and wiring VEG can be prevented. Therefore, in the arithmetic unit IM, potential fluctuations at node Nm caused by this leakage current can be prevented, thereby maintaining the potential of node Nm for a long period. Furthermore, localized electric field concentration in the dielectrics of capacitors C1 and C2 can be suppressed, thus improving the reliability of the arithmetic unit IM.

[0609] Additionally, for example in Figure 1 In the driving unit IMD, by employing the above structure as capacitor C1d, leakage current between the pair of electrodes of capacitor C1d generated between node Nd and wiring XCL can be prevented. Therefore, in the driving unit IMD, potential fluctuations in node Nd caused by this leakage current can be prevented, thereby maintaining the potential of node Nd for a long period. Similarly, by employing the above structure as capacitor C2d, leakage current between the pair of electrodes of capacitor C2d generated between node Nmd and wiring VEG can be prevented. Therefore, in the driving unit IMD, potential fluctuations in node Nmd caused by this leakage current can be prevented, thereby maintaining the potential of node Nmd for a long period. Furthermore, localized electric field concentration in the dielectrics of capacitors C1d and C2d can be suppressed, thus improving the reliability of the driving unit IMD. As a result, the reliability of the operational circuit CC can be improved.

[0610] In addition, Figure 28 In the structural example, the conductive layer used for wiring XCL and the conductive layer used for wiring VEG both extend in the channel width direction of each of transistors M1, M2, M3 and M5.

[0611] In addition, such as Figure 28 As shown, in each of transistors M1, M2, M3, and M5, a conductive layer serving as a back gate can also be provided below the island-shaped semiconductor layer of each transistor. By providing a back gate in each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0612] For example, by providing a back gate in each of transistors M1, M2, M3, and M5, the influence of external electric fields can be mitigated, thus stably maintaining the off state. Therefore, data written to capacitors C1 and C2 can be stably maintained. In this way, by providing a back gate, the operation of the arithmetic unit IM is stabilized, improving the reliability of the arithmetic layer OMAL, which includes the arithmetic unit IM.

[0613] The semiconductor layer forming the channel of each of transistors M1, M2, M3, and M5 can be a combination of one or more of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, and amorphous semiconductors. As the semiconductor material, for example, as described in Embodiment 1, silicon or germanium can be used. Other examples include compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, or nitride semiconductors.

[0614] Furthermore, transistors M1, M2, M3, and M5 are preferably oxide semiconductor transistors (OS transistors) in which one of the metal oxides is used in the semiconductor layer forming the channel. Since the bandgap of oxide semiconductors is 2 eV or more, the off-state current is significantly small. Therefore, the power consumption of the arithmetic unit can be reduced. This, in turn, reduces the power consumption of the arithmetic device CDVS, which includes the arithmetic unit IM.

[0615] in addition, Figure 28 The arithmetic unit shown can hold the first data, therefore it is also used as a storage device. Thus, it can be... Figure 28 The arithmetic unit or arithmetic device CDVS is called "OS memory".

[0616] Furthermore, OS transistors operate stably even at high temperatures with minimal characteristic variation. For example, their off-state current hardly increases even at high temperatures. Specifically, the off-state current hardly increases even in environments above room temperature but below 200°C. Additionally, the on-state current does not easily decrease even at high temperatures. Therefore, OS memories operate stably and reliably even at high temperatures.

[0617] In addition, when a back gate is provided in a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid the formation of parasitic capacitance with the back gate.

[0618] <<Example 1 of transistor structure>> Next, it is explained that it can be used Figure 28 The diagram shows specific structural examples of transistors M1 to M3 and M5, which are referred to as the GL (GateLast) structure. Figure 29A and Figure 29BThe transistor 500 shown is usable as Figure 28 An example of a GL structure transistor consisting of transistors M1 to M3 and M5.

[0619] In particular, Figure 29A This diagram shows a cross-sectional view of the transistor 500 along its channel length. Figure 29B A schematic cross-sectional view of the transistor 500 in the channel width direction is shown.

[0620] like Figure 29A and Figure 29B As shown, as an example, transistor 500 includes semiconductor layer 531a, semiconductor layer 531b, conductive layer 505, conductive layer 542a, conductive layer 542b, insulating layer 580, conductive layer 560, insulating layer 514, insulating layer 516, insulating layer 520, insulating layer 522, insulating layer 524, insulating layer 550, insulating layer 554, insulating layer 574, insulating layer 580, and insulating layer 581. Note that transistor 500 may sometimes not include all of the above-described components. For example, conductive layer 505 is used as the back gate electrode in transistor 500, but transistor 500 may also not include conductive layer 505.

[0621] Note that the materials that can be used in the above-mentioned conductive layer, insulating layer and semiconductor layer will be described later.

[0622] Conductive layers 505 (conductive layers 505a and 505b) and insulating layer 516 are disposed above a substrate (not shown). In particular, conductive layer 505 is preferably disposed in a manner embedded within insulating layer 516. Specifically, conductive layer 505a is preferably disposed in a manner that contacts the bottom surface and sidewalls of an opening provided in insulating layer 516. Furthermore, conductive layer 505b is preferably disposed in a manner that embeds into a recess formed in conductive layer 505a. Figure 29A and Figure 29B In the transistor 500 shown, the height of the top surface of the conductive layer 505b is approximately the same as the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516.

[0623] Insulating layer 516, for example, is used as a planarization film to flatten steps caused by plugs, etc., similar to insulating layer 320. Therefore, like insulating layer 320, insulating layer 516 can use a material used as a planarization film. In addition, by using a material with a low relative permittivity in insulating layer 516, parasitic capacitance between wirings can be reduced.

[0624] Therefore, the insulating layer 516 can be, for example, silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride. Alternatively, as the insulating layer 516, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, or porous silicon oxide are preferred because they readily form regions containing oxygen released by heating. Alternatively, the insulating layer 516 can be, for example, made of resin. Furthermore, the above-mentioned insulating materials can be appropriately combined as materials for the insulating layer 516.

[0625] Note that in this specification, "oxynitride" refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while "nitrogen oxide" refers to a material in which the nitrogen content is greater than the oxygen content in its composition. For example, when described as silicon oxynitride, it refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while when described as silicon oxynitride, it refers to a material in which the nitrogen content is greater than the oxygen content in its composition.

[0626] Semiconductor layer 531 and conductive layer 560 are disposed in the region overlapping with conductive layer 505. Semiconductor layer 531b is disposed on semiconductor layer 531a. Conductive layers 542a and 542b are disposed separately on semiconductor layer 531b. Insulating layer 580 is disposed on conductive layers 542a and 542b. Specifically, insulating layer 580 has an opening formed in the region between conductive layers 542a and 542b. Conductive layer 560 is disposed in this opening. In addition, insulating layer 550 is disposed between semiconductor layer 531b, conductive layers 542a and 542b, and insulating layer 580 and conductive layer 560. Here, as... Figure 29A and Figure 29B As shown, the top surface of conductive layer 560 is preferably substantially aligned with the top surfaces of insulating layers 550 and 580. Note that conductive layers 505a and 505b are sometimes collectively referred to as conductive layer 505. Additionally, semiconductor layers 531a and 531b are sometimes collectively referred to as semiconductor layer 531. Furthermore, conductive layers 542a and 542b are sometimes collectively referred to as conductive layer 542.

[0627] In addition, such as Figure 29AAs shown, sometimes region 543a is formed at and near the interface of the conductive layer 542a of semiconductor layer 531b as a low-resistance region. Similarly, sometimes region 543b is formed at and near the interface of semiconductor layer 531b and conductive layer 542b as a low-resistance region. In this case, region 543a is used as one of the source region and drain region, and region 543b is used as the other of the source region and drain region. Therefore, region 543a can be one of the source electrode and drain electrode, and region 543b can be the other of the source electrode and drain electrode. In addition, a channel forming region is formed in the region sandwiched between region 543a and region 543b.

[0628] By providing the conductive layer 542a (conductive layer 542b) in contact with the semiconductor layer 531, the oxygen concentration in region 543a (region 543b) sometimes decreases. Additionally, sometimes a metal compound layer containing the metal contained in the conductive layer 542a (conductive layer 542b) and components of the semiconductor layer 531 is formed in region 543a (region 543b). Furthermore, the concentration of impurities such as hydrogen, nitrogen, and metal elements in region 543a (region 543b) is sometimes high. In this case, the carrier concentration in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region. That is, the source and drain regions are n-type regions (low-resistance regions) with higher carrier concentrations compared to the channel formation region.

[0629] On the other hand, the channel formation region is a high-resistivity region with fewer oxygen vacancies or lower impurity concentrations compared to the source and drain regions, resulting in lower carrier concentrations. Therefore, the channel formation region can be considered an i-type (intrinsic) or essentially i-type region.

[0630] The preferred carrier concentration in the channel formation region is 1×10⁻⁶. 18 cm -3 Below, less than 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Or less than 1×10 10 cm -3Note that there is no specific limit to the lower limit of carrier concentration in the channel formation region; for example, it can be 1 × 10⁻⁶. -9 cm -3 .

[0631] When the aim is to reduce the carrier concentration in semiconductor layer 531, the impurity concentration in semiconductor layer 531 is reduced to reduce the defect state density. In this specification, a state with low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, oxide semiconductors (or metal oxides) with low carrier concentration are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors (or metal oxides).

[0632] To stabilize the electrical characteristics of transistor 500, reducing the impurity concentration in the channel formation region of semiconductor layer 531 is effective. To further reduce the impurity concentration in semiconductor layer 531, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in semiconductor layer 531 refer, for example, to elements other than the main components constituting semiconductor layer 531. For example, elements with a concentration less than 0.1 atomic% can be considered impurities.

[0633] Furthermore, in semiconductor layer 531, it is sometimes difficult to clearly observe the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to vary in stages according to each region; they can vary continuously within each region. That is, the closer to the channel formation region, the lower the concentration of metal elements and impurity elements such as hydrogen and nitrogen can be.

[0634] In transistors using oxide semiconductors as the semiconductor layer 531, if impurities and oxygen vacancies exist in the region where the channel is formed in the oxide semiconductor, the electrical characteristics are prone to change, sometimes reducing reliability. Furthermore, hydrogen near the oxygen vacancy forms a defect where hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V). O H) may generate electrons that become charge carriers. Therefore, when oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor tends to be in a constantly on state. Thus, it is preferable to minimize impurities, oxygen vacancies, and V in the channel formation region of an oxide semiconductor. O H. In other words, the preferred channel formation region in an oxide semiconductor is a region where the carrier concentration is reduced and it is i-typed (intrinsic) or substantially i-typed.

[0635] In contrast, by performing heat treatment with an insulating layer containing oxygen that has been removed by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor, oxygen can be supplied to the oxide semiconductor from the insulating layer, thereby reducing oxygen vacancies and V. OH. Note that supplying excessive oxygen to the source or drain regions can sometimes cause a decrease in the on-state current or field-effect mobility of the transistor 500. Furthermore, when the amount of oxygen supplied to the source or drain regions is uneven within the substrate surface, the characteristics of the semiconductor device, including the transistor, deviate. Additionally, when oxygen supplied from the insulating layer to the oxide semiconductor diffuses to the conductive layers such as the gate, source, and drain electrodes, these conductive layers may sometimes be oxidized, leading to a loss of conductivity and thus negatively impacting the electrical characteristics and reliability of the transistor.

[0636] Therefore, preferably, in the oxide semiconductor, the channel formation region is a region with reduced carrier concentration and is i-type or substantially i-type, while the source and drain regions are regions with high carrier concentration and are n-type. In other words, it is preferable to reduce oxygen vacancies and V0 in the channel formation region of the oxide semiconductor. O H. Additionally, it is preferable that the source and drain regions are not supplied with excessive oxygen and that the V in the source and drain regions... O The amount of hydrogen (H) is not excessively reduced. Furthermore, a structure that suppresses the decrease in conductivity of conductive layers 560, 542a, and 542b is preferred. For example, a structure that suppresses the oxidation of conductive layers 560, 542a, and 542b is preferred. Note that hydrogen in oxide semiconductors may form V2. O H, therefore, in order to reduce V O The amount of H needs to be reduced, so the hydrogen concentration needs to be lowered.

[0637] exist Figure 29A and Figure 29B In the transistor 500 shown, the side surface of the conductive layer 560 of conductive layers 542a and 542b has a generally vertical shape. Note that... Figure 29A and Figure 29B The transistor 500 shown is not limited to this; the angle formed between the side surface and the bottom surface of the conductive layer 542a and the conductive layer 542b can be 10° or more and 80° or less, preferably 30° or more and 60° or less. In addition, the opposing side surfaces of the conductive layer 542a and the conductive layer 542b can also have multiple surfaces.

[0638] Note that in transistor 500, two semiconductor layers, 531a and 531b, are stacked in and around the region forming the channel (hereinafter also referred to as the channel forming region), but the present invention is not limited thereto. For example, a single-layer structure of semiconductor layer 531b or a stacked structure of three or more layers can be used. In addition, semiconductor layers 531a and 531b can each have a stacked structure of two or more layers.

[0639] The conductive la...

Claims

1. A semiconductor device, comprising: Unit 1; as well as Unit 2 The first unit includes a first transistor to a third transistor, a first capacitor, a second capacitor, and a first amplifier circuit. The second unit includes a fourth to a sixth transistor, a third capacitor, a fourth capacitor, and a second amplifier circuit. The first terminal of the first transistor is electrically connected to the gate of the third transistor, the input terminal of the first amplifier circuit, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the output terminal of the first amplifier circuit, and the first terminal of the second capacitor. The first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the input terminal of the second amplifier circuit, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the output terminal of the second amplifier circuit, and the first terminal of the fourth capacitor. The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first wiring. The second terminal of the fifth transistor, the first terminal of the sixth transistor, the second terminal of the first capacitor, and the second terminal of the third capacitor are electrically connected to the second wiring. The gates of the first transistor, the second transistor, the fourth transistor, and the fifth transistor are electrically connected to the third wiring. Furthermore, the first amplifier circuit and the second amplifier circuit are used as buffer circuits for output analog potential.

2. The semiconductor device according to claim 1, The first to sixth transistors contain oxide semiconductors in the channel formation region. The transistors in the first amplifier circuit and the second amplifier circuit contain the oxide semiconductor or silicon in the channel formation region. The oxide semiconductor comprises one or more elements selected from indium, zinc, and element M. And the element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt and antimony.

3. The semiconductor device according to claim 2, The first transistor, the second transistor, the fourth transistor, and the fifth transistor are switching transistors. The third transistor and the sixth transistor are amplification transistors. The channel length of the switching transistor is greater than the channel length of the amplifying transistor. Furthermore, the channel width of the amplifying transistor is greater than the channel width of the switching transistor.

4. A semiconductor device, comprising: Unit 1; as well as Unit 2 The first unit includes a first transistor to a third transistor, a seventh transistor, a first capacitor, a second capacitor, and a first amplifier circuit. The second unit includes transistors four through six, an eighth transistor, a third capacitor, a fourth capacitor, and a second amplifier circuit. The first terminal of the first transistor is electrically connected to the gate of the third transistor, the input terminal of the first amplifier circuit, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the output terminal of the first amplifier circuit, and the first terminal of the second capacitor. The first terminal of the third transistor is electrically connected to the first terminal of the seventh transistor. The first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the input terminal of the second amplifier circuit, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the output terminal of the second amplifier circuit, and the first terminal of the fourth capacitor. The first terminal of the sixth transistor is electrically connected to the first terminal of the eighth transistor. The second terminal of the second transistor and the second terminal of the seventh transistor are electrically connected to the first wiring. The second terminal of the sixth transistor, the second terminal of the eighth transistor, the second terminal of the first capacitor, and the second terminal of the third capacitor are electrically connected to the second wiring. The gates of the first transistor, the second transistor, the fourth transistor, and the fifth transistor are electrically connected to the third wiring. Furthermore, the first amplifier circuit and the second amplifier circuit are used as buffer circuits for output analog potential.

5. The semiconductor device according to claim 4, The first to eighth transistors contain oxide semiconductors in the channel formation region. The transistors in the first amplifier circuit and the second amplifier circuit contain the oxide semiconductor or silicon in the channel formation region. The oxide semiconductor comprises one or more elements selected from indium, zinc, and element M. And the element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt and antimony.

6. The semiconductor device according to claim 5, The first transistor, the second transistor, the fourth transistor, and the fifth transistor are switching transistors. The third transistor and the sixth transistor are amplification transistors. The channel length of the switching transistor is greater than the channel length of the amplifying transistor. Furthermore, the channel width of the amplifying transistor is greater than the channel width of the switching transistor.

7. A semiconductor device, comprising: Unit 1; as well as Unit 2 The first unit includes a first transistor to a third transistor, a seventh transistor, a ninth transistor, a tenth transistor, a first capacitor, and a second capacitor. The second unit includes transistors four through six, transistor eight, transistor eleven, transistor twelfth, capacitor three, and capacitor four. The first terminal of the first transistor is electrically connected to the gate of the third transistor, the gate of the ninth transistor, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the first terminal of the ninth transistor, the first terminal of the tenth transistor, and the first terminal of the second capacitor. The first terminal of the third transistor is electrically connected to the first terminal of the seventh transistor. The first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the gate of the eleventh transistor, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the first terminal of the eleventh transistor, the first terminal of the twelfth transistor, and the first terminal of the fourth capacitor. The first terminal of the sixth transistor is electrically connected to the first terminal of the eighth transistor. The second terminal of the second transistor and the second terminal of the seventh transistor are electrically connected to the first wiring. The second terminal of the fifth transistor, the second terminal of the eighth transistor, the second terminal of the first capacitor, and the second terminal of the third capacitor are electrically connected to the second wiring. Furthermore, the gates of the first transistor, the second transistor, the fourth transistor, and the fifth transistor are electrically connected to the third wiring.

8. The semiconductor device according to claim 7, The first to eighth transistors contain oxide semiconductors in the channel formation region. The ninth to twelfth transistors contain the oxide semiconductor or silicon in the channel formation region. The oxide semiconductor comprises one or more elements selected from indium, zinc, and element M. And the element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt and antimony.

9. The semiconductor device according to claim 8, The first transistor, the second transistor, the fourth transistor, and the fifth transistor are switching transistors. The third transistor, the sixth transistor, and the ninth through twelfth transistors are amplification transistors. The channel length of the switching transistor is greater than the channel length of the amplifying transistor. Furthermore, the channel width of the amplifying transistor is greater than the channel width of the switching transistor.

10. A semiconductor device, comprising: Unit 1; as well as Unit 2 The first unit includes a first transistor to a third transistor, a ninth transistor, a tenth transistor, a first capacitor, and a second capacitor. The second unit includes transistors four through six, transistor eleven, transistor twelfth, a third capacitor, and a fourth capacitor. The first terminal of the first transistor is electrically connected to the gate of the third transistor, the gate of the ninth transistor, and the first terminal of the first capacitor. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor, the first terminal of the ninth transistor, the first terminal of the tenth transistor, and the first terminal of the second capacitor. The first terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, the gate of the eleventh transistor, and the first terminal of the third capacitor. The second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the first terminal of the eleventh transistor, the first terminal of the twelfth transistor, and the first terminal of the fourth capacitor. The second terminal of the second transistor and the first terminal of the third transistor are electrically connected to the first wiring. The second terminal of the fifth transistor, the first terminal of the sixth transistor, the second terminal of the first capacitor, and the second terminal of the third capacitor are electrically connected to the second wiring. Furthermore, the gates of the first transistor, the second transistor, the fourth transistor, and the fifth transistor are electrically connected to the third wiring.

11. The semiconductor device according to claim 10, The first to sixth transistors contain oxide semiconductors in the channel formation region. The ninth to twelfth transistors contain the oxide semiconductor or silicon in the channel formation region. The oxide semiconductor comprises one or more elements selected from indium, zinc, and element M. And the element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt and antimony.

12. The semiconductor device according to claim 11, The first transistor, the second transistor, the fourth transistor, and the fifth transistor are switching transistors. The third transistor, the sixth transistor, and the ninth through twelfth transistors are amplification transistors. The channel length of the switching transistor is greater than the channel length of the amplifying transistor. Furthermore, the channel width of the amplifying transistor is greater than the channel width of the switching transistor.

13. The semiconductor device according to any one of claims 1 to 12, comprising above the plurality of transistors in the first unit and the plurality of transistors in the second unit: A first insulating layer, a second insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first insulating layer is located on the first conductive layer. The first insulating layer includes an opening leading to the first conductive layer. The second conductive layer is located on the top surface of the first conductive layer in the opening and in a first region on the side of the opening. The second insulating layer is located on the top surface of the second conductive layer, in the second region on the side of the opening, and on the top surface of the first insulating layer. The third conductive layer is located on the top surface of the second insulating layer in the opening. The second conductive layer and the third conductive layer are used as a pair of electrodes selected from one or more of the first capacitor to the fourth capacitor. Furthermore, the second insulating layer is used as a dielectric material selected from one or more of the first capacitor to the fourth capacitor.

14. A computing device, comprising: The semiconductor device of claim 13; as well as First drive circuit to fourth drive circuit The first driving circuit and the fourth driving circuit are electrically connected to the first wiring. The second driving circuit is electrically connected to the second wiring. The third driving circuit is electrically connected to the third wiring. The first driving circuit has the function of generating a first current corresponding to the first data and causing it to flow through the first wiring. The second driving circuit has the function of generating a second current corresponding to the second data and causing it to flow through the second wiring. The third driving circuit has the function of supplying a high-level potential or a low-level potential to the third wiring. The fourth driving circuit has the function of obtaining a third current generated in the first unit from the first wiring, using the value corresponding to the third current as an input value to perform function calculation and output the calculation result, wherein the third current corresponds to the product of the first data and the second data. Furthermore, the current amounts of the first current to the third current are the current amounts of the third transistor and the sixth transistor within the range of operation in the subthreshold region.

15. An electronic device comprising: The computing device as described in claim 14; as well as Frame.

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