Cycle optimization based method for task scheduling in graph machine learning models

Abstract

A processor-implemented method for representing computations in a machine learning (ML) model as loops includes receiving the ML model. The ML model is initially represented as a graph having a plurality of nodes coupled by edges. A value numbering is assigned to each node in the graph based on a similarity of characteristics of the plurality of nodes. Loops are reconstructed for computations in the graph based on the value numbering. An affine scalar evolution analysis technique is used to determine loop boundaries.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 592,222, filed February 29, 2024, entitled “LOOP OPTIMIZATION-BASEDAPPROACH FOR TASK SCHEDULING IN GRAPH MACHINE LEARNING MODELS,” the entire disclosure of which is expressly incorporated herein by reference. Technical Field

[0003] The various aspects of this disclosure generally relate to machine learning, and more specifically to scheduling tasks in graph machine learning models using loop optimization. Background Technology

[0004] Artificial neural networks can comprise interconnected groups of artificial neurons (e.g., neuron models). An artificial neural network (ANN) can be a computing device or represented as a method to be performed by a computing device. A convolutional neural network (CNN) is a type of feedforward ANN. A CNN can comprise an ensemble of neurons, where each neuron has a receptive field and collectively constructs the input space. CNNs such as deep convolutional neural networks (DCNs) have numerous applications. Specifically, these neural network architectures are used in a variety of technologies, such as image recognition, speech recognition, acoustic scene classification, keyword retrieval, autonomous driving, and other classification tasks.

[0005] The tasks of machine learning (ML) models can be scheduled and data allocated by ML optimization frameworks. Optimal graph scheduling under resource constraints can be a nondeterministic polynomial (NP) complete problem, which can lead to poor tractability for ML optimizers as the model width increases. Therefore, the time spent by these optimizers optimizing ML models may be unacceptable to users. Summary of the Invention

[0006] In some aspects of this disclosure, a processor-implemented method includes receiving a machine learning (ML) model. The ML model is represented as a graph having a plurality of nodes coupled by edges. The processor-implemented method further includes assigning a value number to each node in the graph based on the similarity of characteristics of the plurality of nodes. The processor-implemented method additionally includes reconstructing a computational loop in the graph based on the value number to generate a reconstruction loop. The processor-implemented method further includes using affine scalar evolutionary analysis techniques to determine the loop boundaries of the reconstruction loop.

[0007] Various aspects of this disclosure relate to an apparatus including components for receiving a machine learning (ML) model. The ML model is represented as a graph having a plurality of nodes coupled by edges. The apparatus also includes components for assigning a value number to each node in the graph based on the similarity of characteristics of the plurality of nodes. The apparatus additionally includes components for reconstructing computational loops in the graph based on the value number to generate a reconstruction loop. The apparatus also includes components for determining the loop boundaries of the reconstruction loop using affine scalar evolutionary analysis techniques.

[0008] Some aspects of this disclosure relate to an apparatus having at least one memory and one or more processors coupled to the at least one memory. The processors are configured to receive a machine learning (ML) model. The ML model is represented as a graph having a plurality of nodes coupled by edges. The processors are also configured to assign a value number to each node in the graph based on the similarity of the characteristics of the plurality of nodes. The processors are additionally configured to reconstruct computational loops in the graph based on the value number to generate a reconstruction loop. The processors are further configured to determine the loop boundaries of the reconstruction loop using affine scalar evolutionary analysis techniques.

[0009] Additional features and advantages of this disclosure will be described below. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for implementing the same purposes as this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. Novel features considered characteristic of this disclosure, in both their organization and manner of operation, along with further objects and advantages, will be better understood when considered in conjunction with the accompanying drawings. However, it is to be clearly understood that each drawing is provided for illustrative and descriptive purposes only and is not intended to be a definition of a limitation of this disclosure. Attached Figure Description

[0010] The features, substance, and advantages of this disclosure will become more apparent when understood in conjunction with the accompanying drawings, in which the same reference numerals are always used to identify the subjects.

[0011] Figure 1 Example implementations of neural networks using a system-on-a-chip (SoC) (including a general-purpose processor) according to certain aspects of this disclosure are illustrated.

[0012] Figure 2A , Figure 2B and Figure 2C These are illustrations of neural networks according to various aspects of this disclosure.

[0013] Figure 2D This is a diagram illustrating exemplary deep convolutional networks (DCNs) according to various aspects of this disclosure.

[0014] Figure 3 This is a block diagram illustrating exemplary deep convolutional networks (DCNs) according to various aspects of this disclosure.

[0015] Figure 4 This is a block diagram illustrating exemplary software architectures that enable modularization of artificial intelligence (AI) functions according to various aspects of this disclosure.

[0016] Figure 5 This is a flowchart illustrating the example value numbering process according to various aspects of this disclosure.

[0017] Figure 6 This is a block diagram illustrating example processes for cyclic re-rolling according to various aspects of this disclosure.

[0018] Figure 7 This is a block diagram illustrating example scalar evolution analysis according to various aspects of this disclosure.

[0019] Figure 8 This is a flowchart illustrating various aspects of the present disclosure of a processor implementation for scheduling tasks in a graph machine learning model using loop optimization. Detailed Implementation

[0020] The detailed description that follows, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only configurations in which the described concepts can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0021] Based on the teachings, those skilled in the art will recognize that the scope of this disclosure is intended to cover any aspect of this disclosure, whether implemented independently of or in combination with any other aspect of this disclosure. For example, an apparatus or method may be implemented using any number of the aspects described. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods practiced using other structures, functionalities, or structures and functionalities that complement or differ from the various aspects of this disclosure described. It should be understood that any aspect of this disclosure may be embodied by one or more elements of the claims.

[0022] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” need not be interpreted as superior to or better than other aspects.

[0023] While specific aspects have been described, numerous variations and substitutions of these aspects fall within the scope of this disclosure. Although some benefits and advantages of preferred aspects have been mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or purpose. Rather, aspects of this disclosure are intended to be broadly applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated by way of example in the accompanying drawings and the following description of preferred aspects. The detailed description and drawings are merely illustrative and not limiting of this disclosure, the scope of which is defined by the appended claims and their equivalents.

[0024] Many machine learning (ML) optimization tools (e.g., compilers) represent the computation of an ML model as a task graph, where vertices represent computations and edges represent data dependencies between computations. The compiler can leverage this expanded representation of the ML model to perform such optimizations. In some respects, this expanded representation may be generated unconsciously. That is, the ML writer may not be aware that the process performed by the ML model corresponds to an expansion. For example, a generative pre-trained transformer (GPT) model may include a sequence of transformers that can produce an expansion loop.

[0025] For example, the graph could include a directed acyclic graph of layers. Layers can be partitioned and can represent tasks. For example, optimizations could include task execution scheduling and / or memory allocation. However, the size of the graph increases with the width of the model. The size of the input can have a direct impact on the number of nodes in the graph. This is because the tile size can be fixed (e.g., constant). The tensors of the ML model can be two-dimensional (2D) or higher-dimensional; therefore, the size of the graph can be O(n^2). 2 The rate of increase is ).

[0026] Each node can represent a task in the graph. These tasks can be scheduled and allocated data by the ML optimization framework. Optimal graph scheduling under resource constraints may be a nondeterministic polynomial-time (NP) complete problem, which can lead to poor tractability for ML optimizers as the model width increases. Therefore, the time spent by these optimizers optimizing ML models may be unacceptable to users.

[0027] To address these and other issues, scheduling large task graphs can leverage the highly repetitive nature of such graphs to transform them into cyclic representations. That is, the graph can be reconstructed in a cyclic form. Each task becomes an iteration of a cyclic-based program. The loops access data elements, which can be described as functions of loop counters (e.g., linear or non-linear functions), so tasks, along with the data they consume and produce, can be indexed and represented as loop counters (and then loop optimization techniques can be applied to determine task scheduling).

[0028] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, the described techniques (e.g., assigning value numbers to similar substructures of a graph, reconstructing loops based on value numbers, and performing scalar evolution analysis) can advantageously reduce the latency when computing the scheduling of nodes used to perform the ML model. This is because the time required to compute the scheduling is constant as a function of the model width.

[0029] Furthermore, by using loop representations of ML computations, various loop optimization techniques can be applied to improve scheduling performance and ML model processing efficiency. For example, such loop optimizations may include loop fusion, loop partitioning, placement across multiple cores, direct memory access (DMA) generation and coarsening, multi-buffering (sometimes referred to as high-level software pipelines), and other loop optimizations.

[0030] Furthermore, performance debugging can be simplified because the behavior of multiple tasks (in the same loop) can be analyzed at once, rather than the sum of their individual behaviors as is the case in some conventional methods.

[0031] Furthermore, optimization decisions can be performed in batches on the original tasks, resulting in more consistent behavior. Consistency allows for the allocation of the same local memory offset to specific data slices across all cores. Multicasting to the same address from anywhere may be more efficient than assigning the same address to different addresses on each core.

[0032] Figure 1 An example implementation of a System-on-a-Chip (SOC) 100 is illustrated, which may include a Central Processing Unit (CPU) 102 or a multi-core CPU configured to schedule tasks in a graph machine learning model using loop optimization. Variables (e.g., neural signals and synaptic weights), system parameters associated with the computing device (e.g., a neural network with weights), latency, frequency window (bin) information, and task information may be stored in a memory block associated with a Neural Processing Unit (NPU) 108, a memory block associated with the CPU 102, a memory block associated with a Graphics Processing Unit (GPU) 104, a memory block associated with a Digital Signal Processor (DSP) 106, a memory block 118, or may be distributed across multiple blocks. Instructions executed at the CPU 102 may be loaded from the program memory associated with the CPU 102 or may be loaded from memory block 118.

[0033] The SOC 100 may also include additional processing blocks tailored for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth-generation (5G) connectivity, fourth-generation LTE (4G) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 capable of, for example, detecting and recognizing gestures. In one specific implementation, an NPU 108 is implemented within a CPU 102, a DSP 106, and / or a GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120, which may include a global positioning system.

[0034] The SOC 100 can be based on ARM, RISC-V (RISC-5), or any Reduced Instruction Set Computing (RISC) architecture. In various aspects of this disclosure, instructions loaded into the general-purpose processor 102 may include code for receiving a machine learning (ML) model. The ML model is represented as a graph with multiple nodes coupled by edges. Instructions loaded into the general-purpose processor 102 may also include code for assigning value numbers to each node in the graph based on the similarity of characteristics of the multiple nodes. Instructions loaded into the general-purpose processor 102 may additionally include code for reconstructing computational loops in the graph based on value numbers to generate reconstructed loops. Instructions loaded into the general-purpose processor 102 may also include code for determining the loop boundaries of the reconstructed loops using affine scalar evolutionary analysis techniques.

[0035] Deep learning architectures perform object recognition tasks by learning to represent inputs at progressively higher levels of abstraction in each layer, thereby constructing useful feature representations of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Before deep learning, machine learning methods for object recognition problems often relied heavily on human-designed features, possibly in conjunction with shallow classifiers. Shallow classifiers could be two-class linear classifiers, where a weighted sum of feature vector components is compared to a threshold to predict which class the input belongs to. Human-designed features could be templates or kernels customized for a specific problem domain by engineers with domain expertise. In contrast, while deep learning architectures can learn to represent features similar to those that human engineers might design, this requires training. Furthermore, deep networks can learn to represent and recognize novel types of features that humans might not have considered.

[0036] Deep learning architectures can learn hierarchical structures of features. For example, if presented with visual data, the first layer can learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer can learn to recognize spectral power at specific frequencies. The second layer, taking the output of the first layer as input, can learn to recognize combinations of features, such as simple shapes in visual data or combinations of sounds in auditory data. For example, higher layers can learn to represent complex shapes in visual data or words in auditory data. Even higher layers can learn to recognize common visual objects or spoken phrases.

[0037] Deep learning architectures perform particularly well when applied to problems with a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to identify features such as wheels, windshields, and others. These features can then be combined in different ways at higher levels to identify cars, trucks, and airplanes.

[0038] Neural networks can be designed to have multiple connectivity patterns. In feedforward networks, information is passed from lower layers to higher layers, where each neuron in a given layer communicates with neurons in higher layers. As described above, hierarchical representations can be built in successive layers of a feedforward network. Neural networks can also have recurrent or feedback (also known as top-down) connections. In recurrent connections, the output from a neuron in a given layer can be passed to another neuron in the same layer. Recurrent architectures can help identify patterns across more than one block of input data that is sequentially delivered to the neural network. Connections from neurons in a given layer to neurons in lower layers are called feedback (or top-down) connections. Networks with many feedback connections can be helpful when the recognition of higher-level concepts can aid in discerning specific lower-level features of the input.

[0039] The connections between layers in a neural network can be fully connected or locally connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In the fully connected neural network 202, neurons in the first layer can transmit their outputs to each neuron in the second layer, such that each neuron in the second layer receives input from each neuron in the first layer. Figure 2BAn example of a locally connected neural network 204 is illustrated. In the locally connected neural network 204, neurons in a first layer can connect to a finite number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 204 can be configured such that each neuron in the layer will have the same or similar connectivity pattern, but the connection strength can have different values ​​(e.g., 210, 212, 214, and 216). The connectivity pattern of locally connected layers can produce spatially different receptive fields in higher layers because neurons in higher layers in a given region can receive inputs that are tuned to the characteristics of a restricted portion of the total input to the network through training.

[0040] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 can be configured such that the connection strength associated with the input for each neuron in the second layer is shared (e.g., 208). Convolutional neural networks may be well-suited for problems where the spatial location of the input is meaningful.

[0041] One type of convolutional neural network is the deep convolutional network (DCN). Figure 2D A detailed example of a DCN 200 designed to recognize visual features from an image 226 input from an image capture device 230 (such as an in-vehicle camera) is illustrated. The DCN 200 in this example can be trained to identify traffic signs and the numbers provided on them. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or traffic lights.

[0042] Supervised learning can be used to train the DCN 200. During training, an image (such as image 226 of a speed limit sign) can be presented to the DCN 200, and a forward pass can then be computed to produce an output 222. The DCN 200 may include a feature extraction part and a classification part. Upon receiving image 226, convolutional layer 232 may apply a convolutional kernel (not shown) to image 226 to generate a first set 218 of feature maps. As an example, the convolutional kernel used for convolutional layer 232 may be a 5x5 kernel that generates a 28x28 feature map. In this example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels are applied to image 226 at convolutional layer 232. A convolutional kernel may also be referred to as a filter or convolutional filter.

[0043] The first set of feature maps 218 can be subsampled by a max-pooling layer (not shown) to generate a second set of feature maps 220. The max-pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220 (e.g., 14×14) is smaller than the size of the first set of feature maps 218 (e.g., 28×28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 can be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0044] exist Figure 2D In the example, the second set of feature maps 220 is convolved to generate a first feature vector 224. Furthermore, the first feature vector 224 is further convolved to generate a second feature vector 228. Each feature of the second feature vector 228 may include a number corresponding to a possible feature of image 226, such as "sign", "60", and "100". A softmax function (not shown) converts the numbers in the second feature vector 228 into probabilities. Thus, the output 222 of DCN 200 can be the probability that image 226 includes one or more features.

[0045] In this example, the probabilities for "sign" and "60" in output 222 are higher than the probabilities for other numbers in output 222 (such as "30", "40", "50", "70", "80", "90", and "100"). Before training, output 222 generated by DCN 200 may be incorrect. Therefore, the error between output 222 and the target output can be calculated. The target output is the ground truth value of image 226 (e.g., "sign" and "60"). The weights of DCN 200 can then be adjusted so that output 222 of DCN 200 is more closely aligned with the target output.

[0046] To adjust the weights, the learning algorithm computes the gradient vector of the weights. The gradient indicates by how much the error will increase or decrease as the weights are adjusted. At the top layers, the gradient corresponds directly to the values ​​of the weights connecting the activated neurons in the penultimate layer to the neurons in the output layer. In lower layers, the gradient depends on the values ​​of the weights and the error gradient computed in the higher layers. The weights can then be adjusted to reduce the error. This method of adjusting weights is called "backpropagation" because it involves "passing backward" through the neural network.

[0047] In practice, the error gradient of the weights can be calculated using a small number of examples to make the calculated gradient approximate the true error gradient. This approximation method is called stochastic gradient descent. Stochastic gradient descent can be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, a new image (e.g., a speed limit sign in image 226) can be presented to DCN 200, and output 222 can be generated through the forward pass of DCN 200. This output can be considered as an inference or prediction of DCN 200.

[0048] Deep Belief Networks (DBNs) are probabilistic models that include multiple layers of hidden nodes. DBNs can be used to extract hierarchical representations of training datasets. DBNs are obtained by stacking layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that learns a probability distribution from a set of inputs. Because RBMs can learn a probability distribution without information about the class each input should be classified into, they are often used for unsupervised learning. Using a hybrid paradigm of supervised and unsupervised learning, the bottom RBM of a DBN can be trained unsupervised and used as a feature extractor, while the top RBM can be trained supervisedly (on the joint distribution of inputs from the previous layer and the target class) and used as a classifier.

[0049] DCN is a network of convolutional networks configured with additional pooling and normalization layers. DCN has achieved state-of-the-art performance on many tasks. DCN can be trained using supervised learning, where both the input and output targets are known for many paradigms and are used to modify the network's weights using gradient descent.

[0050] DCNs can be feedforward networks. Furthermore, as described above, connections from neurons in the first layer of a DCN to a set of neurons in the next higher layer are shared across neurons in the first layer. The feedforward and shared connections of a DCN can be used for fast processing. For example, the computational cost of a DCN may be much smaller than that of a similarly sized neural network that includes recurrent or feedback connections.

[0051] The processing at each layer of a convolutional network can be thought of as a spatially invariant template or base projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then a convolutional network trained on that input can be thought of as three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The output of the convolutional connections can be thought of as forming a feature map in the next layer, where each element in the feature map (e.g., 220) receives input from a range of neurons in the previous layer (e.g., feature map 218) and from each of the multiple channels. The values ​​in the feature map can be further processed non-linearly (e.g., rectified, max(0, x)). Values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and provides additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied through lateral inhibition between neurons in the feature map.

[0052] Figure 3 This is a block diagram illustrating a DCN 350. A DCN 350 can include multiple layers of different types based on connectivity and weight sharing. For example... Figure 3 As shown, DCN 350 includes convolutional blocks 354A and 354B. Each convolutional block in convolutional blocks 354A and 354B can be configured with a convolutional layer (CONV) 356, a normalization layer (LNorm) 358, and a max pooling layer (MAX POOL) 360.

[0053] Although only two convolutional blocks 354A and 354B are shown, this disclosure is not limited thereto, and any number of convolutional blocks 354A and 354B may be included in the DCN 350 according to design preferences.

[0054] Convolutional layer 356 may include one or more convolutional filters that can be applied to the input data to generate feature maps. Normalization layer 358 may normalize the output of the convolutional filters. For example, normalization layer 358 may provide whitening or lateral suppression. Max pooling layer 360 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0055] Parallel filter banks of deep convolutional networks can be loaded onto an SOC 100 (e.g., Figure 1 The CPU 102 or GPU 104 of the SOC 100 can be used to achieve high performance and low power consumption. In an alternative implementation, a parallel filter bank can be loaded onto the DSP 106 or ISP 116 of the SOC 100. In addition, the DCN 350 can access other processing blocks that may exist on the SOC 100, such as the sensor processor 114 and navigation module 120, which are dedicated to sensors and navigation, respectively.

[0056] The DCN 350 may also include one or more fully connected layers 362 (FC1 and FC2). The DCN 350 may also include logistic regression (LR) layers 364. Weights (not shown) to be updated are located between each of the layers 356, 358, 360, 362, and 364 of the DCN 350. The output of each layer (e.g., 356, 358, 360, 362, and 364) can be used as input to the next layer in the DCN 350 (e.g., 356, 358, 360, 362, and 364) to learn hierarchical feature representations from the input data 352 (e.g., images, audio, video, sensor data, and / or other input data) supplied at the first convolutional block in convolutional block 354A. The output of the DCN 350 is a classification score 366 of the input data 352. The classification score 366 may be a set of probabilities, where each probability is the probability that the input data includes a feature from the feature set.

[0057] Figure 4 This is a block diagram illustrating an exemplary software architecture 400 that enables modularization of artificial intelligence (AI) functionality. According to various aspects of this disclosure, using architecture 400, a system-on-a-chip (SoC) 420 (which may be similar to...) can be designed... Figure 1 Various processing blocks of the SOC 100 (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) support application-based task scheduling for AI applications 402, with loop optimization. Architecture 400 may be included, for example, in a computing device such as a smartphone.

[0058] AI application 402 can be configured to invoke functions defined in user space 404, which may, for example, provide the detection and recognition of a scene indicating the current location of the computing device (including architecture 400). For example, AI application 402 may configure microphones and cameras differently depending on whether the recognized scene is an office, lecture hall, restaurant, or outdoor environment (such as a lake). AI application 402 may make requests to compiled program code associated with libraries defined in AI Function Application Programming Interface (API) 406. This request may ultimately rely on the output of a deep neural network configured to provide inferred responses based on, for example, video and location data.

[0059] Runtime engine 408 (which may be compiled code of a runtime framework) may be further accessible to AI application 402. AI application 402 may cause runtime engine 408 to request inference, for example, at specific time intervals or when triggered by an event detected by the user interface of AI application 402. When runtime engine 408 provides an inference response, it may then signal to the operating system (OS) space 410 running on SOC 420, such as kernel 412. In some examples, kernel 412 may be a LINUX kernel. The operating system may then enable sequential relaxation of quantization to be performed on CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. CPU 422 may be directly accessible by the operating system, while other processing blocks may be accessed via drivers, such as drivers 414, 416, or 418 for DSP 424, GPU 426, or NPU 428, respectively. In an exemplary example, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422, DSP 424 and GPU 426, or on NPU 428.

[0060] Figure 5 This is a block diagram illustrating example value numbering process 500 according to various aspects of this disclosure. (See reference) Figure 5 The example value numbering process 500 may receive Figure 502 as input. Figure 502 may represent an ML model. The ML model may be, for example (but not limited to), a transformer model. Figure 502 may be, for example (but not limited to), a directed acyclic graph (DAG). Figure 502 includes multiple nodes connected by edges. Figure 502 includes input nodes (e.g., input 1 and input 2), weight nodes, bias nodes, and convolutional nodes (e.g., Conv1 and Conv2). The number and type of nodes shown are merely examples for illustrative purposes and are not restrictive. Rather, Figure 502 may include any number of nodes and nodes of different types.

[0061] Value numbering procedure 500 can perform value numbering traversal 506. In value numbering traversal 506, value numbering procedure 500 can assign a value number to each of the inputs, nodes, and constants. Value numbering procedure 500 can use similar features (e.g., Single Static Assignment (SSA) and Intermediate Representation (IR)) and control flow to group nodes. In various ways, for example, constant value numbers can be assigned to input nodes by hashing based on operation names or group identifiers. For example, input nodes (e.g., input 1 and input 2) can be grouped due to the similarity of node types. Input nodes can be assigned value number 1. Other nodes can be assigned, for example, by hashing operation names and the number of operands.

[0062] Therefore, as Figure 5As shown, the weight nodes and bias nodes have different node types than the other nodes in Figure 502 and can be assigned values ​​2 and 3, respectively. Finally, the convolutional nodes (Conv1 and Conv2) have the same node type, and both consume the input (e.g., input 1 or input 2) along with the weight and bias nodes. Therefore, the convolutional nodes (e.g., Conv1 and Conv2) can be grouped and assigned value 4. In various respects, each of these groups (also called buckets) can represent the same computational expression. The complexity of the analysis of node similarity may be limited by multiple edges.

[0063] Figure 6 This is a block diagram illustrating an example process 600 for cyclic re-rolling according to various aspects of this disclosure. Re-rolling may refer to a graph-based process (e.g., Figure 5 The edges in (502) are used to reconstruct the loop and loop visits. Example procedure 600 for loop rerolling can perform loop rerolling 602 to reconstruct the loop and loop visits. In various respects, the same computational expression can indicate separate iterations of unrolling the loop. For example,

[0064] R1 = Conv_Op(input 1, weight, bias)

[0065] R2 = Conv_Op(input 2, weights, bias).

[0066] It can be represented as:

[0067] for (i=0, i<2; i++)

[0068] R[i] = Conv_Op(input[i], weight, bias).

[0069] A new DAG 604 can be generated. Nodes of a DAG 604 can be identified using value numbers. Each value number can represent an operation within a loop body. For example, node 1 can represent an input node (e.g., from...). Figure 5 In Figure 502, inputs 1 and 2), nodes 2 and 3 can represent weight nodes and bias nodes, respectively, and node 4 can represent convolution nodes (e.g., Conv1 and Conv2).

[0070] However, information about loop boundaries, access functions, and the number of loop variables / loop nesting within each loop body may be unknown. For example, the initial value iteration, the final value iteration, and the step size may be unknown, as follows:

[0071] for (i = initial value; i < final value; i += step size):

[0072] R[i] = Conv_Op(input[i], weight, bias)

[0073] To determine these cyclical characteristics (e.g., initial value iteration, final value iteration, or step size), scalar evolutionary analysis can be used, for example, to determine the affine expression of each inductive variable / derived inductive variable in the defined cycle.

[0074] Figure 7 This is a block diagram illustrating an example scalar evolutionary analysis 700 according to various aspects of this disclosure. Scalar evolutionary analysis refers to compiler techniques involving analysis used to derive the step size of a loop, as well as upper and lower bounds. The splitting history of each operation in the diagram provides the offset of each node (e.g., operation) value across the block dimension. The offset of each node in each dimension can be mapped to an iteration sequence. The step size of the loop can be derived by taking the difference between adjacent offsets.

[0075] refer to Figure 7 The split history offset 704 corresponding to the input nodes (e.g., input 1, input 2) can be determined. The difference array 706 can store the result of the difference between the split history offsets (e.g., (2) - (1) = +1). Therefore, the step size of the loop can be +1.

[0076] The first element in the array (with a split history offset of 704) can represent the initial value, and the last element can represent the final value. Therefore, the initial value can be determined as 1, and the final value can be determined as 2.

[0077] The affine scalar evolution (SCEV) can be derived for operands and loop results using the corresponding split history (e.g., 704) of operands and loop results. The SCEV for all components helps to derive the following: (a) the loop variable based on the number of dimensions, (b) the iteration length across each dimension (final value - initial value), (c) consistency across all SCEV expressions to define the loop control construct, and (d) the SCEV expression, which also defines the access function for each node in the loop. Therefore, the re-rolled loop expression can be represented as follows:

[0078] for (i=1; i<2; i+=1):

[0079] R[i] = Conv_Op(input[i], weight, bias)

[0080] Figure 8This is a flowchart illustrating a processor implementation of a method 800 for scheduling tasks in a graph machine learning model using loop optimization, according to various aspects of this disclosure. For example, the processor-implemented method 800 may be executed by one or more processors (such as CPUs (e.g., 102, 422), GPUs (e.g., 104, 426), and / or other processing units (e.g., DSP 424, NPU 428)). In some aspects, for example, the processor-implemented method may be executed in a compiler.

[0081] At box 802, at least one processor receives a machine learning (ML) model, which is represented as a graph having multiple nodes coupled by edges. See, for example, a reference. Figure 5 As described, the example value numbering process 500 may receive Figure 502 as input. Figure 502 may represent an ML model. The ML model may be, for example (but not limited to), a transformer model. Figure 502 may be, for example (but not limited to), a directed acyclic graph (DAG). Figure 502 may include multiple nodes connected by edges. Figure 502 may include input nodes (e.g., input 1 and input 2), weight nodes, bias nodes, and convolutional nodes (e.g., Conv1 and Conv2).

[0082] At box 804, at least one processor assigns a value number to each node in the graph based on the similarity of characteristics among multiple nodes. For example, as referenced... Figure 5 As described, value numbering procedure 500 can perform value numbering traversal 506. In value numbering traversal 506, value numbering procedure 500 can assign a value number to each of the inputs, nodes, and constants. Value numbering procedure 500 can use similar features (e.g., Single Static Assignment (SSA) and Intermediate Representation (IR)) and control flow to group nodes. In various ways, for example, constant value numbers can be assigned to input nodes by hashing based on operation names or group identifiers. For example, input nodes (e.g., input 1 and input 2) can be grouped due to the similarity of node types. Input nodes can be assigned value number 1. Other nodes can be assigned, for example, by hashing operation names and the number of operands.

[0083] At box 806, at least one processor reconstructs the computation loop in the graph based on the value number to generate a reconstruction loop. For example, as referenced... Figure 6 The description may be based on a graph (e.g., Figure 5 The edges in (502) are used to reconstruct (also known as re-roll) the loop. Example procedure 600 for loop re-rolling can perform loop re-rolling 602 to reconstruct the loop and loop visits. In various respects, the same computational expression can indicate separate iterations of unrolling the loop.

[0084] At box 808, at least one processor uses affine scalar evolutionary analysis to determine the cycle boundary of the reconstruction loop. See, for example, the reference... Figure 7 As described, scalar evolution analysis refers to compiler techniques involved in the analysis used to derive the step size of a loop, as well as upper and lower bounds. Affine scalar evolution (SCEV) can be derived for operands and loop results using the corresponding split history of the operands (e.g., 704). The split history of each operation in the graph provides the offset of each node (e.g., operation) value across the block dimension. The offset of each node in each dimension can be mapped to the iteration sequence. The step size of the loop can be derived by taking the difference between adjacent offsets.

[0085] All components of the SCEV can help derive the following: (a) loop variables based on the number of dimensions, (b) the iteration length across each dimension (final value - initial value), (c) consistency across all SCEV expressions to define the loop control construct, and (d) SCEV expressions, which can also define the access function for each node in the loop.

[0086] Example

[0087] Aspect 1: An apparatus comprising: at least one memory; and at least one processor coupled to the at least one memory, the at least one processor being configured to: receive a machine learning (ML) model, the ML model being represented as a graph having a plurality of nodes coupled by edges; assign a value number to each node in the graph based on the similarity of characteristics of the plurality of nodes; reconstruct a computational loop in the graph based on the value number to generate a reconstruction loop; and determine the loop boundary of the reconstruction loop using an affine scalar evolutionary analysis technique.

[0088] Aspect 2: According to the apparatus of aspect 1, wherein the at least one processor is further configured to group the plurality of nodes by applying a hash function based on node type.

[0089] Aspect 3: The apparatus according to aspect 1 or 2, wherein the group represents the same computational expression.

[0090] Aspect 4: The apparatus according to any one of the preceding aspects, wherein the same computational expression corresponds to an iteration of the expansion loop.

[0091] Aspect 5: The apparatus according to any one of the preceding aspects, wherein the loop boundary is determined based on the split history offset of each operation in the figure.

[0092] Aspect 6: The apparatus according to any one of the preceding aspects, wherein the at least one processor is further configured to determine the step size of the reconstruction loop based on the difference between adjacent split history offsets.

[0093] Aspect 7: The apparatus according to any one of the preceding aspects, wherein the at least one processor is further configured to determine a schedule for performing operations in the ML model using one or more loop optimization techniques on the reconstruction loop.

[0094] Aspect 8: A processor-implemented method executed by one or more processors, the processor-implemented method comprising: receiving a machine learning (ML) model, the ML model being represented as a graph having a plurality of nodes coupled by edges; assigning a value number to each node in the graph based on the similarity of characteristics of the plurality of nodes; reconstructing a computational loop in the graph based on the value number to generate a reconstruction loop; and determining the loop boundary of the reconstruction loop using an affine scalar evolutionary analysis technique.

[0095] Aspect 9: The processor-implemented method according to aspect 8 further includes grouping the plurality of nodes by applying a hash function based on node type.

[0096] Aspect 10: A method implemented by a processor according to aspect 8 or 9, wherein the group represents the same computational expression.

[0097] Aspect 11: A method implemented by a processor according to any one of Aspects 8 to 10, wherein the same computational expression corresponds to an iteration of an unrolled loop.

[0098] Aspect 12: A method implemented by a processor according to any one of Aspects 8 to 11, wherein the loop boundary is determined based on the split history offset of each operation in the figure.

[0099] Aspect 13: The processor-implemented method according to any one of Aspects 8 to 12, the processor-implemented method further comprising determining the step size of the reconstruction loop based on the difference between adjacent split history offsets.

[0100] Aspect 14: A processor-implemented method according to any one of Aspects 8 to 13, the processor-implemented method further comprising determining a schedule for performing operations in the ML model using one or more loop optimization techniques on the refactoring loop.

[0101] Aspect 15: An apparatus comprising: components for receiving a machine learning (ML) model, the ML model being represented as a graph having a plurality of nodes coupled by edges; components for assigning a value number to each node in the graph based on the similarity of characteristics of the plurality of nodes; components for reconstructing a computational loop in the graph based on the value number to generate a reconstruction loop; and components for determining the loop boundary of the reconstruction loop using an affine scalar evolutionary analysis technique.

[0102] Aspect 16: The apparatus according to aspect 15 further includes components for grouping the plurality of nodes by applying a hash function based on node type.

[0103] Aspect 17: The apparatus according to aspect 15 or 16, wherein the group represents the same computational expression, and the same computational expression corresponds to an iteration of an expansion loop.

[0104] Aspect 18: The apparatus according to any one of Aspects 15 to 17, wherein the loop boundary is determined based on the split history offset of each operation in the figure.

[0105] Aspect 19: The apparatus according to any one of aspects 15 to 18, the apparatus further comprising means for determining the step size of the reconstruction cycle based on the difference between adjacent split history offsets.

[0106] Aspect 20: The apparatus according to any one of aspects 15 to 19, the apparatus further comprising a component for determining a schedule for performing operations in the ML model using one or more loop optimization techniques on the refactoring loop.

[0107] In one aspect, the receiving component, assigning component, reconfiguration component, and / or determining component may be a CPU 102, a program memory associated with the CPU 102, an NPU 108, a dedicated memory block 118, a fully connected layer 362, an NPU 428, and / or a routing connection processing unit 216 configured to perform the described functions. In another configuration, the aforementioned components may be any module or any device configured to perform the functions described by the aforementioned components.

[0108] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. These components may include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the cases where operations are illustrated in the accompanying drawings, these operations may have corresponding paired components with similar numbering plus functional components.

[0109] As used, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculation, computation, processing, derivation, research, searching (e.g., looking in a table, database, or other data structure), assertion, etc. Additionally, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. Furthermore, "determine" can include parsing, selecting, choosing, building, etc.

[0110] As used, the phrase "at least one of the items" in a list of items refers to any combination of these items, including a single member. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0111] The various exemplary logic blocks, modules, and circuits described in this disclosure can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the described functions. While the general-purpose processor may be a microprocessor, in alternative embodiments, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0112] The steps or algorithms of the methods described in this disclosure may be directly embodied in hardware, software modules executed by a processor, or a combination of both. The software modules may reside in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. Software modules may include a single instruction or multiple instructions and may be distributed across several different code segments, across different programs, and across multiple storage media. The storage medium may be coupled to the processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor.

[0113] The disclosed method includes one or more steps or actions for implementing the described method. The steps and / or actions of the method may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claims.

[0114] The described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system within the device. This processing system may utilize a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnect buses and bridges. The bus can link various circuits together, including processors, machine-readable media, and bus interfaces. The bus interface can be used to connect network adapters, etc., to the processing system via the bus. The network adapter can be used to implement signal processing functions. In some respects, user interfaces (e.g., keypads, displays, mice, joysticks, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0115] A processor may be responsible for managing the bus and general-purpose processing, including executing software stored on a machine-readable medium. A processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software should be interpreted broadly as instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. By way of example, a machine-readable medium may include random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, disks, optical disks, hard disks, or any other suitable storage medium, or any combination thereof. A machine-readable medium may be embodied as a computer program product. A computer program product may include packaging material.

[0116] In a hardware implementation, machine-readable media can be part of a processing system separate from the processor. However, as those skilled in the art will readily understand, machine-readable media, or any portion thereof, can be external to the processing system. By way of example, machine-readable media may include transmit lines, carrier waves modulated by data, and / or computer components separate from the device, all accessible to the processor via a bus interface. Alternatively or additionally, machine-readable media, or any portion thereof, may be integrated into the processor, such as in the case of a cache and / or a general-purpose register file. Although the various components discussed may be described as having a specific location, such as local components, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

[0117] The processing system may be configured as a general-purpose processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of machine-readable medium, all of which are linked together with other supporting circuitry via an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron and nervous system models. As another alternative, the processing system may be implemented using an application-specific integrated circuit (ASIC) having a processor, bus interface, user interface, supporting circuitry, and at least a portion of machine-readable medium integrated on a single chip, or using one or more field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic components, discrete hardware components, or any other suitable circuitry, or any combination of circuitry capable of performing the various functionalities described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality of the processing system depends on the specific application and the overall design constraints imposed on the system as a whole.

[0118] Machine-readable media may include multiple software modules. These software modules include instructions that, when executed by a processor, cause the processing system to perform various functions. Software modules may include send and receive modules. Each software module may reside in a single storage device or be distributed across multiple storage devices. For example, when a triggering event occurs, a software module may be loaded from a hard disk drive into RAM. During the execution of a software module, the processor may load some of the instructions into a cache to improve access speed. One or more cache lines may then be loaded into a general-purpose register file for processor execution. When the functionality of a software module is referred to below, it will be understood that such functionality is implemented by the processor when executing the instructions from that software module. Furthermore, it should be understood that aspects of this disclosure result in improvements to the functionality of a processor, computer, machine, or other system implementing such aspects.

[0119] If implemented in software, the functions may be stored as one or more instructions or codes on or transmitted through a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Additionally, any connection is also appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then such coaxial cable, optical fiber, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. The disks and optical discs used include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. ® Optical discs, where magnetic disks typically reproduce data magnetically, and optical discs reproduce data optically using lasers. Therefore, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Furthermore, in other aspects, computer-readable media may include transient computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0120] Therefore, certain aspects may include a computer program product for performing the presented operations. For example, such a computer program product may include a computer-readable medium on which instructions are stored (and / or encoded) that can be executed by one or more processors to perform the described operations. In some aspects, the computer program product may include packaging material.

[0121] Furthermore, it should be understood that modules and / or other suitable components for performing the described methods and techniques may be downloaded and / or otherwise obtained by the user terminal and / or base station where applicable. For example, such devices can be coupled to a server to facilitate the transfer of components for performing the described methods. Alternatively, the various methods described can be provided via storage components (e.g., RAM, ROM, physical storage media such as CDs or floppy disks) so that the user terminal and / or base station can obtain the various methods once the storage component is coupled to or provided to the device. Furthermore, any other suitable techniques suitable for providing the described methods and techniques to the device may be utilized.

[0122] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, variations, and alterations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An apparatus, the apparatus comprising: At least one memory; and At least one processor, coupled to the at least one memory, the at least one processor being configured to: Receive a machine learning (ML) model, which is represented as a graph with multiple nodes coupled by edges; Each node in the graph is assigned a value number based on the similarity of the characteristics of the multiple nodes. Based on the value number, the calculation loop in the graph is reconstructed to generate a reconstruction loop; as well as The affine scalar evolutionary analysis technique was used to determine the cycle boundary of the reconstructed loop.

2. The apparatus of claim 1, wherein the at least one processor is further configured to group the plurality of nodes by applying a hash function based on node type.

3. The apparatus of claim 2, wherein the group represents the same computational expression.

4. The apparatus of claim 3, wherein the same computational expression corresponds to an iteration of the expansion loop.

5. The apparatus of claim 1, wherein the cycle boundary is determined based on the split history offset of each operation in the figure.

6. The apparatus of claim 5, wherein the at least one processor is further configured to determine the step size of the reconstruction loop based on the difference between adjacent split history offsets.

7. The apparatus of claim 1, wherein the at least one processor is further configured to determine a schedule for performing operations in the ML model using one or more loop optimization techniques on the reconstruction loop.

8. A processor-implemented method executed by one or more processors, the processor-implemented method comprising: Receive a machine learning (ML) model, which is represented as a graph with multiple nodes coupled by edges; Each node in the graph is assigned a value number based on the similarity of the characteristics of the multiple nodes. Based on the value number, the calculation loop in the graph is reconstructed to generate a reconstruction loop; as well as The affine scalar evolutionary analysis technique was used to determine the cycle boundary of the reconstructed loop.

9. The processor-implemented method according to claim 8, further comprising grouping the plurality of nodes by applying a hash function based on node type.

10. The processor-implemented method of claim 9, wherein the group represents the same computational expression.

11. The processor-implemented method of claim 10, wherein the same computational expression corresponds to an iteration of an unrolled loop.

12. The processor implementation of the method of claim 8, wherein the loop boundary is determined based on the split history offset of each operation in the graph.

13. The processor-implemented method of claim 12, further comprising determining the step size of the reconstruction loop based on the difference between adjacent split history offsets.

14. The processor-implemented method of claim 8, further comprising determining a schedule for performing operations in the ML model using one or more loop optimization techniques on the refactoring loop.

15. An apparatus comprising: Components for receiving machine learning (ML) models, which are represented as graphs with multiple nodes coupled by edges; A component for assigning a value number to each node in the graph based on the similarity of the characteristics of the plurality of nodes; Components for reconstructing the calculation loop in the graph based on the value number to generate a reconstructed loop; and A component used to determine the cycle boundary of the reconstructed cycle using affine scalar evolution analysis techniques.

16. The apparatus of claim 15, further comprising means for grouping the plurality of nodes by applying a hash function based on node type.

17. The apparatus of claim 16, wherein the group represents the same computational expression, and the same computational expression corresponds to an iteration of an expansion loop.

18. The apparatus of claim 15, wherein the cycle boundary is determined based on the split history offset of each operation in the figure.

19. The apparatus of claim 18, further comprising a component for determining the step size of the reconstruction cycle based on the difference between adjacent split history offsets.

20. The apparatus of claim 15, further comprising a component for determining a schedule for performing operations in the ML model using one or more loop optimization techniques on the refactoring loop.

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