Coarse and fine programming of non-volatile memory cells

Abstract

A method of programming non-volatile memory cells, the method comprising: determining a target read current for respective ones of the memory cells based on incoming data; associating respective ones of the memory cells with respective ones of a plurality of cell groups based on the determined target read current for the respective memory cells being within a target read current range associated with the respective cell group; fast programming respective ones of the memory cells to a coarse target read current associated with the cell group to which the respective memory cell is associated, wherein the coarse target read current for respective ones of the cell groups is greater than the target read current range for the respective cell group; and then slow programming respective ones of the memory cells until the determined target read current for the respective memory cell is achieved.

Description

Related applications

[0001] This application claims the benefits of U.S. Provisional Application No. 63 / 620,687, filed January 12, 2024, and U.S. Patent Application No. 18 / 648,219, filed April 26, 2024. Technical Field

[0002] This invention relates to non-volatile memory cells in semiconductor devices, and more particularly to improving the efficiency and accuracy of programming non-volatile memory cells. Background Technology

[0003] Split-gate nonvolatile memory semiconductor devices are well known in the art. See, for example, U.S. Patent 7,868,375, which discloses a four-gate memory cell configuration and is incorporated herein by reference for all purposes. Specifically, this disclosure… Figure 1 An example is illustrated of a pair of split-gate nonvolatile memory cells 10, each having a spaced-apart source region 14 and a drain region 16 formed in a silicon semiconductor substrate 12. The source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other nonvolatile memory cells 10 in the same row or column), and the drain region 16 is typically connected to a bit line. A channel region 18 of the substrate 12 extends between the source / drain regions 14 / 16. A floating gate 20 is disposed above a first portion of the channel region 18 (i.e., vertically disposed above and laterally overlapping it) and is insulated from (and directly controls) its conductivity (and is partially located above and insulated from) the source region 14). A control gate 22 is disposed above and insulated from the floating gate 20. A select gate 24 (also referred to as a word line gate) is disposed above and insulated from (and directly controls) its conductivity from a second portion of the channel region 18. An erase gate 26 is disposed above and insulated from the source region 14 and is laterally adjacent to the floating gate 20. The erase gate 26 may include a notch facing the edge of the floating gate 20.

[0004] Multiple such memory cells 10 can be arranged in rows and columns to form a memory cell array, such as Figure 2 exemplified. Although Figure 1 Only one pair of memory cells 10 is shown (sharing a common source region 14 and an erase gate 26), but the memory cell pairs can be arranged end-to-end to form a column of memory cells 10 (where the memory cell pairs can share a common drain region 16). Although in Figure 2Only two such columns are shown, but many such columns may exist. Each column may include a bit line 16a electrically connecting all drain regions 16 in that column together. Each row of memory cells 10 may include a control gate line 22a electrically connecting all control gates 22 in that row of memory cells 10 together. For example, all control gates 22 in each row of memory cells 10 may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell 10 serves as its control gate 22. Each row of memory cells 10 may include a select gate line 24a electrically connecting all select gates 24 in that row of memory cells 10 together. For example, all select gates 24 in each row of memory cells 10 may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell 10 serves as its select gate 24. Each row of memory cells may include an erase gate line 26a electrically connecting all erase gates 26 in that row of memory cells together. For example, all erase gates 26 in each row of memory cells may be formed as a continuous line of conductive material, wherein a portion of the continuous line passing through any given memory cell pair serves as its erase gate 26. Finally, each row of memory cell pairs may include a source line 14a that electrically connects all source regions 14 together in that row of memory cell pairs. For example, all source regions 14 in each row of memory cell pairs may be formed as a continuous line of conductive diffusion in the substrate 12, wherein a portion of the continuous line passing through any given memory cell pair serves as its source region 14.

[0005] Various combinations of voltages are applied to the control gate 22, select gate 24, erase gate 26, and source region 14 / drain region 16 to program the split-gate nonvolatile memory cell 10 (i.e., inject electrons into the floating gate 20), erase the split-gate nonvolatile memory cell 10 (i.e., remove electrons from the floating gate 20), and read the split-gate nonvolatile memory cell 10 (i.e., measure or detect the conductivity of the channel region 18 by, for example, measuring or detecting the read current through the channel region 18 to determine the programming state of the floating gate 20).

[0006] The split-gate nonvolatile memory cell 10 can be operated digitally, wherein the split-gate nonvolatile memory cell 10 is configured to only one of two possible states: a programmed state and an erased state. The split-gate nonvolatile memory cell 10 is erased by applying a high positive voltage to the erase gate 26 and optionally a negative voltage to the control gate 22, causing electrons to tunnel from the floating gate 20 to the erase gate 26 (putting the floating gate 20 in a more positively charged state – the erased state). The split-gate nonvolatile memory cell 10 can be programmed by applying positive voltages to the control gate 22, the erase gate 26, the select gate 24, and the source region 14, and by applying current to the drain region 16. Electrons then flow along the channel region 18 from the drain region 16 to the source region 14, where the electrons become accelerated and heated, thereby some of them being injected into the floating gate 20 via hot electron injection (putting the floating gate 20 in a more negatively charged state – the programmed state).

[0007] One technique for programming memory cell 10 is sequential programming, which involves applying a programming voltage as a series of pulses, where each pulse of the programming voltage injects more electrons onto the floating gate, thus increasing the programming state of memory cell 10 with each pulse until a desired programming state is achieved (i.e., until a desired read current is achieved for the desired programming state). In the case of sequential programming, there may be intervening read operations between programming pulses to determine whether the desired programming state has been achieved by the last applied programming pulse (in which case programming stops) or has not yet been achieved (in which case programming continues with one or more programming pulses). For example, each desired programming state may be associated with a target read current Irtarget (i.e., the desired current through channel region 18 during a read operation associated with the desired programming state and is therefore the target current). The higher the programming state (i.e., the more electrons on the floating gate), the lower the read current Ir. Therefore, the read current Ir will decrease after each programming pulse. Once the target read current Irtarget (reflecting the desired programming state) is reached, programming of the memory cell 10 stops.

[0008] If the same set of programming voltages is applied during each pulse in sequential programming, the programming amount decreases pulse-by-pulse because fewer electrons are injected onto the floating gate as the floating gate becomes more negatively charged with each pulse, if the parameters of the programming pulses (applied voltage, supplied current, duration) remain constant. Therefore, when it is determined that memory cell 10 has not reached its desired programming state after any given pulse, one or more programming parameters can be progressively increased to higher values ​​in the next pulse to compensate for the pulse-to-pulse programming amount that would otherwise occur. For example, for Figure 1The memory cell 10 may have programming parameters that increase progressively from one programming pulse to the next, including increases in one or more of the following: voltage applied to the control gate, voltage applied to the erase gate, voltage applied to the source region, current supplied to the drain region, and duration of the programming pulse.

[0009] The split-gate nonvolatile memory cell 10 can be read by applying a positive voltage to the select gate 24 (which conducts a portion of the channel region 18 below the select gate 24 by making it conductive) and the drain region 16 (and optionally on the erase gate 26 and the control gate 22) and sensing the current flowing through the channel region 18. If the floating gate 20 is positively charged (i.e., the split-gate nonvolatile memory cell 10 is erased), the split-gate nonvolatile memory cell 10 will be turned on because both portions of the channel region 18 are conductive due to the lack of electrons on the floating gate 20, and current will flow from the drain region 16 to the source region 14 (i.e., the split-gate nonvolatile memory cell 10 is sensed to be in its erase "1" state based on the sensed current flow). If the floating gate 20 is negatively charged (i.e., the split-gate nonvolatile memory cell 10 is programmed), a portion of the channel region 18 below the floating gate is turned off (low conductivity), thereby preventing significant current flow (i.e., the split-gate nonvolatile memory cell 10 is sensed to be in its programmed "0" state based on no or minimal current flow). The memory cells 10 are considered nonvolatile because they retain their programmed state even when no power is applied to the semiconductor device. The memory cell 10 can be called a split-gate nonvolatile memory cell because the two distinct gates (floating gate 20 and select gate 24) directly control the conductivity of two different portions of the channel region 18.

[0010] The split-gate nonvolatile memory cell 10 can alternatively operate in an analog manner, wherein the programming state of the split-gate nonvolatile memory cell 10 (i.e., the amount of charge on the floating gate 20, such as the number of electrons) can be incrementally changed anywhere from a fully erased state (the minimum number of electrons on the floating gate 20) to a fully programmed state (the maximum number of electrons on the floating gate 20), or only a portion of that range. This means that the storage of the split-gate nonvolatile memory cell 10 is analog, which allows for very precise and individual tuning of each split-gate nonvolatile memory cell 10 in the array of split-gate nonvolatile memory cells 10. Alternatively, the split-gate nonvolatile memory cell 10 can operate as an MLC (multi-level cell), wherein it is configured to be programmed to one of many discrete values ​​(such as 16 or 64 different values).

[0011] Split-gate nonvolatile memory cells with fewer gates are also known. For example, Figure 3An example is a known split-gate non-volatile memory cell 10, which is... Figure 1 The split-gate non-volatile memory cell is the same, except that the control gate 22 is omitted. See, for example, U.S. Patent 7,315,056, which is incorporated herein by reference for all purposes. Figure 1 The voltage coupling from the control gate 22 of the split-gate nonvolatile memory cell 10 to the floating gate 20 is alternatively provided by... Figure 3 The erase gate 26 and source region 14 of the split-gate non-volatile memory cell 10 are provided. Figure 4 Examples Figure 3 Example layout of an array of split-gate nonvolatile memory cells 10.

[0012] As another example, Figure 5 Examples similar to Figure 1 The known split-gate nonvolatile memory cell 10 differs from the split-gate nonvolatile memory cell in that the control gate 22 and erase gate 26 are omitted. See, for example, U.S. Patent 5,029,130, which is incorporated herein by reference for all purposes. [The last sentence appears to be incomplete and possibly refers to a different context.] Figure 5 An erase voltage is applied to the select gate 24 of the split-gate non-volatile memory cell 10, which has a first portion laterally adjacent to the floating gate 20 and a second portion extending upward and above the floating gate 20. Figure 6 Examples Figure 5 Example layout of an array of split-gate nonvolatile memory cells 10.

[0013] As yet another example, Figure 7 Examples similar to Figure 5 The known split-gate nonvolatile memory cell 10 differs from the split-gate nonvolatile memory cell in that a block of conductive material 28 is formed to contact the source region 14 to act as an extended source line. See, for example, U.S. Patent 6,855,980, which is incorporated herein by reference for all purposes. Figure 7 An example layout of the array of split-gate non-volatile memory cells 10 can be compared with... Figure 6 The layout is the same as in the previous one.

[0014] One problem that arises is how to best program multiple memory cells simultaneously, even if the memory cells are to be programmed to different programming states. For example, it is known to program an entire row of memory cells simultaneously. Once a memory cell in a row reaches its desired programming state (confirmed by an intervention read operation), the voltage on the corresponding bit line rises to a so-called inhibit voltage (to prevent further programming), making the voltage difference between the source and drain regions of the memory cell insufficient to allow further programming, even if a subsequent programming pulse is applied to the memory cell in that row. Stopping programming of memory cells in a row can be implemented individually because each memory cell in the row is connected to a different bit line. Programming stops once all memory cells in the row have reached their desired programming states.

[0015] One problem with sequential programming in analog or MLC operations is overshoot, where a given programming pulse over-programs a memory cell. If this occurs, it may be necessary to erase an entire row of memory cells (since they all share a common erase gate line 26a), and programming may have to restart, which is wasteful. To prevent programming overshoot (and thus improve programming accuracy), the amount of programming per pulse can be kept small (e.g., by reducing the incremental increments of any programming parameters after each programming pulse). However, this means that too many programming pulses may be needed for those memory cells programmed to higher programming states, increasing programming time and thus reducing programming efficiency. Too many programming pulses can also cause programming interference, where the programming state of a memory cell that has reached its desired programming state is undesirably and incrementally further programmed by too many subsequent programming pulses, even though the disable voltage on the corresponding bit line is used to prevent further programming. This problem is most problematic for memory cells being programmed to lower programming states. Alternatively, using larger incremental increments of programming parameters to accelerate programming and improve programming efficiency will result in an increased overshoot rate and therefore a decrease in accuracy. The goal is to improve programming efficiency without excessively reducing programming accuracy. Summary of the Invention

[0016] The aforementioned problems and needs are addressed by a method for programming non-volatile memory cells, the method comprising: determining a target read current for a corresponding non-volatile memory cell based on incoming data to be stored in the corresponding non-volatile memory cell; associating the corresponding non-volatile memory cell with a corresponding cell group based on the determined target read current for the corresponding non-volatile memory cell being within a target read current range associated with a corresponding cell group in a plurality of cell groups, wherein the target read current ranges for the corresponding cell groups are different from each other; rapidly programming the corresponding non-volatile memory cell in the non-volatile memory cell to a coarse target read current associated with the cell group associated with the corresponding non-volatile memory cell in a first programming operation, wherein the coarse target read current for the corresponding cell group in the cell group is greater than the target read current range for the corresponding cell group; and, after rapid programming, slowly programming the corresponding non-volatile memory cell in the non-volatile memory cell in a second programming operation until the target read current determined for the corresponding non-volatile memory cell is achieved. Slow programming programs non-volatile memory cells at a rate slower than fast programming.

[0017] A semiconductor device includes a plurality of nonvolatile memory cells and control circuitry configured to: determine a target read current for a respective nonvolatile memory cell based on incoming data to be stored in the respective nonvolatile memory cell; associate the respective nonvolatile memory cell with a respective cell group based on the determined target read current for the respective nonvolatile memory cell being within a target read current range associated with a respective cell group in a plurality of cell groups, wherein the target read current ranges for the respective cell groups are different from each other; in a first programming operation, rapidly program the respective nonvolatile memory cell to a coarse target read current associated with the cell group associated with the respective nonvolatile memory cell, wherein the coarse target read current for the respective cell group in the cell group is greater than the target read current range for the respective cell group; and after rapid programming, in a second programming operation, slowly program the respective nonvolatile memory cell to a different nonvolatile memory cell until the determined target read current for the respective nonvolatile memory cell is achieved. Slow programming is used to program non-volatile memory cells at a rate slower than fast programming.

[0018] Other objects and features of this disclosure will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0019] Figure 1 It is a side sectional view of a typical pair of memory cells.

[0020] Figure 2 yes Figure 1 A schematic layout diagram of a conventional memory cell array.

[0021] Figure 3 It is a side sectional view of a typical pair of memory cells.

[0022] Figure 4 yes Figure 3 A schematic layout diagram of a conventional memory cell array.

[0023] Figure 5 It is a side sectional view of a typical pair of memory cells.

[0024] Figure 6 yes Figure 5 A schematic layout diagram of a conventional memory cell array.

[0025] Figure 7 It is a side sectional view of a typical pair of memory cells.

[0026] Figure 8 This is a diagram illustrating the components of a semiconductor device.

[0027] Figure 9 This is a flowchart illustrating the boxes used for coarse (fast) and fine (slow) programming of memory cells.

[0028] Figure 10 It is a graph illustrating coarse (fast) and fine (slow) programming.

[0029] Figure 11 This is a flowchart illustrating the boxes used for coarse (fast), medium, and fine (slow) programming of memory cells.

[0030] Figure 12 It is a graph illustrating coarse (fast), medium, and fine (slow) programming. Detailed Implementation

[0031] This example illustrates a memory cell programming method for improving programming efficiency without excessively reducing programming accuracy. The programming method can be implemented as part of a control circuit 46 that controls various device elements used in the memory array, such as... Figure 8 To better understand, the architecture of the example semiconductor device illustrated herein is provided. The semiconductor device includes an array 30 of non-volatile memory cells 10, which can be divided into two separate planes (plane A32a and plane B32b). The non-volatile memory cells can be... Figure 1 , Figure 3 , Figure 5 or Figure 7 The types shown are as follows: Figure 2 , Figure 4 or Figure 6 The illustrated array is arranged in multiple rows and columns within the semiconductor substrate 12 and thus formed on a single chip. Alternatively, the non-volatile memory cells may have a stacked gate structure, similar to... Figure 5 The stacked gate structure is shown, but in which the floating gate 20 extends completely across the channel region 18 (and controls the conductivity of the channel region), and the control gate is vertically positioned above the floating gate 20. Adjacent to the array of the array 30 of split-gate nonvolatile memory cells 10 are an address decoder 34 (e.g., XDEC), a source line driver 36 (e.g., SLDRV), a column decoder 38 (e.g., YMUX), a high-voltage row decoder 40 (e.g., HVDEC), a bit line controller 42 (e.g., BLINHCTL), and a charge pump 44 (e.g., CHRGPMP), which are used to decode addresses under the control of the control circuitry 46 and supply various voltages to the individual gates and regions of the split-gate nonvolatile memory cells 10 during read, program, and erase operations of selected split-gate nonvolatile memory cells 10 of the array 30. The column decoder 38 includes a sense amplifier containing circuitry for measuring the current on the bit lines during read operations. Control circuitry 46 controls various device elements to perform each operation (programming, erasing, reading) on ​​selected split-gate nonvolatile memory cells 10 of array 30, as described herein. Control circuitry 46 operates semiconductor devices to program, erase, and read selected split-gate nonvolatile memory cells 10 of array 30. As part of these operations, access to incoming data (which is the data to be programmed into the selected split-gate nonvolatile memory cells 10 of array 30) and programming, erasing, and reading commands provided on the same or different lines can be provided to control circuitry 46. Data read from array 30 (i.e., from the selected split-gate nonvolatile memory cells 10 of array 30) is provided as outgoing data.

[0032] The programming method involves control circuitry 46 implementing memory cell programming. Therefore, control circuitry 46 may be loaded with software (i.e., non-transitory electronically readable instructions) or firmware, or may consist of corresponding circuitry, or any combination thereof, to perform the methods described herein. Control circuitry 46 may be implemented by a microcontroller, special-purpose circuitry, a processor, a general-purpose processor running firmware or software, or a combination thereof.

[0033] In operation, programming is performed by applying programming voltages in discrete pulses, with read operations intervening to verify the programming state between programming pulses (i.e., sequential programming). Specifically, after each programming pulse, a programming verification read operation can be performed to determine whether the selected cell has reached its corresponding target programming state (i.e., reached its target read current Irtarget associated with the target programming state). If this is determined for any given memory cell, a programming disable voltage can be applied to that given memory cell so that subsequent programming pulses for other cells do not further program the given memory cell. For example, once it is determined that a memory cell in a particular row has achieved its desired programming state, a programming disable voltage can be applied to the corresponding bit line to prevent further programming of that memory cell. Memory cells determined not to have reached their desired programming state are programmed with additional programming pulses (also known as programming retry pulse trains), typically with a gradual increase in programming parameters. The programming retry pulse train continues until all memory cells in the row to be programmed have reached their target programming state.

[0034] The memory cell programming method is well-suited for programming multiple memory cells in a single row of memory cells (which may involve only some or all of the memory cells in that row) to different programming states during a single programming operation to store incoming data. This is achieved by first using faster coarse programming, followed by slower fine programming. Each data value of the incoming data is associated with one of the possible programming states, and therefore with a corresponding target read current Irtarget. For simplicity, the following non-limiting example is described relative to the target read current Irtarget. In this example, the semiconductor device is operating in MLC mode with ten possible different and discrete target read currents Irtarget for storing incoming data: 10nA, 20nA, 30nA, 40nA, 50nA, 60nA, 70nA, 80nA, 90nA, and 100nA. In this example, there are three cell groups: cell group 1, cell group 2, and cell group 3, each associated with a different range of target read currents. In this example, cell group 1 is associated with a range of 10nA to 30nA, cell group 2 with a range of 40nA to 60nA, and cell group 3 with a range of 70nA to 100nA. Therefore, a memory cell to be programmed to achieve a target read current Irtarget of 10nA, 20nA, or 30nA is associated with cell group 1. A memory cell to be programmed to achieve a target read current Irtarget of 40nA, 50nA, or 60nA is associated with cell group 2. A memory cell to be programmed to achieve a target read current Irtarget of 70nA, 80nA, 90nA, or 100nA is associated with cell group 3. As detailed below, the programming of memory cells varies depending on the cell group to which the corresponding memory cell belongs. The use of three cell groups is for illustrative purposes only and does not imply any limitation in any way.

[0035] This method begins as follows Figure 9As shown in block 1, for a plurality of memory cells to be programmed, the target read current Irtarget of the memory cell is determined based on the incoming data of the respective memory cell to be stored in the memory cell. In block 2, based on the target read current Irtarget, a corresponding memory cell in the memory cell is associated with one of a plurality of cell groups, as indicated above, whereby the target read current Irtarget is based on the target programming state of the memory cell (i.e., where the target read current Irtarget corresponds to the data stored in that memory cell), and each cell group is associated with a different range of target read current Irtarget. In this non-limiting example, memory cells to be programmed to a target read current Irtarget of 10nA, 20nA, or 30nA are associated with cell group 1 (which, in this example, is associated with a target read current range of 10nA to 30nA). Memory cells to be programmed to a target read current Irtarget of 40nA, 50nA, or 60nA are associated with cell group 2 (which, in this example, is associated with a target read current range of 40nA to 60nA). The memory cell to be programmed to a target read current Irtarget of 70nA, 80nA, 90nA, or 100nA is associated with cell group 3 (which, in this example, is associated with a target read current range of 70nA to 100nA).

[0036] At block 3, coarse programming is performed, wherein memory cells in a corresponding cell group undergo rapid programming in the first programming operation until the corresponding memory cell in the corresponding cell group reaches the coarse target read current Irct associated with its cell group. Specifically, each cell group is associated with a corresponding coarse target read current Irct, which is higher than the range of target read currents for the memory cells in the cell group. In this non-limiting example, cell group 1, associated with a target read current range of 10nA to 30nA, may be associated with a coarse target read current Irct of 50nA. Cell group 2, associated with a target read current range of 40nA to 60nA, may be associated with a coarse target read current Irct of 80nA. Cell group 3, associated with a target read current range of 70nA to 100nA, may be associated with a coarse target read current Irct of 120nA. This means that the coarse target read current Irct for any given cell group can be within the target read current range of adjacent cell groups (i.e., the coarse target read current Irct for group 1 can be within the target current range of group 2, and the coarse target read current Irct for group 2 can be within the target current range of group 3). Sequential programming using applied voltage pulses and intervention of the read operation can be used for coarse programming, which continues for each memory cell in the row until each memory cell reaches the coarse target read current Irct of the cell group to which it belongs. Since the coarse target read current Irct for any given memory cell is higher than the target read current to which it will be programmed, sequential programming can be used with the amplitude of one or more programming parameters gradually increasing between pulses without the risk of excessive overprogramming.

[0037] At block 4, fine programming is performed, where memory cells in all cell groups are slowly programmed during the second programming operation until the respective memory cell reaches its corresponding target read current Irtarget. Slow programming means that in the sequential programming in block 4, one or more programming parameters, or a progressively increasing increment of one or more such programming parameters, or both, are smaller than the corresponding values ​​of the fast programming in block 3, such that the programming rate (i.e., the rate at which electrons are injected onto the floating gate) is smaller relative to the fast programming in block 3 during the slow programming in block 4. Therefore, during the fine (slow) programming in block 4, the programming rate is slowed down or reduced relative to the coarse (fast) programming in block 3 to reduce the risk of any overprogramming. Fine (slow) programming intervening in the read operation can continue for each memory cell until each memory cell reaches its target read current Irtarget. At this point, programming is stopped by stopping the programming pulse or by providing a suppressor voltage on the bit line for that memory cell so that subsequent programming pulses used to program other memory cells do not further program that memory cell.

[0038] In a non-limiting example, fast programming may include applying a plurality of first programming pulses to a non-volatile memory cell and intervening in a read operation, wherein the first programming pulses include a programming voltage of 6V in steps of 0.1V (i.e., the first pulse includes a programming voltage of 6V, the second pulse includes a programming voltage of 6.1V, and so on), a programming current of 0.1mA, and a duration of 20μs for each first programming pulse. Slow programming may include applying a plurality of second programming pulses to a non-volatile memory cell and intervening in a read operation, wherein the second programming pulses include a programming voltage of 7V (in steps of 0.05V), a programming current of 0.01mA, and a duration of 10μs for each second programming pulse.

[0039] Figure 10 The coarse (fast) and fine (slow) programming of memory cells in the above non-limiting example are illustrated graphically, where the x-axis represents time (or programming pulses) and the y-axis represents the cell read current Ir. The programming rate during coarse (fast) programming is greater than the relative programming rate during fine (slow) programming to improve programming efficiency. The programming rate during fine (slow) programming is lower than the relative programming rate during coarse (fast) programming to improve programming accuracy. In general, coarse and fine programming using different coarse target read currents Irct for different groups of memory cells to be programmed to different programming state ranges is faster and more accurate than conventional programming techniques. Coarse (fast) programming is used to achieve better programming efficiency and reduced programming interference (by reducing the overall number of programming pulses), while fine programming is used to achieve better accuracy (by reducing overshoot in programming and causing the distribution of the actual read current to more closely approximate the corresponding target read current for each memory cell).

[0040] Although the above method is described in relation to two programming boxes (coarse and fine), it is also possible to use more than two programming boxes, with each subsequent programming box having a lower programming rate than the previous one. For example, three programming boxes (coarse, medium, and fine) can be used, such as... Figure 11 (Add medium programming in box 3A between coarse programming and fine programming) and Figure 12(Illustrated in the diagram showing three programming rates). In the intermediate programming of block 3A, in the third programming operation, the corresponding memory cell in the memory cell is programmed to the intermediate target read current associated with the cell group associated with the corresponding memory cell. Thus, the intermediate programming of block 3A involves programming each cell group to its corresponding intermediate target read current, wherein the intermediate target read current for the corresponding cell group within the cell group is less than the coarse target read current for the corresponding cell group but greater than the target read current range for the corresponding cell group. Any number of such programming blocks can be used between the coarse programming block and the fine programming block. The term third programming operation is intended to distinguish it from the first programming operation and the second programming operation, and is not intended to indicate the order.

[0041] It should be understood that the foregoing is not limited to the examples described above and shown herein, but covers any and all variations falling within the scope of any claim. For example, while the method described above uses three unit groups, two or more unit groups may also be used. Any references to examples or inventions herein are not intended to limit the scope of any claim or claim terminology, but only to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and values ​​described above are merely illustrative and should not be construed as limiting the scope of the claims.

Claims

1. A method for programming a non-volatile memory cell, the method comprising: The target read current for the corresponding non-volatile memory cell is determined based on the incoming data to be stored in the corresponding non-volatile memory cell. Based on the target read current determined for the corresponding non-volatile memory cell within the target read current range associated with the corresponding cell group in a plurality of cell groups, the corresponding non-volatile memory cell is associated with the corresponding cell group, wherein the target read current ranges for the corresponding cell group are different from each other. In the first programming operation, a corresponding non-volatile memory cell in the non-volatile memory cell is rapidly programmed to a coarse target read current associated with the cell group associated with the corresponding non-volatile memory cell, wherein the coarse target read current for the corresponding cell group in the cell group is greater than the target read current range for the corresponding cell group. as well as Following the rapid programming, in the second programming operation, the corresponding non-volatile memory cell in the non-volatile memory cell is slowly programmed until the target read current determined for the corresponding non-volatile memory cell is achieved. The slow programming method programs the non-volatile memory cell at a rate less than that of the fast programming method.

2. The method according to claim 1, wherein the rapid programming comprises: Multiple first programming pulses are applied to the non-volatile memory cell and a read operation is initiated.

3. The method of claim 2, wherein the slow programming comprises: Multiple second programming pulses are applied to the non-volatile memory cell and a read operation is initiated.

4. The method according to claim 1, wherein the method comprises: In the third programming operation, the corresponding non-volatile memory cells in the non-volatile memory cells are equally programmed to a moderate target read current associated with the group of cells associated with the corresponding non-volatile memory cells, wherein: The intermediate target read current for a given unit group within the unit group is less than the coarse target read current for the given unit group but greater than the target read current range for the given unit group. The medium-speed programming follows the fast programming and precedes the slow programming, and The medium programming rate is used to program the non-volatile memory cells at a rate lower than the fast programming rate but higher than the slow programming rate.

5. The method according to claim 1, wherein: The plurality of unit groups includes at least a first unit group and a second unit group; The first unit group is associated with the first target read current range; The second unit group is associated with a second target read current range that is greater than the first target read current range; and The coarse target read current associated with the first unit group is within the range of the second target read current.

6. The method according to claim 1, wherein: The plurality of unit groups include at least a first unit group, a second unit group, and a third unit group; The first unit group is associated with the first target read current range; The second unit group is associated with a second target read current range that is greater than the first target read current range; The third unit group is associated with a third target read current range that is greater than the second target read current range; The coarse target read current associated with the first unit group is within the range of the second target read current; and The coarse target read current associated with the second unit group is within the range of the third target read current.

7. The method of claim 1, wherein the corresponding non-volatile memory cell in the non-volatile memory cell comprises: A source region and a drain region are formed in a semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source region and the drain region; A floating gate, wherein the floating gate is disposed above and insulated from the first portion of the channel region; and The selection gate is disposed above and insulated from the second portion of the channel region.

8. The method of claim 7, wherein the corresponding non-volatile memory cell in the non-volatile memory cell comprises: An erase gate is disposed above and insulated from the source region.

9. The method of claim 8, wherein the corresponding non-volatile memory cell in the non-volatile memory cell comprises: A control gate is disposed above and insulated from the floating gate.

10. A semiconductor device, the semiconductor device comprising: Multiple non-volatile memory cells; and Control circuit, the control circuit being used for: The target read current for the corresponding non-volatile memory cell is determined based on the incoming data to be stored in the corresponding non-volatile memory cell. Based on the target read current determined for the corresponding non-volatile memory cell within the target read current range associated with the corresponding cell group in a plurality of cell groups, the corresponding non-volatile memory cell is associated with the corresponding cell group, wherein the target read current ranges for the corresponding cell group are different from each other. In the first programming operation, a corresponding non-volatile memory cell in the non-volatile memory cell is rapidly programmed to a coarse target read current associated with the cell group associated with the corresponding non-volatile memory cell, wherein the coarse target read current for the corresponding cell group in the cell group is greater than the target read current range for the corresponding cell group. as well as Following the rapid programming, in the second programming operation, the corresponding non-volatile memory cell in the non-volatile memory cell is slowly programmed until the target read current determined for the corresponding non-volatile memory cell is achieved. The slow programming method programs the non-volatile memory cell at a rate less than that of the fast programming method.

11. The semiconductor device of claim 10, wherein the fast programming includes applying a plurality of first programming pulses to the non-volatile memory cell and initiating a read operation.

12. The semiconductor device of claim 11, wherein the slow programming includes applying a plurality of second programming pulses to the non-volatile memory cell and intervening in a read operation.

13. The semiconductor device of claim 10, wherein the control circuit is used for: In the third programming operation, the corresponding non-volatile memory cells in the non-volatile memory cells are equally programmed to a moderate target read current associated with the group of cells associated with the corresponding non-volatile memory cells, wherein: The intermediate target read current for a given unit group within the unit group is less than the coarse target read current for the given unit group but greater than the target read current range for the given unit group. The medium-speed programming follows the fast programming and precedes the slow programming, and The medium programming is used to program the non-volatile memory cell at a rate less than that of the fast programming but greater than that of the slow programming.

14. The semiconductor device according to claim 10, wherein: The plurality of unit groups includes at least a first unit group and a second unit group; The first unit group is associated with the first target read current range; The second unit group is associated with a second target read current range that is greater than the first target read current range; and The coarse target read current associated with the first unit group is within the range of the second target read current.

15. The semiconductor device according to claim 10, wherein: The plurality of unit groups include at least a first unit group, a second unit group, and a third unit group; The first unit group is associated with the first target read current range; The second unit group is associated with a second target read current range that is greater than the first target read current range; The third unit group is associated with a third target read current range that is greater than the second target read current range; The coarse target read current associated with the first unit group is within the range of the second target read current; and The coarse target read current associated with the second unit group is within the range of the third target read current.

16. The semiconductor device of claim 10, wherein the corresponding non-volatile memory cell in the non-volatile memory cell comprises: A source region and a drain region are formed in a semiconductor substrate, wherein a channel region of the semiconductor substrate extends between the source region and the drain region; A floating gate, wherein the floating gate is disposed above and insulated from the first portion of the channel region; and The selection gate is disposed above and insulated from the second portion of the channel region.

17. The semiconductor device of claim 16, wherein the corresponding non-volatile memory cell in the non-volatile memory cell comprises: An erase gate is disposed above and insulated from the source region.

18. The semiconductor device of claim 17, wherein the corresponding non-volatile memory cell in the non-volatile memory cell comprises: A control gate is disposed above and insulated from the floating gate.

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