Semiconductor device and method of manufacturing the same

Abstract

Provided are a novel semiconductor device using a metallic delafossite-type oxide and a method for manufacturing the same. According to one embodiment of the present invention, there is provided a semiconductor device having an electrode of PdCoO2 disposed on a (001) surface of a compound semiconductor and forming a Schottky junction with the aforementioned compound semiconductor.

Description

[0001] Reference to related applications This application enjoys the priority of prior Japanese applications Japan Special Application 2024-30870 (filed on March 1, 2024) and Japan Special Application 2024-71069 (filed on April 25, 2024), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This invention relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0003] In semiconductor devices such as diodes and transistors, there exists a metal-semiconductor interface. Among these interfaces are Schottky interfaces, which exhibit rectifying characteristics, and Ohmic interfaces, which allow current to flow without loss; these can be fabricated according to their respective purposes. One parameter determining whether a Schottky or Ohmic interface is formed is the work function of the metal. For example, at the interface with an n-type semiconductor, a larger work function makes it easier to form a Schottky interface, thus improving the voltage withstand capability of the semiconductor device. Furthermore, the more stable a metal is in the atmosphere, the more stable the characteristics of the Schottky interface. Although the work function varies depending on the type of metal, the work function of elemental metals stable in the atmosphere is limited to approximately 4.0–5.7 eV (Non-Patent Literature 16, 17).

[0004] On the other hand, metallic copper-iron oxides are stable materials with large work functions. Metallic copper-iron oxides are compounds represented by the general formula AMO2 (A = Pd or Pt, M = Co, Cr, or Rh), and are materials with high electrical conductivity and stability (Non-Patent Documents 1, 10). Therefore, by stacking semiconductors with metallic copper-iron oxides, a stable and large Schottky interface can be formed at their interface, enabling high voltage withstand and high-temperature operation of semiconductor devices. For example, in Non-Patent Document 2, a large Schottky barrier is formed at the interface by forming a PdCoO2 layer on the (-201) facet of β-Ga2O3. It should be noted that the "-" in the facet orientation marking indicates a horizontal line above the following text. Additionally, there are also reports of PdCrO2 layers formed on the (001) facet of 4H-SiC, although the electrical properties of the interface are not shown (Non-Patent Document 3). It should be noted that non-patent documents 18 and 19 disclose the barrier heights of representative metals.

[0005] In addition, metallic copper-iron oxides have A + With [BO2] - The alternatingly layered structure, and the known work function will change with A + Still [BO2] - It changes as it becomes the end face (Non-Patent Document 4).

[0006] In recent years, various methods have been reported for forming films of metallic copper-iron oxides. For example, methods for forming PdCoO2 thin films on Al2O3 substrates using pulsed laser deposition (Non-Patent Document 5) and molecular beam epitaxy (Non-Patent Document 6) have been reported. Furthermore, methods for forming PdCoO2 thin films by using a PdCoO2 sintered body as a target material in a sputtering method suitable for large-area film formation have also been reported (Non-Patent Document 7).

[0007] In addition, the application of metallic copper-iron oxides in transparent electrode layers (non-patent document 5), catalysts (non-patent document 8), and terahertz wave oscillation sources (non-patent document 9) has also been reported.

[0008] Furthermore, by using gallium oxide (β-Ga2O3) substrates with a β-gallium oxide structure having a band gap of approximately 4.7eV to 4.9eV, which is larger than that of silicon carbide (SiC) and gallium nitride (GaN) (3.3eV to 3.4eV), it is expected that semiconductor devices can achieve further high voltage withstand capability.

[0009] Regarding gallium oxide (β-Ga2O3), for example, besides Non-Patent Document 2, Non-Patent Document 11 fabricates a Schottky diode by forming a PdCoO2 layer on the (-201) surface of β-Ga2O3 and reports the high-frequency characteristics of its Schottky diode. Furthermore, Non-Patent Document 4 fabricates a Schottky diode by forming a PdCoO2 layer on the (-201) surface of β-Ga2O3, and then forming metal layers such as Ni, Ti, Cr, and Pt on it, and reports the characteristics of its Schottky diode. Moreover, Non-Patent Document 5 reports the XRD (X-Ray Diffraction) analysis results of the PdCrO2 layer formed on the (-201) surface of β-Ga2O3, and the characteristics of the Schottky interface at the interface between the (-201) surface of β-Ga2O3 and the PdCrO2 layer.

[0010] However, the (-201) facet of β-Ga2O3 used in the above-mentioned non-patent documents 2, 11 to 13 is prone to dislocation defects and stacking faults in the epitaxial layer, which is not conducive to high voltage resistance and high mobility, and is not suitable for power device applications (non-patent documents 14, 15).

[0011] Existing technical documents Non-patent literature Non-Patent Literature 1: Takayuki Harada, “Surface and interface properties of quasi-two-dimensional metallic oxides”, JSAP Review, Volume 2022, Page 220303, 2022 Non-Patent Literature 2: Takayuki Harada, 2 others, "Electric dipole effect in PdCoO2 / β-Ga2O3 Schottky diodes for high-temperature operation", Science Advances, Vol. 5, p. eaax5733, 2019 Non-patent literature 3: Jong Mok Ok, 10 others, "Pulsed-laser epitaxy of metallic delafossite PdCrO2 films", APL Materials, Volume 8, Page 051104, 2020 Non-patent literature 4: Chi Ming Yim, 5 others, “Quasiparticle interference and quantum confinement in a correlated Rashba spin-split 2D electron liquid”, Science Advances, Vol. 7, p. 7361, 2021 Non-Patent Literature 5: Takayuki Harada, 2 others, "Highly conductive PdCoO2 ultrathin films for transparent electrode", APL Materials, Vol. 6, p. 046107, 2018 Non-patent literature 6: Matthew Brahlek, 10 others, "Growth of metallic delafossite PdCoO2 by molecular beamepitaxy", Physical Review Materials, Volume 3, page 093401, 2019 Non-patent literature 7: Takayuki Harada, 3 others, "Sputter-grown c-axis-oriented PdCoO2 thin films", Journal of Applied Physics, Vol. 133, p. 085302, 2023 Non-patent literature 8: Filip Podjaski, 2 others, "Rational strain engineering indelafossite oxides for highly efficient hydrogen evolution catalysis in acidic media", Nature Catalysis, Vol. 3, p. 55, 2020 Non-Patent Literature 9: Petar Yordanov, 6 others, "Generation of Terahertz Radiation via the Transverse Thermoelectric Effect", Advanced Materials, Vol. 35, p. 2305622, 2023 Non-patent literature 10: RD Shannon, 2 others, "Chemistry of Noble Metal Oxides.I. Syntheses and Properties of ABO2 Delafossite Compounds", InorganicChemistry, Vol. 10, p. 713, 1971 Non-patent literature 11: Takayuki Harada, 1 other author, "Dynamic characteristics of PdCoO2 / β-Ga2O3 Schottky junctions", Applied Physics Letters, Vol. 116, p. 232104, 2020 Non-Patent Literature 12: Takayuki Harada, 1 other author, "Control of Schottky barrier height in metal / β-Ga2O3 junctions by insertion of PdCoO2 layers", APLMaterials, Vol. 8, p. 041109, 2020 Non-patent literature 13: T. Miyakawa, 2 others, "Inhomogeneous interface dipole effect at the Schottky junctions of PdCrO2 on β-Ga2O3 (-201)substrates", Journal of Applied Physics, Vol. 128, p. 025302, 2020 Non-patent literature 14: O. Ueda, 8 others, “Structural evaluation of defects in β-Ga2O3 single crystals grown by edge-defined film-fed growth process”, Japanese Journal of Applied Physics, Vol. 55, p. 1202BD, 2016 Non-patent literature 15: E. Ahmadi, 1 other author, “Materials issues and devices of α- and β-Ga2O3”, Journal of Applied Physics, Vol. 126, p. 160901, 2019 Non-patent literature 16: WMHaynes, “CRC handbook of chemistry and physics”, 2016, CRC Press Non-Patent Literature 17: H.B. Michaelson, 1 other author, “The work function of theelements and its periodicity”, Journal of Applied Physics, Vol. 48, pp. 4729–4733, 1977, AIP Publishing Non-Patent Literature 18: QZ Liu, 1 other author, “Areview of the metal-GaN contact technology”, Solid-State Electronics, Vol. 42, pp. 677-691, 1998, Elsevier Non-Patent Literature 19: M. Vivona, 2 others, "Materials and processes for Schottky contacts on silicon carbide", Materials, Volume 15, page 298, 2021, MDPI Summary of the Invention

[0012] The problem that the invention aims to solve In one aspect of the present invention, an object is to provide a novel semiconductor device using metallic copper-iron oxide and a method for manufacturing the same.

[0013] Methods for solving problems This invention includes the following inventions.

[0014] [1] A semiconductor device having: a compound semiconductor; and a PdCoO2 electrode disposed on the aforementioned compound semiconductor and forming a Schottky junction therebetween.

[0015] [2] The semiconductor device as described in [1] above, wherein the electrode of the aforementioned PdCoO2 is disposed on the (001) surface of the aforementioned compound semiconductor.

[0016] [3] The semiconductor device described in [1] or [2] above further includes a cathode electrode of a Schottky barrier diode electrically connected to the aforementioned compound semiconductor, wherein the electrode of the aforementioned PdCoO2 is the anode electrode of the aforementioned Schottky barrier diode.

[0017] [4] The semiconductor device as described in [1] or [2] above, wherein the electrode of the aforementioned PdCoO2 is the gate electrode of the field-effect transistor, and the aforementioned compound semiconductor is the electron supply layer of the aforementioned field-effect transistor.

[0018] [5] The semiconductor device as described in any one of [1] to [4] above, wherein the aforementioned compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide.

[0019] [6] The semiconductor device as described in [5] above, wherein the aforementioned compound semiconductor is gallium nitride, and the aforementioned PdCoO2 at the interface with the aforementioned compound semiconductor is [CoO2]. - End.

[0020] [7] The semiconductor device as described in any one of [1] to [3] above, wherein the aforementioned compound semiconductor is gallium oxide.

[0021] [8] The semiconductor device as described in [7] above, wherein the crystal structure of the aforementioned gallium oxide is a β gallium oxide structure.

[0022] [9] The semiconductor device as described in [7] or [8] above, wherein the c-axis of the aforementioned PdCoO2 is inclined from the normal direction of the (001) plane.

[0023]

[10] The semiconductor device as described in any one of [1] to [9] above, wherein the normal direction of the surface of the aforementioned compound semiconductor is deviated from the (001) direction, and the aforementioned PdCoO2 electrode is provided on the aforementioned surface.

[0024]

[11] A method for manufacturing a semiconductor device, comprising forming a PdCoO2 electrode on a compound semiconductor, wherein a Schottky junction is formed between the PdCoO2 electrode and the compound semiconductor.

[0025]

[12] The method for manufacturing a semiconductor device as described in

[11] above further includes heat treatment of the aforementioned electrodes in an oxygen-containing atmosphere.

[0026]

[13] The semiconductor device manufacturing method described in

[12] above, wherein the formation of the aforementioned electrode is carried out in an oxygen-containing atmosphere, and the oxygen partial pressure in the aforementioned oxygen-containing atmosphere during the aforementioned heat treatment is higher than the oxygen partial pressure in the aforementioned oxygen-containing atmosphere during the formation of the aforementioned electrode.

[0027]

[14] The method of manufacturing a semiconductor device as described in any one of

[11] to

[13] above, wherein the method further includes forming a cathode electrode of a Schottky barrier diode in a manner electrically connected to the aforementioned compound semiconductor, wherein the aforementioned electrode is the anode electrode of the aforementioned Schottky barrier diode.

[0028]

[15] The method of manufacturing a semiconductor device as described in any one of

[11] to

[13] above, wherein the aforementioned electrode is the gate electrode of a field-effect transistor and the aforementioned compound semiconductor is the electron supply layer of the aforementioned field-effect transistor.

[0029]

[16] The method of manufacturing a semiconductor device as described in any one of

[11] to

[15] above, wherein the aforementioned compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide.

[0030]

[17] The method of manufacturing a semiconductor device as described in any one of

[11] to

[14] above, wherein the aforementioned compound semiconductor is gallium oxide.

[0031]

[18] The method for manufacturing a semiconductor device as described in

[11] above, wherein the normal direction of the surface of the aforementioned compound semiconductor is deviated from the (001) direction, and the aforementioned PdCoO2 electrode is formed on the aforementioned surface.

[0032]

[19] A semiconductor device having: a compound semiconductor; and an electrode of a metallic copper-iron oxide disposed on the aforementioned compound semiconductor and forming a Schottky junction therebetween.

[0033] The effects of the invention According to the present invention, a novel semiconductor device using metallic copper-iron oxide and a method thereof can be provided. Attached Figure Description

[0034] [ Figure 1 ] Figure 1 This is a schematic diagram illustrating the structure of metallic copper-iron oxides.

[0035] [ Figure 2 ] Figure 2 A graph illustrating the electrical conductivity of various materials.

[0036] [ Figure 3 ] Figure 3 This is a schematic diagram illustrating the polarization of metallic copper-iron oxides.

[0037] [ Figure 4 ] Figure 4 This is a schematic diagram illustrating the relationship between the end caps of a PdCoO2 layer and the work function.

[0038] [ Figure 5 ] Figure 5 This is an energy band diagram near the interface between a metal and a semiconductor.

[0039] [ Figure 6 ] Figure 6 This is a schematic diagram illustrating the lattice mismatch between the (-201) plane of β-Ga2O3 and the oxide layer of PdCoO2.

[0040] [ Figure 7 ] Figure 7 (a) is a schematic diagram showing the lattice mismatch between the (001) plane of wurtzite gallium nitride (GaN) and the oxide layer of PdCoO2. Figure 7 (b) is a schematic diagram showing the lattice mismatch between the (001) plane of 4H silicon carbide (4H-SiC) and the oxide layer of PdCoO2.

[0041] [ Figure 8 ] Figure 8(a) and (b) in the figure are cross-sectional views during the manufacturing process of the semiconductor device according to the first embodiment (the first one).

[0042] [ Figure 9 ] Figure 9 This is a cross-sectional view (2) taken during the manufacturing process of the semiconductor device according to the first embodiment.

[0043] [ Figure 10 ] Figure 10 HAADF-STEM image of the (001) facet of the n-type GaN constituting the compound semiconductor layer according to the first embodiment and the interface with the PdCoO2 constituting the anode electrode.

[0044] [ Figure 11 ] Figure 11 This is a diagram showing the analysis results obtained by using XRD to analyze the anode electrode, the substrate thereunder, and the compound semiconductor layer according to the first embodiment.

[0045] [ Figure 12 ] Figure 12 The figure was obtained for investigating the J (current density)-V (voltage) characteristics of the semiconductor device according to the first embodiment.

[0046] [ Figure 13 ] Figure 13 The figure was obtained for investigating the C (capacitance)-V (voltage) characteristics of the semiconductor device according to the first embodiment.

[0047] [ Figure 14 ] Figure 14 To be based on Figure 12 and Figure 13 The result of the barrier height , The graph is obtained by plotting the work function of the CoO2 end face of PdCoO2 as reported in Non-Patent Literature 4.

[0048] [ Figure 15 ] Figure 15 (a) and (b) in the figure are cross-sectional views during the manufacturing process of the semiconductor device according to the second embodiment.

[0049] [ Figure 16 ] Figure 16 (a) and (b) are HAADF-STEM images of the (001) surface of the 4H-SiC compound semiconductor substrate according to the second embodiment and the interface with the PdCoO2 constituting the anode electrode.

[0050] [ Figure 17 ] Figure 17This is a diagram showing the analysis results obtained by using XRD to analyze the anode electrode 14 and the compound semiconductor substrate 21 thereunder according to the second embodiment.

[0051] [ Figure 18 ] Figure 18 The figure was obtained for investigating the CV characteristics of the semiconductor device according to the second embodiment.

[0052] [ Figure 19 ] Figure 19 To be based on Figure 18 The result of the barrier height The graph is obtained by plotting the work function of the CoO2 end face of PdCoO2 as reported in Non-Patent Literature 4.

[0053] [ Figure 20 ] Figure 20 (a) and (b) in the figure are cross-sectional views during the manufacturing process of the semiconductor device according to the third embodiment (the first one).

[0054] [ Figure 21 ] Figure 21 This is a cross-sectional view (2) taken during the manufacturing process of the semiconductor device according to the third embodiment.

[0055] [ Figure 22 ] Figure 22 A graph showing the analytical results obtained by analyzing the evaluation sample using XRD.

[0056] [ Figure 23 ] Figure 23 The figure was obtained to investigate the CV characteristics between the gate electrode and the electron transport layer in the sample used for evaluation.

[0057] [ Figure 24 ] Figure 24 (a) and (b) in the figure are cross-sectional views during the manufacturing process of the semiconductor device according to the fourth embodiment.

[0058] [ Figure 25 ] Figure 25 Schematic diagrams of the (001) facet of β-Ga2O3 and the oxide layer of PdCoO2.

[0059] [ Figure 26 ] Figure 26 (a), (b), and (c) are cross-sectional views (1) taken during the manufacturing process of the semiconductor device according to the fifth embodiment.

[0060] [ Figure 27 ] Figure 27 This is a cross-sectional view (2) taken during the manufacturing process of the semiconductor device according to the fifth embodiment.

[0061] [ Figure 28 ] Figure 28 Image (a) shows a HAADF-STEM image of the interface between the β-Ga2O3 layer and the PdCoO2 that forms the anode electrode. Figure 28 (b) in the diagram is shown schematically. Figure 28 A cross-sectional view of state (a) in the diagram.

[0062] [ Figure 29 ] Figure 29 The figure was obtained for investigating the J (current density)-V (voltage) characteristics of the semiconductor device according to the fifth embodiment.

[0063] [ Figure 30 ] Figure 30 The figure was obtained for investigating the C (capacitance)-V (voltage) characteristics of the semiconductor device according to the fifth embodiment.

[0064] [ Figure 31 ] Figure 31 To be based on Figure 30 The result of the barrier height The graph was obtained by plotting the work function of PdCoO2 as reported in Non-Patent Literature 4.

[0065] [ Figure 32 ] Figure 32 A graph showing the results of a survey on the withstand voltage of the semiconductor device according to the fifth embodiment.

[0066] [ Figure 33 ] Figure 33 A diagram illustrating the structure of the device involved in other embodiments.

[0067] [ Figure 34 ] Figure 34 A graph showing the analysis results obtained by using XRD to analyze the PdCoO2 layer of the device involved in other embodiments. Detailed Implementation

[0068] Before describing this embodiment, the matters researched by the inventors of this application will be explained.

[0069] (The matters researched by the inventors of this application) Figure 1 This diagram illustrates the structure of metallic copper-iron oxides. Metallic copper-iron oxides are compounds represented by the general formula AMO2 (A = Pd or Pt, M = Co, Cr, or Rh) and possess a Fermi surface, hence the designation "metallic". Specifically, metallic copper-iron oxides represent any one of PdCoO2, PtCoO2, PdCrO2, and PdRhO2.

[0070] like Figure 1 As shown, metallic copper-iron oxide is a quasi-two-dimensional layered compound obtained by stacking two atomic layers: an oxide layer 1 formed from MO2 and a metal layer 2 composed of element A arranged in a triangular lattice in the (001) plane. Due to the atomic arrangement in its metal layer 2, the normal direction of the Fermi surface of the metallic copper-iron oxide at most k points in the reciprocal lattice space becomes perpendicular to the c-axis direction. As a result, the movement of electrons is restricted to the plane formed by the a-axis and b-axis directions, thus suppressing surface scattering of electrons. Even when the metallic copper-iron oxide is made into an extremely thin film, it can maintain high conductivity.

[0071] Figure 2 A graph illustrating the electrical conductivity of various materials is shown. For example... Figure 2 As shown, PtCoO2 and PdCoO2 exhibit electrical conductivity comparable to Au, and are about 5 times higher than their corresponding elemental metals Pt and Pd.

[0072] Furthermore, metallic copper-iron oxides are stable substances that do not deteriorate in corrosive solutions such as acids and alkalis, or in the atmosphere. For example, PdCoO2 layers exhibit heat resistance up to 800°C in the atmosphere. Although metallic copper-iron oxides are layered crystals, they also possess ionic bonds along the c-axis, thus exhibiting mechanical strength and peel strength comparable to other ceramic materials.

[0073] Figure 3 This is a schematic diagram illustrating the polarization of metallic copper-iron oxides. [MO2] in oxide layer 1. - and A in metal layer 2 + It possesses ionic charge, thus exhibiting polarization at the c-face. Due to this surface polarization, corresponding to the end cap, metallic copper-iron oxides exhibit an unparalleled large work function.

[0074] Figure 4 This is a schematic diagram illustrating the relationship between the end caps of a PdCoO2 layer and the work function. (See diagram below.) Figure 4 As shown, [CoO2] - The work function of PdCoO2 capped with oxide layer 1 It is 7.8 eV, significantly greater than that of Pd. + The work function of PdCoO2 capped with metal layer 2 The value is 4.7 eV (Non-Patent Document 4). Due to such a large work function, it is expected that a Schottky barrier with a large barrier height can be formed at the interface between the semiconductor and the metallic copper-iron oxide.

[0075] Figure 5This is an energy band diagram near the interface between a metal and a semiconductor. It should be noted that the equations in the diagram correspond to the Schottky model. For example... Figure 5 As shown, if a metal and a semiconductor are brought into contact, a potential barrier height is formed at their interface. The Schottky barrier. The work function of a metal. From vacuum energy level E vac With Fermi energy E F The difference is used to define it. Additionally, the electron affinity χ of a semiconductor... s From vacuum energy level E vac Defined by the energy difference with the lower conduction band of the semiconductor. In this case, according to the Schottky model, Furthermore, if the lower conduction band of a semiconductor is connected to the Fermi energy E... F Let the difference be E c Then the built-in potential V bi The product of the elementary charge q and the elementary charge q·V bi With energy E c The sum of these becomes the barrier height. .

[0076] According to the Schottky model, the barrier height Work function of metal The barrier height increases proportionally. Therefore, by stacking metallic copper-iron oxide layers with high work functions, as described above, on a semiconductor layer, it is possible to achieve a very high barrier height, which is believed to enable the development of novel semiconductor devices such as Schottky diodes with extremely high withstand voltage and high-temperature operating performance that have not been achieved until now.

[0077] Furthermore, if a metallic copper-iron oxide layer is formed on a semiconductor with a large band gap, such as β-Ga2O3, the barrier height can be increased. It can also improve the voltage resistance of semiconductor devices.

[0078] The stacked structure of a semiconductor layer and a metallic copper-iron oxide layer is a heterostructure in which different materials are stacked in the lower and upper layers, respectively. In order to obtain a good heterostructure in which lattice defects in the upper layer are suppressed, it is common sense to minimize the surface mismatch between the lower layer and the upper layer. For example, in Non-Patent Document 2, a PdCoO2 layer is formed on the (-201) plane of β-Ga2O3.

[0079] Figure 6This is a schematic diagram illustrating the lattice mismatch value between the (-201) plane of β-Ga₂O₃ and the oxide layer 1 of PdCoO₂. The lattice mismatch value is defined as the percentage of the ratio of the lattice constants of the layers at the interface. The (-201) plane of β-Ga₂O₃ has lattice points arranged in a hexagonal pattern, similar to the PdCoO₂ layer, and has a lattice constant of the same degree as the oxide layer 1 of PdCoO₂. Therefore, it is possible to form a well-ordered PdCoO₂ layer with a lattice mismatch value as low as approximately 3.2% and few defects.

[0080] On the other hand, if the surface for forming metallic copper-iron oxides such as PdCoO2 layers is limited to the (-201) surface, the applicability of metallic copper-iron oxides becomes narrower, making it difficult to provide new semiconductor devices that are advantageous for high voltage withstand due to the high Schottky barrier height.

[0081] As the surface on which the metallic copper-iron oxide layer is formed, other than the (-201) surface, the inventors of this application focus on the (001) surface. Since the (001) surface is mostly used in the mass production process of various semiconductor devices, if the metallic copper-iron oxide layer can be formed on the (001) surface, its application in the mass production process of the metallic copper-iron oxide layer will become easier, and new semiconductor devices can be provided to the market.

[0082] For example, in Non-Patent Document 3, a PdCrO2 layer is formed on the (001) facet of 4H silicon carbide (4H-SiC). It should be noted that "4H" before SiC is a designation identifying one of the various polymorphs of SiC; "H" indicates hexagonal, and "4" indicates the number of SiC unit cells in one period along the c-axis. According to Non-Patent Document 3, the lattice mismatch between the (001) facet of 4HSiC and the PdCrO2 layer is approximately 4.8%. This level of lattice mismatch is considered the limit for forming a PdCrO2 layer with good crystallinity and few lattice defects. In Non-Patent Document 3, in addition to the PdCrO2 layer, the formation of impurity phases is also observed. Non-Patent Document 3 does not show the conductivity of the PdCrO2 layer on 4H silicon carbide, nor does it evaluate the electrical properties of the interface between 4H silicon carbide and the PdCrO2 layer; the Schottky barrier at the interface is unclear.

[0083] However, as Figure 2 As shown, the conductivity of PdCrO2 is only about one-third that of other metallic copper-iron oxides such as PtCoO2 and PdCoO2, indicating that there is still room for improvement in promoting the low resistance of semiconductor devices such as Schottky barrier diodes.

[0084] Therefore, the inventors of this application focused on PdCoO2, which has an electrical conductivity approximately three times higher than that of PdCrO2 in Non-Patent Document 3 (see [reference]). Figure 2The degree of lattice mismatch between the (001) plane of the semiconductor layer and PdCoO2 was calculated. The results are shown in... Figure 7 (a) and (b) in the text.

[0085] Figure 7 (a) in the diagram is a schematic showing the lattice mismatch between the (001) plane of wurtzite gallium nitride (GaN) and the oxide layer 1 of PdCoO2. Figure 7 As shown in (a), the (001) plane of GaN has a lattice mismatch of 11% with PdCoO2.

[0086] Figure 7 (b) is a schematic diagram showing the lattice mismatch between the (001) plane of 4H silicon carbide (4H-SiC) and the oxide layer 1 of PdCoO2. Figure 7 As shown in (b), the lattice mismatch between the (001) plane of 4H-SiC and PdCoO2 is 7.8%.

[0087] In such Figure 7 In cases like (a) and (b), where the lattice mismatch is large, it is considered difficult to grow the PdCoO2 layer without damaging its crystallinity. Therefore, based on common technical knowledge, it would be difficult for someone skilled in the art to select the combination of the (001) plane and PdCoO2. Thus, the inventors of this application anticipated that it would be impossible to form a PdCoO2 layer on the (001) plane, or even if it could be formed, lattice defects would be generated in the PdCoO2 layer, resulting in a significant reduction in the crystallinity of the PdCoO2 layer. However, contrary to this expectation, the following unexpected effect has been clearly achieved: as in the following embodiments, a PdCoO2 layer that functions as a good Schottky electrode can be formed.

[0088] (First Embodiment) Regarding the semiconductor device according to the first embodiment, its manufacturing process will be described. In this embodiment, a Schottky barrier diode with a Schottky barrier formed at the interface between gallium nitride and PdCoO2 is manufactured as follows.

[0089] Figure 8 (a), (b) and Figure 9 This is a cross-sectional view taken during the manufacturing process of the semiconductor device involved in this embodiment.

[0090] First, such as Figure 8As shown in (a), a substrate 10 is prepared on which a GaN (wisteria gallium nitride) layer 12 is formed on a sapphire (Al2O3) substrate 11 with a thickness of 100 nm to 2000 nm, for example, 300 nm to 1700 nm, or 500 nm to 1500 nm, and here 1000 nm. When the thickness of the GaN layer 12 is 100 nm or more, the crystallinity of the compound semiconductor layer 13 grown on the GaN layer 12 can be improved. The surface of the GaN layer 12 is the (001) plane. It should be noted that a crystal substrate formed from other crystals such as silicon carbide can also be used instead of the sapphire substrate 11. In addition, a separate bulk GaN layer 12 that is not bonded to a substrate such as the sapphire substrate 11 can also be used instead of the stack of the sapphire substrate 11 and the GaN layer 12. As an example, the thickness of the GaN layer 12 in this bulk material is 0.1 mm to 1.2 mm, for example, 0.2 mm to 1.0 mm, or 0.3 mm to 0.8 mm, and in this case, 0.40 mm.

[0091] Next, on the (001) facet of the GaN layer 12, an n-type wurtzite GaN layer is formed as the compound semiconductor layer 13 using MOVPE (Metal Organic Vapor Phase Epitaxy) with a thickness of 0.2 μm to 200 μm or less, for example, 1.0 μm to 150 μm or less, 1.5 μm to 100 μm or less, 2.0 μm to 50 μm or less, and in this case, 2.4 μm. When the thickness of the compound semiconductor layer 13 or the GaN layer serving as the compound semiconductor layer 13 is 0.2 μm or more, the withstand voltage can be sufficiently improved; conversely, when it is 200 μm or less, the on-resistance can be sufficiently reduced.

[0092] During the deposition of the compound semiconductor layer 13, impurities are typically not doped, but it is also possible to dope with 1×10⁻⁶ impurities. 15 cm -3 Above 5×10 17 cm -3 The following concentrations, for example, 3 × 10 15 cm -3 Above 1×10 17 cm -3 The following concentrations, or 5×10 15 cm -3 Above 5×10 16 cm -3 The following concentrations are used to dope n-type impurities such as silicon (Si) and germanium (Ge). By doping the compound semiconductor layer 13 with n-type impurities at this concentration, the on-resistance can be reduced. For example, a concentration of 1 × 10⁻⁶ is used in the compound semiconductor layer 13.16 cm -3 The concentration of silicon doped.

[0093] The surface of the compound semiconductor layer 13 is the (001) face of n-type wurtzite GaN. The surface orientation of the compound semiconductor layer 13 (GaN in this case) can be determined using an X-ray diffraction apparatus (e.g., "Empyrean3" manufactured by Malvern Panalytical Ltd.). It should be noted that the compound semiconductor layer 13 can also be formed using MOCVD (Metal Organic Chemical Vapor Deposition), sputtering, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), solid phase deposition, or atomization CVD instead of MOVPE.

[0094] Next, to obtain Figure 8 The process up to the cross-sectional structure shown in (b) will be described. First, on the (001) surface of the compound semiconductor layer 13, a PdCoO2 layer is formed as the anode electrode 14 in a cavity (not shown) using pulsed laser deposition with a thickness of 1 nm to 200 nm, for example 10 nm to 100 nm, or 20 nm to 50 nm, here 25 nm. When the thickness of the anode electrode 14 or the PdCoO2 layer serving as the anode electrode 14 is 1 nm or more, the Schottky barrier height at the interface can be increased; and when it is 200 nm or less, the on-resistance can be sufficiently reduced.

[0095] In pulsed laser deposition, the energy density for irradiating the target is 0.5 J / cm². 2 Above 4J / cm 2 For example, 0.8 J / cm 2 Above 3J / cm 2 Below, or 1.2 J / cm 2 Above 2J / cm 2 The value here is 1.5 J / cm. 2 The fourth-harmonic wavelength (266 nm) of the Nd:YAG laser. For example, granules made by sintering PdCoO2 powder can be used as the target material.

[0096] Furthermore, the film-forming atmosphere is set to an atmosphere formed by plasma-plating either oxygen or ozone gas, or an atmosphere formed by plasma-plating both oxygen and ozone gas. When oxygen is included in the film-forming atmosphere, it is preferable from the perspective of suppressing the formation of oxygen defects and the reductive decomposition of the PdCoO2 film. In this example, the partial pressure of oxygen in the film-forming atmosphere is set to 0.1 Pa to 300 Pa or less, for example, 5 Pa to 200 Pa or less, or 10 Pa to 100 Pa or less, in this case, 20 Pa.

[0097] Furthermore, the substrate temperature during film formation is 400°C to 850°C, preferably 500°C to 750°C, and more preferably 650°C to 750°C. In this example, it is set to 660°C. When the substrate temperature during film formation is 850°C or lower, the reductive decomposition of the grown film can be prevented.

[0098] It should be noted that pulsed laser deposition is a type of physical vapor deposition (PVD) method. Other PVD methods, different from pulsed laser deposition, can also be used to form the anode electrode 14. Examples of such PVD methods include vapor deposition, ion plating, ion beam deposition, sputtering, and molecular beam epitaxy. Alternatively, chemical vapor deposition methods such as hydride vapor phase epitaxy (HVPE), solid phase deposition, MOVPE, MOCVD, and atomization CVD can be used instead of PVD.

[0099] When a PdCoO2 layer is formed using physical vapor deposition, the PdCoO2 layer at the interface with the (001) plane of GaN spontaneously forms [CoO2]. - oxide layer 1 (see Figure 4 End cap. Therefore, as shown in reference Figure 4 To illustrate, compared to the case where the metal layer 2 is used as the end cap, the work function at the interface is increased, which can increase the barrier height of the Schottky barrier.

[0100] Furthermore, the anode electrode 14 grown in this manner can be subjected to heat treatment to improve the crystallinity of PdCoO2. For example, to prevent oxygen from escaping from PdCoO2 and causing the anode electrode 14 to decompose, it is preferable to perform the heat treatment in the same atmosphere as when the anode electrode 14 was formed, i.e., an oxygen-containing atmosphere. Moreover, by performing the heat treatment in an oxygen-containing atmosphere with a higher oxygen partial pressure than the film-forming atmosphere of the anode electrode 14, it is possible to prevent the oxygen absorbed into the anode electrode 14 during film formation from escaping. As an example, the anode electrode 14 can be heat-treated in an oxygen-containing atmosphere with an oxygen partial pressure of 0.1 Pa or more but less than atmospheric pressure, for example, atmospheric pressure, and a substrate temperature of 400°C or more but less than 900°C, for example, 600°C or more but less than 850°C, or 700°C or more but less than 850°C, in this case, 800°C. As an apparatus for performing the heat treatment, a furnace with air and oxygen flowing at atmospheric pressure is provided.

[0101] Then, a resist pattern (not shown) is formed on the anode electrode 14. Using this pattern as a mask, the anode electrode 14 is patterned using RIE (Reactive Ion Etching) based etching. For example, a mixed gas composed of Ar gas and BCl3 gas at a flow ratio of 1:4 can be used as the etching gas in this RIE. Afterward, the resist pattern is removed. It should be noted that a stripping method can also be used to pattern the anode electrode 14 instead of etching-based patterning.

[0102] Next, as Figure 9 As shown, an aluminum wire 15a is directly bonded to the compound semiconductor layer 13, and an indium layer 15b is pressed onto it, thereby forming a cathode electrode 15 electrically connected to the compound semiconductor layer 13 via an ohmic junction. The method of forming the cathode electrode 15 is not limited to this; a metal layer such as a titanium layer or an aluminum layer can also be deposited on the compound semiconductor layer 13 as the cathode electrode 15.

[0103] The basic structure of the semiconductor device 20 according to this embodiment is completed through the above method. The semiconductor device 20 includes: a compound semiconductor layer 13; and an anode electrode 14 of PdCoO2 disposed on the compound semiconductor layer 13 and having a Schottky junction formed between it and the compound semiconductor layer 13. Specifically, it is a Schottky barrier diode with a Schottky barrier formed at the interface between the compound semiconductor layer 13 and the anode electrode 14. To apply a forward bias voltage to the semiconductor device 20, the potential of the anode electrode 14 only needs to be higher than the potential of the cathode electrode 15. Similarly, to apply a reverse bias voltage, the potential of the anode electrode 14 only needs to be lower than the potential of the cathode electrode 15.

[0104] Next, the results of various investigations conducted by the inventors of this application in this embodiment will be explained.

[0105] Figure 10 The image is a HAADF-STEM (High Angle Annular Dark-Field Scanning Transmission Electron Microscopy) image of the interface between the (001) facet of the n-type GaN constituting the compound semiconductor layer 13 and the PdCoO2 constituting the anode electrode 14.

[0106] like Figure 7 As shown in (a), the lattice mismatch between the (001) plane of GaN and PdCoO2 is as large as 11%. According to current technical common sense, it is expected that a PdCoO2 layer will not grow, or even if it does grow, it will become a PdCoO2 layer with significantly impaired crystallinity due to a large number of lattice defects. However, contrary to expectations, as shown in (a), the lattice mismatch between GaN and PdCoO2 is as follows: Figure 10 In this way, the PdCoO2 layer is neatly oriented along the c-axis, indicating that a PdCoO2 layer with good crystallinity can be obtained.

[0107] Figure 11 A graph showing the analytical results obtained by analyzing the anode electrode 14, the substrate 10 below it, and the compound semiconductor layer 13 using XRD (X-ray diffraction). An Empyrean 3 manufactured by Malvern Panalytical was used as the XRD apparatus. Figure 11 The horizontal axis represents the diffraction angle of X-rays (2). θ The vertical axis represents the intensity of X-rays measured in arbitrary intensities. Additionally, Figure 11 In the diagram, downward arrows indicate the diffraction peaks of the (00l) plane (l=1, 2, ...) of PdCoO2 constituting the anode electrode 14.

[0108] like Figure 11 As shown, the diffraction peaks of PdCoO2 on the (00l) plane (l=1, 2, ...) are clearly visible. This result shows that even when a PdCoO2 layer is formed on the (001) plane of GaN with a lattice mismatch of 11%, a PdCoO2 layer with few lattice defects and excellent crystallinity can be obtained.

[0109] Figure 12 The graph was obtained for investigating the J (current density)-V (voltage) characteristics of semiconductor device 20. The JV characteristics were measured using an Agilent Technologies 4155B semiconductor parameter analyzer. Figure 12 The horizontal axis represents the voltage between the anode electrode 14 and the cathode electrode 15, with the case where the potential of the anode electrode 14 is higher than that of the cathode electrode 15 being defined as positive. Additionally, Figure 12The vertical axis represents the absolute value of the current density of the current flowing between the anode electrode 14 and the cathode electrode 15.

[0110] In this investigation, the anode electrode 14 was made into a circle with a diameter D = 100 μm when viewed from above, and measurements were taken at room temperature (298 K). The barrier height of the Schottky barrier based on this JV characteristic was determined. The value is 1.66 eV. Furthermore, the ideal factor n of the Schottky barrier is 1.03. It should be noted that the ideal factor n is defined by the following equation (1).

[0111] [Mathematical Expression 1] In equation (1), Let T be the effective Richardson constant, q be the absolute temperature, q be the elementary charge, and k be the Boltzmann constant. In this investigation, following standard procedures, the rising portion of the JV characteristic (J=10) is... -7 A / cm 2 ~10 -5 A / cm 2 The slope obtained by linear fitting of the region is compared with the above formula to obtain the value of n. The closer the value of n is to 1, the more the JV characteristics of the Schottky barrier can be presented with ideal thermionic emission.

[0112] Figure 13 The graph was obtained to investigate the C (capacitance)-V (voltage) characteristics of semiconductor device 20. The CV characteristics were measured using an E4980A LCR meter manufactured by Keysight. Figure 13 The meaning of the horizontal axis and Figure 12 The horizontal axis is the same for both, therefore its description is omitted. Additionally, Figure 13 The vertical axis represents the square of the ratio (S / C) of the area S of the anode electrode 14 as viewed from above to the depletion layer capacitance C of the Schottky barrier. 2 .

[0113] Similar to the JV characteristic measurement, in this investigation, the anode electrode 14 was also set as a circle with a diameter D = 100 μm when viewed from above, and measurements were performed at room temperature (298 K). Then, measurements were taken at multiple voltage values ​​(S / C). 2 Find the fitted straight line that fits multiple measured values. When the intercept of this fitted straight line with the horizontal axis is set to b, the built-in potential V... bi It can be calculated using the following formula (2).

[0114] [Mathematical Expression 2] Where k is the Boltzmann constant and T is the absolute temperature. The built-in potential V at room temperature (298 K) is calculated using equation (2). bi As a result, in this example, q·V bi =1.93eV.

[0115] In addition, if Figure 13 Let the absolute value of the slope of the fitted straight line be a, then the doping density N of the compound semiconductor layer 13 is... D It can be calculated using the following formula (3).

[0116] [Mathematical Expression 3] Where ε is the dielectric constant of the compound semiconductor layer 13. The doping density N is calculated according to equation (3). D As a result, in this example, N D =1.1×10 16 cm -3 .

[0117] For reference Figure 5 The barrier height is explained. Equal to q·V bi With energy E c The sum of. Energy E c The density of states N that can be used in the conduction band c Doping density N D Boltzmann constant k and absolute temperature T are calculated according to the following formula (4).

[0118] [Mathematical Expression 4] The doping density N in equation (4) D The value calculated according to equation (3) above is used. Additionally, the state density N in equation (4) is... c It can be obtained from the following formula (5).

[0119] [Mathematical Expression 5] The derivation of equation (5) is described, for example, in the following paper 1.

[0120] (Paper 1) W. Goetz, 2 others, “Nitrogen donors in 4Hsilicon carbide”, Journal of Applied Physics, Vol. 73, p. 3332, 1993 In equation (5) For GaN, the effective mass of electrons is... (Paper 2). Where m0 is the effective mass of an electron in a vacuum.

[0121] (Paper 2) P. Perlina, 10 others, “Determination of the effective mass of GaN from infrared reflectivity and Hall effect”, Applied Physics Letters, Vol. 68, p. 1114, 1996 In addition, M in equation (5) c M represents the number of conduction band bottoms contained in the first Brillouin zone; for GaN, M c =1.

[0122] If they are used, then for GaN, at room temperature (298K) E c =0.14eV, add q·V to it bi Barrier height at room temperature It becomes 2.07 eV.

[0123] Figure 14 To be based on Figure 12 and Figure 13 The result of the barrier height , The graph is obtained by plotting the work function of the CoO2 end face of PdCoO2 as reported in Non-Patent Literature 4. Figure 14 For comparison, the barrier heights and work functions of representative metals such as titanium (Ti), chromium (Cr), nickel (Ni), palladium (Pd), silver (Ag), platinum (Pt), gold (Au), and lead (Pb) are also plotted. Regarding the barrier height, reference is made to Non-Patent Literature 18; regarding the work function, references are made to Non-Patent Literatures 16 and 17. Furthermore, for reference, the half-value of the band gap Eg of GaN (0.5E) is also recorded. g ).

[0124] It should be noted that, regarding the CV characteristic, the barrier height is calculated by averaging the area of ​​the interface. In contrast, the JV characteristic provides information about regions with low barriers and easy current flow. Therefore, the barrier height typically obtained from the JV characteristic is... The height becomes the average barrier height of the surface calculated based on CV characteristics. Low value.

[0125] Barrier height obtained from CV properties Subtract the barrier height obtained from the JV characteristic The obtained value is the standard deviation σ of the barrier height.s It has the relationship of equation (6) (Paper 3).

[0126] [Mathematical Expression 6] (Paper 3) Juergen H. Werner, 1 other author, “Barrier inhomogeneities at Schottky contacts”, Journal of Applied Physics Physics Letters, Vol. 69, p. 1522, 1991 Equation (6) means that, and The greater the difference, the greater the fluctuation in barrier height within the interface. This fluctuation varies depending on the uniformity of crystal orientation, the amount of defects, and the doping level of the semiconductor layer at the interface. Since the ideal barrier height at the interface is better reflected by... Therefore, with compared to, It has higher reliability.

[0127] Figure 14 The barrier height of the metal shown is at most about 1.3 eV, while the barrier height involved in this embodiment is... The result shows that if the PdCoO2 anode 14 is formed on the (001) surface of the GaN compound semiconductor layer 13 as in this embodiment, a Schottky barrier with a very high barrier height of more than 2.0 eV is formed at their interface.

[0128] Therefore, for the semiconductor device 20 according to this embodiment, it becomes a device that has the capability to... Figure 14 The representative metal shown can achieve high-temperature operation and very high withstand voltage, which is not possible when used for the anode electrode 14, enabling new power devices that are not easily broken down even when a reverse bias is applied.

[0129] In addition, as referenced Figure 2 As explained, PdCoO2 has a conductivity comparable to Au, thus enabling not only high voltage withstand but also high current and high speed in the semiconductor device 20. The same applies to the second, third, and fourth embodiments described later.

[0130] Furthermore, since the (001) surface of GaN is often used in the mass production process of various semiconductor devices, a PdCoO2 layer is formed on the (001) surface of GaN as in this embodiment, thereby enabling the efficient use of existing mass production processes to mass produce semiconductor devices 20.

[0131] It should be noted that in this embodiment, the surface orientation of the compound semiconductor layer 13 is set to the (001) direction, but the normal direction of the compound semiconductor layer 13 can also be slightly deviated from the (001) direction within a range that does not significantly disrupt the crystallinity of the anode electrode 14. As an example, the normal direction of the compound semiconductor layer 13 can be deviated from the (001) direction within a range of less than 10°.

[0132] (Second Implementation) Next, the semiconductor device according to the second embodiment will be described according to its manufacturing process. In this embodiment, a Schottky barrier diode in which a Schottky barrier is formed at the interface between silicon carbide and PdCoO2 is manufactured as follows.

[0133] Figure 15 (a) and (b) in this embodiment are cross-sectional views during the manufacturing process of the semiconductor device.

[0134] First, such as Figure 15 As shown in (a) above, it is prepared with 1×10 17 cm -3 Above 1×10 20 cm -3 The following concentrations, for example 5 × 10 17 cm -3 Above 5×10 19 cm -3 The following concentrations, or 1×10 18 cm -3 Above 1×10 19 cm -3 The following concentrations, here 8×10 18 cm -3 A 4H-SiC substrate doped with nitrogen at a concentration as an n-type impurity is used as the compound semiconductor substrate 21. By doping the compound semiconductor substrate 21 with nitrogen at this concentration, the on-resistance can be reduced. The surface of the compound semiconductor substrate 21 is the (001) plane of 4H-SiC.

[0135] In addition, the method adopted is the same as that in the first embodiment. Figure 8 Using the same physical vapor deposition and patterning conditions as in (b), a PdCoO2 layer is formed on the (001) surface of the compound semiconductor substrate 21 as the anode electrode 14 with a thickness of 1 nm to 200 nm, for example 10 nm to 100 nm, or 20 nm to 50 nm, here 25 nm.

[0136] Similar to the first embodiment, even in the case where the substrate is a (001) surface of 4H-SiC as in this embodiment, by forming a PdCoO2 layer using physical vapor deposition, most of the PdCoO2 layer at the interface with the (001) surface of 4H-SiC is coated with [CoO2]. - oxide layer 1 (see Figure 4 (Spontaneous closure.) As a result, such as Figure 4 Thus, compared with the case of being capped with metal layer 2, the work function at the interface becomes larger, which can increase the barrier height of the Schottky barrier.

[0137] Alternatively, as described in the first embodiment, oxygen can be prevented from leaving the anode electrode 14 by heat treatment in an oxygen-containing atmosphere.

[0138] Then, as Figure 15 As shown in (b), a nickel layer is formed on both the compound semiconductor substrate 21 and the anode electrode 14 using a vapor deposition or sputtering method. This nickel layer is then patterned to form a cathode electrode 22 electrically connected to the compound semiconductor substrate 21. Subsequently, the cathode electrode 22 is heat-treated to silicideize it, simultaneously making the interface between the compound semiconductor substrate 21 and the cathode electrode 22 an ohmic bond. For example, by heat-treating the substrate at 750°C for 5 minutes in an atmosphere with an oxygen partial pressure of 0.3 Pa, the cathode electrode 22 can be nickel-silicided while maintaining the crystallinity of the PdCoO2 layer of the anode electrode 14. The thickness of the cathode electrode 22 is not particularly limited; in this example, it is formed with a thickness of 10 nm to 200 nm, for example, 20 nm to 100 nm, or 30 nm to 80 nm, here 50 nm. When the thickness of the cathode electrode 22 is 10 nm or more, the effect of surface oxidation of the nickel layer before silicide physicochemical treatment can be reduced. In addition, when the thickness is 200 nm or less, the peeling of the nickel layer can be prevented.

[0139] The basic structure of the semiconductor device 30 according to this embodiment is completed through the above methods. The semiconductor device 30 includes: a compound semiconductor substrate 21; and an anode electrode 14 of PdCoO2 disposed on the compound semiconductor substrate 21 and having a Schottky junction formed between it and the compound semiconductor substrate 21. Specifically, it is a Schottky barrier diode with a Schottky barrier formed at the interface between the compound semiconductor substrate 21 and the anode electrode 14. To apply a forward bias voltage to the semiconductor device 30, the potential of the anode electrode 14 is made higher than the potential of the cathode electrode 22. Conversely, to apply a reverse bias voltage, the potential of the anode electrode 14 is made lower than the potential of the cathode electrode 22.

[0140] Next, the results of various investigations conducted by the inventors of this application in this embodiment will be explained.

[0141] Figure 16 Images (a) and (b) are HAADF-STEM images of the interface between the (001) surface of the 4H-SiC substrate 21 and the PdCoO2 substrate 14. It should be noted that... Figure 16 (a) and Figure 16 In (b) of the images, the parts of the interface that were photographed are different.

[0142] like Figure 7 As shown in (b), the lattice mismatch between the (001) plane of 4H-SiC and PdCoO2 is as high as 7.8%. Therefore, based on current technical common sense, it is expected that a PdCoO2 layer will not grow, or even if it does, it will be a PdCoO2 layer with significantly impaired crystallinity due to numerous lattice defects. However, contrary to expectations, as shown in (b), the lattice mismatch between the (001) plane of 4H-SiC and PdCoO2 is as high as 7.8%. Figure 16 In (a) and (b), the PdCoO2 layer is neatly oriented in several directions, indicating that a PdCoO2 layer that can function as an excellent Schottky electrode can be obtained.

[0143] In addition, it was clarified that, such as Figure 16 (a) and Figure 16 As shown in (b), the orientation direction (c-axis direction) of the PdCoO2 layer varies depending on the location. This means that there are multiple domains with different c-axis directions in the PdCoO2 layer, thus indicating that the PdCoO2 layer on the (001) plane of 4H-SiC is polycrystalline. The reason for this polycrystalline nature is that, in addition to the (001) plane of PdCoO2, there are multiple other PdCoO2 planes that are easily oriented on the (001) plane of 4H-SiC.

[0144] Figure 17 A figure showing the analytical results obtained by analyzing the anode electrode 14 and the underlying compound semiconductor substrate 21 using XRD. Figure 17 The meanings of the vertical and horizontal axes are as follows: Figure 11 The same as in [the previous text], therefore its description is omitted. Additionally, Figure 17 In, with Figure 11 Similarly, downward arrows indicate the diffraction peaks in the (00l) plane (l=1, 2, ...) of PdCoO2 constituting the anode electrode 14.

[0145] like Figure 17As shown, the diffraction peaks of PdCoO2 on the (00l) plane (l=1, 2, ...) are clearly visible. This result shows that even when a PdCoO2 layer is formed on the (001) plane of 4H-SiC with a lattice mismatch of 7.8%, a PdCoO2 layer with mostly (001) orientation, few lattice defects, and excellent crystallinity can be obtained.

[0146] Figure 18 The figure was obtained for investigating the CV characteristics of semiconductor device 30. Figure 18 The meanings of the vertical and horizontal axes are as follows: Figure 13 The vertical axis and the horizontal axis are the same, so their description is omitted.

[0147] In this investigation, the anode electrode 14 was a circle with a diameter D = 200 μm when viewed from above, and measurements were performed at room temperature (298 K). Then, measurements were taken at multiple voltage values ​​(S / C). 2 The fitting line for multiple measured values ​​is obtained. Based on the fitting line and the aforementioned equation (2), q·V at room temperature (298K) is calculated. bi The value becomes 2.77 eV. Furthermore, the donor concentration N of the compound semiconductor substrate 21, calculated according to the aforementioned equation (3), is... D It is 7.7×10 18 cm -3 .

[0148] In 4H-SiC, equation (5) The value is 0.19m0 (Paper 1), M c The value is 12. The density of states N will be calculated based on these values ​​using equation (5). c And the donor concentration N mentioned above D (7.7×10) 18 cm -3 When used in equation (4), for 4H-SiC, E at room temperature (298K) c =0.03 eV. The result is that for q·V bi Add E c The barrier height obtained at room temperature (298K) It becomes 2.80 eV, which is higher than the barrier height in the first embodiment. (It is) larger.

[0149] Figure 19 To be based on Figure 18 The result of the barrier height The graph was obtained by plotting the work function of the CoO2 end face of PdCoO2 as reported in Patent Document 4 and Non-Patent Document 4. Additionally, in Figure 19For comparison, the barrier heights and work functions of representative metals in region A are plotted. The metals included in region A are Ni, Pt, Au, Ir, Ta, Ti, W, and Mo. For the barrier heights, reference 19 is cited; for the work functions, references 16 and 17 are cited.

[0150] Figure 19 The barrier heights of the metals shown are at most around 1.8 eV. In contrast, the barrier height involved in this embodiment is... The value is 2.82 eV, which is significantly higher than that value. Based on this result, it is clear that if the PdCoO2 anode electrode 14 is formed on the (001) surface of the 4H-SiC compound semiconductor substrate 21 as in this embodiment, a Schottky barrier with a very high barrier height of 2.82 eV is formed at their interface.

[0151] Therefore, the semiconductor device 30 according to this embodiment becomes capable of […]. Figure 19 The very high withstand voltage and operating temperature that cannot be achieved when the various metals shown are used for the anode electrode 14 enable the realization of a new type of power device that is not easily broken down even when a reverse bias is applied.

[0152] Furthermore, the (001) surface of 4H-SiC is often used in the mass production process of various semiconductor devices. Therefore, by forming a PdCoO2 layer on the (001) surface of 4H-SiC as in this embodiment, it is possible to effectively utilize existing mass production processes to mass produce semiconductor devices 30.

[0153] It should be noted that in this embodiment, a 4H-SiC substrate is used as the compound semiconductor substrate 21, but other hexagonal polymorph substrates of silicon carbide can also be used as the compound semiconductor substrate 21, and a PdCoO2 anode electrode 14 is formed on its (001) surface. Examples of such polymorphs include 2H, 6H, 8H, and 10H polymorphs. The (001) surface of these polymorphs has lattice points arranged in a hexagonal pattern similar to those of 4H-SiC, so it is expected that a PdCoO2 layer can be formed that is neatly oriented in the c-axis direction, similar to that of 4H-SiC.

[0154] It should be noted that in this embodiment, the surface orientation of the compound semiconductor substrate 21 is set to the (001) direction, but the normal direction of the compound semiconductor substrate 21 can also be slightly deviated from the (001) direction within a range that does not significantly disrupt the crystallinity of the anode electrode 14. As an example, the normal direction of the compound semiconductor substrate 21 can be deviated from the (001) direction by a range of less than 10°.

[0155] (Third implementation) Next, the semiconductor device according to the third embodiment will be described according to its manufacturing process. In this embodiment, a GaN-HEMT (High Electron Mobility Transistor) using GaN-based compound semiconductor layers in the electron supply layer and electron transport layer is manufactured as a semiconductor device as follows.

[0156] Figure 20 (a), (b) and Figure 21 This is a cross-sectional view taken during the manufacturing process of the semiconductor device involved in this embodiment.

[0157] First, such as Figure 20 As shown in (a), an undoped GaN layer is formed as an electron transport layer 42 on a SiC substrate 41 using the MOVPE method, with a thickness of 0.2 μm to 4 μm, for example, 1.0 μm to 3.5 μm, or 1.5 μm to 3.2 μm, and in this case, 3 μm. When the thickness of the electron transport layer 42 is 0.2 μm or more, the crystallinity of the electron transport layer 42 can be improved, and when it is 4 μm or less, flatness can be ensured.

[0158] Then, on the electron transport layer 42, an AlGaN layer with a thickness of 10 nm to 50 nm, for example 15 nm to 45 nm, or 20 nm to 40 nm (here, 30 nm), is formed using the MOVPE method as the body layer 43a of the electron supply layer 43. When the thickness of the body layer 43a or the AlGaN layer is 10 nm or more, the gate leakage current can be reduced; when it is 50 nm or less, the work function of the PdCoO2 electrode can be improved.

[0159] During the film formation of the bulk layer 43a, impurities are usually not added, but it is also possible to dope with 1×10⁻⁶ impurities. 16 cm -3 Above 7×10 18 cm -3 For example, 5×10 16 cm -3 Above 6×10 18 cm -3 The following concentrations, or 1×10 17 cm -3 Above 6×10 18 cm -3 The following concentrations are used to dope n-type impurities such as silicon (Si) and germanium (Ge). By doping the bulk layer 43a with n-type impurities at these concentrations, the concentration of the two-dimensional electron gas can be increased. For example, silicon is doped at a concentration of 5 × 10⁻⁶. 18 cm -3 The concentration of doping is incorporated into the bulk layer 43a.

[0160] Thereafter, on the bulk layer 43a, MOVPE is used to form a layer with 1×10 16 cm -3 or more and 7×10 18 cm -3 or less, for example 5×10 16 cm -3 or more and 6×10 18 cm -3 or less, or 1×10 17 cm -3 or more and 6×10 18 cm -3 or less, specifically 5×10 18 cm -3 doped n-type wurtzite GaN layer with silicon (Si) and germanium (Ge) as n-type impurities at the concentration, and this n-type GaN layer is used as the compound semiconductor layer 43b of the electron supply layer 43. By forming a wurtzite GaN layer doped with n-type impurities at this concentration on the bulk layer 43a, HEMT characteristics can be improved. It should be noted that an undoped wurtzite GaN layer can also be formed as the compound semiconductor layer 43b.

[0161] In addition, a wurtzite aluminum gallium nitride (Al x Ga 1-x N: 0 < x < 1) layer can be formed as the compound semiconductor layer 43b. Alternatively, a wurtzite aluminum nitride layer can also be formed as the compound semiconductor layer 43b. In addition, the thickness of the compound semiconductor layer 43b is not particularly limited, and is 5 nm or more and 20 nm or less, for example 6 nm or more and 15 nm or less, or 8 nm or more and 12 nm or less, specifically 10 nm in the present case. In addition, the surface of the compound semiconductor layer 43b is a (001) plane.

[0162] Next, as shown in Figure 20 (b) herein, after patterning the compound semiconductor layer 43b to expose the surface of the bulk layer 43a, a titanium layer and an aluminum layer are sequentially formed on the bulk layer 43a, and these films are used as the source electrode 45a and the drain electrode 45b.

[0163] If each of the electrodes 45a and 45b remains in its original state, the bonding between the electrodes and the bulk layer 43a as well as the compound semiconductor layer 43b will be a Schottky junction, making it difficult to effectively inject carriers from each of the electrodes 45a and 45b into these layers 43a and 43b.

[0164] Therefore, it is preferable that after forming the source electrode 45a and the drain electrode 45b, heat treatment is performed to cause slight interdiffusion between each of the electrodes 45a, 45b and each of the layers 43a, 43b, so that the aforementioned Schottky junction becomes an ohmic junction.

[0165] Then, as Figure 21 As shown, a PdCoO2 layer is formed on the (001) surface of the compound semiconductor layer 43b using pulsed laser deposition with a thickness of 1 nm to 200 nm, for example 10 nm to 100 nm, or 20 nm to 50 nm, here 25 nm. The PdCoO2 layer is then patterned to form the gate electrode 51. The growth conditions and patterning conditions of the PdCoO2 layer are the same as those of the anode electrode 14 in the first embodiment (see...). Figure 8 The same as (b) in the above text is omitted here. It should be noted that the gate electrode 51 is formed after the formation of each electrode 45a and 45b, but it is also possible to reverse this and form each electrode 45a and 45b after the formation of the gate electrode 51.

[0166] A Schottky barrier is formed between the (001) facet of the n-type GaN constituting the compound semiconductor layer 43b and the PdCoO2 layer of the gate electrode 51. As described in the first embodiment, the barrier height of this Schottky barrier is... This is an extremely high value exceeding 2.0 eV, which is unattainable by titanium (Ti), chromium (Cr), nickel (Ni), palladium (Pd), silver (Ag), platinum (Pt), gold (Au), and lead (Pb).

[0167] The basic structure of the semiconductor device 60 according to this embodiment is completed through the above methods. This semiconductor device 60 includes: a compound semiconductor layer 43b; and a gate electrode 51 of a PdCoO2 layer disposed on the compound semiconductor layer 43b and having a Schottky junction formed therebetween. Specifically, it is a GaN-HEMT, and a two-dimensional electron gas is induced in the electron transport layer 42 between each electrode 45a, 45b. Furthermore, the depletion layer width of the Schottky junction is controlled by applying a gate voltage to the gate electrode 51, thereby controlling the flow of the two-dimensional electron gas.

[0168] According to this embodiment, a Schottky barrier with a very high barrier height is formed between the compound semiconductor layer 43b of the electron supply layer 43 and the gate electrode 51 as described above, thus enabling the provision of a novel semiconductor device 60 with a small turn-off current.

[0169] Furthermore, the (001) surface of GaN is often used in the mass production process of various semiconductor devices. Therefore, by forming a PdCoO2 layer on the (001) surface of GaN as in this embodiment, it is possible to effectively utilize existing mass production processes to mass produce semiconductor devices 20.

[0170] The inventors of this application evaluate the crystallinity of the gate electrode 51 according to this embodiment as follows. In this investigation, a GaN body layer 43a is formed on a sapphire (Al2O3) substrate, and a wurtzite-type aluminum gallium nitride (Al2O3) layer is formed thereon. 0.03 Ga 0.97 The N) layer serves as the compound semiconductor layer 43b. Then, in this Al... 0.03 Ga 0.97 A gate electrode 51 of PdCoO2 was formed on the (001) facet of the N layer, and an evaluation sample was fabricated.

[0171] Figure 22 A graph showing the analytical results obtained by analyzing the sample using XRD. Figure 22 The horizontal axis represents the diffraction angle of X-rays (2). θ The vertical axis represents the intensity of X-rays (counts / second). Additionally, in... Figure 22 In, with Figure 11 Similarly, the diffraction peaks of PdCoO2 constituting the gate electrode 51 in the (00l) plane (l=1, 2, ...) are shown with downward arrows.

[0172] like Figure 22 As shown, the diffraction peaks of PdCoO2 at the (00l) plane (l=3, 6, 9, ...) are clearly visible. Based on this result, it can be concluded that PdCoO2 can be used in Al... 0.03 Ga 0.97 A gate electrode 51 of PdCoO2 with few lattice defects and excellent crystallinity is formed on the (001) surface of N.

[0173] Figure 23 The figure was obtained to investigate the CV characteristics between the gate electrode 51 and the electron transport layer 43 in the above sample. Figure 23 The vertical axis represents the square of the reciprocal of the depletion layer capacitance C per unit area of ​​the gate electrode 51 when viewed from above (1 / C). 2 ).in addition, Figure 23 The horizontal axis represents the voltage between the gate electrode 51 and the electron transport layer 43. Similar to the first embodiment, the CV characteristics were measured using an E4980A LCR meter manufactured by Keysight.

[0174] In this investigation, the gate electrode 51 was made into a circle with a diameter D = 200 μm when viewed from above, and measurements were performed at room temperature (298 K). Then, 1 / C was measured at multiple voltage values. 2 The fitting line for multiple measured values ​​is obtained. Based on the fitting line and the aforementioned equation (2), q·V at room temperature (298K) is calculated. bi The value becomes 1.72 eV. Furthermore, Al is calculated according to the aforementioned equation (3). 0.03 Ga0.97 donor concentration of N D Become 1.1×10 16 cm -3 .

[0175] As described in the aforementioned paper 2, regarding GaN, Furthermore, as described in Paper 4 below, regarding Al 0.2 Ga 0.8 For N, .

[0176] (Paper 4) D.Wines, F.Ersan, C.Ataca, “Engineering the Electronic, Thermoelectric, and Excitonic Properties of Two-Dimensional Group-III Nitridesthrough Alloying for Optoelectronic Devices (B 1-x Al x N, Al 1-x Ga x N, and Ga 1-x In x N), ACS Applied Materials & Interfaces, Volume 12, No. 41, pp. 46416-46428, 2020, ACS Publications Therefore, through linear approximation, in Al 0.03 Ga 0.97 In N, equation (5) The estimate is 0.25m0. M c The value is 1. The density of states N is calculated based on these values ​​using equation (5). c And the donor concentration N mentioned above D (1.1×10) 16 cm -3 When used in equation (4), Al 0.03 Ga 0.97 For N, at room temperature (298K) E c =0.15eV. The result is for q·V bi Add E c The barrier height obtained at room temperature (298K) It becomes 1.87 eV. Therefore, it is clear that by using aluminum gallium nitride (Al... 0.03 Ga 0.97 A PdCoO2 gate electrode 51 is formed on the compound semiconductor layer 43b of N, thereby enabling the realization of a higher performance than N. Figure 14 The barrier height of any metal shown is higher than the barrier height of the metal shown.

[0177] (Fourth implementation) Next, the semiconductor device according to the fourth embodiment will be described according to its manufacturing process. In this embodiment, a vertical Schottky barrier diode in which a Schottky barrier is formed at the interface between the compound semiconductor and PdCoO2 is manufactured as follows.

[0178] Figure 24 (a) and (b) in this embodiment are cross-sectional views during the manufacturing process of the semiconductor device.

[0179] First, such as Figure 24 As shown in (a), for example, a SiC (001) or GaN (001) substrate is prepared as an n-type high-conductivity compound semiconductor substrate 46. To reduce the on-resistance of the diode, the resistivity of the compound semiconductor substrate 46 is preferably low. Therefore, the compound semiconductor substrate 46 preferably contains 1 × 10⁻⁶... 18 cm -3 Above 1×10 21 cm -3 The following, for example, 3×10 18 cm -3 Above 5×10 20 cm -3 Below, 5×10 18 cm -3 Above 5×10 19 cm -3 The following, here is 1×10 19 cm -3 The left and right n-type impurities. In addition, the compound semiconductor substrate 46 has a first main surface 46a and a second main surface 46b opposite to each other, wherein the first main surface 46a is the (001) surface.

[0180] Next, on the first main surface 46a of the compound semiconductor substrate 46, a compound semiconductor layer 47 is epitaxially grown using chemical vapor deposition (CVD) with a thickness of 0.2 μm to 200 μm, for example, 1 μm to 100 μm, 2 μm to 50 μm, or 3 μm to 25 μm, in this case, 5 μm. When the thickness of the compound semiconductor layer 47 is 0.2 μm or more, the withstand voltage can be sufficiently improved; conversely, when it is 200 μm or less, the on-resistance can be sufficiently reduced.

[0181] For example, if the compound semiconductor substrate 46 is a SiC (001) substrate, a 4H-SiC layer is formed as the compound semiconductor layer 47; if the compound semiconductor substrate 46 is a GaN (001) substrate, a wurtzite-type gallium nitride layer is formed as the compound semiconductor layer 47. In either case, the surface of the compound semiconductor layer 47 is a (001) surface.

[0182] Furthermore, during the growth of the compound semiconductor layer 47, impurities are typically not doped, but it is also possible to dope with 1×10⁻⁶ impurities. 15 cm -3 Above 5×10 17 cm -3 The following concentrations are for doping with n-type impurities. It should be noted that sputtering, MBE, HVPE, solid-state deposition, and atomized CVD can also be used instead of CVD.

[0183] Next, the method used in the first embodiment is adopted. Figure 8 Using the same physical vapor deposition and patterning conditions as in (b), a PdCoO2 layer is formed on the (001) surface of the compound semiconductor layer 47 as the anode electrode 14 with a thickness of 1 nm to 200 nm, for example 10 nm to 100 nm, or 20 nm to 50 nm, here 25 nm.

[0184] Next, a cathode electrode 15 is deposited on the second main surface 46b of the compound semiconductor substrate 46. If the compound semiconductor substrate 46 is a GaN substrate, a metal layer such as a titanium layer or an aluminum layer is deposited to form the cathode electrode 15. If the compound semiconductor substrate 46 is a SiC substrate, in conjunction with the second embodiment... Figure 15 Under the same conditions as in (b), nickel silicide is formed by heat treatment after depositing a nickel layer, thereby forming the cathode electrode 15.

[0185] The basic structure of the semiconductor device 70 according to this embodiment is completed through the above method. The semiconductor device 70 includes: a compound semiconductor layer 47; and an anode electrode 14 of a PdCoO2 layer disposed on the compound semiconductor layer 47 and having a Schottky junction formed therebetween. Specifically, it is a vertical Schottky barrier diode with a Schottky barrier formed at the interface between the compound semiconductor layer 47 and the anode electrode 14. To apply a forward bias voltage to the semiconductor device 70, the potential of the anode electrode 14 is made higher than the potential of the cathode electrode 15. Conversely, to apply a reverse bias voltage, the potential of the anode electrode 14 is made lower than the potential of the cathode electrode 15.

[0186] It should be noted that in this embodiment, the orientation of the first main surface 46a of the compound semiconductor substrate 46 is set to the (001) direction, but the normal direction of the first main surface 46a can also be slightly deviated from the (001) direction within a range that does not significantly disrupt the crystallinity of the anode electrode 14. As an example, the normal direction of the first main surface 46a can be deviated from the (001) direction by a range of less than 10°.

[0187] In addition, to prevent electric field concentration at the outer periphery of the anode electrode 14, edge termination and passivation layer deposition can be implemented.

[0188] The embodiments have been described in detail above, but the embodiments are not limited to the above content. For example, the PdCoO2 layer involved in each embodiment can have any of the functions of wiring, transparent electrode layer, catalyst, and terahertz wave oscillation source.

[0189] (Fifth implementation) Before describing this embodiment, the matters researched by the inventors of this application will be explained.

[0190] (The matters researched by the inventors of this application) In addition to the matters studied by the inventors of this application in the first embodiment described above, the following matters were also studied. As explained in the first embodiment, the (-201) plane of β-Ga2O3 has lattice points arranged in a hexagonal pattern in the same way as the PdCoO2 layer, and has a lattice constant of the same degree as the oxide layer 1 of PdCoO2. Therefore, the lattice mismatch value is as low as about 3.2%, and a neat PdCoO2 layer with few defects can be formed.

[0191] However, the (-201) plane of β-Ga2O3 is a crystal plane that easily introduces dislocations and stacking faults, thus its defects prevent it from fully improving the breakdown voltage and electron mobility of semiconductor devices such as Schottky diodes. Therefore, when a metallic copper-iron oxide layer is formed on the (-201) plane of β-Ga2O3, the characteristics of β-Ga2O3, such as large band gap and high breakdown voltage, cannot be fully utilized.

[0192] Therefore, as a surface that forms a metallic copper-iron oxide layer other than the (-201) surface, the inventors of this application focus on the (001) surface of β-Ga2O3.

[0193] Figure 25 The (001) facet of β-Ga2O3 and oxide layer 1 of PdCoO2 (see [reference]). Figure 1 (Each of the above is a schematic diagram.)

[0194] Compared to the (-201) facet, the (001) facet of β-Ga2O3 is less prone to introducing dislocation defects and stacking faults, thus reducing the breakdown strength and mobility caused by defects. On the other hand, as Figure 25 As shown, the gallium atoms on the (001) facet have a rectangular atomic arrangement, which differs from the symmetry of the hexagonal atomic arrangement of the PdCoO2 oxide layer 1. Therefore, if PdCoO2 only stretches along the a-axis and b-axis, the atomic arrangements of the (001) facet of β-Ga2O3 and PdCoO2 are inconsistent, and according to common sense, it is expected that PdCoO2 with excellent Schottky properties due to good crystallinity cannot be formed. However, contrary to this expectation, the following unexpected effect has been clearly obtained, namely, as in the following embodiment, a PdCoO2 layer that functions as a good Schottky electrode can be formed.

[0195] The semiconductor device involved in this embodiment will be described according to its manufacturing method. In this embodiment, a Schottky barrier diode with a Schottky barrier formed at the interface between the (001) facet of β-Ga2O3 and PdCoO2 is manufactured as follows.

[0196] Figure 26 (a), (b), (c) and Figure 27 This is a cross-sectional view taken during the manufacturing process of the semiconductor device involved in this embodiment.

[0197] First, such as Figure 26 As shown in (a), a substrate 80 is prepared. This substrate 80 is a substrate on which a β-Ga2O3 layer 82 with low carrier density is epitaxially grown on a β-Ga2O3 substrate 81 doped with a high concentration of n-type impurities. The layer has a thickness of 100 nm to 100 μm, for example, 1 μm to 80 μm, 3 μm to 50 μm, 5 μm to 25 μm, and in this case, 11 μm. When the thickness of the β-Ga2O3 layer 82 is 100 nm or more, the voltage withstand capability can be sufficiently improved. When the thickness is 100 μm or less, the on-resistance can be sufficiently reduced.

[0198] The concentration of n-type impurities in substrate 80 is not particularly limited. For example, in β-Ga2O3 substrate 81, the concentration is 1×10⁻⁶. 17 cm -3 Above 1×10 20 cm -3 The following concentrations, for example, 1×10 17 cm -3 Above 2×10 19 cm -3 The following concentrations, or 1×10 18 cm -3 Above 1×1019 cm -3 The following concentrations of Si or Sn are used as n-type impurities. Additionally, the carrier density of the β-Ga₂O₃ layer 82 is 1 × 10⁻⁶. 15 cm -3 Above 1×10 17 cm -3 The following concentrations, for example 5 × 10 15 cm -3 Above 8×10 16 cm -3 The following concentrations, or 8×10 15 cm -3 Above 5×10 16 cm -3 The following concentrations are used. By doping the substrate 80 with n-type impurities in this way, the on-resistance of the diode can be reduced. On the other hand, by making the carrier density of the β-Ga2O3 layer 82 lower than that in the β-Ga2O3 substrate 81, the depletion layer width near the interface between the subsequently formed anode electrode and the β-Ga2O3 layer 82 can be increased, thereby improving the breakdown voltage.

[0199] In addition, the substrate 80 has a first main surface 80a and a second main surface 80b. The first main surface 80a is formed by the (001) surface of the β-Ga2O3 layer 82.

[0200] Next, as Figure 26 As shown in (b), a PdCoO2 layer is formed as an anode electrode 84 on the first main surface 80a of the substrate 80 in a cavity (not shown) using pulsed laser deposition to a thickness of 1 nm to 100 nm, for example 5 nm to 80 nm, 10 nm to 50 nm, and here 20 nm. In this pulsed laser deposition method, the energy density for irradiating the target material is 0.5 J / cm². 2 Above 4J / cm 2 For example, 0.8 J / cm 2 Above 3J / cm 2 Below, or 1.2 J / cm 2 Above 2J / cm 2 The value here is 1.5 J / cm. 2 The target material is a fourth-harmonic wavelength (266 nm) of Nd:YAG laser. For example, granules prepared by sintering PdCoO2 powder are used. The film-forming atmosphere and substrate temperature during film formation are the same as in the first embodiment, and therefore descriptions are omitted. Alternatively, the anode electrode 84 can be formed using methods different from pulsed laser deposition. The method described in the first embodiment can be cited as an example of such a method, and therefore descriptions are omitted.

[0201] Furthermore, similar to the first embodiment, the anode electrode 84 thus grown can be subjected to heat treatment to improve the crystallinity of PdCoO2. The atmosphere, oxygen partial pressure, substrate temperature, and heat treatment apparatus during the heat treatment are the same as in the first embodiment, and therefore descriptions are omitted.

[0202] Next, as Figure 26 As shown in (c), a nickel layer 85a and a gold layer 85b are sequentially formed on the anode electrode 84 using either vapor deposition or sputtering as a metal laminate 85. The thickness of each layer is not particularly limited. The thickness of the nickel layer 85a is 5 nm to 100 nm, for example, 10 nm to 80 nm, 15 nm to 60 nm, or 20 nm to 50 nm, here 30 nm. A thickness of 5 nm or more for the nickel layer 85a reduces the impact of surface oxidation, while a thickness of 100 nm or less allows for the formation of the nickel layer 85a without peeling. Similarly, the thickness of the gold layer 85b is 5 nm to 300 nm, for example, 20 nm to 275 nm, 40 nm to 250 nm, or 60 nm to 200 nm, here 150 nm. A thickness of 5 nm or more for the gold layer 85b reduces the sheet resistance of the metal laminate, while a thickness of 300 nm or less ensures the flatness of the gold layer 85b.

[0203] Then, a resist pattern (not shown) is formed on the laminated film 85. Using this as a mask, the laminated film 85 and the anode electrode 84 are patterned by RIE (Reactive Ion Etching). The etching gas in this RIE is, for example, a mixture of Ar and BCl3. Afterward, the resist pattern is removed.

[0204] Next, as Figure 27As shown, a titanium layer 86a and a gold layer 86b are sequentially formed on the second main surface 80b of the substrate 80 using a vapor deposition or sputtering method to obtain a cathode electrode 86 electrically connected to the substrate 80. The thickness of the cathode electrode 86 is not particularly limited. Furthermore, heat treatment can be performed to reduce the interface resistance between the cathode electrode 86 and the substrate 81. In this example, the titanium layer 86a is formed with a thickness of 2 nm to 100 nm, for example, 10 nm to 90 nm, 20 nm to 80 nm, or 30 nm to 70 nm, here 50 nm. When the thickness of the titanium layer 86a is 2 nm or more, the effect of surface oxidation can be reduced; conversely, when it is 100 nm or less, the on-resistance can be sufficiently reduced. The thickness of the gold layer 86b is set to 5 nm to 300 nm, for example, 10 nm to 275 nm, 20 nm to 250 nm, or 30 nm to 225 nm, here 200 nm. When the thickness of the gold layer 86b is 5nm or more, the on-resistance can be significantly reduced. In addition, when it is 300nm or less, the flatness of the gold layer 86b can be ensured.

[0205] The basic structure of the semiconductor device 90 according to this embodiment is completed through the above method. The semiconductor device 90 includes: a β-Ga₂O₃ layer 82 as a compound semiconductor layer; and an anode electrode 84 of PdCoO₂ disposed on the β-Ga₂O₃ layer 82 and having a Schottky junction formed therebetween. Specifically, it is a Schottky barrier diode with a Schottky junction formed at the interface between the β-Ga₂O₃ layer 82 and the anode electrode 84. To apply a forward bias voltage to the semiconductor device 90, the potential of the anode electrode 84 only needs to be higher than the potential of the cathode electrode 86. Conversely, to apply a reverse bias voltage, the potential of the anode electrode 84 only needs to be lower than the potential of the cathode electrode 86.

[0206] Next, the results of various investigations conducted by the inventors of this application in this embodiment will be explained.

[0207] Figure 28 (a) is a HAADF-STEM (High Angle Annular Dark-Field Scanning Transmission Electron Microscopy) image of the interface between the β-Ga2O3 layer 82 and the PdCoO2 constituting the anode electrode 84.

[0208] like Figure 25As shown, the atomic configuration symmetry differs in β-Ga₂O₃ and PdCoO₂. Therefore, based on common technical knowledge, it is expected that the crystallinity of PdCoO₂ will be disrupted, preventing the formation of a PdCoO₂ layer with excellent Schottky properties. However, contrary to this expectation, as... Figure 28 As shown in (a), the PdCoO2 layer grows with its c-axis direction tilted from the normal direction of the β-Ga2O3 layer, and its crystallinity is not significantly damaged.

[0209] Figure 28 (b) in the diagram is shown schematically. Figure 28 A cross-sectional view of state (a) in the diagram. For example... Figure 28 As shown in (b), the following unexpected phenomenon was observed: by tilting the c-axis of the PdCoO2 layer from the normal direction n of the (001) plane of the β-Ga2O3 layer, atomic layers are stacked along the c-axis direction to form a well-crystallized PdCoO2 layer. It should be noted that in this example, the angle between the c-axis direction and the normal direction n... θ It is 22.4°. It is believed that by making the angle... θ This value ensures that the symmetry of the atomic configuration of the PdCoO2 layer at the interface with the β-Ga2O3 layer is consistent with the symmetry of the atomic configuration in the (001) plane of the β-Ga2O3 layer, thus forming a well-crystallized PdCoO2 layer.

[0210] Thus, good crystallinity is achieved. On the other hand, the bottommost atomic layer forming the PdCoO2 layer is not entirely in contact with the β-Ga2O3 layer, but rather the ends of each atomic layer are in contact with the β-Ga2O3 layer. The inventors of this application have confirmed through investigation that good Schottky properties can be obtained with this structure.

[0211] Figure 29 The graph was obtained to investigate the J (current density)-V (voltage) characteristics of semiconductor device 90. The JV characteristics were measured using an Agilent Technologies 4155B semiconductor parameter analyzer. Figure 29 The horizontal axis represents the voltage between the anode electrode 84 and the cathode electrode 86, with the case where the potential of the anode electrode 84 is higher than that of the cathode electrode 86 being defined as positive. Additionally, Figure 29 The vertical axis represents the absolute value of the current density of the current flowing between the anode electrode 84 and the cathode electrode 86.

[0212] In this investigation, the anode electrode 84 was made into a circle with a diameter D = 200 μm when viewed from above, and measurements were taken at room temperature (298 K). The barrier height of the Schottky barrier based on this JV characteristic was determined. The voltage becomes 1.73 eV. Furthermore, the interface resistance of the Schottky barrier in the on-state becomes 25 mΩcm. 2 .

[0213] Furthermore, the ideal factor n of the Schottky barrier becomes 1.10. It should be noted that the ideal factor n is defined by the aforementioned equation (1).

[0214] Figure 30 The graph was obtained to investigate the C (capacitance)-V (voltage) characteristics of semiconductor device 90. The CV characteristics were measured using an E4980A LCR meter manufactured by Keysight. Figure 30 The meaning of the horizontal axis and Figure 29 The horizontal axis is the same, therefore its description is omitted. Additionally, Figure 30 The vertical axis represents the square of the reciprocal of the depletion layer capacitance C of the Schottky barrier, 1 / C. 2 .

[0215] Similar to the determination of JV characteristics, in this investigation, the anode electrode 84 was also made into a circle with a diameter D = 200 μm when viewed from above, and the measurements were performed at room temperature (298 K). Then, 1 / C was measured at multiple voltage values. 2 Find the fitting line that fits multiple measured values. Set the intercept of the fitting line to the horizontal axis as b, and calculate the built-in potential V at room temperature (298K) according to the aforementioned equation (2). bi As a result, in this example, it becomes q·V bi =1.88eV.

[0216] In addition, Figure 30 Let the absolute value of the slope of the fitted straight line be a, and calculate the doping density N of the β-Ga2O3 layer 82 according to the aforementioned equation (3). D In this example, N D =5.7×10 15 cm -3 In the aforementioned equation (3), ε is the dielectric constant of the β-Ga2O3 layer 82.

[0217] For reference Figure 5 The barrier height is explained. Equal to q·V bi With energy E c The sum of. Energy E c It can be calculated based on formula (4).

[0218] The doping density N in the aforementioned equation (4) D The value is calculated using equation (3) above. Additionally, the state density N in equation (4) above... c It can be obtained from the aforementioned equation (5).

[0219] In addition, M in the aforementioned equation (5) cM represents the number of conduction band bases contained in the first Brillouin zone, for β-Ga₂O₃. c =1.

[0220] If they are used, then for β-Ga2O3, E at room temperature (298K) c =0.17eV, which, when added to q·V bi Barrier height at post-room temperature It becomes 2.05 eV.

[0221] Figure 31 To be based on Figure 30 The result of the barrier height The graph was obtained by plotting the work function of PdCoO2 as reported in Non-Patent Literature 4. Figure 31 For comparison, the barrier heights and work functions of nickel (Ni) and platinum (Pt), as representative metals, are also plotted. For the barrier heights, reference 2 is cited; for the work functions, references 16 and 17 are cited.

[0222] It should be noted that, as described in the first embodiment, the barrier height is typically obtained based on the JV characteristics. The height becomes the average barrier height of the surface calculated based on CV characteristics. Low value.

[0223] As described in the first embodiment, the barrier height is obtained from the CV characteristics. Subtract the barrier height obtained from the JV characteristics The obtained value is the standard deviation σ of the barrier height. s It has the relationship of the aforementioned equation (6) (see the aforementioned paper 3).

[0224] As explained in the first embodiment, the aforementioned equation (6) means that, and The greater the difference, the greater the deviation in barrier height within the interface. This deviation varies depending on the uniformity of crystal orientation at the interface, the amount of defects, and the doping level of the semiconductor layer. Since the ideal barrier height at the interface is better reflected by... Therefore, with compared to, Higher reliability Figure 31 The barrier heights of the metals shown are at most around 1.45 eV. In contrast, the barrier height involved in this embodiment is... Exceeding 2.0 eV. This result clarifies that even if... Figure 28In (a) and (b), the c-axis direction is tilted from the normal direction n, which can also form a Schottky barrier at the interface between the (001) plane of the β-Ga2O3 layer and the PdCoO2 layer that exceeds the barrier height of the representative metal.

[0225] Therefore, the semiconductor device 90 according to this embodiment becomes capable of […]. Figure 31 The representative metal shown is used to achieve high-temperature operation and very high withstand voltage, which is not achievable when using the anode electrode 84, enabling new power devices that are not easily broken down even when a reverse bias is applied.

[0226] Furthermore, in this embodiment, the anode electrode 84 is formed on the (001) facet of the β-Ga2O3 layer 82, instead of on the (-201) facet of the β-Ga2O3 layer, where dislocation defects and stacking faults make it difficult to improve breakdown voltage and mobility. Therefore, the advantages of β-Ga2O3, such as its wide bandgap and ease of improving breakdown voltage, can be fully utilized, further improving the breakdown voltage of the semiconductor device 90. The inventors of this application investigated the breakdown voltage of the semiconductor device 90 to confirm this. The results are shown in… Figure 32 .

[0227] Figure 32 A graph showing the results of an investigation into the withstand voltage of semiconductor device 90. Figure 32 The horizontal axis represents the reverse bias voltage value, and the vertical axis represents the absolute value of the current density flowing between the anode electrode 84 and the cathode electrode 86.

[0228] like Figure 32 As shown, in this embodiment, breakdown does not occur even when a reverse bias voltage of -500 eV is applied, but breakdown only occurs with a reverse bias voltage of around -530 eV. This confirms that forming an anode electrode 84 on the (001) facet of the β-Ga2O3 layer 82 is effective in improving the breakdown voltage of the semiconductor device 90.

[0229] (Other implementation methods) In the first embodiment, a Schottky barrier diode is formed at the interface between the gallium nitride and the PdCoO2 layer, where a Schottky barrier is formed. However, in this embodiment, indium gallium nitride (In) is used. 0.07 Ga 0.93 To replace gallium nitride, a PdCoO2 layer is formed on its (001) surface.

[0230] Figure 33 A diagram illustrating the structure of the device involved in this embodiment is provided. Figure 34 This is a graph showing the analysis results obtained by analyzing the PdCoO2 layer of the device according to this embodiment using XRD. Figure 33 XRD analysis of the PdCoO2 layer was performed on the device structure shown. Figure 34 As shown, the diffraction peaks of PdCoO₂ on the (00l) plane (l=1, 2, ...) are clearly visible. It can be seen from the result that even on In 0.07 Ga 0.93 N (001) plane with a lattice mismatch of as much as 12%, when the PdCoO₂ layer is formed, a PdCoO₂ layer with few lattice defects and excellent crystallinity can still be obtained. It should be noted that there is no particular limitation on the composition ratio of indium gallium nitride, and the composition formula is In x Ga 1-x N, the value of x in N can be arbitrarily selected from the range of 0<x<1. In addition, indium nitride InN can also be used instead of indium gallium nitride.

[0231] The present embodiment has been described in detail above, but the present embodiment is not limited to the above aspects. For example, in the present embodiment, the plane orientation of the first main surface 80a of the substrate 80 (see Figure 26 (a) in the figure) is set to the (001) direction of β-Ga₂O₃, but the normal direction of the first main surface 80a may be slightly deviated from the (001) direction within a range where a good Schottky barrier can be obtained between the first main surface 80a and the anode electrode 84. As an example, the normal direction of the first main surface 80a may deviate from the (001) direction within a range of 10° or less.

[0232] In addition, in the semiconductor device 90 (see Figure 27 ), in order to prevent electric field from concentrating on the outer periphery of the anode electrode 84, edge termination and deposition of a passivation layer can also be implemented. In addition, in order to prevent electric field from concentrating on the β-Ga₂O₃ layer 82 near the anode electrode 84, a trench structure can be formed in the β-Ga₂O₃ layer 82.

[0233] In addition, the PdCoO₂ layer constituting the anode electrode 84 can also have any one of functions of wiring, transparent electrode layer, catalyst, and terahertz wave oscillation source.

[0234] In addition, considering the commonality of characteristics of bulk single crystals of metallic delafossite oxides PdCoO₂, PdCrO₂, PdRhO₂ and PtCoO₂, and the commonality of characteristics between palladium and platinum, as well as between chromium, cobalt and rhodium, it is considered that in the case of metallic delafossite oxides PdCrO₂, PdRhO₂ and PtCoO₂ other than PdCoO₂, a large Schottky barrier can also be induced at the interface through the same mechanism as that confirmed for the PdCoO₂ layer in the above-described embodiment. In addition, it is considered that the matters related to the PdCoO₂ layer, the Schottky barrier diode having the PdCoO₂ layer and the manufacturing method of the PdCoO₂ are naturally common for other aspects.

[0235] Description of Reference Numerals 1…Oxide layer, 2…Metal layer, 10…Substrate, 11…Alumina substrate, 12…GaN layer, 13…Compound semiconductor layer, 14…Anode electrode, 15, 22…Cathode electrode, 15a…Aluminum layer, 15b…Indium layer, 20, 30, 60, 70…Semiconductor device, 21…Compound semiconductor substrate, 41…SiC substrate, 42…Electron transport layer, 43…Electron supply layer, 43a…Body layer, 43b…Compound semiconductor layer, 45a…Source electrode, 45b…Drain electrode, 46…Compound semiconductor substrate, 46a…First main surface, 46b…Second main surface, 47…Compound semiconductor layer, 51…Gate electrode, 80…Substrate, 81…β-Ga2O3 substrate, 82…β-Ga2O3 layer, 84…Anode electrode, 85…Metal laminate, 85a…Nickel layer, 85b…Gold layer, 86…Cathode electrode, 86a…Titanium layer, 86b…Gold layer, 90…Semiconductor device. Claims (as amended under Article 19 of the Treaty) 1. (Revised) A semiconductor device having: Compound semiconductors; and The electrode of PdCoO2 is disposed on the (001) surface of the compound semiconductor and forms a Schottky junction with the compound semiconductor. 2. (Delete). 3. (Modified) The semiconductor device of claim 1, further comprising a cathode electrode of a Schottky barrier diode electrically connected to the compound semiconductor. The electrode of the PdCoO2 is the anode electrode of the Schottky barrier diode. 4. (Delete). 5. (Modified) The semiconductor device of claim 1 or 3, wherein the compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide. 6. (Modified) The semiconductor device of claim 5, wherein the compound semiconductor is gallium nitride or aluminum gallium nitride. The PdCoO2 at the interface with the compound semiconductor is [CoO2]. - End. 7. (Amended) The semiconductor device of claim 1 or 2, wherein the compound semiconductor is gallium oxide. 8. The semiconductor device of claim 7, wherein the crystal structure of the gallium oxide is a β-gallium oxide structure. 9. The semiconductor device of claim 7 or 8, wherein the c-axis of the PdCoO2 is inclined from the normal direction of the (001) plane. 10. The semiconductor device of claim 1, wherein the normal direction of the surface of the compound semiconductor deviates from the (001) direction, and the PdCoO2 electrode is disposed on the surface. 11. (Amended) A method for manufacturing a semiconductor device, comprising: A PdCoO2 electrode is formed on the (001) facet of a compound semiconductor, and a Schottky junction is formed between the PdCoO2 electrode and the compound semiconductor. 12. The method of manufacturing a semiconductor device as claimed in claim 11, further comprising heat-treating the electrode in an oxygen-containing atmosphere. 13. The method of manufacturing a semiconductor device as claimed in claim 12, wherein the electrode is formed in an oxygen-containing atmosphere. The oxygen partial pressure in the oxygen-containing atmosphere during the heat treatment is higher than the oxygen partial pressure in the oxygen-containing atmosphere during the formation of the electrode. 14. The method of manufacturing a semiconductor device according to any one of claims 11 to 13, further comprising forming a cathode electrode of a Schottky barrier diode in a manner electrically connected to the compound semiconductor. The electrode is the anode electrode of the Schottky barrier diode. 15. (Deleted). 16. (Amended) A method of manufacturing a semiconductor device according to any one of claims 11 to 14, wherein the compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide. 17. The method of manufacturing a semiconductor device according to any one of claims 11 to 14, wherein the compound semiconductor is gallium oxide. 18. The method of manufacturing a semiconductor device as claimed in claim 11, wherein the normal direction of the surface of the compound semiconductor is deviated from the (001) direction, and the PdCoO2 electrode is formed on the surface. 19. (Deleted).

Claims

1. A semiconductor device having: Compound semiconductors; and The PdCoO2 electrode is disposed on the compound semiconductor and forms a Schottky junction with the compound semiconductor.

2. The semiconductor device of claim 1, wherein, The electrode of the PdCoO2 is disposed on the (001) surface of the compound semiconductor.

3. The semiconductor device of claim 1 or 2, further comprising a cathode electrode of a Schottky barrier diode electrically connected to the compound semiconductor. The electrode of the PdCoO2 is the anode electrode of the Schottky barrier diode.

4. The semiconductor device as claimed in claim 1 or 2, wherein, The PdCoO2 electrode is the gate electrode of the field-effect transistor, and the compound semiconductor is the electron supply layer of the field-effect transistor.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide.

6. The semiconductor device of claim 5, wherein, The compound semiconductor is gallium nitride. The PdCoO2 at the interface with the compound semiconductor is [CoO2]. - End.

7. The semiconductor device according to any one of claims 1 to 3, wherein, The compound semiconductor is gallium oxide.

8. The semiconductor device of claim 7, wherein, The crystal structure of the gallium oxide is a β-gallium oxide structure.

9. The semiconductor device as claimed in claim 7 or 8, wherein, The c-axis of the PdCoO2 is inclined from the normal direction of the (001) plane.

10. The semiconductor device of claim 1, wherein, The normal direction of the surface of the compound semiconductor deviates from the (001) direction, and the PdCoO2 electrode is disposed on the surface.

11. A method for manufacturing a semiconductor device, comprising: A PdCoO2 electrode is formed on a compound semiconductor, and a Schottky junction is formed between the PdCoO2 electrode and the compound semiconductor.

12. The method of manufacturing a semiconductor device as claimed in claim 11, further comprising heat-treating the electrode in an oxygen-containing atmosphere.

13. The method of manufacturing a semiconductor device as claimed in claim 12, wherein, The electrode is formed in an oxygen-containing atmosphere. The partial pressure of oxygen in the oxygen-containing atmosphere during the heat treatment is higher than the partial pressure of oxygen in the oxygen-containing atmosphere during the formation of the electrode.

14. The method of manufacturing a semiconductor device according to any one of claims 11 to 13, wherein, It also includes a cathode electrode that forms a Schottky barrier diode in a manner electrically connected to the compound semiconductor. The electrode is the anode electrode of the Schottky barrier diode.

15. The method of manufacturing a semiconductor device according to any one of claims 11 to 13, wherein, The electrode is the gate electrode of the field-effect transistor, and the compound semiconductor is the electron supply layer of the field-effect transistor.

16. The method of manufacturing a semiconductor device according to any one of claims 11 to 15, wherein, The compound semiconductor is any one of gallium nitride, indium gallium nitride, aluminum gallium nitride, indium nitride, aluminum nitride, and silicon carbide.

17. The method of manufacturing a semiconductor device according to any one of claims 11 to 14, wherein, The compound semiconductor is gallium oxide.

18. The method of manufacturing a semiconductor device as claimed in claim 11, wherein, The normal direction of the surface of the compound semiconductor deviates from the (001) direction, and the PdCoO2 electrode is formed on the surface.

19. A semiconductor device having: Compound semiconductors; and An electrode of metallic copper-iron oxide is disposed on the compound semiconductor and forms a Schottky junction with the compound semiconductor.

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