Semiconductor device

Abstract

The semiconductor device of the present application includes: an active region provided to a main surface of a SiC chip; a peripheral region surrounding a periphery of the active region; a semiconductor region including a base region spanning the active region and the peripheral region, and a cap region formed in a surface layer portion of the base region in at least the active region and having a higher impurity concentration than the base region; a device structure including a body region of a second conductivity type formed in the active region and formed in a surface layer portion of the semiconductor region, and a source region of a first conductivity type formed in a surface layer portion of the body region; an outer well region of the second conductivity type formed in a surface layer portion of the semiconductor region in the peripheral region; and a field stop region formed outside the outer well region, having a higher impurity concentration than the base region, and having the same depth as the cap region.

Description

[0001] Related applications

[0002] This application corresponds to Japanese Patent Application No. 2024-025724 filed with the Japanese Patent Office on February 22, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a SiC semiconductor device. Background Technology

[0004] Patent document 1 (US2008 / 0277669A1) discloses a semiconductor device having a terminal structure in the outer peripheral region of a drift layer.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: U.S. Patent Application Publication No. 2008 / 0277669 Summary of the Invention

[0008] One embodiment of this disclosure provides a semiconductor device comprising: a SiC chip having a main surface; an active region disposed on the main surface; a peripheral region disposed on the main surface and surrounding the active region; a semiconductor region being a first conductivity type semiconductor region formed on a surface portion of the main surface, and including a base region spanning the active region and the peripheral region, and a cap region formed on the surface portion of the base region at least in the active region and having a higher impurity concentration than the base region; a device structure being a device structure formed on the active region, and including a second conductivity type body region formed on the surface portion of the semiconductor region, and a first conductivity type source region formed on the surface portion of the body region; a second conductivity type outer well region formed on the surface portion of the semiconductor region in the peripheral region; and a field cutoff region formed outside the outer well region, having a higher impurity concentration than the base region and having the same depth as the cap region. Attached Figure Description

[0009] Figure 1 This is a top view showing a semiconductor device according to the first embodiment of the present disclosure.

[0010] Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown.

[0011] Figure 3 This is a top view showing an example of chip layout.

[0012] Figure 4 This is a 3D diagram showing an example of chip layout.

[0013] Figure 5 It means Figure 3 An enlarged top view of a major portion of the first main surface shown.

[0014] Figure 6 It means Figure 3 An enlarged top view of a major portion of the first main surface shown.

[0015] Figure 7 It is along Figure 5 The sectional view along line VII-VII shown.

[0016] Figure 8 It is along Figure 5 The cross-sectional view of line VIII-VIII shown.

[0017] Figure 9 It is along Figure 6 The cross-sectional view of the IX-IX line shown.

[0018] Figure 10 It means along Figure 1 A cross-sectional view of the outer periphery of the XX line shown.

[0019] Figure 11 yes Figure 10 An enlarged sectional view of one of the areas shown.

[0020] Figure 12 It means along Figure 9 A graph illustrating an example of the concentration gradient of p-type impurities in the region shown by the XII-XII line.

[0021] Figure 13 It means along Figure 11 A graph illustrating an example of the concentration gradient of p-type impurities in the region shown by the XIII-XIII line.

[0022] Figure 14 It means along Figure 9 A graph illustrating an example of the concentration gradient of n-type impurities in the region shown by the XIV-XIV line.

[0023] Figure 15 It means along Figure 11 A graph illustrating an example of the concentration gradient of n-type impurities in the region shown by the XV-XV line.

[0024] Figure 16 This is a cross-sectional view showing the field cutoff region of the second example.

[0025] Figure 17This is a cross-sectional view showing the outer well region of the second example.

[0026] Figure 18 This is a cross-sectional view showing the outer well region of the third example.

[0027] Figure 19 This is a cross-sectional view showing the outer well region of the fourth type example.

[0028] Figure 20 This is a cross-sectional view showing the outer well region of the fifth example.

[0029] Figure 21 This is a graph representing the concentration gradient in the outer trap region of the second example.

[0030] Figure 22 This is a top view showing an example of the layout of the chip of the semiconductor device according to the second embodiment of the present disclosure.

[0031] Figure 23 It means Figure 22 An enlarged top view of a major portion of the first main surface shown.

[0032] Figure 24 It means Figure 22 An enlarged top view of a major portion of the first main surface shown.

[0033] Figure 25 It is along Figure 23 The cross-sectional view of the XXV-XXV line shown.

[0034] Figure 26 It is along Figure 23 The sectional view of the XXVI-XXVI line shown.

[0035] Figure 27 It is along Figure 24 The sectional view of line XXVII-XXVII shown.

[0036] Figure 28 This is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of this disclosure.

[0037] Figure 29 This is a cross-sectional view of the main part of the semiconductor device according to the fourth embodiment of this disclosure. Detailed Implementation

[0038] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] The specific methods are explained in detail below with reference to the accompanying drawings. The drawings are schematic diagrams, not strict illustrations; relative positions, scales, ratios, angles, etc., may not be consistent. Corresponding structures in the drawings are labeled with the same reference symbols, and repeated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions preceding the omission or simplification shall apply.

[0040] When the term "substantially" is used in this specification, this term includes not only the numerical value (shape) that is equal to the numerical value (shape) of the comparison object, but also a numerical error (shape error) within a range of ±10% based on the numerical value (shape) of the comparison object. In the following description, terms such as "first," "second," and "third" are used, but these are notations assigned to the names of each structure to clarify the order of description, and are not intended to define the essence of the names of each structure.

[0041] In the following description, "p-type" or "n-type" is used to refer to the conductivity type of the semiconductor (impurity), but "p-type" can also be called the "first conductivity type" and "n-type" the "second conductivity type." "P-type" is a conductivity type derived from trivalent elements, and "n-type" is a conductivity type derived from pentavalent elements. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0042] Figure 1 This is a top view showing the semiconductor device 1A according to the first embodiment of the present disclosure. Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown. Figure 3 This is a top view showing a layout example of chip 2. Figure 4 This is a 3D view showing a layout example of chip 2.

[0043] Reference Figures 1-4 Semiconductor device 1A is a semiconductor switching device having an insulated-gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench-gate vertical structure.

[0044] Semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically a cuboid shape). In this embodiment, chip 2 comprises a single crystal of a wide-bandgap semiconductor. That is, semiconductor device 1A is a "wide-bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0045] A wide bandgap semiconductor is a semiconductor having a bandgap greater than that of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, chip 2 is an example of a "SiC chip" comprising a hexagonal SiC single crystal as a wide bandgap semiconductor. That is, semiconductor device 1A is a "SiC semiconductor device".

[0046] Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown where chip 2 includes a 4H-SiC single crystal, but chip 2 can also include other polymorphs.

[0047] Chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are quadrilaterals when viewed from the vertical direction Z (hereinafter referred to as "top view"). The vertical direction Z is also the thickness direction of chip 2.

[0048] The first main surface 3 and the second main surface 4 are preferably formed from the c-plane of a SiC single crystal. In this case, the first main surface 3 is preferably formed from the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed from the carbon surface ((000-1) surface) of the SiC single crystal.

[0049] The first side surface 5A and the second side surface 5B extend along the first main surface 3 in a first direction X and are opposite each other along the first main surface 3 in a second direction Y that intersects the first direction X. Specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and are opposite each other in the first direction X.

[0050] In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the first direction X can be the a-axis direction of the SiC single crystal, and the second direction Y can be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first principal surface 3 will sometimes be referred to as the "horizontal direction". The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, which is orthogonal to the vertical direction Z.

[0051] Chip 2 (first main surface 3 and second main surface 4) has a deviation angle that is tilted at a predetermined angle relative to the c-plane of the SiC single crystal in a predetermined deviation direction. That is, the amount of the deviation angle by which the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical line along the vertical direction Z toward the deviation direction. In addition, the amount of the deviation angle by which the c-plane of the SiC single crystal is tilted relative to the horizontal plane.

[0052] The deviation direction is preferably the a-axis direction of the SiC single crystal (in this case, the second direction Y). The deviation angle can be greater than 0° and less than 10°. The deviation angle can have a value belonging to at least one of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0053] The deviation angle is preferably 5° or less. Particularly preferred is a deviation angle of 2° or more but less than 4.5°. The deviation angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a deviation angle of 0° (i.e., the first main surface 3 is facing the front relative to surface c).

[0054] Semiconductor device 1A includes an n-type first semiconductor region 6 formed on the surface layer of a second main surface 4. A drain potential, which is a first potential (high potential), is assigned to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "base region (layer)," "semiconductor region (layer)," "drain region (layer)," etc.

[0055] The first semiconductor region 6 extends in a layered manner along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this configuration, the first semiconductor region 6 is composed of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is composed of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), forming the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the aforementioned offset direction and offset angle.

[0056] The first semiconductor region 6 may have a thickness T1 of 10 μm or more and 500 μm or less. The thickness T1 of the first semiconductor region 6 may have a value belonging to at least one of the following ranges: 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0057] Semiconductor device 1A includes an n-type second semiconductor region 7 formed on the surface layer of a first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)" or "drift region (layer)". The second semiconductor region 7 has an n-type impurity concentration lower than that of the first semiconductor region 6. In a cross-sectional view, the second semiconductor region 7 is formed on the side of the first main surface 3 relative to the first semiconductor region 6 and is electrically connected to the first semiconductor region 6.

[0058] The second semiconductor region 7 extends in layers along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this configuration, the second semiconductor region 7 is composed of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is composed of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), forming the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0059] The second semiconductor region 7 (epitaxial layer) has the aforementioned offset direction and offset angle. The second semiconductor region 7 preferably has a thickness T2 that is less than the thickness T1 of the first semiconductor region 6. The thickness T2 of the second semiconductor region 7 may be greater than the thickness T1 of the first semiconductor region 6.

[0060] The thickness T2 of the second semiconductor region 7 can be 5 μm or more and 15 μm or less. The thickness T2 of the second semiconductor region 7 can have a value belonging to at least one of the following ranges: 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0061] Semiconductor device 1A includes an active region 8 disposed on chip 2. The active region 8 is a region that includes a device structure (transistor structure Tr) and generates an output current (drain current). The active region 8 is disposed in the inner part of chip 2 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0062] The active region 8 is configured to have a polygonal shape (in this case, a quadrilateral shape) with four sides parallel to the periphery of the chip 2 when viewed from above. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 can be 0.5 or higher and 0.95 or lower. The area ratio can be 0.5 or higher and 0.6 or lower, 0.6 or higher and 0.7 or lower, 0.7 or higher and 0.8 or lower, 0.8 or higher and 0.9 or lower, or 0.9 or higher and 0.95 or lower.

[0063] Semiconductor device 1A includes an outer peripheral region 9 disposed in chip 2 outside the active region 8. The outer peripheral region 9 is a region excluding device structures (transistor structures Tr). The outer peripheral region 9 is disposed at the periphery of chip 2. That is, in top view, the outer peripheral region 9 is disposed in the region between the periphery of chip 2 and the active region 8. In top view, the outer peripheral region 9 extends in a strip along the active region 8 and is configured as a polygonal ring surrounding the active region 8 (in this case, a quadrilateral ring).

[0064] Semiconductor device 1A includes multiple gate structures 15 of trench type (trench electrode type) formed in active region 8. The gate structure 15 may also be referred to as "trench structure" or "trench gate structure".

[0065] Multiple gate structures 15 are formed at intervals on the inner portion of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D), but not on the outer peripheral region 9. When viewed from above, the multiple gate structures 15 are arranged at intervals in the first direction X (=m-axis direction), and extend in a strip-like shape in the second direction Y (=a-axis direction). When viewed from above, the multiple gate structures 15 are arranged in a stripe-like pattern extending along the second direction Y.

[0066] Semiconductor device 1A includes a p-type outer well region 40 formed in the outer peripheral region 9. The outer well region 40 includes a first outer well region 42 and a plurality of second outer well regions 43.

[0067] Reference Figure 3 and Figure 4 The first outer well region 42 is a quadrilateral ring-shaped region divided by thick solid lines and thick dashed lines. The first outer well region 42 has a portion extending along a first direction X and a portion extending along a second direction Y. In this manner, the first outer well region 42 is formed as a polygonal ring (quadrilateral ring in this manner) with four sides parallel to the periphery of the chip 2 when viewed from above, and surrounds a plurality of gate structures 15.

[0068] The first outer well region 42 may also have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y into an arc shape (preferably a quarter arc shape). In this manner, the first outer well region 42 is formed in the outer peripheral region 9, surrounding the active region 8.

[0069] Reference Figure 3 and Figure 4 Each of the multiple second outer well regions 43 is represented by a solid line. Each of the multiple second outer well regions 43 has a portion extending along a first direction X and a portion extending along a second direction Y. In this configuration, each second outer well region 43 is formed as a polygonal ring (in this configuration, a quadrilateral ring) with four sides parallel to the periphery of the chip 2 when viewed from above, and surrounds the first outer well region 42.

[0070] The plurality of second outer well regions 43 may also each have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y into an arc shape (preferably a quarter arc shape). In this manner, the plurality of second outer well regions 43 are arranged at intervals from the first outer well region 42 outward in the outer peripheral region 9.

[0071] Semiconductor device 1A includes an n-type field-stop region 12 formed in the outer peripheral region 9. (See reference...) Figure 3 as well as Figure 4The field cutoff region 12 has a portion extending along a first direction X and a portion extending along a second direction Y. In this configuration, the field cutoff region 12 is formed as a polygonal ring (in this configuration, a quadrilateral ring) with four sides parallel to the periphery of the chip 2 when viewed from above, surrounding a plurality of second outer well regions 43. The field cutoff region 12 is disposed separately from the plurality of second outer well regions 43 to the outside, and separately disposed separately from the end faces (first to fourth side faces 5A to 5D) of the chip 2 to the inside.

[0072] Semiconductor device 1A includes a p-type voltage easing region 60 formed in the outer peripheral region 9. The voltage easing region 60 may also be referred to as an "end voltage easing region". (See reference...) Figure 3 as well as Figure 4 The voltage mitigation region 60 has a portion extending along a first direction X and a portion extending along a second direction Y. In this configuration, the voltage mitigation region 60 is formed as a polygonal ring (in this embodiment, a quadrilateral ring) with four sides parallel to the periphery of the chip 2 when viewed from above, and surrounds the field cutoff region 12. The voltage mitigation region 60 is disposed separately from the field cutoff region 12 and exposed from the end faces (first to fourth side faces 5A to 5D) of the chip 2. The voltage mitigation region 60 is exposed from the end faces of the chip 2 throughout its entire circumference. In this configuration, the voltage mitigation region 60 is integrally exposed from both sides of the first main surface 3 and the end faces (first to fourth side faces 5A to 5D) at the peripheral corner of the first main surface 3 of the chip 2.

[0073] Semiconductor device 1A includes an insulating interlayer film 47 formed on a first main surface 3. The interlayer film 47 may also be referred to as an "insulating film," "interlayer insulating film," "intermediate insulating film," etc. The interlayer film 47 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 47 preferably includes a silicon oxide film.

[0074] Semiconductor device 1A includes a source electrode 51 disposed on a first main surface 3. The source electrode 51 is a terminal electrode to which a source potential is applied from the outside. The source electrode 51 may also be referred to as a "source pad electrode", "first pad electrode", "first main surface electrode", "first terminal electrode", etc. The source electrode 51 is disposed on a portion of the interlayer film 47 covering the active region 8.

[0075] In this configuration, the source electrode 51 has a first pad portion 51a, a second pad portion 51b, and a third pad portion 51c. The first pad portion 51a has a relatively large planar area and forms the main body of the source electrode 51. In this configuration, the first pad portion 51a is formed into a polygonal shape (in this configuration, a quadrilateral shape) with four sides parallel to the periphery of the chip 2 when viewed from above, and is offset towards the fourth side surface 5D relative to the center of the first main surface 3.

[0076] The second pad portion 51b has a planar area smaller than that of the first pad portion 51a, and extends in a strip (quadrilateral shape) from one end of the first pad portion 51a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 51c has a planar area smaller than that of the first pad portion 51a, and extends in a strip (quadrilateral shape) from the other end of the first pad portion 51a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and is opposite to the second pad portion 51b in the second direction Y.

[0077] The planar area of ​​the third pad portion 51c can also be approximately equal to the planar area of ​​the second pad portion 51b. The planar area of ​​the third pad portion 51c can be larger or smaller than the planar area of ​​the second pad portion 51b. Either or both of the second pad portion 51b and the third pad portion 51c can also be used as a terminal portion for current monitoring.

[0078] The source electrode 51 does not necessarily need to have both the second pad portion 51b and the third pad portion 51c. The source electrode 51 may also have only one of the second pad portion 51b and the third pad portion 51c. The source electrode 51 may also be composed only of the first pad portion 51a, without both the second pad portion 51b and the third pad portion 51c.

[0079] Semiconductor device 1A includes source wiring 56 disposed on an interlayer film 47 around a source electrode 51. The source wiring 56 is given the same potential (source potential) as the potential (source potential) given to the source electrode 51. The source wiring 56 may also be referred to as a "terminal electrode (wiring)," "wiring," "first wiring," "finger electrode," "source finger," etc.

[0080] The source wiring 56 has a wiring width smaller than the electrode width of the source electrode 51 and is selectively wound onto the interlayer film 47. In this manner, the source wiring 56 extends from the source electrode 51 (first pad portion 51a) toward the fourth side surface 5D. The source wiring 56 extends from the active region 8 to the outer peripheral region 9.

[0081] The source wiring 56 extends in a strip along the periphery of the first main surface 3 (the periphery of the active region 8). In this configuration, the source wiring 56 is formed as a polygonal ring (in this configuration, a quadrilateral ring) with four sides parallel to the periphery of the chip 2 when viewed from above, surrounding the inner square portion (active region 8) of the first main surface 3. The source wiring 56 may also have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y into an arc shape (preferably a quarter arc shape). The source wiring 56 may also be terminal or terminalless.

[0082] Semiconductor device 1A includes a gate electrode 57 disposed on a first main surface 3. The gate electrode 57 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 57 may also be referred to as a "second pad electrode", "second main surface electrode", "second terminal electrode", etc.

[0083] The gate electrode 57 is disposed at intervals from the source electrode 51 on a portion of the interlayer film 47 covering the active region 8. In this configuration, the gate electrode 57 is disposed on the third side surface 5C side relative to the first pad portion 51a, and is opposite to the first pad portion 51a in the first direction X. The region of the gate electrode 57 between the second pad portion 51b and the third pad portion 51c is opposite to both the second pad portion 51b and the third pad portion 51c in the second direction Y.

[0084] Viewed from above, the gate electrode 57 is formed as a polygon (in this case, a quadrilateral) with four sides parallel to the periphery of the chip 2. The gate electrode 57 has a planar area smaller than that of the source electrode 51. The gate electrode 57 has a planar area smaller than that of the first pad portion 51a. The gate electrode 57 may also have a planar area smaller than that of the second pad portion 51b (or the third pad portion 51c).

[0085] Semiconductor device 1A includes a gate wiring 58 extending from a gate electrode 57 to a first main surface 3. The gate wiring 58 may also be referred to as a "wiring", "second wiring", "finger electrode", "gate finger", etc. The gate wiring 58 transmits the gate potential assigned to the gate electrode 57 to other regions.

[0086] Gate wiring 58 extends from gate electrode 57 to a portion of the interlayer film 47 covering the active region 8, and is wound at intervals from source electrode 51 and source wiring 56 to the region between source electrode 51 and source wiring 56.

[0087] The gate wiring 58 has a portion extending in a strip shape along a first direction X and a portion extending in a strip shape along a second direction Y when viewed from above, intersecting (specifically orthogonal) the ends (two ends in this case) of the plurality of gate structures 15. In this case, the gate wiring 58 is formed as an end strip with four sides parallel to the periphery of the first main surface 3, surrounding the source electrode 51.

[0088] Semiconductor device 1A includes a drain electrode 59 covering a second main surface 4. The drain electrode 59 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 59 may also be referred to as a "third pad electrode", "third main surface electrode", "third terminal electrode", etc.

[0089] The drain electrode 59 is electrically connected to the first semiconductor region 6. The drain electrode 59 may also cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. Alternatively, the drain electrode 59 may partially cover the second main surface 4, exposing the periphery of the second main surface 4.

[0090] The breakdown voltage that can be applied between the source electrode 51 and the drain electrode 59 (between the first main surface 3 and the second main surface 4) can be 500V or more and 3000V or less. The breakdown voltage can have a value belonging to at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or less, and 2750V or more and 3000V or less.

[0091] Figure 5 It means Figure 3 An enlarged top view of a major part of the first main surface 3 shown. Figure 6 It means Figure 3 An enlarged top view of a major part of the first main surface 3 shown. Figure 7 It is along Figure 5 The sectional view along line VII-VII shown. Figure 8 It is along Figure 5 The cross-sectional view of line VIII-VIII shown. Figure 9 It is along Figure 6 The cross-sectional view of the IX-IX line shown. Figure 10 It means along Figure 1 A cross-sectional view of the outer periphery region 9 of the XX line shown. Figure 11 yes Figure 10 An enlarged sectional view of one of the areas shown. Figures 9-11 The image shows the outer well region 40 of a first embodiment of the semiconductor device 1A. Figure 11 In order to make the structure of the periphery of chip 2 clear, a part between the active region 8 and the outer peripheral region 9 is omitted with a wavy line, and the periphery of chip 2 is enlarged and represented.

[0092] Reference Figures 5 to 11 This describes the transistor structure Tr formed in the active region 8 of the semiconductor device 1A and the structure within the outer peripheral region 9.

[0093] Semiconductor device 1A includes a p-type main body region 10 formed on the surface layer of the first main surface 3 in the active region 8 (inner part of the first main surface 3). The main body region 10 may also be referred to as an "impurity region," "channel region," etc. A source potential may be applied to the main body region 10. The source potential may also be a reference potential that serves as a reference for circuit operation. The reference potential may also be a ground potential. The main body region 10 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7. The main body region 10 may, for example, have a 1×10⁻⁶ p-type impurity concentration. 17 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentrations are used as peak values.

[0094] Reference Figure 10 The main body region 10 is formed at intervals from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) in the inner portion of the first main surface 3, and is not formed in the outer peripheral region 9. In this configuration, the main body region 10 is formed over the entire area of ​​the active region 8. The main body region 10 is formed on the surface portion of the second semiconductor region 7 and extends in layers along the first main surface 3.

[0095] The main body region 10 is formed at intervals from the bottom of the second semiconductor region 7 (the first semiconductor region 6) toward the first main surface 3, and is opposite to the first semiconductor region 6 across a portion of the second semiconductor region 7. The main body region 10 is formed at intervals from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3.

[0096] The main body region 10, when viewed in cross-section, is the region formed on the side of the first main surface 3 relative to the second semiconductor region 7, and is electrically connected to the second semiconductor region 7. The main body region 10 and the second semiconductor region 7 form a pn junction (body diode). When a reverse bias voltage is applied, the main body region 10 extends the depletion layer into the second semiconductor region 7. The depletion layer, originating from the main body region 10, extends within the second semiconductor region 7 in both the horizontal and thickness directions.

[0097] Semiconductor device 1A includes an n-type source region 11 formed in the surface portion of a first main surface 3 in an active region 8. The source region 11 is given a source potential. The source region 11 has an n-type impurity concentration that is higher than that of the second semiconductor region 7. The n-type impurity concentration of the source region 11 is higher than that of the p-type impurity concentration of the main region 10.

[0098] The source region 11 is formed at intervals from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) in the inner part of the first main surface 3, and is not formed in the outer peripheral region 9. The source region 11 may also be formed at intervals from the periphery of the main body region 10 inward. The source region 11 is formed in the surface part of the main body region 10 and extends in layers along the first main surface 3.

[0099] The source region 11 is formed at intervals from the bottom of the main body region 10 toward the first main surface 3, and is opposed to the second semiconductor region 7 across a portion of the main body region 10. In cross-section, the source region 11 is formed relative to the main body region 10 on the side of the first main surface 3 and is electrically connected to the main body region 10.

[0100] Semiconductor device 1A includes a plurality of trench-type (trench electrode type) gate structures 15 formed in the inner portion of a first main surface 3. The gate structure 15 may also be referred to as a "trench structure" or "trench gate structure". A gate potential (gate signal) is applied to the plurality of gate structures 15 as a control potential. The plurality of gate structures 15 control the inversion and non-inversion of the channel within the main body region 10 in response to the gate potential.

[0101] Multiple gate structures 15 are formed at intervals on the inner portion of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D), but not on the outer peripheral region 9. When viewed from above, the multiple gate structures 15 are arranged at intervals in the first direction X (=m-axis direction) and extend in a strip-like shape in the second direction Y (=a-axis direction). When viewed from above, the multiple gate structures 15 are arranged in a stripe-like pattern extending along the second direction Y.

[0102] The extension direction of the plurality of gate structures 15 is consistent with the offset direction of the SiC single crystal. In the second direction Y, the two ends of the plurality of gate structures 15 may also be located in the region between the periphery of the main body region 10 and the periphery of the source region 11. The plurality of gate structures 15 may also be arranged at intervals in the second direction Y when viewed from above, and extend in a strip shape in the first direction X.

[0103] Multiple gate structures 15 penetrate the main body region 10 and the source region 11 in a manner that reaches the second semiconductor region 7. The multiple gate structures 15 are formed at intervals from a depth position at the bottom of the second semiconductor region 7 toward the first main surface 3, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7.

[0104] Multiple gate structures 15 may be formed at intervals from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3, or they may be located at the bottom side of the second semiconductor region 7 relative to the depth position in the middle of the second semiconductor region 7. The multiple gate structures 15 are formed substantially perpendicular to the first main surface 3. The multiple gate structures 15 may also be formed into a pointed shape facing the bottom of the second semiconductor region 7.

[0105] The sidewalls (long sides) of the plurality of gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. The sidewalls (long sides) of the plurality of gate structures 15 may also be formed by the a-plane ((11-20) plane) of the SiC single crystal, depending on the extension direction of the gate structure 15. The bottom wall of the plurality of gate structures 15 is formed by the c-plane (Si plane) of the SiC single crystal. The bottom wall of the plurality of gate structures 15 preferably extends approximately flat along the horizontal direction. The bottom wall of the plurality of gate structures 15 may also be curved into an arc shape towards the second main surface 4.

[0106] The tilt angle (absolute value) of the sidewall (long side) of the gate structure 15, referenced to a vertical line, can also be 85° or more and 95° or less. The tilt angle can have a value belonging to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The tilt angle is preferably 87° or more and 93° or less.

[0107] The gate structure 15 may also have a width of 0.1 μm or more and 2 μm or less. The width of the gate structure 15 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0108] The gate structure 15 may also have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 is the depth relative to the first main surface 3. The depth of the gate structure 15 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0109] The gate structure 15 may also have an aspect ratio of 1 or more and 3 or less. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 3 or less. The aspect ratio is preferably 1.5 or more and 2.5 or less.

[0110] The multiple gate structures 15 each include a first trench 16, a first insulating film 17, and a first buried electrode 18. The first trench 16 is formed on the first main surface 3, dividing the walls (side walls and bottom walls) of the gate structure 15.

[0111] The first insulating film 17 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 17 has a single-layer structure composed of a silicon oxide film. The first insulating film 17 is particularly preferably composed of a silicon oxide film composed of the oxide of the chip 2.

[0112] A first insulating film 17 covers the wall of the first trench 16. The first insulating film 17 includes a first film portion and a second film portion. The first film portion covers the sidewall of the first trench 16 in a film-like manner. The second film portion covers the bottom wall of the first trench 16 in a film-like manner and is connected to the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0113] The first insulating film 17 may also have a thickness of 10 nm or more and 150 nm or less. The thickness of the first insulating film 17 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0114] The first embedded electrode 18 is embedded in the first trench 16 through the first insulating film 17. The first embedded electrode 18 may also include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The first embedded electrode 18 is positioned opposite the second semiconductor region 7, the main body region 10, and the source region 11 through the first insulating film 17.

[0115] The first embedded electrode 18 has an electrode surface exposed from the first trench 16. The height position of the electrode surface relative to the first main surface 3 is located on the bottom wall side of the first trench 16. The depth position of the electrode surface relative to the bottom of the source region 11 is located on the side of the first main surface 3. The electrode surface has a groove in its inner portion that is recessed in a pointed shape towards the bottom wall of the first trench 16.

[0116] The semiconductor device 1A includes gate well regions 25 formed in the chip 2 (second semiconductor region 7) of the active region 8, respectively, below a plurality of gate structures 15. The gate well regions 25 may also be referred to as "first well regions", etc.

[0117] The gate well region 25 is given a source potential. The gate well region 25 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate well region 25 can be higher or lower than the p-type impurity concentration of the main region 10. The p-type impurity (trivalent element) of the gate well region 25 is preferably aluminum.

[0118] Multiple gate well regions 25 are formed at intervals in the horizontal direction (first direction X) within the second semiconductor region 7, respectively, below (specifically directly below) the multiple gate structures 15. The multiple gate well regions 25 are formed within a thickness range between the bottom of the second semiconductor region 7 and the bottom wall of the multiple gate structures 15, and overlap with the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.

[0119] When viewed from above, the multiple gate well regions 25 extend in a stripe-like pattern along the extension direction of their respective gate structures 15 in the second direction Y. That is, the multiple gate well regions 25 are arranged in a stripe-like pattern extending in the second direction Y when viewed from above.

[0120] The extension direction of the plurality of gate well regions 25 is consistent with the offset direction of the SiC single crystal. Alternatively, the plurality of gate well regions 25 may extend in the first direction X, depending on the extension direction of the plurality of gate structures 15. In this case, the plurality of gate well regions 25 intersect (specifically, are orthogonal) the offset direction.

[0121] Multiple gate well regions 25 are formed spaced apart from the bottom of the second semiconductor region 7 toward the bottom wall side of the multiple gate structures 15, and are opposite to the first semiconductor region 6 across a portion of the second semiconductor region 7. The multiple gate well regions 25 each have an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side (second main surface 4 side) of the second semiconductor region 7.

[0122] The upper ends of a plurality of gate well regions 25 are formed spaced apart from the bottom of the main body region 10 toward the bottom wall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may also be connected to the bottom wall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may also have a portion along the sidewall of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 25 may also be formed spaced apart from the bottom wall of the corresponding gate structure 15 toward the bottom of the second semiconductor region 7.

[0123] The bottom of the plurality of gate well regions 25 may be located on the bottom wall side of the plurality of gate structures 15 relative to the middle portion of the second semiconductor region 7, or it may be located on the bottom side (second main surface 4 side) of the second semiconductor region 7 relative to the middle portion of the second semiconductor region 7.

[0124] Each of the multiple gate well regions 25 has a bulge 25a. The bulge 25a extends in an arc shape from the region directly below the corresponding gate structure 15 to both sides of the corresponding gate structure 15 in a horizontal direction. Each of the multiple gate well regions 25 is formed into a pointed shape from the bulge 25a toward the bottom.

[0125] The gate well region 25 may have a width greater than or less than the width of the gate structure 15. The width of the gate well region 25 may be greater than or less than 0.1 μm and less than 2 μm. The width of the gate well region 25 may have a value belonging to at least one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0126] The gate well region 25 may have a thickness less than the depth of the gate structure 15, or it may have a thickness greater than the depth of the gate structure 15. The thickness of the gate well region 25 is the depth of the gate well region 25 relative to the bottom wall of the gate structure 15.

[0127] The thickness of the gate well region 25 may also be greater than 0 μm and less than 5 μm. The thickness of the gate well region 25 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, greater than 1.5 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, greater than 3.5 μm and less than 4 μm, greater than 4 μm and less than 4.5 μm, and greater than 4.5 μm and less than 5 μm.

[0128] The gate well region 25 may also have an aspect ratio greater than 0 and less than 2. The aspect ratio of the gate well region 25 is the ratio of the thickness of the gate well region 25 to the width of the gate well region 25.

[0129] The aspect ratio can have a value that is greater than 0 and less than 0.25, greater than 0.25 and less than 0.5, greater than 0.5 and less than 0.75, greater than 0.75 and less than 1, greater than 1 and less than 1.25, greater than 1.25 and less than 1.5, greater than 1.5 and less than 1.75, and greater than 1.75 and less than 2.

[0130] The gate well region 25 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the gate well region 25 extends a depletion layer in the second semiconductor region 7. The depletion layer, originating from the gate well region 25, extends in both the horizontal and thickness directions, mitigating the electric field on the active region 8 (gate structure 15).

[0131] Reference Figure 5 , Figure 6 as well as Figure 8 The semiconductor device 1A includes a plurality of gate contact regions 27 formed in the active region 8 within the chip 2 (second semiconductor region 7). The gate contact regions 27 may also be referred to as "first contact regions", etc. A source potential is assigned to the gate contact regions 27.

[0132] The gate contact region 27 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate contact region 27 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the gate contact region 27 is higher than the p-type impurity concentration of the gate well region 25.

[0133] Multiple gate contact regions 27 are formed at intervals along multiple gate structures 15. The multiple gate contact regions 27 are formed in a one-to-many correspondence with respect to the multiple gate structures 15. The multiple gate contact regions 27 are formed at intervals along the extension direction of the corresponding gate structure 15 in a second direction Y.

[0134] Regarding the gate structures 15 of one and the other, a plurality of gate contact regions 27 along one gate structure 15 are opposite to a plurality of gate contact regions 27 along the other gate structure 15 in a first direction X when viewed from above. That is, the plurality of gate contact regions 27 are arranged in a matrix with spacing between them in the first direction X and the second direction Y when viewed from above.

[0135] The multiple gate contact regions 27 on one side can also be opposite to the regions between the multiple gate contact regions 27 on the other side in the first direction X when viewed from above. That is, the multiple gate contact regions 27 can also be arranged in an alternating pattern with intervals between them in the first direction X and the second direction Y when viewed from above.

[0136] In this configuration, multiple gate contact regions 27 extend in a strip-like shape along multiple gate structures 15 when viewed from above. The lengths of the multiple gate contact regions 27 in the second direction Y can be equal or different from each other. The lengths of the multiple gate contact regions 27 in the second direction Y are adjusted according to the channel area to be formed.

[0137] The channel area is the total area of ​​the portion of the source region 11 exposed from the plurality of gate contact regions 27. That is, the channel area increases or decreases as a proportion of the total planar area of ​​the plurality of gate contact regions 27 increases or decreases. Preferably, the total planar area of ​​the plurality of gate contact regions 27 is smaller than the channel area.

[0138] That is, in the region between a pair of adjacent gate structures 15, the total planar area of ​​the plurality of gate contact regions 27 is preferably smaller than the planar area of ​​the source region 11. According to such a structure, it is possible to suppress the increase in resistance (on-resistance) caused by short channels.

[0139] The length of the gate contact region 27 can be greater than or less than the width of the gate structure 15. The length of the gate contact region 27 can be greater than or less than the spacing between the gate structures 15. The length of the gate contact region 27 can be greater than or less than the spacing between two adjacent gate structures 15.

[0140] The spacing between the multiple gate contact regions 27 can be larger or smaller than the width of the gate structure 15. The spacing between the gate contact regions 27 can be larger or smaller than the pitch of the gate structures 15. The spacing between the gate contact regions 27 can be larger or smaller than the pitch between two adjacent gate structures 15.

[0141] Multiple gate contact regions 27 are located between the bottom walls of multiple gate structures 15 and the bottoms of multiple gate well regions 25. The multiple gate contact regions 27 are connected to the bottom walls of the corresponding gate structures 15 and the corresponding gate well regions 25.

[0142] Multiple gate contact regions 27 increase the p-type impurity concentration at the upper end of the corresponding gate well region 25. The gate contact region 27 has an extension that extends from the region directly below the gate structure 15 to both sides of the gate structure 15 and along the sidewall of the gate structure 15.

[0143] The thickness of the portion (extension) of the gate contact region 27 along the sidewall of the gate structure 15 in the horizontal direction (first direction X) may also be less than the thickness of the portion of the gate contact region 27 along the bottom wall of the gate structure 15 in the vertical direction Z.

[0144] The extension of the gate contact region 27 is electrically connected to the main body region 10 on the surface of the first main surface 3, thereby electrically connecting the corresponding gate well region 25 to the main body region 10. This suppresses the possibility of the gate well region 25 becoming electrically floating, thereby improving the electrical response characteristics of the gate well region 25.

[0145] The gate contact region 27 has an upper end portion exposed from the first main surface 3. In this configuration, the upper end portion of the gate contact region 27 is exposed from the sidewall of the first trench 16 at the opening end of the first trench 16. The upper end portion of the gate contact region 27 may also extend horizontally in the surface portion of the main body region 10.

[0146] The second semiconductor region 7 of the semiconductor device 1A includes a stacked structure of a base region 71 and a cap region 72.

[0147] The base region 71 is formed separately from the main region 10, closer to the second main surface 4 than the gate well region 25. The base region 71 is formed in a layer extending along the first main surface 3 at the location where it separates from the main region 10 and the first trench 16 towards the second main surface 4. The base region 71 may also be formed over the entire surface portion of the second semiconductor region 7 on the second main surface 4 side, exposed from the first to fourth side surfaces 5A to 5D. The base region 71 forms the boundary surface between the second semiconductor region 7 and the first semiconductor region 6.

[0148] The thickness of the base region 71 can be, for example, 0.5 μm or more and 20 μm or less. Preferably, the thickness of the base region 71 is 1 μm or more and 10 μm or less.

[0149] The n-type impurity concentration in the base region 71 is preferably lower than that in the first semiconductor region 6. The base region 71 may also have a concentration of 1 × 10⁻⁶. 16 cm -3 Above and 1×10 17 cm -3The following n-type impurity concentrations are taken as peak values. The n-type impurity concentration in the base region 71 can also be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the base region 71 can also have a concentration gradient that gradually increases and / or decreases towards the thickness direction (crystal growth direction) of the chip 2.

[0150] A cap region 72 is formed at least in the active region 8. The cap region 72 is formed on the base region 71. The cap region 72 contacts the body region 10 and the gate well region 25, and is formed as a layer extending along the first main surface 3. In this manner, the cap region 72 forms the boundary surface with the body region 10 in the second semiconductor region 7. The body region 10 is formed on the surface portion of the cap region 72. The body region 10 is physically separated from the base region 71 by sandwiching the cap region 72 in the thickness direction of the chip 2. The gate structure 15 penetrates the source region 11 and the body region 10 and has a bottom within the cap region 72.

[0151] The n-type impurity concentration in the cap region 72 is preferably higher than that in the base region 71. The cap region 72 may also have a concentration of 1 × 10⁻⁶. 17 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentrations are taken as peak values. The n-type impurity concentration in the cap region 72 can also be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the cap region 72 can also have a concentration gradient that gradually increases and / or decreases towards the thickness direction (crystal growth direction) of the chip 2.

[0152] In this manner, the n-type impurity concentrations of the base region 71 and the cap region 72 are adjusted by nitrogen. The base region 71 and the cap region 72 may also have n-type impurity concentrations adjusted by at least one pentavalent element. For example, the n-type impurity concentrations of the base region 71 and the cap region 72 may also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0153] Reference Figure 9 The outermost gate structure 15 among the plurality of gate structures 15 is the end gate structure 15A. In this manner, among the plurality of gate structures 15 arranged in a stripe pattern extending along the second direction Y, an end gate structure 15A is formed at the end of each of the two sides (the third side 5C side and the fourth side 5D side) in the first direction X (see also...). Figure 3 as well as Figure 4 ).exist Figure 9 The terminal gate structure 15A on the fourth side 5D side is shown in the figure.

[0154] In this configuration, the terminal gate structure 15A includes a terminal first trench 16A, a terminal first insulating film 17A, and a terminal first buried electrode 18A. The terminal first trench 16A is a boundary trench forming the boundary portion 19 between the active region 8 and the outer peripheral region 9. Except for the arrangement in the stripes, the terminal gate structure 15A has the same structure as the remaining gate structure 15.

[0155] Reference Figure 6 and Figures 9-11 Semiconductor device 1A includes a p-type outer well region 40 formed in the outer peripheral region 9 on the surface portion of the first main surface 3. The outer well region 40 is given a source potential. The outer well region 40 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7.

[0156] The p-type impurity concentration in the outer well region 40 is less than that in the gate well region 25. The p-type impurity concentration in the outer well region 40 is less than that in the gate contact region 27.

[0157] The p-type impurity concentration in the outer well region 40 can also be approximately equal to the p-type impurity concentration in the gate well region 25. The p-type impurity concentration in the outer well region 40 can be either higher or lower than the p-type impurity concentration in the gate well region 25.

[0158] The p-type impurity concentration in the outer well region 40 can also be approximately equal to the p-type impurity concentration in the main body region 10. It can be higher or lower than the p-type impurity concentration in the main body region 10.

[0159] As described above, the outer well region 40 includes a first outer well region 42 and a plurality of second outer well regions 43. The first outer well region 42 and the plurality of second outer well regions 43 may also be referred to as a "terminal region" and a "field region," respectively. Alternatively, the first outer well region 42 and the plurality of second outer well regions 43 may be collectively referred to as the "outer well region." The first outer well region 42 may also be referred to as a "terminal well region," a "JTE region (Junction Termination Extension region)," etc. The second outer well regions 43 may also be referred to as a "protection region," a "field confinement region," etc.

[0160] A source potential is assigned to the first outer well region 42. The first outer well region 42 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7.

[0161] Main reference Figure 9 and Figure 10A first outer well region 42 is formed on the surface portion of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The first outer well region 42 is formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and is opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. Preferably, the first outer well region 42 is formed at intervals from a depth position in the middle portion of the second semiconductor region 7 toward the first main surface 3.

[0162] The first outer well region 42 is formed along the outer peripheral boundary 19 and is shallower than the gate well region 25. The depth D1 of the first outer well region 42 can, for example, be greater than 0 μm and less than 4 μm. The depth D1 of the first outer well region 42 can have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, greater than 1.75 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, and greater than 3.5 μm and less than 4 μm.

[0163] When the first outer well region 42 is arranged at intervals from the first main surface 3 to the bottom side of the second semiconductor region 7 (when the first outer well region 42 is not exposed from the first main surface 3), the depth D1 of the first outer well region 42 can also be referred to as the thickness of the first outer well region 42. Alternatively, the first outer well region 42 may also have a depth approximately the same as that of the gate well region 25.

[0164] Along the horizontal direction of the first main surface 3, the first outer well region 42 at least partially covers the gate well region 25 of the end first trench 16A.

[0165] More specifically, the gate well region 25 includes a well side portion (in this case, a bulge 25a) extending in the thickness direction of the second semiconductor region 7 and a well bottom portion 25b extending from the bulge 25a in a direction along the first main surface 3. The first outer well region 42 selectively covers the bulge 25a on the outer peripheral region 9 side (outer side) of the gate well region 25 at the end of the first trench 16A. The bulge 25a on the active region 8 side (inner side) not covered by the first outer well region 42 and the well bottom portion 25b are covered by the second semiconductor region 7 (in this case, a cap region 72).

[0166] The first outer trap region 42 has a first upper end portion 42a on the side of the first main surface 3, a first lower end portion 42b on the opposite side thereof, and a first body portion 42c between the first lower end portion 42b and the first upper end portion 42a.

[0167] The first upper portion 42a extends horizontally along the first main surface 3 and protrudes from the first main surface 3. The depth position of the first upper portion 42a relative to the bottom of the gate structure 15 is located on the side of the first main surface 3. The depth position of the first upper portion 42a relative to the bottom of the gate well region 25 is located on the side of the first main surface 3. The depth position of the first upper portion 42a relative to the bottom of the main body region 10 is located on the side of the first main surface 3. The depth position of the first upper portion 42a relative to the boundary 62 between the cap region 72 and the base region 71 is located on the side of the first main surface 3.

[0168] The first upper part 42a is formed in an arc shape extending from the first body portion 42c toward the first main surface 3. The first upper part 42a includes a central portion 63 exposed from the first main surface 3 and an end portion 64 disposed at a distance spaced apart from the bottom side of the first main surface 3 toward the second semiconductor region 7.

[0169] A gap 65 is formed between the end 64 of the first upper end portion 42a and the first main surface 3. The gap 65 is a region defined between the flat first main surface 3 and the arc-shaped first upper end portion 42a. A portion of the second semiconductor region 7 (in this case, the base region 71) enters the gap 65. This portion of the second semiconductor region 7 is sandwiched between the first main surface 3 and the first upper end portion 42a.

[0170] The first lower end portion 42b extends horizontally along the first main surface 3, forming a pn junction with the second semiconductor region 7. In this configuration, the first lower end portion 42b forms a pn junction with the base region 71. The depth of the first lower end portion 42b relative to the bottom of the gate structure 15 is located on the bottom side of the second semiconductor region 7. The depth of the first lower end portion 42b relative to the bottom of the gate well region 25 is located on the side of the first main surface 3. The depth of the first lower end portion 42b relative to the bottom of the main body region 10 is located on the bottom side of the second semiconductor region 7. The depth of the first lower end portion 42b relative to the boundary 62 between the cap region 72 and the base region 71 is located on the side of the first main surface 3.

[0171] The first lower end portion 42b is formed in a flat shape that is substantially parallel to the first main surface 3. The first lower end portion 42b may also be formed in a flat shape that extends in a direction perpendicular to the thickness direction of the second semiconductor region 7.

[0172] The first body portion 42c is sandwiched between a first upper end portion 42a and a first lower end portion 42b. The first body portion 42c may also be a portion covering the first outer well region 42 of the gate structure 15 and the gate well region 25.

[0173] The first body portion 42c includes a first side portion 42d connecting the first upper end portion 42a and the first lower end portion 42b. In this configuration, the first side portion 42d slopes towards the active region 8 from the first upper end portion 42a toward the first lower end portion 42b. For example, the first outer trap region 42 may also be formed with a cross-sectional terrace shape having a first side portion 42d that slopes in a manner that narrows in width W1 from the first upper end portion 42a toward the first lower end portion 42b.

[0174] The first outer well region 42 has a width W1 larger than the width of the gate structure 15 (e.g., the width of the first lower end 42b). The width W1 of the first outer well region 42 is larger than the width of the end gate structure 15A. The width W1 of the first outer well region 42 may also be greater than the total width of the plurality of end gate structures 15A. The width W1 of the first outer well region 42 may also be greater than the total width of the plurality of gate well regions 25.

[0175] The width W1 of the first outer well region 42 can be greater than 0 μm and less than 300 μm. The width W1 of the first outer well region 42 can have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, greater than 25 μm and less than 50 μm, greater than 50 μm and less than 75 μm, greater than 75 μm and less than 100 μm, greater than 100 μm and less than 125 μm, greater than 125 μm and less than 150 μm, greater than 150 μm and less than 175 μm, greater than 175 μm and less than 200 μm, greater than 200 μm and less than 225 μm, greater than 225 μm and less than 250 μm, greater than 250 μm and less than 275 μm, and greater than 275 μm and less than 300 μm.

[0176] When a reverse bias voltage is applied, the first outer well region 42 causes the depletion layer to extend into the second semiconductor region 7. The depletion layer, originating from the first outer well region 42, extends in both the horizontal and thickness directions, mitigating the electric field near the outer perimeter boundary 19 between the active region 8 and the outer perimeter region 9.

[0177] Semiconductor device 1A includes a p-type outer contact region 41 formed in the outer peripheral region 9 on the surface layer of a first main surface 3. A source potential is applied to the outer contact region 41. The outer contact region 41 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7 (cap region 72). The p-type impurity concentration of the outer contact region 41 is higher than the p-type impurity concentration of the main body region 10 and the first outer well region 42.

[0178] The p-type impurity concentration in the outer contact region 41 is higher than that in the gate well region 25. Alternatively, the p-type impurity concentration in the outer contact region 41 can be approximately equal to that in the gate well region 25. Or, the p-type impurity concentration in the outer contact region 41 can be lower than that in the gate well region 25.

[0179] The p-type impurity concentration in the outer contact region 41 can also be approximately equal to the p-type impurity concentration in the gate contact region 27. The p-type impurity concentration in the outer contact region 41 can be either higher or lower than the p-type impurity concentration in the gate contact region 27.

[0180] An outer contact region 41 is formed on the surface portion of the first outer well region 42. That is, the outer contact region 41 is formed within the thickness range between the first main surface 3 and the bottom of the first outer well region 42. In this manner, the outer contact region 41 is selectively formed at the first upper end portion 42a of the first outer well region 42. This increases the p-type impurity concentration of the first outer well region 42, thereby improving the electrical response speed of the first outer well region 42.

[0181] The outer contact region 41 extends in a strip shape along the end gate structure 15A in the second direction Y. The outer contact region 41 extends in a strip shape across multiple gate structures 15 in the first direction X.

[0182] In this configuration, the outer contact area 41 is formed as a polygonal ring with four sides parallel to the periphery of the chip 2 when viewed from above (in this configuration, it is a quadrilateral ring), and surrounds the inner square portion (active area 8) of the first main surface 3. The outer contact area 41 may also have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y into an arc shape (preferably a quarter arc shape).

[0183] Multiple external contact regions 41 may also be formed at intervals along the extension direction of the end gate structure 15A and in the direction that crosses the multiple gate structures 15.

[0184] The outer contact region 41 has a width smaller than that of the first outer well region 42 and is formed within the first outer well region 42. The outer contact region 41 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3.

[0185] In this configuration, the inner edge of the outer contact region 41 is connected to the terminal gate structure 15A. In this configuration, the inner edge of the outer contact region 41 is connected to the gate well region 25 of the terminal first trench 16A. The inner edge of the outer contact region 41 extends along the terminal gate structure 15A (outer peripheral boundary 19) in the thickness direction of the second semiconductor region 7 and is connected to the gate well region 25 of the terminal first trench 16A. The first outer well region 42 is electrically connected to the main body region 10 via the gate well region 25 of the terminal first trench 16A. The first outer well region 42 may also be formed spaced apart from the terminal gate structure 15A.

[0186] The outer edge of the outer contact region 41 is formed at intervals from the outer edge of the first outer well region 42 toward the end gate structure 15A. The outer contact region 41 may also have a portion that crosses the outer edge of the first outer well region 42 and is connected to the second semiconductor region 7.

[0187] The outer contact region 41 has a width greater than that of the gate well region 25. The width of the outer contact region 41 is greater than that of the terminal gate structure 15A. The width of the outer contact region 41 may also be less than that of the first outer well region 42. The width of the outer contact region 41 may also be greater than that of the first outer well region 42.

[0188] The width of the outer contact region 41 may also be greater than 0 μm and less than 300 μm. The width of the outer contact region 41 may also have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, greater than 25 μm and less than 50 μm, greater than 50 μm and less than 75 μm, greater than 75 μm and less than 100 μm, greater than 100 μm and less than 125 μm, greater than 125 μm and less than 150 μm, greater than 150 μm and less than 175 μm, greater than 175 μm and less than 200 μm, greater than 200 μm and less than 225 μm, greater than 225 μm and less than 250 μm, greater than 250 μm and less than 275 μm, and greater than 275 μm and less than 300 μm.

[0189] The outer contact region 41 has an upper end portion located on the side of the first main surface 3 and a bottom end portion located on the bottom side of the first outer well region 42. The upper end portion of the outer contact region 41 protrudes from the first main surface 3. The bottom of the outer contact region 41 is located on the side of the first main surface 3 at a depth relative to the bottom of the gate well region 25.

[0190] The bottom of the outer contact area 41 is located on the side of the first main surface 3 relative to the bottom of the first outer well area 42. The bottom of the outer contact area 41 may be located on the side of the first main surface 3 relative to the bottom of the main body area 10, or it may be located on the bottom side of the first outer well area 42.

[0191] The depth (thickness) of the outer contact region 41 may also be greater than 0 μm and less than 1 μm. The depth of the outer contact region 41 may also have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.1 μm, greater than 0.1 μm and less than 0.2 μm, greater than 0.2 μm and less than 0.3 μm, greater than 0.3 μm and less than 0.4 μm, greater than 0.4 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.6 μm, greater than 0.6 μm and less than 0.7 μm, greater than 0.7 μm and less than 0.8 μm, greater than 0.8 μm and less than 0.9 μm, and greater than 0.9 μm and less than 1 μm.

[0192] The second outer well region 43 is formed in an electrically floating state. A source potential can also be assigned to the second outer well region 43.

[0193] The number of second outer well regions 43 is arbitrary. The number of second outer well regions 43 can also be more than one and less than 15. The number of second outer well regions 43 can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. Typically, the number of second outer well regions 43 is more than one and less than ten. In this embodiment, as an example, semiconductor device 1A includes three second outer well regions 43.

[0194] The second outer well region 43 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the second outer well region 43 may also be approximately equal to the p-type impurity concentration of the first outer well region 42. The p-type impurity concentration of the second outer well region 43 may be higher or lower than the p-type impurity concentration of the first outer well region 42.

[0195] The p-type impurity concentration in the second outer well region 43 can also be lower than the p-type impurity concentration in the gate contact region 27. The p-type impurity concentration in the second outer well region 43 can be either higher or lower than the p-type impurity concentration in the gate well region 25. The p-type impurity concentration in the second outer well region 43 can also be either higher or lower than the p-type impurity concentration in the main body region 10.

[0196] In this configuration, the p-type impurity concentrations of the multiple second outer well regions 43 are approximately equal to each other. The p-type impurity concentrations of the multiple second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be mitigated. Alternatively, the p-type impurity concentrations of the multiple second outer well regions 43 can also be different from each other.

[0197] Main reference Figure 10 and Figure 11 A plurality of second outer well regions 43 are formed on the surface portion of the second semiconductor region 7 and are electrically connected to the second semiconductor region 7. The plurality of second outer well regions 43 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. The plurality of second outer well regions 43 are preferably formed at intervals from a depth position in the middle portion of the second semiconductor region 7 toward the first main surface 3.

[0198] The depth D2 of the second outer well region 43 can also be approximately equal to the depth D1 of the first outer well region 42. The depth D2 of the second outer well region 43 can be deeper or shallower than the depth D1 of the first outer well region 42.

[0199] The depth D2 of the second outer well region 43 can, for example, be greater than 0 μm and less than 4 μm. The depth D2 of the second outer well region 43 can have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, greater than 1.75 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, and greater than 3.5 μm and less than 4 μm. When the second outer well region 43 is arranged at intervals from the first main surface 3 to the bottom side of the second semiconductor region 7 (when the second outer well region 43 is not exposed from the first main surface 3), the depth D2 of the second outer well region 43 can also be referred to as the thickness of the second outer well region 43.

[0200] In this configuration, the depths D2 of the multiple second outer well regions 43 are approximately equal to each other. The depths D2 of the multiple second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be mitigated. The depths D2 of the multiple second outer well regions 43 can also be different from each other.

[0201] The depth D2 of the plurality of second outer well regions 43 may also increase sequentially toward the periphery of the first main surface 3. The depth D2 of the plurality of second outer well regions 43 may also increase toward the periphery of the first main surface 3 in two or more groups of units, each including two or more second outer well regions 43.

[0202] The depth D2 of the plurality of second outer well regions 43 may also decrease sequentially toward the periphery of the first main surface 3. The depth D2 of the plurality of second outer well regions 43 may also decrease toward the periphery of the first main surface 3 in two or more groups of units, each comprising two or more second outer well regions 43.

[0203] Multiple second outer well regions 43 are formed at intervals between the periphery of the first main surface 3 and the terminal gate structure 15A (outer peripheral boundary portion 19). Multiple second outer well regions 43 are formed at intervals between the periphery of the first main surface 3 and the first outer well region 42.

[0204] The second outer trap region 43 has a second upper end portion 43a on the side of the first main surface 3, a second lower end portion 43b on the opposite side thereof, and a second body portion 43c between the second lower end portion 43b and the second upper end portion 43a.

[0205] The second upper portion 43a extends horizontally along the first main surface 3 and protrudes from the first main surface 3. The depth position of the second upper portion 43a relative to the bottom of the gate structure 15 is located on the side of the first main surface 3. The depth position of the second upper portion 43a relative to the bottom of the gate well region 25 is located on the side of the first main surface 3. The depth position of the second upper portion 43a relative to the bottom of the main body region 10 is located on the side of the first main surface 3. The depth position of the second upper portion 43a relative to the boundary 62 between the cap region 72 and the base region 71 is located on the side of the first main surface 3.

[0206] The second upper part 43a is formed in an arc shape extending from the second body part 43c toward the first main surface 3. The second upper part 43a includes a central part 66 exposed from the first main surface 3 and an end part 67 disposed at a distance spaced apart from the bottom side of the first main surface 3 toward the second semiconductor region 7.

[0207] A gap 68 is formed between the end 67 of the second upper end portion 43a and the first main surface 3. The gap 68 is a region defined between the flat first main surface 3 and the arc-shaped second upper end portion 43a. A portion of the second semiconductor region 7 (in this case, the base region 71) enters the gap 68. This portion of the second semiconductor region 7 is sandwiched between the first main surface 3 and the second upper end portion 43a.

[0208] The second lower end portion 43b extends horizontally along the first main surface 3, forming a pn junction with the second semiconductor region 7. In this configuration, the second lower end portion 43b forms a pn junction with the base region 71. The depth of the second lower end portion 43b relative to the bottom of the gate structure 15 is located on the bottom side of the second semiconductor region 7. The depth of the second lower end portion 43b relative to the bottom of the gate well region 25 is located on the side of the first main surface 3. The depth of the second lower end portion 43b relative to the bottom of the main body region 10 is located on the bottom side of the second semiconductor region 7. The depth of the second lower end portion 43b relative to the boundary 62 between the cap region 72 and the base region 71 is located on the side of the first main surface 3.

[0209] The second lower end portion 43b is formed into a flat shape that is substantially parallel to the first main surface 3. The second lower end portion 43b may also be formed into a flat shape that extends in a direction perpendicular to the thickness direction of the second semiconductor region 7.

[0210] The second body portion 43c is sandwiched between a second upper end portion 43a and a second lower end portion 43b. The second body portion 43c includes a second side portion 43d that connects the second upper end portion 43a and the second lower end portion 43b. In this configuration, the second side portion 43d slopes from the second upper end portion 43a toward the second lower end portion 43b. For example, the second outer well region 43 may also be formed with a cross-sectional terrace shape having a second side portion 43d that slopes in a manner that narrows in width W2 from the second upper end portion 43a toward the second lower end portion 43b.

[0211] The plurality of second outer well regions 43 may also have a width W2 that is smaller than the width W1 of the first outer well region 42. The width W2 of the plurality of second outer well regions 43 (e.g., the width of the second lower end 43b) may be smaller than or larger than the width of the gate structure 15. The width W2 of the second outer well regions 43 may be smaller than or larger than the width of the gate well region 25.

[0212] In this configuration, the widths W2 of the plurality of second outer well regions 43 are approximately equal to each other. The widths W2 of the plurality of second outer well regions 43 are arbitrary and can take various values ​​depending on the electric field to be mitigated. The widths W2 of the plurality of second outer well regions 43 can also be different from each other.

[0213] The width W2 of the plurality of second outer well regions 43 may also increase sequentially toward the periphery of the first main surface 3. The width W2 of the plurality of second outer well regions 43 may also increase toward the periphery of the first main surface 3 in two or more groups of units, each including two or more second outer well regions 43.

[0214] The width W2 of the plurality of second outer well regions 43 may also decrease sequentially toward the periphery of the first main surface 3. The width W2 of the plurality of second outer well regions 43 may also decrease toward the periphery of the first main surface 3 in two or more groups of units, each comprising two or more second outer well regions 43.

[0215] The width W2 of the second outer well region 43 is narrower than the width W1 of the first outer well region 42. The width W2 of the second outer well region 43 can also be greater than 0 μm and less than 5 μm. The width W2 of the second outer well region 43 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, greater than 1.75 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, greater than 3.5 μm and less than 4 μm, greater than 4 μm and less than 4.5 μm, and greater than 4.5 μm and less than 5 μm.

[0216] The spacing between the plurality of second outer well regions 43 may also be less than or equal to the width W2 of the second outer well region 43. Preferably, the spacing between the plurality of second outer well regions 43 is less than the width W2 of the second outer well region 43. Alternatively, the spacing between the plurality of second outer well regions 43 may be greater than the width W2 of the second outer well region 43.

[0217] In this configuration, the spacing between the plurality of second outer well regions 43 is approximately equal to that between them. The spacing between the plurality of second outer well regions 43 is arbitrary and can take various values ​​depending on the electric field to be mitigated. The spacing between the plurality of second outer well regions 43 can also be different from that between them.

[0218] The spacing between the plurality of second outer well regions 43 may also increase sequentially toward the periphery of the first main surface 3. The spacing between the plurality of second outer well regions 43 may also increase toward the periphery of the first main surface 3 in two or more groups, each comprising two or more second outer well regions 43.

[0219] The spacing between the plurality of second outer well regions 43 may also decrease sequentially toward the periphery of the first main surface 3. The spacing between the plurality of second outer well regions 43 may also decrease toward the periphery of the first main surface 3 in two or more groups of units, each comprising two or more second outer well regions 43.

[0220] The spacing of the second outer well region 43 can be greater than 0 μm and less than 5 μm. The spacing can have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, greater than 1.5 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, greater than 3.5 μm and less than 4 μm, greater than 4 μm and less than 4.5 μm, and greater than 4.5 μm and less than 5 μm.

[0221] The ratio (spacing ratio) of the spacing of the second outer well region 43 to the width W2 of the second outer well region 43 can be greater than 0.1 and less than 5. The spacing ratio can have a value belonging to at least one of the following ranges: greater than 0.1 and less than 0.5, greater than 0.5 and less than 1, greater than 1 and less than 1.5, greater than 1.5 and less than 2, greater than 2 and less than 2.5, greater than 2.5 and less than 3, greater than 3 and less than 3.5, greater than 3.5 and less than 4, greater than 4 and less than 4.5, and greater than 4.5 and less than 5.

[0222] When a reverse bias voltage is applied, the multiple second outer well regions 43 cause the depletion layer to extend towards the second semiconductor region 7. The depletion layer originating from the multiple second outer well regions 43 extends in both the horizontal and thickness directions, integrating with the depletion layer originating from the first outer well region 42. The multiple second outer well regions 43 cause the depletion layer originating from the first outer well region 42 to expand towards the periphery of the first main surface 3, mitigating the electric field at the periphery (outer peripheral region 9) of the first main surface 3.

[0223] Reference Figure 10 and Figure 11 The semiconductor device 1A includes an n-type field-stop region 12 formed in the outer peripheral region 9 on the surface portion of the first main surface 3. The field-stop region 12 has the same depth as the cap region 72. The field-stop region 12 and the cap region 72 may have a bottom at the same depth from the first main surface 3.

[0224] The depth D3 of the field cutoff region 12 and the depth D4 of the cap region 72 can be the distances from the first main surface 3 to the bottom of the field cutoff region 12 and the bottom of the cap region 72, respectively. The depth D3 of the field cutoff region 12 and the depth D4 of the cap region 72 can be referred to as the "thickness of the field cutoff region 12" and the "thickness of the cap region 72", respectively.

[0225] The depth D3 of the field cutoff region 12 and the depth D4 of the cap region 72 can be, for example, 0.1 μm or more and 0.5 μm or less. Preferably, the depth D3 of the field cutoff region 12 and the depth D4 of the cap region 72 are 0.15 μm or more and 0.4 μm or less.

[0226] The field cutoff region 12 may also be formed deeper than the outer well region 40. The bottom of the field cutoff region 12 may be located at the bottom side of the second semiconductor region 7 relative to the depth of the bottom of the outer well region 40. The bottom of the field cutoff region 12 may be located at the bottom side of the second semiconductor region 7 relative to the depth of either the bottom of the first outer well region 42 or the bottom of the second outer well region 43. The bottom of the field cutoff region 12 may also be located at the bottom side of the second semiconductor region 7 relative to the depths of both the bottom of the first outer well region 42 and the bottom of the second outer well region 43. That is, the depth D3 of the field cutoff region 12 may also be greater than at least one of the depth D1 of the first outer well region 42 and the depth D2 of the second outer well region 43. The depth D1 of the first outer well region 42 and the depth D2 of the second outer well region 43 may also be the distances from the first main surface 3 to the bottom of the first outer well region 42 and the bottom of the second outer well region 43, respectively.

[0227] The field cutoff region 12 can be formed to be deeper than the main body region 10. The bottom of the field cutoff region 12 can be located at the bottom side of the second semiconductor region 7 at a depth relative to the bottom of the main body region 10. That is, the depth D3 of the field cutoff region 12 can be greater than the depth D5 of the main body region 10.

[0228] The depth D5 (thickness of the main body region 10) of the main body region 10 can be, for example, 0.1 μm or more and 3.0 μm or less. Preferably, the depth D5 of the main body region 10 is 0.5 μm or more and 1.0 μm or less. The depth D5 of the main body region 10 can also be the distance from the first main surface 3 to the bottom of the main body region 10.

[0229] The field cutoff region 12 can be formed deeper than the gate structure 15. The bottom of the field cutoff region 12 can be located at the bottom side of the second semiconductor region 7 relative to the depth of the bottom of the gate structure 15. That is, the depth D3 of the field cutoff region 12 can be greater than the depth D6 of the gate structure 15.

[0230] As described above, the depth D6 of the gate structure 15 can be, for example, 0.1 μm or more and 3 μm or less. The depth D6 of the gate structure 15 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth D6 of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less. The depth D6 of the gate structure 15 can also be the distance from the first main surface 3 to the bottom of the gate structure 15.

[0231] The field-stop region 12 can be formed deeper than the gate well region 25. The bottom of the field-stop region 12 can be located at the bottom side of the second semiconductor region 7 relative to the depth of the bottom of the gate well region 25. That is, the depth D3 of the field-stop region 12 can be greater than the depth D7 of the gate well region 25.

[0232] The depth D7 of the gate well region 25 can be, for example, 0.1 μm or more and 3.0 μm or less. Preferably, the depth D7 of the gate well region 25 is 0.5 μm or more and 2.0 μm or less. The depth D7 of the gate well region 25 can also be the distance from the first main surface 3 to the bottom of the gate well region 25.

[0233] Reference Figure 11 The first main surface 3 of chip 2 extends from the active region 8 through the peripheral region 9 to the end face (first to fourth side surfaces 5A to 5D) of chip 2 in a flat surface without steps. The "no steps" of the first main surface 3 can also be defined as the absence of a recess formed when a portion of the first main surface 3 is selectively removed, for example by etching, after the epitaxial growth of the second semiconductor region 7.

[0234] Therefore, the first main surface 3 of the active region 8 and the first main surface 3 of the outer peripheral region 9 can also be flat surfaces. The thickness of the second semiconductor region 7 in the active region 8 and the thickness of the second semiconductor region 7 in the outer peripheral region 9 can also be the same. The distance from the boundary between the second semiconductor region 7 and the first semiconductor region 6 in the active region 8 to the first main surface 3 and the distance from the boundary between the second semiconductor region 7 and the first semiconductor region 6 in the outer peripheral region 9 to the first main surface 3 can also be the same.

[0235] In this configuration, the field cutoff region 12 and the source region 11 each have an upper surface 12a exposed from the first main surface 3 of the outer peripheral region 9 and an upper surface 11a exposed from the first main surface 3 of the active region 8, respectively. The upper surface 12a of the field cutoff region 12 and the upper surface 11a of the source region 11 are positioned at the same height. That is, no height difference is formed between the upper surface 12a and the upper surface 11a.

[0236] The field cutoff region 12 includes a stacked structure of a first region 13 and a second region 14. The stacked structure can be a two-layer structure consisting of a lower layer composed of the first region 13 and an upper layer composed of the second region 14. The first region 13 can also be referred to as the "base region" or "base layer," etc. The second region 14 can also be referred to as the "high-concentration region" or "high-concentration layer," etc.

[0237] Both the first region 13 and the second region 14 can have a higher impurity concentration than the base region 71. In comparing the first region 13 and the second region 14, the second region 14 can also have a higher impurity concentration than the first region 13.

[0238] The impurity concentration in the first region 13 can also be the same as that in the cap region 72. The first region 13 can also have a concentration of 1×10⁻⁶. 17 cm -3 Above and 1×10 18 cm -3 The following n-type impurity concentration is used as the peak value. The impurity concentration of the second region 14 can also be the same as that of the source region 11. The second region 14 can also have a concentration of 1 × 10⁻⁶. 18 cm -3 Above and 1×10 19 cm -3 The following n-type impurity concentrations are taken as peak values.

[0239] The thickness T3 of the first region 13 can also be greater than the thickness T4 of the second region 14. The thickness T3 of the first region 13 can be greater than the depth D1 of the first outer well region 42 and the depth D2 of the second outer well region 43. The thickness T4 of the second region 14 can be less than the depth D1 of the first outer well region 42 and the depth D2 of the second outer well region 43.

[0240] The boundary 61 between the first region 13 and the second region 14 can also be positioned at the same depth as the bottom of the source region 11. The boundary 61 can also be located on the first main surface 3 at a depth relative to the bottom of the outer well region 40 (first outer well region 42 and second outer well region 43). The boundary 61 can also be located on the first main surface 3 at a depth relative to the bottom of the main body region 10. The boundary 61 can also be located on the first main surface 3 at a depth relative to the bottom of the gate structure 15. The boundary 61 can also be located on the first main surface 3 at a depth relative to the bottom of the gate well region 25.

[0241] Reference Figure 10 and Figure 11 The semiconductor device 1A includes a p-type voltage mitigation region 60 formed in the outer peripheral region 9 on the surface portion of the first main surface 3. The voltage mitigation region 60 has the same depth as the main body region 10. The voltage mitigation region 60 and the main body region 10 may have a bottom at the same depth from the first main surface 3. That is, the depth D8 of the voltage mitigation region 60 may be the same as the depth D5 of the main body region 10.

[0242] The voltage mitigation region 60 has an upper surface 60a exposed from the first main surface 3 of the outer peripheral region 9 and side surfaces 60b exposed from the first to fourth side surfaces 5A to 5D. The upper surface 60a and side surfaces 60b are continuous at the peripheral corners of the first main surface 3 of the chip 2. Thus, the voltage mitigation region 60 is exposed from both the first main surface 3 and the first to fourth side surfaces 5A to 5D of the chip 2.

[0243] The upper surface 60a of the voltage mitigation region 60 and the upper surface 11a of the source region 11 are positioned at the same height. That is, no height difference is formed between the upper surface 60a and the upper surface 11a. In addition, the side surface 60b does not form steps on the first to fourth side surfaces 5A to 5D of the chip 2, and the first to fourth side surfaces 5A to 5D are continuous as flat surfaces without steps from the second main surface 4 to the first main surface 3 in the entirety including the side surface 60b.

[0244] The impurity concentration in the voltage easing region 60 can also be the same as that in the main region 10. The voltage easing region 60 can also have a concentration of 1×10⁻⁶. 17 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentrations are taken as peak values.

[0245] Semiconductor device 1A includes a main surface insulating film 45 selectively covering a first main surface 3. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 45 preferably comprises an insulating material of the same type as the first insulating film 17. In this manner, the main surface insulating film 45 has a single-layer structure composed of a silicon oxide film. The main surface insulating film 45 is particularly preferably composed of a silicon oxide film composed of the oxide of the chip 2.

[0246] The main insulating film 45 is connected to the first insulating film 17 of the plurality of gate structures 15 in the active region 8, so that the first buried electrode 18 of the plurality of gate structures 15 is exposed.

[0247] The main surface insulating film 45 covers the second semiconductor region 7, the first outer well region 42, the outer contact region 41, the second outer well region 43, the field cutoff region 12, and the voltage mitigation region 60 in the outer peripheral region 9. In this configuration, the main surface insulating film 45 is connected to the first to fourth side surfaces 5A to 5D at the peripheral edge of the first main surface 3. The main surface insulating film 45 can be formed by spacing from the peripheral edge of the first main surface 3 inward, thus exposing the peripheral edge of the first main surface 3 (the second semiconductor region 7).

[0248] Semiconductor device 1A includes an insulating interlayer film 47 that selectively covers a first main surface 3 via a main surface insulating film 45. The interlayer film 47 may also be referred to as an "insulating film," "interlayer insulating film," "intermediate insulating film," etc. The interlayer film 47 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 47 preferably includes a silicon oxide film.

[0249] Interlayer film 47 covers multiple gate structures 15 (first buried electrode 18) on the active region 8 side. Interlayer film 47 covers the second semiconductor region 7, the first outer well region 42, the outer contact region 41, the second outer well region 43, the field cutoff region 12 and the voltage mitigation region 60 on the outer peripheral region 9 side, separated by main surface insulating film 45.

[0250] In this configuration, the interlayer film 47 is connected to the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The interlayer film 47 may also be formed at intervals from the periphery of the first main surface 3 inward, exposing the periphery of the first main surface 3 (the second semiconductor region 7).

[0251] The interlayer membrane 47 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer membrane 47 may have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0252] Semiconductor device 1A includes a plurality of gate openings (not shown) formed in an interlayer film 47 in an active region 8. The plurality of gate openings are formed in a one-to-many correspondence with respect to a corresponding gate structure 15. In this manner, the plurality of gate openings penetrate the interlayer film 47, exposing one end or the other end of the plurality of gate structures 15 (first buried electrode 18).

[0253] The multiple gate openings may also each have an opening end that is bent into an arc shape. The multiple gate openings may also be formed, when viewed from above, into a quadrilateral shape, a rectangular shape (strip) extending along a first direction X, a rectangular shape (strip) extending along a second direction Y, a circular shape, etc. The multiple gate openings may also each have an opening end that is bent into an arc shape.

[0254] Semiconductor device 1A includes a plurality of source openings 49 formed in an interlayer film 47 in an active region 8. Figure 10 For clarity, the source openings 49 are omitted. Multiple source openings 49 are formed in portions of the interlayer film 47 covering the active regions 8. In this configuration, multiple source openings 49 are formed in regions between adjacent gate structures 15, exposing multiple source regions 11 and multiple gate contact regions 27.

[0255] Multiple source openings 49 penetrate the main surface insulating film 45 and the interlayer film 47, exposing the corresponding multiple source regions 11 and multiple gate contact regions 27. The multiple source openings 49 may also each have an opening end bent into an arc shape.

[0256] Multiple source openings 49 can also be formed in a one-to-many correspondence with respect to the regions between adjacent gate structures 15. In this case, multiple source openings 49 can also be formed spaced apart along the regions between corresponding gate structures 15. In addition, in this case, multiple source openings 49 can also be formed in a quadrilateral shape, a rectangular shape (strip shape), a circular shape, etc. when viewed from above.

[0257] Semiconductor device 1A includes at least one (in this case, one) external opening 50 formed in an interlayer film 47 in an outer peripheral region 9. The external opening 50 penetrates the main insulating film 45 and the interlayer film 47, exposing an outer contact region 41. The external opening 50 extends in a strip along the outer contact region 41 when viewed from above.

[0258] In this configuration, the outer opening 50, when viewed from above, is formed as a polygonal ring (specifically a quadrilateral ring) surrounding the inner square portion (active region 8) of the first main surface 3 along the outer contact region 41. The outer opening 50 may also have an opening end that is curved into an arc shape.

[0259] The semiconductor device 1A may also have multiple external openings 50. In this case, the multiple external openings 50 may also be formed at intervals along the external contact region 41 in a manner that surrounds the inner square portion (active region 8) of the first main surface 3. In this case, the multiple external openings 50 may also be formed in the form of a quadrilateral (square), a rectangle, a hexagon, a circle, etc. when viewed from above.

[0260] Semiconductor device 1A includes a source electrode 51 disposed on a first main surface 3. The source electrode 51 extends from an interlayer film 47 into a plurality of source openings 49 and is electrically connected to a plurality of source regions 11 and a plurality of gate contact regions 27 within the plurality of source openings 49.

[0261] In this configuration, the source electrode 51 has a stacked structure comprising a lower electrode film 52 and a main electrode film 53 sequentially stacked from the chip 2 side. In this configuration, the lower electrode film 52 has a stacked structure comprising a first electrode film and a second electrode film. In this configuration, the first electrode film comprises a Ti film, and the second electrode film comprises a TiN film. The lower electrode film 52 does not necessarily need to have a stacked structure; it can also have a single-layer structure composed of either the first electrode film (Ti film) or the second electrode film (TiN film).

[0262] The lower electrode film 52 covers the region in the interlayer film 47 where multiple source openings 49 are formed in a film-like manner, and extends from the interlayer film 47 into the multiple source openings 49. The lower electrode film 52 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surface of the multiple source openings 49 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner within the multiple source openings 49. The lower electrode film 52 is mechanically and electrically connected to the multiple source regions 11 and the multiple gate contact regions 27 within the source openings 49.

[0263] The main electrode film 53 comprises a different conductive material than the lower electrode film 52. The main electrode film 53 may also comprise at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also comprise at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 53 has a thickness greater than the thickness (total thickness) of the lower electrode film 52. Preferably, the thickness of the main electrode film 53 is greater than the thickness of the interlayer film 47.

[0264] The thickness of the main electrode film 53 can also be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 53 can have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0265] The main electrode film 53 directly covers the lower electrode film 52. The main electrode film 53 covers the region in the interlayer film 47 where multiple source openings 49 are formed in a film-like manner, and backfills the multiple source openings 49.

[0266] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 via the lower electrode film 52, a portion that covers the wall surfaces of the plurality of source openings 49 via the lower electrode film 52, and a portion that covers the first main surface 3 via the lower electrode film 52. The main electrode film 53 is electrically connected to the plurality of source regions 11 and the plurality of gate contact regions 27 within the plurality of source openings 49 via the lower electrode film 52.

[0267] Semiconductor device 1A includes source wiring 56 disposed on interlayer film 47 around source electrode 51.

[0268] Source wiring 56 is led out from active region 8 to outer peripheral region 9 and has a portion that faces outer contact region 41 across interlayer film 47. Source wiring 56 enters outer opening 50 from interlayer film 47 and is electrically connected to outer contact region 41 within outer opening 50. That is, source wiring 56 is electrically connected to first outer well region 42 via outer contact region 41.

[0269] The source wiring 56 has an inner edge portion on the inner square side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source wiring 56 is located within the active region 8 and is opposed to one or more (in this case, multiple) gate structures 15 across an interlayer film 47. The inner edge portion of the source wiring 56 is opposed to at least the terminal gate structure 15A across the interlayer film 47.

[0270] The outer edge of the source wiring 56 is formed at intervals from the periphery of the first main surface 3 inward (toward the active region 8). The outer edge of the source wiring 56 is also formed at intervals from the innermost second outer well region 43 among the plurality of second outer well regions 43. In other words, the source wiring 56 is not separated from the plurality of second outer well regions 43, the field cutoff region 12, and the voltage mitigation region 60 by the interlayer film 47.

[0271] According to this structure, the situation where the dispersion path of the electric field in the region of the multiple second outer well regions 43 is blocked by the source wiring 56 is suppressed, and the electric field (electric field lines) is properly dispersed through the multiple second outer well regions 43.

[0272] The source wiring 56 is not electrically connected to the field cutoff region 12 and the voltage easing region 60, but is mechanically connected. Thus, the field cutoff region 12 and the voltage easing region 60 are formed in an electrically floating state.

[0273] Like the source electrode 51, the source wiring 56 has a stacked structure including a lower electrode film 52 and a main electrode film 53 stacked sequentially from the chip 2 side.

[0274] The lower electrode film 52 covers the area of ​​the interlayer film 47 where the outer opening 50 is formed in a film-like manner, and extends from the interlayer film 47 into the outer opening 50. The lower electrode film 52 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surface of the outer opening 50 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner within the outer opening 50. The lower electrode film 52 is mechanically and electrically connected to the outer contact area 41 within the outer opening 50.

[0275] The main electrode film 53 directly covers the lower electrode film 52. The main electrode film 53 covers the area in the interlayer film 47 where the external opening 50 is formed in a film-like manner, and backfills the external opening 50.

[0276] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 through the lower electrode film 52, a portion that covers the wall surface of the outer opening 50 through the lower electrode film 52, and a portion that covers the first main surface 3 through the lower electrode film 52. The main electrode film 53 is electrically connected to the outer contact area 41 within the outer opening 50 via the lower electrode film 52.

[0277] In addition, although the cross-sectional structure is omitted, the aforementioned gate electrode 57 and gate wiring 58 (see reference) Figure 1 It also has the same stacked structure as the source electrode 51 and the source wiring 56, including the lower electrode film 52 and the main electrode film 53 stacked sequentially from the chip 2 side.

[0278] The following details the concentration gradients of n-type and p-type impurities in the impurity region within chip 2.

[0279] The impurity concentration, thickness, and other values ​​shown below are examples illustrating the basic structure of the outer contact region 41, the first outer well region 42, the second outer well region 43, the source region 11, the cap region 72, and the field cutoff region 12 (second region 14 and first region 13) based on the concentration gradient. They are not intended to uniquely define the structure of the outer contact region 41, the first outer well region 42, the second outer well region 43, the source region 11, the cap region 72, and the field cutoff region 12 (second region 14 and first region 13). The impurity concentration, thickness, etc., are adjusted to various values ​​depending on the implantation conditions (dose, implantation temperature, implantation energy, etc.) of the trivalent or pentavalent elements. Furthermore, the term "concentration gradient" can be completely replaced by the term "concentration distribution curve."

[0280] Figure 12 It means along Figure 9 A graph illustrating an example of the concentration gradient of p-type impurities in the region shown by the XII-XII line. Figure 12 In the figure, the vertical axis represents the p-type impurity concentration of the outer contact region 41 and the outer well region 40 (first outer well region 42), and the horizontal axis represents the depth of the second semiconductor region 7 in the thickness direction with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0281] Reference Figure 12 The outer contact region 41 has a concentration gradient characteristic of the impurity region formed by random injection. Figure 12 The diagram illustrates the concentration gradient of the outer contact region 41 when a predetermined trivalent element (in this case, aluminum) is introduced into the second semiconductor region 7 in a random direction using an injection energy of 190 keV. The random direction is a direction that is not parallel (approximately parallel) to the axial channel of the second semiconductor region 7 (e.g., the vertical Z direction). The depth (thickness) of the outer contact region 41 is approximately 0.5 μm, and the dose of the trivalent element is 1 × 10⁻⁶.13 cm -2 .

[0282] The outer contact region 41 has a rapidly increasing portion 73, a peak portion 74 (peak value P1), and a rapidly decreasing portion 75 within a range of 0.5 μm.

[0283] The rapid increase portion 73 is the portion where the impurity concentration increases rapidly from the first main surface 3 toward the peak portion 74. The rapid decrease portion 75 is the portion where the impurity concentration decreases rapidly from the peak portion 74 toward the first lower end portion 42b of the first outer well region 42. For example, the depth of the peak portion 74 is 0.2 μm or more and 0.3 μm or less. The outer contact region 41 may also have the rapid increase portion 73 and the rapid decrease portion 75 in a range of 0.1 μm or more and 0.2 μm or less on the shallow side and the deep side of the peak portion 74, respectively.

[0284] The rapidly increasing portion 73 has a thickness of 0.1 μm or more and 0.2 μm or less, and within this thickness range, it has a concentration change rate of 100% or more. Similarly, the rapidly decreasing portion 75 has a thickness of 0.1 μm or more and 0.2 μm or less, and within this thickness range, it has a concentration change rate of 100% or more.

[0285] The first outer well region 42 has a concentration gradient characteristic of the impurity region formed by the channel effect injection method. Figure 12 The diagram shows the concentration gradient of the first outer well region 42 when a predetermined trivalent element (in this case, aluminum) is introduced into the second semiconductor region 7 with an injection energy of 650 keV, parallel or substantially parallel to the axial channel of the second semiconductor region 7. The depth (thickness) of the first outer well region 42 is approximately 3 μm, and the dose of the trivalent element is 1 × 10⁻⁶. 13 cm -2 .

[0286] The concentration of p-type impurities in the first outer well region 42 has a concentration gradient from the first upper end portion 42a toward the first lower end portion 42b, including an increasing portion 20, a peak portion 21, a slow portion 22, and a decreasing portion 23. The increasing portion 20 is the part forming the first upper end portion 42a of the first outer well region 42, and is the part where the concentration of p-type impurities gradually increases from the first upper end portion 42a toward the first lower end portion 42b to the peak portion 21 at a relatively rapid rate.

[0287] Peak 21 is the portion with the peak value P2 (maximum value) of p-type impurity concentration. Peak 21 is also a convex main concentration transition portion that includes a series of concentration changes (inflection points) from increasing (increasing tendency) to decreasing (decreasing tendency) of p-type impurity concentration. The depth of peak 21 is above 0.5 μm and below 1 μm.

[0288] The slow-reduction section 22 is formed in the region closer to the first lower end portion 42b of the peak section 21, and is a portion where the impurity concentration gradually decreases at a relatively slow rate. That is, the slow-reduction section 22 is a portion that maintains a certain p-type impurity concentration within a certain depth range, forming the body portion of the first outer well region 42. The p-type impurity concentration of the slow-reduction section 22 gradually decreases within a concentration range that is lower than the p-type impurity concentration of the peak section 21.

[0289] The slow-release portion 22 is defined by a portion having a concentration reduction rate of less than 50% over a thickness range of at least 1 μm. In this example, the slow-release portion 22 has a thickness of 0.7 μm or more and 1.5 μm or less, and has a concentration reduction rate of less than 50% within this thickness range. In this example, the p-type impurity concentration of the slow-release portion 22 converges to 4.5 × 10⁻⁶. 16 cm -3 Above and 9×10 16 cm -3 The following concentration range.

[0290] The tapering section 23 is the portion forming the first lower end portion 42b of the first outer trap region 42. The tapering section 23 has a higher concentration reduction rate than the slow section 22, and is the portion where the p-type impurity concentration gradually decreases from the slow section 22 towards the first lower end portion 42b. The concentration reduction rate per unit thickness of the tapering section 23 is greater than the concentration reduction rate per unit thickness of the slow section 22. The p-type impurity concentration in the tapering section 23 gradually decreases from the slow section 22 to 1×10⁻⁶. 15 cm -3 .

[0291] Figure 13 It means along Figure 11 A graph illustrating an example of the concentration gradient in the region along line XIII-XIII. Figure 13 In the figure, the vertical axis represents the p-type impurity concentration of the outer well region 40 (second outer well region 43), and the horizontal axis represents the depth of the second semiconductor region 7 in the thickness direction with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0292] Reference Figure 13 The second outer well region 43 has a concentration gradient characteristic of the impurity region formed by the channel effect injection method. Figure 13 The diagram shows the concentration gradient of the second outer well region 43 when a predetermined trivalent element (in this case, aluminum) is introduced into the second semiconductor region 7 with an injection energy of 650 keV, parallel or substantially parallel to the axial channel of the second semiconductor region 7. The depth (thickness) of the second outer well region 43 is approximately 3 μm, and the dose of the trivalent element is 1 × 10⁻⁶. 13 cm -2 .

[0293] The concentration of p-type impurities in the second outer well region 43 has a concentration gradient from the second upper end portion 43a toward the second lower end portion 43b, including an increasing portion 85, a peak portion 86, a slow portion 87, and a decreasing portion 88. The increasing portion 85 is the part forming the second upper end portion 43a of the second outer well region 43, and is the part where the concentration of p-type impurities gradually increases from the second upper end portion 43a toward the second lower end portion 43b to the peak portion 86 at a relatively rapid rate.

[0294] Peak 86 is the portion with the peak value P3 (maximum value) of p-type impurity concentration. Peak 86 is also a convex main concentration transition section that includes a series of concentration changes (inflection points) from increasing (increasing tendency) to decreasing (decreasing tendency) of p-type impurity concentration. The depth of peak 86 is above 0.5 μm and below 1 μm.

[0295] The slow-reduction section 87 is formed in the region closer to the second lower end portion 43b than the peak section 86, and is a portion where the impurity concentration gradually decreases at a relatively slow rate. That is, the slow-reduction section 87 is a portion that maintains a certain p-type impurity concentration within a certain depth range, forming the body portion of the second outer well region 43. The p-type impurity concentration in the slow-reduction section 87 gradually decreases within a concentration range lower than the p-type impurity concentration in the peak section 86.

[0296] The slow-release portion 87 is defined by a portion having a concentration reduction rate of less than 50% over a thickness range of at least 1 μm. In this example, the slow-release portion 87 has a thickness of 0.7 μm or more and 1.5 μm or less, and has a concentration reduction rate of less than 50% within this thickness range. In this example, the p-type impurity concentration of the slow-release portion 87 converges to 4.5 × 10⁻⁶. 16 cm -3 Above and 9×10 16 cm -3 The following concentration range.

[0297] The tapering section 88 is the portion forming the second lower end portion 43b of the second outer trap region 43. The tapering section 88 has a higher concentration reduction rate than the slow section 87, and is the portion where the p-type impurity concentration gradually decreases from the slow section 87 towards the second lower end portion 43b. The concentration reduction rate per unit thickness of the tapering section 88 is greater than the concentration reduction rate per unit thickness of the slow section 87. The p-type impurity concentration in the tapering section 88 gradually decreases from the slow section 87 to 1×10⁻⁶. 15 cm -3 .

[0298] Figure 14 It means along Figure 9 A graph illustrating an example of the concentration gradient of n-type impurities in the region along the XIV-XIV line. Figure 14In the figure, the vertical axis represents the n-type impurity concentration of the source region 11, the cap region 72 and the base region 71, and the horizontal axis represents the depth of the second semiconductor region 7 in the thickness direction with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0299] Reference Figure 14 In the depth direction of the second semiconductor region 7, the second semiconductor region 7 has a first concentration gradient 76 based on the cap region 72 in a relatively shallow portion, and a second concentration gradient 77 based on the base region 71 in a portion relatively deeper than the first concentration gradient 76. The second semiconductor region 7 exhibits a concentration gradient comprising two stages including the first concentration gradient 76 and the second concentration gradient 77. Furthermore, in Figure 14 In this context, the source concentration gradient 78 is based on the concentration gradient of the n-type source region 11.

[0300] The first concentration gradient 76 and the source concentration gradient 78 have peaks 79 (peak value P4 (maximum value)) and 80 (peak value P5 (maximum value)), respectively. Peak value P5 is higher than peak value P4. For example, peak value P4 is 1 × 10⁻⁶. 17 cm -3 Above and 1×10 18 cm -3 The following are the concentrations of n-type impurities. Peak P5 is 1 × 10⁻⁶. 18 cm -3 Above and 1×10 19 cm -3 The following are the concentrations of n-type impurities.

[0301] The first concentration gradient 76 has an increasing portion 81 on the side shallower and a decreasing portion 82 on the side deeper than the peak 79. The thickness of the increasing portion 81 can be, for example, 1 μm or more and 2 μm or less. The thickness of the decreasing portion 82 can be, for example, 1 μm or more and 2 μm or less.

[0302] The source concentration gradient 78 has an increasing portion 83 on the side shallower and a decreasing portion 84 on the side deeper from the peak 80. The thickness of the increasing portion 83 can be, for example, 0.1 μm or more and 0.2 μm or less. The thickness of the decreasing portion 84 can be, for example, 0.1 μm or more and 0.2 μm or less.

[0303] Figure 15 It means along Figure 11 A graph illustrating an example of the concentration gradient of n-type impurities in the region shown by the XV-XV line. Figure 15 In the figure, the vertical axis represents the n-type impurity concentration of the field cutoff region 12 (second region 14 and first region 13) and the base region 71, and the horizontal axis represents the depth of the second semiconductor region 7 in the thickness direction with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0304] Reference Figure 15 In the depth direction of the second semiconductor region 7, the field cutoff region 12 has a second concentration gradient 70 based on the second region 14 in a relatively shallow portion, and a first concentration gradient 69 based on the first region 13 in a portion relatively deeper than the second concentration gradient 70. The field cutoff region 12 shows a concentration gradient comprising two stages including the first concentration gradient 69 and the second concentration gradient 70.

[0305] The first concentration gradient 69 and the second concentration gradient 70 have peaks 94 (peak value P6 (maximum value)) and 95 (peak value P7 (maximum value)), respectively. Peak value P7 is higher than peak value P6. For example, peak value P6 is 1 × 10⁻⁶. 17 cm -3 Above and 1×10 18 cm -3 The following are the concentrations of n-type impurities. The peak P7 is 1 × 10⁻⁶. 18 cm -3 Above and 1×10 19 cm -3 The following are the concentrations of n-type impurities.

[0306] The first concentration gradient 69 has an increasing portion 96 on the side shallower and a decreasing portion 97 on the side deeper from the peak 94, respectively. The thickness of the increasing portion 96 can be, for example, 1 μm or more and 2 μm or less. The thickness of the decreasing portion 97 can be, for example, 1 μm or more and 2 μm or less.

[0307] The second concentration gradient 70 has an increasing portion 98 and a decreasing portion 99 on the side shallower and deeper from the peak 95, respectively. The thickness range of the increasing portion 98 can be, for example, 0.1 μm or more and 0.2 μm or less. The thickness range of the decreasing portion 99 can be, for example, 0.1 μm or more and 0.2 μm or less.

[0308] Compare Figure 14 and Figure 15 In the depth direction of chip 2, Figure 15 The first concentration gradient 69 in the first region 13 shown is equal to Figure 14 The first concentration gradient 76 of the cap region 72 is shown. Here, equal concentration gradients can also be defined, for example, as concentration distribution curves that are approximately identical when analyzing impurity concentrations in the depth direction of chip 2 using secondary ion mass spectrometry (SIMS). Furthermore, in the depth direction of chip 2, Figure 15 The second concentration gradient 70 in the second region 14 shown is... Figure 14 The source concentration gradient 78 of the source region 11 shown is equal.

[0309] The above describes how, according to semiconductor device 1A, such as Figure 10 as well as Figure 11 As shown, an n-type field-stop region 12 is disposed on the outer side of the outer well region 40. This prevents the depletion layer from extending from the outer well region 40 in front of the end faces (first to fourth sides 5A to 5D) of the chip 2. By designing the position of the field-stop region 12 (e.g., the distance from the end face of the chip 2 inwards), the extension of the depletion layer can be appropriately controlled. As a result, the size of the chip 2 can be reduced, thus enabling miniaturization of the semiconductor device 1A.

[0310] Furthermore, the field cutoff region 12 is formed deeper than the outer well region 40. As a result, the depletion layer extending in the horizontal direction along the first main surface 3 is unlikely to exceed the outer side of the field cutoff region 12, thus effectively suppressing the expansion of the depletion layer.

[0311] Furthermore, the first concentration gradient 69 of the first region 13 of the field stop region 12 is equal to the first concentration gradient 76 of the cap region 72. That is, since the first region 13 and the cap region 72 can be formed in the same process, the decrease in manufacturing efficiency accompanying the addition of the field stop region 12 (first region 13) can be suppressed.

[0312] Furthermore, the second concentration gradient 70 of the second region 14 of the field stop region 12 is equal to the source concentration gradient 78 of the source region 11. That is, since the second region 14 and the source region 11 can be formed in the same process, the decrease in manufacturing efficiency accompanying the addition of the field stop region 12 (second region 14) can be suppressed.

[0313] Furthermore, the p-type impurity concentration of the first outer well region 42 formed by the channel effect implantation method has a gradually increasing portion 20, a peak portion 21, a slow portion 22, and a gradually decreasing portion 23. The slow portion 22 occupies more than 1 / 4 of the thickness range of the first outer well region 42 and is located within the second semiconductor region 7. Specifically, the slow portion 22 occupies more than 1 / 3 of the first outer well region 42. The slow portion 22 typically occupies less than 1 / 2 of the first outer well region 42. The slow portion 22 can occupy more than 1 / 2 of the first outer well region 42.

[0314] On the other hand, when the outer contact region 41 is formed by random injection, it is difficult to exhibit a concentration gradient similar to the concentration gradient having the above-mentioned increasing portion 20, peak portion 21, slow portion 22 and decreasing portion 23.

[0315] Therefore, in the formation of random injection method Figure 9In the case of the first outer well region 42 shown, a multi-stage random implantation method is required. In this method, a process is performed to introduce trivalent elements into different depths in multiple stages using multiple implantation energies. For example, trivalent elements are introduced into the second semiconductor region 7 using different implantation energies such as 3 stages, 5 stages, and 7 stages. While this process allows the introduction of trivalent elements into the target depth, the thickness of the region where trivalent elements can be introduced is narrow. Therefore, to implant to deeper depths, the number of steps in the random implantation method must be increased, complicating the manufacturing process. As a result, the design of the first outer well region 42 becomes more complex, and the increased number of ion implantation steps also increases the device load.

[0316] In contrast, with the channel effect implantation method, a first outer well region 42 with a relatively large thickness of slow portion 22 can be formed in a single ion implantation process. By using fewer processes than with the random implantation method, the first outer well region 42, which improves withstand voltage, can be formed. As a result, the design of the first outer well region 42 can be simplified, and the device load can be reduced.

[0317] Similarly, the p-type impurity concentration in the second outer trap region 43 also has a gradually increasing portion 85, a peak portion 86, a slow portion 87, and a gradually decreasing portion 88. Therefore, the design of the second outer trap region 43 can be simplified, and the burden on the device can be reduced.

[0318] Figure 16 This is a cross-sectional view showing the field cutoff region 12 in the second example. (Refer to...) Figure 16 (Second example) The field cutoff region 12 can also be formed by the first region 13 alone. Therefore, the upper surface of the first region 13 can also be exposed from the first main surface 3 as the upper surface 12a of the field cutoff region 12.

[0319] Figures 17-20 This is a cross-sectional view showing the outer well regions 40 of the second to fifth embodiments. The semiconductor device 1A may also include at least one of the outer well regions 40 of the first to fifth embodiments. The semiconductor device 1A may also include at least two of the outer well regions 40 of the first to fifth embodiments in the same cross-sectional region or in different cross-sectional regions.

[0320] Reference Figure 17(Second embodiment) In the semiconductor device 1A, the first lower end portion 42b of the first outer well region 42 may also be located at the bottom side of the second semiconductor region 7 relative to the depth of the boundary 62 between the cap region 72 and the base region 71. The first lower end portion 42b may also be a portion of the first outer well region 42 that protrudes further towards the bottom side of the second semiconductor region 7 in the thickness direction than the boundary 62 between the cap region 72 and the base region 71. Thus, the inner end portion of the first outer well region 42 may also traverse the boundary 62 between the cap region 72 and the base region 71 in the thickness direction of the second semiconductor region 7, and contact both sides of the cap region 72 and the base region 71.

[0321] Reference Figure 18 (Third embodiment) The first lower end portion 42b of the first outer well region 42 of the semiconductor device 1A may also be located on the first main surface 3 side relative to the depth position of the boundary 62 between the cap region 72 and the base region 71. The first lower end portion 42b may also be spaced further away from the first main surface 3 side than the boundary 62 between the cap region 72 and the base region 71 in the thickness direction of the second semiconductor region 7. Thus, the cap region 72 may have an extension 29 that extends across the outer peripheral boundary 19 into the outer peripheral region 9 and covers the first lower end portion 42b of the first outer well region 42 from the second main surface 4 side. The extension 29 contacts the first lower end portion 42b of the first outer well region 42 along the first main surface 3, forming a flat boundary along the first main surface 3.

[0322] Reference Figure 19 (Fourth embodiment) The semiconductor device 1A may also include a first outer well region 42 having a first side portion 42d extending vertically from the first upper end portion 42a toward the first lower end portion 42b. That is, the first side portion 42d may not be inclined relative to the first main surface 3.

[0323] Reference Figure 20 (Fifth embodiment) The semiconductor device 1A may also include a second outer well region 43 having a second side portion 43d extending vertically from the second upper end portion 43a toward the second lower end portion 43b. That is, the second side portion 43d may not be inclined relative to the first main surface 3.

[0324] Figure 21 This is a graph representing the concentration gradient in the outer trap region 40 of the second example. Figure 21 In the figure, the vertical axis represents the p-type impurity concentration of the outer well region 40 (the first outer well region 42 and the second outer well region 43), and the horizontal axis represents the depth of the second semiconductor region 7 in the thickness direction with the upper end (first main surface 3) of the second semiconductor region 7 as the reference (zero point).

[0325] Figure 21This is a graph showing the results when the outer well region 40 is formed using a random injection method. Figure 21 This represents the concentration gradient of the outer well region 40 when a predetermined trivalent element (in this case, aluminum) is introduced into the second semiconductor region 7 in a random direction using injection energies of 190 keV, 380 keV, 650 keV, 960 keV, or 2000 keV. The random direction is a direction that is not parallel (approximately parallel) to the axial channel of the second semiconductor region 7 (e.g., the vertical direction Z).

[0326] Figure 22 This is a top view showing an example of the layout of the chip of the semiconductor device 1B according to the second embodiment of this disclosure. Figure 23 It means Figure 22 An enlarged top view of a major part of the first main surface 3 shown. Figure 24 It means Figure 22 An enlarged top view of a major part of the first main surface 3 shown. Figure 25 It is along Figure 23 The cross-sectional view of the XXV-XXV line shown. Figure 26 It is along Figure 23 The sectional view of the XXVI-XXVI line shown. Figure 27 It is along Figure 24 The sectional view of line XXVII-XXVII shown.

[0327] Reference Figures 22-27 The semiconductor device 1B has a structure in which multiple source structures 90 and multiple discrete structures 30 are incorporated.

[0328] Semiconductor device 1B includes multiple trench-type (trench electrode type) source structures 90 formed in the inner portion of a first main surface 3. The source structures 90 may also be referred to as "first source structure," "source structure," "second trench structure," etc. Source potentials are assigned to the multiple source structures 90.

[0329] Multiple source structures 90 are formed at intervals on the inner part of the first main surface 3 (first to fourth side surfaces 5A to 5D) and are not formed in the outer peripheral region 9. When viewed from above, the multiple source structures 90 are arranged at intervals in the first direction X (=m axis direction) and extend in a strip shape in the second direction Y (=a axis direction).

[0330] Multiple source structures 90 are disposed at intervals between multiple gate structures 15 in a first direction X, and are opposed to the multiple gate structures 15 in the first direction X. That is, the multiple source structures 90 are arranged alternately with the multiple gate structures 15 in the first direction X, and extend in a strip shape in the second direction Y. The multiple source structures 90 are arranged in a stripe shape extending in the second direction Y.

[0331] The extension direction of the plurality of source structures 90 is consistent with the offset direction of the SiC single crystal. In the second direction Y, the two ends of the plurality of source structures 90 may also be located in the region between the periphery of the main body region 10 and the periphery of the source region 11. The plurality of source structures 90 may also be arranged at intervals in the second direction Y according to the extension direction of the plurality of gate structures 15, and extend in a strip shape in the first direction X.

[0332] Multiple source structures 90 penetrate the main body region 10 and the source region 11 in a manner that reaches the second semiconductor region 7. The multiple source structures 90 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7.

[0333] Multiple source structures 90 may be formed at intervals from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3, or they may be located at the bottom side of the second semiconductor region 7 relative to the depth position in the middle of the second semiconductor region 7. The multiple source structures 90 are formed substantially perpendicular to the first main surface 3. The multiple source structures 90 may also be formed into a pointed shape facing the bottom of the second semiconductor region 7.

[0334] The sidewalls of the multiple source structures 90 are formed by the m-plane ((1-100) plane) of a SiC single crystal. Alternatively, the sidewalls of the multiple source structures 90 may be formed by the a-plane ((11-20) plane) of a SiC single crystal, depending on the extension direction of the source structure 90. The bottom wall of the multiple source structures 90 is formed by the c-plane (Si plane) of a SiC single crystal. Preferably, the bottom wall of the multiple source structures 90 extends approximately flat along the horizontal direction. Alternatively, the bottom wall of the multiple source structures 90 may be curved into an arc shape towards the second main surface 4.

[0335] The tilt angle (absolute value) of the sidewall of the source structure 90, relative to a vertical line, can be 85° or more and 95° or less. The tilt angle can have a value belonging to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The tilt angle is preferably 87° or more and 93° or less.

[0336] The source structure 90 has a width approximately equal to that of the gate structure 15. The width of the source structure 90 may be greater than or less than the width of the gate structure 15.

[0337] The width of the source structure 90 can also be 0.1 μm or more and 2 μm or less. The width of the source structure 90 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0338] The source structure 90 has a depth approximately equal to that of the gate structure 15. The depth of the source structure 90 is the depth relative to the first main surface 3. The depth of the source structure 90 may be greater than or less than the depth of the gate structure 15.

[0339] The depth ratio (depth ratio) of the source structure 90 to the gate structure 15 can also be 0.8 or more and 1.2 or less. The depth ratio can have a value belonging to at least one of the following ranges: 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.11 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less. The depth ratio is preferably 0.95 or more and 1.05 or less.

[0340] The depth of the source structure 90 can also be 0.1 μm or more and 3 μm or less. The depth of the source structure 90 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the source structure 90 is preferably 0.5 μm or more and 1.5 μm or less.

[0341] The source structure 90 may also have an aspect ratio of 1 or more and 3 or less. The aspect ratio of the source structure 90 is the ratio of the depth of the source structure 90 to the width of the source structure 90. The aspect ratio may have a value belonging to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 3 or less. The aspect ratio is preferably 1.5 or more and 2.5 or less.

[0342] The spacing between the central portion of the source structure 90 and the central portion of the gate structure 15 can also be 0.1 μm or more and 2.5 μm or less. The spacing can have a value belonging to at least one range of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, and 2.25 μm or more and 2.5 μm or less.

[0343] The multiple source structures 90 each include a second trench 91, a second insulating film 92, and a second embedded electrode 93. The second trench 91 is formed on the first main surface 3, dividing the walls (side walls and bottom walls) of the source structure 90.

[0344] The second insulating film 92 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the second insulating film 92 comprises an insulating material of the same type as the insulating material of the first insulating film 17. In this configuration, the second insulating film 92 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the second insulating film 92 comprises a silicon oxide film composed of the oxide of the chip 2.

[0345] A second insulating film 92 covers the wall of the second trench 91. The second insulating film 92 includes a first film portion and a second film portion. The first film portion covers the sidewall of the second trench 91 in a film-like manner. The second film portion covers the bottom wall of the second trench 91 in a film-like manner and is connected to the first film portion.

[0346] The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion can be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the second insulating film 92 can also be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the second insulating film 92 can also be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0347] The second insulating film 92 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the second insulating film 92 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0348] The second embedded electrode 93 is embedded in the second trench 91 through the second insulating film 92. The second embedded electrode 93 may also include either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the second embedded electrode 93 includes the same conductive material as the first embedded electrode 18. The second embedded electrode 93 is positioned opposite the second semiconductor region 7, the main body region 10, and the source region 11 through the second insulating film 92.

[0349] The second embedded electrode 93 has an electrode surface exposed from the second trench 91. The height position of the electrode surface relative to the first main surface 3 is located on the bottom wall side of the second trench 91. The depth position of the electrode surface relative to the bottom of the source region 11 is located on the first main surface 3 side. The electrode surface has a groove with a pointed shape recessed in its inner portion toward the bottom wall of the second trench 91.

[0350] Semiconductor device 1B includes multiple source-well regions 26 formed in the chip 2 (second semiconductor region 7) of active region 8, respectively, below multiple source structures 90. The source-well regions 26 may also be referred to as "second well regions," etc. A source potential is assigned to the source-well regions 26.

[0351] The source-well region 26 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the source-well region 26 can be higher or lower than the p-type impurity concentration of the main body region 10.

[0352] The p-type impurity concentration in the source well region 26 can be approximately equal to the p-type impurity concentration in the gate well region 25. The p-type impurity concentration in the source well region 26 can be higher or lower than the p-type impurity concentration in the gate well region 25. The preferred p-type impurity (trivalent element) in the source well region 26 is aluminum.

[0353] Multiple source-well regions 26 are formed, spaced apart in the horizontal direction (first direction X), in regions below (specifically directly below) the multiple source structures 90 within the second semiconductor region 7. The multiple source-well regions 26 are formed within a thickness range between the bottom of the second semiconductor region 7 and the bottom wall of the multiple source structures 90, overlapping the multiple source structures 90 in a one-to-one correspondence in the thickness direction.

[0354] Multiple source-well regions 26 extend in a strip-like pattern along the extension direction of their corresponding source structures 90 in the second direction Y when viewed from above. That is, the multiple source-well regions 26 are arranged in a stripe-like pattern extending along the second direction Y when viewed from above.

[0355] The extension direction of the plurality of source-well regions 26 is consistent with the offset direction of the SiC single crystal. Alternatively, the plurality of source-well regions 26 may extend in the first direction X, depending on the extension direction of the plurality of source structures 90. In this case, the plurality of source-well regions 26 intersect (specifically, are orthogonal to) the offset direction.

[0356] Multiple source-well regions 26 are formed at intervals from the periphery of the active region 8 toward the inward side. In the second direction Y, the two ends of the multiple source-well regions 26 may be located inside the multiple source structures 90 relative to the two ends of the multiple source structures 90, or they may be located at the periphery of the active region 8 relative to the two ends of the multiple source structures 90.

[0357] Multiple source-well regions 26 are formed spaced apart from the bottom of the second semiconductor region 7 toward the bottom wall side of the multiple source structures 90, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. The multiple source-well regions 26 each have an upper end located on the bottom wall side of the corresponding source structure 90 and a bottom located on the bottom side of the second semiconductor region 7.

[0358] The upper ends of the plurality of source-well regions 26 may also be connected to the bottom wall of the corresponding source structure 90. The upper ends of the plurality of source-well regions 26 may also extend along the side wall of the corresponding source structure 90 and be connected to the main body region 10. The upper ends of the plurality of source-well regions 26 may also be formed at intervals from the bottom wall of the corresponding source structure 90 toward the bottom side of the second semiconductor region 7.

[0359] The bottom of the plurality of source well regions 26 may be located on the bottom wall side of the plurality of source structures 90 relative to the middle part of the second semiconductor region 7, or it may be located on the bottom side (second main surface 4 side) of the second semiconductor region 7 relative to the middle part of the second semiconductor region 7.

[0360] Each of the multiple source-well regions 26 has a bulge 26a. The bulge 26a extends in an arc shape horizontally from the region directly below the corresponding source structure 90 to both sides of the corresponding source structure 90. Each of the multiple source-well regions 26 is formed into a pointed shape extending from the bulge 26a toward the bottom.

[0361] The source well region 26 may also have a width approximately equal to that of the gate well region 25. The width of the source well region 26 may be greater than or less than the width of the gate well region 25. The width of the source well region 26 may be greater than or less than the width of the source structure 90.

[0362] The width of the source-well region 26 can be greater than 0.1 μm and less than 2 μm. The width of the source-well region 26 can have a value belonging to at least one of the following ranges: greater than 0.1 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, and greater than 1.75 μm and less than 2 μm.

[0363] The source well region 26 may also have a depth approximately equal to that of the gate well region 25. That is, the bottom of the source well region 26 may also be at a depth approximately equal to that of the bottom of the gate well region 25. The depth of the source well region 26 is the depth of the source well region 26 relative to the bottom wall of the source structure 90. The depth of the source well region 26 may be greater than or less than the depth of the gate well region 25.

[0364] The depth of the source-well region 26 can be greater than 0 μm and less than 5 μm. The depth of the source-well region 26 can have a value belonging to at least one of the following ranges: greater than 0 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, greater than 1.5 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, greater than 3.5 μm and less than 4 μm, greater than 4 μm and less than 4.5 μm, and greater than 4.5 μm and less than 5 μm.

[0365] The source-well region 26 can also have an aspect ratio greater than 0 and less than 2. The aspect ratio of the source-well region 26 is the ratio of the depth of the source-well region 26 to the width of the source-well region 26.

[0366] The aspect ratio can have a value that is greater than 0 and less than 0.25, greater than 0.25 and less than 0.5, greater than 0.5 and less than 0.75, greater than 0.75 and less than 1, greater than 1 and less than 1.25, greater than 1.25 and less than 1.5, greater than 1.5 and less than 1.75, and greater than 1.75 and less than 2.

[0367] The spacing between the central portion of the source-well region 26 and the central portion of the gate-well region 25 (the spacing of the source-well regions 26) is approximately equal to the spacing between the source structure 90 and the gate structure 15. The spacing of the source-well regions 26 can be greater than 0.1 μm and less than 2.5 μm.

[0368] The spacing of the source-well regions 26 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, and 2.25 μm or more and 2.5 μm or less.

[0369] The source-well region 26 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the source-well region 26 extends the depletion layer into the second semiconductor region 7. The depletion layer originating from the source-well region 26 extends in both the horizontal and thickness directions, mitigating the electric field on the active region 8 (source structure 90). The depletion layer originating from the source-well region 26 is integrated with the depletion layer originating from the gate-well region 25.

[0370] Semiconductor device 1B includes a plurality of source contact regions 28 formed within chip 2 (second semiconductor region 7). The source contact regions 28 may also be referred to as "second contact regions," etc. A source potential is assigned to the source contact regions 28.

[0371] The source contact region 28 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the source contact region 28 is higher than the p-type impurity concentration of the main region 10.

[0372] The p-type impurity concentration in the source contact region 28 is higher than that in the source-well region 26. The p-type impurity concentration in the source contact region 28 can also be approximately equal to that in the gate contact region 27. The p-type impurity concentration in the source contact region 28 can be either higher or lower than that in the gate contact region 27.

[0373] Multiple source contact regions 28 are formed at intervals along the regions of the multiple source structures 90, spaced apart from the multiple gate structures 15. The multiple source contact regions 28 have a planar layout different from the planar layout of the multiple gate contact regions 27. In this manner, the multiple source contact regions 28 are formed in a one-to-one correspondence with the multiple source structures 90.

[0374] Multiple source contact regions 28 extend in a strip-like manner along the extension direction of the corresponding source structure 90 in the second direction Y. That is, when viewed from above, the multiple source contact regions 28 are formed as stripes extending along the multiple source structures 90.

[0375] The multiple source contact regions 28 have a length greater than the length of the multiple gate contact regions 27 in the second direction Y, and traverse the multiple gate contact regions 27 in the second direction Y. In the second direction Y, the multiple source contact regions 28 may have a length greater than the length of the multiple source structures 90, or a length less than the length of the multiple source structures 90.

[0376] The plurality of source contact regions 28 preferably have a total planar area larger than the total planar area of ​​the plurality of gate contact regions 27. The total planar area of ​​the plurality of source contact regions 28 may be larger than or smaller than the channel area.

[0377] The multiple source contact regions 28 can also be formed in a one-to-many correspondence with respect to the multiple source structures 90, similar to the multiple gate contact regions 27. In this case, with respect to one and the other source structures 90, the multiple gate contact regions 27 along one source structure 90 can also be opposite to the multiple source contact regions 28 along the other source structure 90 in the first direction X when viewed from above.

[0378] In other words, the multiple source contact regions 28 can also be arranged in a matrix with intervals along the first direction X and the second direction Y when viewed from above. The multiple source contact regions 28 of one side can also be opposite to the multiple source contact regions 28 of the other side in the first direction X when viewed from above. That is, the multiple source contact regions 28 can also be arranged in an alternating pattern with intervals along the first direction X and the second direction Y when viewed from above.

[0379] Multiple source contact regions 28 are located between the bottom wall of the corresponding source structure 90 and the bottom of the corresponding source well region 26. The multiple source contact regions 28 are respectively connected to the bottom wall of the corresponding source structure 90 and the corresponding source well region 26.

[0380] Multiple source contact regions 28 increase the p-type impurity concentration at the upper end of the corresponding source trap region 26. The multiple source contact regions 28 have extensions that extend from the region directly below the source structure 90 to both sides of the source structure 90 and along the sidewalls of the source structure 90.

[0381] The thickness of the portion (extension) of the source contact region 28 along the sidewall of the source structure 90 in the horizontal direction (first direction X) may also be less than the thickness of the portion of the source contact region 28 along the bottom wall of the source structure 90 in the vertical direction Z.

[0382] The extension of the source contact region 28 is electrically connected to the main body region 10 on the surface of the first main surface 3, thereby electrically connecting the corresponding source-well region 26 to the main body region 10. This suppresses the source-well region 26 from becoming electrically floating, thus improving the electrical response characteristics of the source-well region 26.

[0383] The source contact region 28 has an upper end portion exposed from the first main surface 3. In this configuration, the upper end portion of the source contact region 28 is exposed from the sidewall of the second trench 91 at the opening end of the second trench 91. The upper end portion of the source contact region 28 may also extend horizontally in the surface portion of the main body region 10.

[0384] The upper end of the source contact region 28 is electrically connected to the upper ends of a plurality of adjacent gate contact regions 27 within the main body region 10. In this manner, the upper ends of the source contact region 28 and the upper ends of the gate contact regions 27 are integrally formed.

[0385] Semiconductor device 1B includes one or more (in this case, multiple) trench-type (trench electrode type) discrete structures 30 formed in the active region 8 on the first main surface 3. The discrete structure 30 may also be referred to as a "trench structure", "third trench structure", "dummy structure", etc.

[0386] The number of discrete structures 30 is arbitrary. The number of discrete structures 30 can be more than one and less than 15. The number of discrete structures 30 can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. Typically, the number of discrete structures 30 is more than one and less than ten. In this embodiment, as an example, the semiconductor device 1B includes five discrete structures 30.

[0387] At least one or all of the plurality of separation structures 30 may be configured as electrically floating. A source potential may also be assigned to at least one or all of the plurality of separation structures 30. The plurality of separation structures 30 may also include one or more separation structures 30 configured as electrically floating, and one or more separation structures 30 assigned a source potential.

[0388] Multiple separation structures 30 are formed at intervals on the inner portion of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D). The multiple separation structures 30 define an active region 8 on the inner side of the first main surface 3 and an outer peripheral region 9 on the periphery side of the first main surface 3. The active region 8 is located on the inner side of the outermost separation structure 30A (the terminal separation structure 30A), and the outer peripheral region 9 is located on the outer side of the terminal separation structure 30A.

[0389] Multiple discrete structures 30 are spaced apart from multiple gate structures 15 and multiple source structures 90 and disposed at intervals on the periphery of the active region 8. The multiple discrete structures 30 are arranged at intervals and are adjacent to each other in the horizontal direction, separated by a portion of the chip 2. The multiple discrete structures 30 extend in a strip shape along the periphery of the first main surface 3. The multiple discrete structures 30 have portions extending along a first direction X and portions extending along a second direction Y.

[0390] That is, the plurality of discrete structures 30 have portions extending in the extension direction (second direction Y) of the plurality of gate structures 15 (the plurality of source structures 90), and portions extending in the direction (first direction X) intersecting the extension direction of the plurality of gate structures 15 (the plurality of source structures 90). The plurality of discrete structures 30 may also be formed as a polygonal ring (quadrilateral ring) that surrounds the plurality of gate structures 15 and the plurality of source structures 90 when viewed from above.

[0391] Multiple separation structures 30 are formed in the region outside the source region 11, penetrating only the main body region 10. Multiple separation structures 30 may also penetrate the source region 11. Multiple separation structures 30 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first main surface 3, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7.

[0392] Multiple separation structures 30 may be formed at intervals from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3, or they may be located at the bottom side of the second semiconductor region 7 relative to the depth position in the middle of the second semiconductor region 7. The multiple separation structures 30 are formed substantially perpendicular to the first main surface 3. The multiple separation structures 30 may also be formed into a pointed shape facing the bottom of the second semiconductor region 7.

[0393] The sidewalls of the plurality of separated structures 30 are formed by the m-plane ((1-100) plane) and the a-plane ((11-20) plane) of the SiC single crystal. The bottom wall of the plurality of separated structures 30 is formed by the c-plane (Si plane) of the SiC single crystal. The bottom wall of the plurality of separated structures 30 preferably extends in a generally flat manner along the horizontal direction. The bottom wall of the plurality of separated structures 30 may also be curved into an arc shape toward the second main surface 4.

[0394] The inclination angle (absolute value) of the sidewall of the separation structure 30, based on a vertical line, can also be 85° or more and 95° or less. The inclination angle can have a value belonging to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0395] The separation structure 30 may also have a width approximately equal to the width of the gate structure 15. The width of the separation structure 30 may be greater than or less than the width of the gate structure 15. The width of the separation structure 30 may be approximately equal to the width of the source structure 90. The width of the separation structure 30 may be greater than or less than the width of the source structure 90.

[0396] The width of the separation structure 30 can be greater than 0.1 μm and less than 2 μm. The width of the separation structure 30 can have a value belonging to at least one of the following ranges: greater than 0.1 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, and greater than 1.75 μm and less than 2 μm.

[0397] The separation structure 30 may also have a depth greater than that of the gate structure 15. The depth of the separation structure 30 is the depth relative to the first main surface 3. The depth of the separation structure 30 may be greater than or less than the depth of the gate structure 15. In this case, the depth of the separation structure 30 is approximately equal to the depth of the gate structure 15.

[0398] The separation structure 30 may also have a depth greater than or equal to that of the source structure 90. The depth of the separation structure 30 may be greater than or less than the depth of the source structure 90. In this embodiment, the depth of the separation structure 30 is approximately equal to the depth of the source structure 90.

[0399] The ratio (depth ratio) of the depth of the separation structure 30 to the depth of the gate structure 15 (source structure 90) can be 0.8 or more and 1.2 or less. The depth ratio can have a value belonging to at least one of the following ranges: 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.15 or less, and 1.15 or more and 1.2 or less. The depth ratio is preferably 0.95 or more and 1.05 or less.

[0400] The depth of the separation structure 30 can be 0.1 μm or more and 3 μm or less. The depth of the separation structure 30 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the separation structure 30 is 0.5 μm or more and 1.5 μm or less.

[0401] The separation structure 30 may have an aspect ratio of 1 or more and 3 or less. The aspect ratio of the separation structure 30 is the ratio of the depth of the separation structure 30 to the width of the separation structure 30. The aspect ratio may have a value belonging to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 3 or less. The aspect ratio is preferably 1.5 or more and 2.5 or less.

[0402] The spacing between the central portions of the plurality of discrete structures 30 (the spacing between the discrete structures 30) is preferably smaller than the spacing between the gate structure 15 and the source structure 90. The spacing between the plurality of discrete structures 30 may also be larger than the spacing between the gate structure 15 and the source structure 90.

[0403] The spacing of the separation structure 30 can be greater than 0.1 μm and less than 2.5 μm. The spacing of the separation structure 30 can have a value belonging to at least one of the following ranges: greater than 0.1 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, greater than 1.75 μm and less than 2 μm, greater than 2 μm and less than 2.25 μm, and greater than 2.25 μm and less than 2.5 μm.

[0404] The multiple separation structures 30 each include a third trench 31, a third insulating film 32, and a third embedded electrode 33. The third trench 31 is formed on the first main surface 3, dividing the walls (side walls and bottom walls) of the separation structure 30. The third trench 31 is a boundary trench forming the boundary portion 19 between the active region 8 and the outer peripheral region 9. The terminal separation structure 30A includes a terminal third trench 31A, a terminal third insulating film 32A, and a terminal third embedded electrode 33A. The terminal third trench 31A among the multiple third trenches 31 can also be a boundary trench.

[0405] The third insulating film 32 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the third insulating film 32 comprises the same insulating material as the insulating material of the first insulating film 17 (second insulating film 92). In this configuration, the third insulating film 32 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the third insulating film 32 comprises a silicon oxide film composed of the oxide of the chip 2.

[0406] The third insulating film 32 covers the wall of the third trench 31. The third insulating film 32 includes a first film portion and a second film portion. The first film portion covers the sidewall of the third trench 31 in a film-like manner. The second film portion covers the bottom wall of the third trench 31 in a film-like manner and is connected to the first film portion.

[0407] The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion can be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the third insulating film 32 can also be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the third insulating film 32 can also be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0408] The third insulating film 32 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the third insulating film 32 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0409] The third buried electrode 33 is buried in the third trench 31 through the third insulating film 32. The third buried electrode 33 may also include either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the third buried electrode 33 includes the same conductive material as the first buried electrode 18. The third buried electrode 33 is opposite to the second semiconductor region 7 and the main body region 10 through the third insulating film 32. The third buried electrode 33 may also have a portion opposite to the source region 11.

[0410] The third embedded electrode 33 has an electrode surface exposed from the third trench 31. The height position of the electrode surface relative to the first main surface 3 is located on the bottom wall side of the third trench 31. The depth position of the electrode surface relative to the bottom of the source region 11 is located on the first main surface 3 side. The electrode surface has a groove with a pointed shape recessed in its inner portion toward the bottom wall of the third trench 31.

[0411] Semiconductor device 1B includes one or more (in this case, four) separate well regions 35 formed within chip 2 (second semiconductor region 7). The separate well regions 35 may also be referred to as "third well region," "first separate well region," etc. The separate well regions 35 are assigned a source potential. The number of separate well regions 35 is less than the number of separation structures 30.

[0412] The separation well region 35 has a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the separation well region 35 can be higher or lower than the p-type impurity concentration of the main body region 10.

[0413] The p-type impurity concentration in the split well region 35 can be approximately equal to the p-type impurity concentration in the gate well region 25. The p-type impurity concentration in the split well region 35 can be higher or lower than the p-type impurity concentration in the gate well region 25.

[0414] The p-type impurity concentration in the separation well region 35 can be approximately equal to that in the source well region 26. The p-type impurity concentration in the separation well region 35 can be higher or lower than that in the source well region 26. The preferred p-type impurity (trivalent element) in the separation well region 35 is aluminum.

[0415] Multiple separation well regions 35 are formed in the second semiconductor region 7 in a horizontally adjacent manner in the regions below (specifically directly below) the multiple separation structures 30. The multiple separation well regions 35 are formed in the regions below the multiple (in this case, four) separation structures 30 located on the side of the active region 8.

[0416] Multiple separation well regions 35 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom wall of the multiple separation structures 30, and overlap with the multiple separation structures 30 in a one-to-one correspondence in the thickness direction.

[0417] Multiple separation trap regions 35 extend in a strip shape along the corresponding separation structure 30 when viewed from above. Each separation trap region 35 has a portion extending along the corresponding separation structure 30 in a first direction X and a portion extending along the corresponding separation structure 30 in a second direction Y when viewed from above. In this configuration, the multiple separation trap regions 35 extend in a polygonal ring shape (in this configuration, a quadrilateral ring shape) along the corresponding separation structure 30 when viewed from above.

[0418] Multiple split-well regions 35 are formed horizontally spaced apart from multiple gate well regions 25 and multiple source well regions 26. In this configuration, the multiple split-well regions 35 are interconnected horizontally. Alternatively, the multiple split-well regions 35 may be formed horizontally spaced apart and horizontally opposed to each other across a portion of the second semiconductor region 7.

[0419] Multiple separation well regions 35 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall side of the multiple separation structures 30, and are opposite to the first semiconductor region 6 across a portion of the second semiconductor region 7. The multiple separation well regions 35 each have an upper end located on the bottom wall side of the corresponding separation structure 30 and a bottom located on the bottom side of the second semiconductor region 7.

[0420] The upper ends of the plurality of separation well regions 35 may also be connected to the bottom wall of the corresponding separation structure 30. The upper ends of the plurality of separation well regions 35 may also extend along the side wall of the corresponding separation structure 30 and be connected to the main body region 10. The upper ends of the plurality of separation well regions 35 may also be formed at intervals from the bottom wall of the corresponding separation structure 30 toward the bottom side of the second semiconductor region 7.

[0421] The bottom of the multiple separation well regions 35 can be located on the bottom wall side of the corresponding separation structure 30 relative to the middle part of the second semiconductor region 7, or it can be located on the bottom side (second main surface 4 side) of the second semiconductor region 7 relative to the middle part of the second semiconductor region 7.

[0422] Each of the multiple separation trap regions 35 has a bulge 35a. The bulge 35a extends in an arc shape from the region directly below the corresponding separation structure 30 to both sides of the corresponding separation structure 30 in a horizontal direction. The multiple bulges 35a are interconnected in the horizontal direction. The multiple separation trap regions 35 are each formed into a pointed shape from the bulge 35a toward the bottom.

[0423] The separated well region 35 may have a width greater than or less than the width of the separated structure 30. The width of the separated well region 35 may be greater than or less than the width of the gate structure 15. The width of the separated well region 35 may be greater than or less than the width of the source structure 90.

[0424] The width of the split-well region 35 can also be approximately equal to the width of the gate well region 25. The width of the split-well region 35 can be greater than or less than the width of the gate well region 25. The width of the split-well region 35 can also be approximately equal to the width of the source well region 26. The width of the split-well region 35 can be greater than or less than the width of the source well region 26.

[0425] The width of the separation trap region 35 can be greater than 0.1 μm and less than 2 μm. The width of the separation trap region 35 can have a value belonging to at least one of the following ranges: greater than 0.1 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, and greater than 1.75 μm and less than 2 μm.

[0426] The separation well region 35 may also have a depth approximately equal to that of the gate well region 25. The depth of the separation well region 35 is the depth of the separation well region 35 relative to the bottom wall of the separation structure 30. The bottom of the separation well region 35 may also be at a depth approximately equal to that of the bottom of the gate well region 25. The depth of the separation well region 35 may be greater than or less than the depth of the gate well region 25.

[0427] The depth of the separation well region 35 can also be approximately equal to the depth of the source well region 26. The bottom of the separation well region 35 can also be located at a depth approximately equal to the bottom of the source well region 26. The depth of the separation well region 35 can be greater than the depth of the source well region 26, or it can be less than the depth of the source well region 26.

[0428] The depth of the separation trap region 35 can be greater than 0 μm and less than 5 μm. The depth of the separation trap region 35 can have a value belonging to at least one of the following ranges: greater than 0 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, greater than 1.5 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, greater than 3.5 μm and less than 4 μm, greater than 4 μm and less than 4.5 μm, and greater than 4.5 μm and less than 5 μm.

[0429] The separation trap region 35 can also have an aspect ratio greater than 0 and less than 2. The aspect ratio of the separation trap region 35 is the ratio of the depth of the separation trap region 35 to the width of the separation trap region 35.

[0430] The aspect ratio can have a value that is greater than 0 and less than 0.25, greater than 0.25 and less than 0.5, greater than 0.5 and less than 0.75, greater than 0.75 and less than 1, greater than 1 and less than 1.25, greater than 1.25 and less than 1.5, greater than 1.5 and less than 1.75, and greater than 1.75 and less than 2.

[0431] The spacing between the central portions of the plurality of split-well regions 35 (the spacing of the split-well regions 35) is approximately equal to the spacing between the plurality of split structures 30. In this configuration, the spacing of the split-well regions 35 is smaller than the spacing between the gate structure 15 and the source structure 90. The spacing of the split-well regions 35 can be approximately equal to or larger than the spacing between the gate structure 15 and the source structure 90.

[0432] In this configuration, the spacing of the split-well regions 35 is smaller than the spacing of the gate well region 25 and the source well region 26. The spacing of the split-well regions 35 can be approximately equal to or larger than the spacing of the gate well region 25 and the source well region 26.

[0433] The spacing of the separation trap regions 35 can be greater than 0.1 μm and less than 2.5 μm. The spacing of the separation trap regions 35 can have a value belonging to at least one of the following ranges: greater than 0.1 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, greater than 1.75 μm and less than 2 μm, greater than 2 μm and less than 2.25 μm, and greater than 2.25 μm and less than 2.5 μm.

[0434] The depletion well region 35 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the depletion well region 35 extends the depletion layer into the second semiconductor region 7. The depletion layer originating from the depletion well region 35 extends in both the horizontal and thickness directions and integrates with the depletion layer originating from the main body region 10 (the inner portion of the active region 8). The depletion well region 35 causes the depletion layer originating from the main body region 10 to extend towards the periphery of the first main surface 3, mitigating the electric field in the plurality of separation structures 30 (the periphery of the active region 8).

[0435] Semiconductor device 1B includes one or more (five in this embodiment) discrete contact regions 37 formed within chip 2 (second semiconductor region 7). The discrete contact regions 37 may also be referred to as "third contact regions," etc. A source potential is assigned to the discrete contact regions 37. The discrete contact regions 37 have a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the discrete contact regions 37 is higher than the p-type impurity concentration of the main region 10.

[0436] The p-type impurity concentration in the separation contact region 37 is higher than that in the separation well region 35. The p-type impurity concentration in the separation contact region 37 is higher than that in the gate well region 25. The p-type impurity concentration in the separation contact region 37 is higher than that in the source well region 26.

[0437] The p-type impurity concentration in the separation contact region 37 can also be approximately equal to the p-type impurity concentration in the gate contact region 27. The p-type impurity concentration in the separation contact region 37 can be either higher or lower than the p-type impurity concentration in the gate contact region 27.

[0438] The p-type impurity concentration in the separation contact region 37 can also be approximately equal to the p-type impurity concentration in the source contact region 28. The p-type impurity concentration in the separation contact region 37 can be higher or lower than the p-type impurity concentration in the source contact region 28.

[0439] Multiple separation contact regions 37 are formed in regions of multiple separation structures 30 along the separation well region 35. The multiple separation contact regions 37 are spaced apart from each other in the regions between the multiple separation structures 30 and are opposite each other across a portion of the second semiconductor region 7. The multiple separation contact regions 37 may also be interconnected in the regions between the multiple separation structures 30.

[0440] Multiple separation contact regions 37 are formed separately from multiple gate structures 15 and multiple source structures 90. The multiple separation contact regions 37 are formed in a one-to-one correspondence with the multiple separation structures 30. The multiple separation contact regions 37 are located in regions between the bottom wall of the corresponding separation structure 30 and the bottom of the corresponding separation well region 35, and extend in a strip shape along the corresponding separation structure 30.

[0441] The plurality of separation contact areas 37 each have a portion extending along the corresponding separation structure 30 in a first direction X when viewed from above, and a portion extending along the corresponding separation structure 30 in a second direction Y. In this manner, the plurality of separation contact areas 37 extend along the corresponding separation structure 30 in a polygonal ring shape (in this manner, a quadrilateral ring shape) when viewed from above.

[0442] Multiple separation contact areas 37 may also be formed at intervals along the extension direction of the corresponding separation structure 30. In this case, the multiple separation contact areas 37 may also extend in a strip shape along the extension direction of the corresponding separation structure 30.

[0443] Multiple separation contact regions 37 are respectively connected to the bottom wall of the corresponding separation structure 30 and the corresponding separation trap region 35. The multiple separation contact regions 37 increase the p-type impurity concentration at the upper end of the corresponding separation trap region 35. Each of the multiple separation contact regions 37 has an extension that extends from the region directly below the separation structure 30 to both sides of the separation structure 30 and extends along the side wall of the corresponding separation structure 30.

[0444] The thickness of the portion (extension) along the sidewall of the separation structure 30 in the plurality of separation contact areas 37 in the horizontal direction (first direction X) may also be less than the thickness of the portion along the bottom wall of the separation structure 30 in the vertical direction Z of the plurality of separation contact areas 37.

[0445] The extensions of the multiple separation contact regions 37 are electrically connected to the main body region 10 on the surface of the first main surface 3, thereby electrically connecting the corresponding separation trap region 35 to the main body region 10. This suppresses the possibility of the multiple separation trap regions 35 becoming electrically floating, thereby improving the electrical response characteristics of the multiple separation trap regions 35.

[0446] Each of the multiple separation contact areas 37 has an upper end exposed from the first main surface 3. In this manner, the upper ends of the multiple separation contact areas 37 are exposed from the sidewall of the third groove 31 at the opening end of the third groove 31.

[0447] The upper ends of the plurality of separate contact areas 37 may also extend horizontally on the surface of the main body region 10. The upper ends of the plurality of separate contact areas 37 are electrically connected to each other within the main body region 10. In this manner, the upper ends of the plurality of separate contact areas 37 are integrally formed within the main body region 10.

[0448] The first outer well region 42 is formed along the outer peripheral boundary 19 and is deeper than the separation well region 35. Alternatively, the first outer well region 42 may also be at approximately the same depth as the separation well region 35.

[0449] Along the horizontal direction of the first main surface 3, the first outer trap region 42 at least partially covers the separation trap region 35 of the end third trench 31A.

[0450] More specifically, the separation well region 35 includes a well side portion (in this case, a bulge 35a) extending in the thickness direction of the second semiconductor region 7 and a well bottom portion 35b extending from the bulge 35a in a direction along the first main surface 3. The first outer well region 42 selectively covers the bulge 35a on the outer peripheral region 9 side (outer side) of the separation well region 35 at the end of the third trench 31A. The bulge 35a on the active region 8 side (inner side) not covered by the first outer well region 42 and the well bottom portion 35b are covered by the second semiconductor region 7 (in this case, a cap region 72).

[0451] The outer contact region 41 extends in a strip shape along the end separation structure 30A in the second direction Y. In this configuration, the inner edge of the outer contact region 41 is connected to the end separation structure 30A. In this configuration, the inner edge of the outer contact region 41 is connected to the separation well region 35 of the end third trench 31A. The inner edge of the outer contact region 41 extends along the end separation structure 30A (outer peripheral boundary 19) in the thickness direction of the second semiconductor region 7 and is connected to the separation well region 35 of the end third trench 31A. The first outer well region 42 is electrically connected to the main body region 10 via the separation well region 35 of the end third trench 31A.

[0452] Semiconductor device 1B includes an external wiring 46 disposed on a main surface insulating film 45 in the outer peripheral region 9. The external wiring 46 may also be referred to as "wiring," "main wiring," "peripheral wiring," "side wiring," etc. The external wiring 46 may also include either or both of p-type and n-type conductive polysilicon. Preferably, the external wiring 46 has the same type of conductive material (conductivity type) as at least one of the first buried electrode 18, the second buried electrode 93, and the third buried electrode 33.

[0453] The external wiring 46 is arranged in the outer peripheral region 9 at intervals from the periphery of the first main surface 3 toward the active region 8. The external wiring 46 is disposed on the outer well region 40 (first outer well region 42) and is opposite to the first outer well region 42 through the main surface insulating film 45.

[0454] When viewed from above, the external wiring 46 extends in a strip along the periphery of the first main surface 3 (the periphery of the active region 8) in the extension direction of the first outer sink region 42. The external wiring 46 has a portion extending along a first direction X and a portion extending along a second direction Y.

[0455] In this configuration, the external wiring 46 is formed as a polygonal ring (in this configuration, a quadrilateral ring) with four sides parallel to the periphery of the chip 2 when viewed from above, surrounding the inner square portion (active region 8) of the first main surface 3. The external wiring 46 may also have an edge portion that connects the portion extending along the first direction X and the portion extending along the second direction Y into an arc shape (preferably a quarter arc shape). The external wiring 46 may also be an end shape or a ring shape.

[0456] The external wiring 46 has an inner edge portion on the inner square side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the external wiring 46 extends from the outer peripheral region 9 into the active region 8. The inner edge portion of the external wiring 46 covers one or more separation structures 30 and is connected to one or more separation structures 30.

[0457] In this manner, the inner edge of the outer wiring 46 covers the end separation structure 30A and is connected to the third embedded electrode 33 of the end separation structure 30A.

[0458] The external wiring 46 may also be connected to at least one or all of the plurality of separation structures 30 used in the separation trap region 35. The external wiring 46 is integrally formed with the third embedded electrode 33 of the separation structure 30. That is, the external wiring 46 is formed as the lead-out portion of the third embedded electrode 33 and is wound onto the main surface insulating film 45.

[0459] The outer edge of the outer wiring 46 is formed spaced inward from the outer edge of the first outer well region 42. In this configuration, the outer edge of the outer wiring 46 is arranged spaced inward from the outer edge of the outer contact region 41, and has a portion that faces the outer contact region 41 across the main surface insulating film 45. The outer edge of the outer wiring 46 may also have a portion that faces the first outer well region 42 in the stacking direction.

[0460] Semiconductor device 1B includes a plurality of gate openings 48 formed in the interlayer film 47 in the active region 8 (see reference). Figure 22 Multiple gate openings 48 are formed in a one-to-many correspondence with respect to a corresponding gate structure 15. In this manner, the multiple gate openings 48 penetrate the interlayer film 47, exposing one end or the other end of the multiple gate structures 15 (first buried electrode 18). Figure 22 The configuration of the gate opening 48 relative to the gate structure 15 shown can also be applied to Figure 3 Gate structure 15.

[0461] The multiple gate openings 48 may also each have an opening end that is bent into an arc shape. The multiple gate openings 48 may also be formed into a quadrilateral shape, a rectangular shape (strip) extending along the first direction X, a rectangular shape (strip) extending along the second direction Y, a circular shape, etc. when viewed from above. The multiple gate openings 48 may also each have an opening end that is bent into an arc shape.

[0462] Semiconductor device 1B includes a plurality of source openings 49 formed in an interlayer film 47 in an active region 8. The plurality of source openings 49 are formed in a portion of the interlayer film 47 covering the active region 8. The plurality of source openings 49 are formed in a one-to-one correspondence with the plurality of source structures 90 in a region between the plurality of gate structures 15. The plurality of source openings 49 extend in a strip shape along the corresponding source structure 90 in a second direction Y.

[0463] Multiple source openings 49 penetrate the main insulating film 45 and the interlayer film 47, exposing a corresponding source structure 90, source region 11, multiple gate contact regions 27, and multiple source contact regions 28. The multiple source openings 49 may also each have an opening end bent into an arc shape.

[0464] Multiple source openings 49 can also be formed in a one-to-many correspondence with a corresponding source structure 90. In this case, multiple source openings 49 can also be formed at intervals along a corresponding source structure 90. In addition, in this case, multiple source openings 49 can also be formed in a quadrilateral shape, a rectangular shape (strip shape), a circular shape, etc. when viewed from above.

[0465] Figure 28 This is a cross-sectional view of the main part of the semiconductor device 1C according to the third embodiment of this disclosure. Figure 28 Indicates and Figure 11 The cut surface at the same location.

[0466] Reference Figure 28 The semiconductor device 1C has a modified configuration of the plurality of gate structures 15 of the semiconductor device 1A. More specifically, the semiconductor device 1C has a gate structure 100, which is an example of a planar gate structure, instead of the gate structure 15, which is an example of a trench gate structure.

[0467] Before describing the gate structure 100, the semiconductor device 1C includes a plurality of p-type main regions 101 formed in the surface portion of the first main surface 3 in the active region 8. The plurality of main regions 101 are arranged at intervals in the first direction X and are respectively formed as strips extending in the second direction Y. That is, the plurality of main regions 101 are arranged as stripes extending along the second direction Y.

[0468] Multiple main body regions 101 are formed spaced apart from the bottom of the first semiconductor region 6 toward the first main surface 3, and are opposite to the second semiconductor region 7 with a portion of the first semiconductor region 6 between them. Preferably, the multiple main body regions 101 are formed spaced apart from the middle portion of the first semiconductor region 6 toward the first main surface 3. The multiple main body regions 101 are exposed from the first main surface 3. In this configuration, the multiple main body regions 101 are formed spaced apart from the bottom of the cap region 72 toward the first main surface 3, and are opposite to the base region 71 with a portion of the cap region 72 between them.

[0469] Semiconductor device 1C includes n-type source regions 102 formed on the surface portions of multiple body regions 101. The source regions 102 have a higher n-type impurity concentration than the n-type impurity concentration of the first semiconductor region 6. The source regions 102 are given a source potential.

[0470] The source region 102 has an upper surface 102a exposed from the first main surface 3 of the active region 8. The upper surface 12a of the field cutoff region 12 and the upper surface 102a of the source region 102 are configured at the same height. That is, no height difference is formed between the upper surface 12a and the upper surface 102a.

[0471] Semiconductor device 1C includes a plurality of p-type channel regions 103 formed on the surface portion of a first main surface 3. The plurality of channel regions 103 are respectively divided into regions between the ends of the plurality of main body regions 101 and the periphery of the source region 102 on the surface portion of the plurality of main body regions 101. In this manner, the plurality of channel regions 103 are arranged at intervals in a first direction X, and are respectively formed as stripes extending in a second direction Y. That is, the plurality of channel regions 103 are arranged as stripes extending along the second direction Y.

[0472] A gate structure 100 is disposed on at least one channel region 103. In this manner, each gate structure 100 is configured to traverse two adjacent main regions 101, covering multiple channel regions 103. Specifically, each gate structure 100 is configured to traverse a source region 102 on one side of a main region 101 and a source region 102 on the other side of a main region 101, covering a portion of the source region 102 and the channel region 103.

[0473] The gate structure 100 has a stacked structure including an insulating film 104 and a gate electrode 105. The insulating film 104 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 104 has a single-layer structure composed of a silicon oxide film. The insulating film 104 is particularly preferably a silicon oxide film composed of an oxide of the chip 2.

[0474] An insulating film 104 covers the first main surface 3 in a film-like manner and is disposed on at least one channel region 103. In this manner, the insulating film 104 is disposed across two adjacent main regions 101, covering a plurality of channel regions 103.

[0475] Specifically, the insulating film 104 is configured to span the source region 102 on one side of the main body region 101 and the source region 102 on the other side of the main body region 101, covering a portion of the source region 102 and the channel region 103.

[0476] The thickness of the insulating film 104 can also be 10 nm or more and 150 nm or less. The thickness of the insulating film 104 can be within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. Preferably, the thickness of the insulating film 104 is 25 nm or more and 75 nm or less.

[0477] A gate electrode 105 is disposed on an insulating film 104 and faces at least one channel region 103 across the insulating film 104. A gate potential, serving as a control potential, is applied to the gate electrode 105. The gate electrode 105 controls the inversion and non-inversion of at least one channel region 103 in response to the gate potential.

[0478] The gate electrode 105 comprises a conductive polysilicon semiconductor. The gate electrode 105 may also comprise either or both of p-type and n-type conductive polysilicon. The conductivity type of the gate electrode 105 is adjusted according to the desired gate threshold voltage. The gate electrode 105 may also be referred to as a "polysilicon gate," "polysilicon gate," etc.

[0479] Semiconductor device 1C includes a second cap region 106 stacked on cap region 72. The second cap region 106 is part of a second semiconductor region 7. That is, the second semiconductor region 7 of semiconductor device 1C includes a stacked structure of base region 71, cap region 72, and second cap region 106.

[0480] The second cap region 106 is formed on the side of the main body region 101 between the cap region 72 and the first main surface 3. The second cap region 106 is in contact with the main body region 101 and is formed as a layer extending along the first main surface 3. The main body region 101 traverses the boundary between the cap region 72 and the second cap region 106 in the thickness direction of the second semiconductor region 7, and contacts both sides of the cap region 72 and the second cap region 106.

[0481] The thickness of the second cap region 106 can also be 0.1 μm or more and 1.0 μm or less. Preferably, the thickness of the second cap region 106 is 0.1 μm or more and 0.5 μm or less.

[0482] The n-type impurity concentration in the second cap region 106 is preferably lower than that in the cap region 72. Alternatively, the n-type impurity concentration in the second cap region 106 can be the same as that in the base region 71. The second cap region 106 can also have a concentration of 1 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 The following n-type impurity concentration is taken as the peak value. The n-type impurity concentration in the second cap region 106 can also be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the second cap region 106 can also have a concentration gradient that gradually increases and / or decreases towards the thickness direction (crystal growth direction) of the chip 2.

[0483] In this manner, the n-type impurity concentration of the second cap region 106 is adjusted by nitrogen. The second cap region 106 may also have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second cap region 106 can also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0484] Figure 29 This is a cross-sectional view of the main part of the semiconductor device 1D according to the fourth embodiment of this disclosure. Figure 29 Indicates and Figure 11 The cut surface at the same location.

[0485] Reference Figure 29 The semiconductor device 1D has a structure in which a superjunction structure is incorporated into the semiconductor device 1C.

[0486] Semiconductor device 1D includes a plurality of p-type first pillar regions 108 formed in an active region 8 within a second semiconductor region 7. The first pillar regions 108 may also be referred to as "first pillar layer," "first column layer (region)," "p-type layer (region)," "p-type region," etc. The plurality of first pillar regions 108 are formed at horizontal intervals within the second semiconductor region 7, dividing a plurality of n-type second pillar regions 109, each formed by a portion of the second semiconductor region 7. In this configuration, the plurality of second pillar regions 109 are formed by cap regions 72. The second pillar regions 109 may also be referred to as "second pillar layer," "second column layer (region)," "n-type layer (region)," "n-type region," etc.

[0487] Multiple first pillar regions 108 form a superjunction structure SJ with multiple second pillar regions 109 within the second semiconductor region 7.

[0488] The multiple first column regions 108 can have a higher or lower p-type impurity concentration than the main region 101. The multiple first column regions 108 can also have a concentration of 1×10⁻⁶. 16 cm -3 Above and 1×10 18 cm -3 The following p-type impurity concentration is taken as the peak value. The p-type impurity concentration of the first column region 108 is preferably adjusted by at least one trivalent element. The p-type impurity concentration of the first column region 108 is particularly preferably adjusted by a trivalent element that is a heavier element than carbon. That is, the first column region 108 preferably includes a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this manner, the p-type impurity concentration of the first column region 108 is adjusted by aluminum.

[0489] The width of the first pillar region 108 is preferably less than the thickness of the second semiconductor region 7. The width of the first pillar region 108 is the width in a direction orthogonal to the extending direction of the first pillar region 108. The width of the first pillar region 108 can be more than 0.1 μm and less than 5 μm.

[0490] The thickness of the first pillar region 108 can also be referred to as the depth of the first pillar region 108. The thickness of the first pillar region 108 can also be less than the thickness of the second semiconductor region 7. The thickness of the first pillar region 108 can also be greater than the thickness of the second semiconductor region 7. The thickness of the first pillar region 108 can also be approximately equal to the thickness of the second semiconductor region 7. The thickness of the first pillar region 108 is preferably 1 μm or more and 5 μm or less.

[0491] The spacing between the plurality of first pillar regions 108 in the first direction X is preferably less than the thickness of the second semiconductor region 7. The spacing between the plurality of first pillar regions 108 can be greater than 0.1 μm and less than 5 μm.

[0492] In this approach, the multiple second pillar regions 109 may also have the same n-type impurity concentration as the cap region 72 of the second semiconductor region 7 as a peak value. The n-type impurity concentration is adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second pillar region 109 can also be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. In this approach, the n-type impurity concentration of the second pillar region 109 is adjusted by phosphorus.

[0493] The width of the second pillar region 109 is the width in a direction orthogonal to the extending direction of the second pillar region 109. Preferably, the width of the second pillar region 109 is the same as the width of the first pillar region 108. Of course, the width of the second pillar region 109 can be wider or narrower than the width of the first pillar region 108. Preferably, the width of the second pillar region 109 is less than the thickness of the second semiconductor region 7. The width of the second pillar region 109 can be 0.1 μm or more and 5 μm or less.

[0494] The thickness of the second pillar region 109 can also be referred to as the depth of the second pillar region 109. The thickness of the second pillar region 109 can also be less than the thickness of the second semiconductor region 7. Alternatively, the thickness of the second pillar region 109 can be greater than the thickness of the second semiconductor region 7. The thickness of the second pillar region 109 can also be approximately equal to the thickness of the second semiconductor region 7. Preferably, the thickness of the second pillar region 109 is 1 μm or more and 5 μm or less.

[0495] The spacing between the plurality of second pillar regions 109 in the first direction X is preferably less than the thickness of the second semiconductor region 7. The spacing between the plurality of second pillar regions 109 can be greater than 0.1 μm and less than 5 μm.

[0496] Multiple main body regions 101 are formed on the surface of the first main surface 3 in such a way that they overlap with the first pillar regions 108 corresponding to the stacking direction. Specifically, the multiple main body regions 101 overlap with the multiple first pillar regions 108 in a one-to-one correspondence in the stacking direction.

[0497] Multiple main body regions 101 are each wider than the first pillar region 108 directly below them, and are formed at intervals from adjacent first pillar regions 108 toward the first pillar region 108 directly below them. The multiple main body regions 101 expose a portion of the second pillar region 109 in the area between adjacent first pillar regions 108 in the first main surface 3.

[0498] The first outer well region 42 is formed along the outer peripheral boundary 19 at a depth greater than that of the plurality of first pillar regions 108. Alternatively, the first outer well region 42 may also have a depth approximately the same as that of the plurality of first pillar regions 108.

[0499] The above-described method (including variations) can also be implemented in other ways. For example, in the second embodiment described above, an example is shown where the external wiring 46 is connected to the source electrode 51. However, the external wiring 46 can also be electrically disconnected from the source electrode 51. In this case, the external wiring 46 can also be formed as a floating wiring or field wiring (so-called field preform) in an electrically floating state.

[0500] In the above embodiments, a chip 2 comprising SiC single crystal is used. However, chip 2 may also comprise single-crystal silicon. Similarly, the first semiconductor region 6 may also comprise single-crystal silicon. Likewise, the second semiconductor region 7 may also comprise single-crystal silicon.

[0501] In the aforementioned methods, a structure can also be adopted in which the conductivity type of the "n-type" semiconductor region is reversed to "p-type" and the conductivity type of the "p-type" semiconductor region is reversed to "n-type". The specific structure in this case is obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the foregoing description and figures.

[0502] In the aforementioned methods, a p-type collector region may also be formed on the surface layer of the second main surface 4 of chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific structure in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, chip 2 can have a single-layer structure including an n-type semiconductor substrate.

[0503] Hereinafter, examples of features extracted from this specification and accompanying drawings are shown. Hereinafter, alphanumeric characters, etc., denote corresponding constituent elements in the foregoing embodiments, but do not imply that the scope of each clause is limited to the embodiments. The term "semiconductor device" as used below can be replaced as "semiconductor device," "wide-bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0504] [Appendix 1-1] A semiconductor device 1A, 1B, 1C, 1D, comprising:

[0505] SiC chip 2, which has a main surface 3;

[0506] Active region 8 is disposed on the main surface 3;

[0507] The outer peripheral region 9 is disposed on the main surface 3 and surrounds the active region 8.

[0508] Semiconductor region 7 is a first conductivity type semiconductor region 7 formed on the surface portion of the main surface 3, and includes a base region 71 spanning the active region 8 and the peripheral region 9, and a cap region 72 formed on the surface portion of the base region 71 in at least the active region 8 and having a higher impurity concentration than the base region 71.

[0509] The device structure is formed in the active region 8 and includes a second conductivity type main region 10, 101 formed in the surface layer of the semiconductor region 7, and a first conductivity type source region 11, 102 formed in the surface layer of the main region 10, 101.

[0510] A second conductivity type outer well region 40 is formed in the outer peripheral region 9 on the surface portion of the semiconductor region 7; and

[0511] The field cutoff region 12 is formed outside the outer well region 40, has a higher impurity concentration than the base region 71, and has the same depth as the cap region 72.

[0512] [Appendix 1-2] According to the semiconductor devices 1A, 1B, 1C, and 1D described in Appendix 1-1, wherein,

[0513] The field cutoff region 12 has a first concentration gradient 69 in the depth direction of the SiC chip 2, which is equal to the concentration gradient of the cap region 72.

[0514] [Appendix 1-3] According to the semiconductor devices 1A, 1B, 1C, and 1D described in Appendix 1-2, wherein,

[0515] The first concentration gradient 69 in the field cutoff region 12 includes a first peak 94 and P6.

[0516] The field cutoff region 12 also has a second concentration gradient 70 on the side of the main surface 3 that includes a second peak 95 and a second peak 97 that are higher than the first peak 94 and P6.

[0517] [Appendix 1-4] According to the semiconductor devices 1A, 1B, 1C, and 1D described in Appendix 1-3, wherein,

[0518] The second concentration gradient 70 of the field cutoff region 12 is equal to the concentration gradient 78 of the source regions 11 and 102 in the depth direction of the SiC chip 2.

[0519] [Appendix 1-5] Semiconductor devices 1A, 1B, 1C, and 1D according to any one of Appendix 1-1 to Appendix 1-4, wherein,

[0520] The field cutoff region 12 is formed to be deeper than the outer trap region 40.

[0521] [Appendix 1-6] Semiconductor devices 1A and 1B according to any one of Appendix 1-1 to Appendix 1-5, wherein,

[0522] The device structure includes: a trench gate structure 15 having a gate trench 16 extending through the source region 11 and the main region 10 to the semiconductor region 7, a gate insulating film 17 formed on the inner surface of the gate trench 16, and a gate electrode 18 buried in the gate trench 16 through the gate insulating film 17.

[0523] The field cutoff region 12 is formed deeper than the trench gate structure 15.

[0524] [Appendix 1-7] According to the semiconductor devices 1A and 1B described in Appendix 1-6, wherein,

[0525] It also includes a gate well region 25 of a second conductivity type, which is formed at the bottom of the gate trench 16.

[0526] The field cutoff region 12 is formed deeper than the gate well region 25.

[0527] [Appendix 1-8] Semiconductor devices 1C and 1D according to any one of Appendix 1-1 to Appendix 1-5, wherein,

[0528] The device structure includes: a planar gate structure 100 formed on the main surface 3, having a gate electrode 105 opposite to the main body region 101 and a gate insulating film 104 between the gate electrode 105 and the main surface 3.

[0529] [Appendix 1-9] The semiconductor devices 1A, 1B, 1C, and 1D according to any one of Appendix 1-1 to Appendix 1-8, further comprising:

[0530] An insulating layer 47 is formed on the main surface 3 of the SiC chip 2; and

[0531] Source electrodes 51 and 56 are selectively connected, via the insulating layer 47, to the device structure, the outer well region 40, and the source regions 11 and 102 in the field cutoff region 12, as well as to the outer well region 40.

[0532] The field cutoff region 12 is covered by the insulating layer 47 and is formed in an electrically floating state.

[0533] [Appendix 1-10] According to the semiconductor devices 1A, 1B, 1C, and 1D described in Appendix 1-9, wherein,

[0534] The source electrodes 51 and 56 are selectively opposed to the device structure, the outer well region 40, and the field cutoff region 12, separated by the insulating layer 47.

[0535] [Appendix 1-11] Semiconductor devices 1A, 1B, 1C, and 1D according to any one of Appendices 1-1 to 1-10, wherein,

[0536] The field cutoff region 12 is configured separately from the end faces 4A, 4B, 4C, and 4D of the SiC chip 2 and inwards.

[0537] The main surface 3 of the SiC chip 2 extends from the active region 8 through the peripheral region 9 to the end surfaces 4A, 4B, 4C, and 4D in a flat surface without steps.

[0538] [Appendix 1-12] According to the semiconductor devices 1A, 1B, 1C, and 1D described in Appendix 1-11, wherein,

[0539] The field cutoff region 12 and the source regions 11 and 102 both have upper surfaces 11a and 12a exposed from the main surface 3.

[0540] The upper surface 12a of the field cutoff region 12 and the upper surface 11a of the source regions 11 and 102 are configured at the same height.

[0541] [Appendix 1-13] Semiconductor devices 1A, 1B, 1C, and 1D according to any one of Appendix 1-1 to Appendix 1-12, wherein,

[0542] The outer trap region 40 includes: a first outer trap region 42 formed along the outer periphery boundary 19 of the active region 8 and the outer peripheral region 9; and a plurality of second outer trap regions 43 formed outside the first outer trap region 42 and surrounding the first outer trap region 42.

[0543] The field cutoff region 12 is configured separately from the plurality of second outer trap regions 43 outward.

[0544] [Appendix 1-14] Semiconductor devices 1A, 1B, 1C, and 1D according to any one of Appendices 1-1 to 1-13, wherein,

[0545] The field cutoff region 12 is formed in a ring shape surrounding the active region 8.

[0546] [Appendix 1-15] According to the semiconductor devices 1A, 1B, 1C, and 1D described in Appendix 1-14, wherein,

[0547] The field cutoff region 12 is configured separately from the end faces 4A, 4B, 4C, and 4D of the SiC chip 2 and inwards.

[0548] It also includes: a second conductivity type end voltage mitigation region 60, which is disposed further outward than the field cutoff region 12, surrounds the field cutoff region 12, and is exposed from the end faces 4A, 4B, 4C, and 4D of the SiC chip 2.

[0549] [Appendix 1-16] A semiconductor device 1A, 1B, comprising:

[0550] SiC chip 2, which has a main surface 3;

[0551] Active region 8 is disposed on the main surface 3;

[0552] The outer peripheral region 9 is disposed on the main surface 3 and surrounds the active region 8.

[0553] Semiconductor region 7 is a first conductivity type semiconductor region 7 formed on the surface portion of the main surface 3, and includes a base region 71 spanning the active region 8 and the peripheral region 9, and a cap region 72 formed on the surface portion of the base region 71 in at least the active region 8 and having a higher impurity concentration than the base region 71.

[0554] The device structure is formed in the active region 8 and includes: a second conductivity type body region 10 formed on the surface of the cap region 72; a first conductivity type source region 11 formed on the surface of the body region 10; and a plurality of trench gate structures 15 having a gate trench 16 that penetrates the source region 11 and the body region 10 and has a bottom in the cap region 72, a gate insulating film 17 formed on the inner surface of the gate trench 16, and a gate electrode 18 buried in the gate trench 16 through the gate insulating film 17.

[0555] The second conductivity type outer well region 40 is selectively formed in the outer peripheral region 9 on the surface portion of the base region 71; and

[0556] The field cutoff region 12 is selectively formed on the surface portion of the base region 71 outside the outer well region 40, has a higher impurity concentration than the base region 71, and has a depth greater than the trench gate structure 15 and the same depth as the cap region 72.

[0557] [Appendix 1-17] According to the semiconductor devices 1A and 1B described in Appendix 1-16, wherein,

[0558] The field cutoff region 12 has a first concentration gradient 69 and a second concentration gradient 70 in the depth direction of the SiC chip 2. The first concentration gradient 69 includes a first peak 94 and P6 and is equal to the concentration gradient of the cap region 72. The second concentration gradient 70 includes a second peak 95 and P7 that are higher than the first peak 94 and P6 on the side closer to the main surface 3 than the first peak 94 and P6.

[0559] [Appendix 1-18] According to the semiconductor devices 1A and 1B described in Appendix 1-17, wherein,

[0560] The second concentration gradient 70 of the field cutoff region 12 is equal to the concentration gradient of the source region 11 in the depth direction of the SiC chip 2.

[0561] [Notes 1-19] Semiconductor devices 1A and 1B according to any one of Notes 1-16 to 1-18, wherein,

[0562] It also includes: a gate well region 25 of a second conductivity type, which is formed at the bottom of the gate trench 16.

[0563] The field cutoff region 12 is formed deeper than the gate well region 25.

[0564] [Appendix 1-20] The semiconductor devices 1A and 1B according to any one of Appendix 1-16 to 1-19 further include:

[0565] An insulating layer 47 is formed on the main surface 3 of the SiC chip 2; and

[0566] Source electrodes 51 and 56 are selectively opposed to the device structure, the outer well region 40, and the device structure and the outer well region 40 in the field cutoff region 12, separated by the insulating layer 47, and are selectively connected to the source region 11 and the outer well region 40, separated by the insulating layer 47.

[0567] The field cutoff region 12 is covered by the insulating layer 47 and is formed in an electrically floating state.

[0568] Symbol Explanation

[0569] 1A—Semiconductor device; 1B—Semiconductor device; 1C—Semiconductor device; 1D—Semiconductor device; 2—Chip; 3—First main surface; 4—Second main surface; 5A—First side surface; 5B—Second side surface; 5C—Third side surface; 5D—Fourth side surface; 6—First semiconductor region; 7—Second semiconductor region; 8—Active region; 9—Outer peripheral region; 10—Main region; 11—Source region; 11a—Upper surface; 12—Field cutoff region; 12a—Upper surface; 13—First region; 14—Second region; 15—Gate structure; 15A—Terminal gate structure; 16—First trench; 16A—Terminal first trench; 17—First insulating film; 17A—Terminal first insulating film; 18—First buried electrode; 18 A—First buried electrode at the end; 19—Outer peripheral boundary; 20—Gradual increase portion; 21—Peak portion; 22—Slow decrease portion; 23—Gradual decrease portion; 25—Gate well region; 25a—Bulging portion; 25b—Bottom of the well; 26—Source well region; 26a—Bulging portion; 27—Gate contact region; 28—Source contact region; 29—Extension portion; 30—Separation structure; 30A—End separation structure; 31—Third trench; 31A—Third trench at the end; 32—Third insulating film; 32A—Third insulating film at the end; 33—Third buried electrode; 33A—Third buried electrode at the end; 35—Separated well region; 35a—Bulging portion; 35b—Bottom of the well; 37—Separated contact region; 40—Outer well region; 41—Outer contact region; 42—First outer well region; 42a—First upper end; 42b—First lower end; 42c—First body portion; 42d—First side portion; 43—Second outer well region; 43a—Second upper end; 43b—Second lower end; 43c—Second body portion; 43d—Second side portion; 45—Main surface insulating film; 46—Outer wiring; 47—Interlayer film; 48—Gate opening; 49—Source opening; 50—Outer opening; 51—Source electrode; 51a—First pad portion; 51b—Second pad portion; 51c—Third pad portion; 52—Lower electrode film; 53—Main electrode film; 56—Source wiring; 57—Gate electrode; 58—Gate wiring; 59—Drain electrode; 60—Voltage easing region; 60a—Upper surface; 60 b—Side; 61—Boundary section; 62—Boundary section; 63—Central section; 64—End; 65—Gap; 66—Central section; 67—End; 68—Gap; 69—First concentration gradient; 70—Second concentration gradient; 71—Base region; 72—Cap region; 73—Rapid increase section; 74—Peak section; 75—Rapid decrease section; 76—First concentration gradient; 77—Second concentration gradient; 78—Source concentration gradient; 79—Peak section; 80—Peak section; 81—Increasing section; 82—Decreasing section; 83—Increasing section; 84—Decreasing section; 85—Gradually increasing section; 86—Peak section; 87—Slow section; 88—Gradually decreasing section; 90—Source structure; 91—Second trench; 92—Second insulating film; 93—Second embedded electrode; 94—Peak section;95—Peak; 96—Increase; 97—Decrease; 98—Increase; 99—Decrease; 100—Gate structure; 101—Main region; 102—Source region; 103—Channel region; 104—Insulating film; 105—Gate electrode; 106—Second cap region; 108—First pillar region; 109—Second pillar region.

Claims

1. A semiconductor device, characterized in that, include: SiC chip, which has a main surface; An active region is located on the main surface; The peripheral region is located on the main surface and surrounds the active region. The semiconductor region is a first conductivity type semiconductor region formed on the surface portion of the main surface, and includes a base region spanning the active region and the peripheral region, and a cap region formed on the surface portion of the base region at least in the active region and having a higher impurity concentration than the base region. A device structure formed in the active region, comprising a second conductivity type body region formed in the surface portion of the semiconductor region and a first conductivity type source region formed in the surface portion of the body region; The outer well region of the second conductivity type is formed in the outer peripheral region on the surface portion of the semiconductor region; as well as The field cutoff region is formed outside the outer well region, has a higher impurity concentration than the base region, and has the same depth as the cap region.

2. The semiconductor device according to claim 1, characterized in that, The field cutoff region has a first concentration gradient in the depth direction of the SiC chip that is equal to the concentration gradient of the cap region.

3. The semiconductor device according to claim 2, characterized in that, The first concentration gradient in the field cutoff region includes a first peak value. The field cutoff region also has a second concentration gradient on the main surface side, which includes a second peak higher than the first peak.

4. The semiconductor device according to claim 3, characterized in that, The second concentration gradient in the field cutoff region is equal to the concentration gradient in the source region along the depth direction of the SiC chip.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The field cutoff region is formed deeper than the outer trap region.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The device structure includes a trench gate structure having a gate trench extending through the source region and the body region to the semiconductor region, a gate insulating film formed on the inner surface of the gate trench, and a gate electrode buried in the gate trench through the gate insulating film. The field cutoff region is formed deeper than the trench gate structure.

7. The semiconductor device according to claim 6, characterized in that, It also includes a second conductivity type gate well region formed at the bottom of the gate trench. The field cutoff region is formed deeper than the gate well region.

8. The semiconductor device according to any one of claims 1 to 5, characterized in that, The device structure includes a planar gate structure formed on the main surface, having a gate electrode opposite to the main region and a gate insulating film between the gate electrode and the main surface.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, Also includes: An insulating layer is formed on the main surface of the SiC chip; as well as The source electrode is selectively connected, via the insulating layer, to the device structure, the outer well region, and the field-stop region, to the source region and the outer well region. The field cutoff region is covered by the insulating layer and is formed in an electrically floating state.

10. The semiconductor device according to claim 9, characterized in that, The source electrode is selectively opposed to the device structure, the outer well region, and the field cutoff region, separated by the insulating layer.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The field cutoff region is configured separately from the end face of the SiC chip, facing inwards. The main surface of the SiC chip is a flat surface without steps, extending from the active region through the peripheral region to the end face.

12. The semiconductor device according to claim 11, characterized in that, Both the field cutoff region and the source region have upper surfaces exposed from the main surface. The upper surface of the field cutoff region and the upper surface of the source region are positioned at the same height.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, The outer well region includes: a first outer well region formed along the outer periphery boundary between the active region and the outer peripheral region; and a plurality of second outer well regions formed outside the first outer well region and surrounding the first outer well region. The field cutoff region is configured separately from the plurality of second outer trap regions outward.

14. The semiconductor device according to any one of claims 1 to 13, characterized in that, The field cutoff region is formed as a ring surrounding the active region.

15. The semiconductor device according to claim 14, characterized in that, The field cutoff region is configured separately from the end face of the SiC chip, facing inwards. It also includes a second conductivity type end voltage easing region, which is disposed further outward than the field cutoff region and surrounds the field cutoff region, and is exposed from the end face of the SiC chip.

16. A semiconductor device, characterized in that, include: SiC chip, which has a main surface; An active region is located on the main surface; The peripheral region is located on the main surface and surrounds the active region. The semiconductor region is a first conductivity type semiconductor region formed on the surface portion of the main surface, and includes a base region spanning the active region and the peripheral region, and a cap region formed on the surface portion of the base region at least in the active region and having a higher impurity concentration than the base region. A device structure formed in the active region, comprising: a body region of a second conductivity type formed on the surface of the cap region; a source region of a first conductivity type formed on the surface of the body region; and a plurality of trench gate structures having a gate trench penetrating the source region and the body region and having a bottom in the cap region, a gate insulating film formed on the inner surface of the gate trench, and a gate electrode buried in the gate trench through the gate insulating film; The outer well region of the second conductivity type is selectively formed in the outer peripheral region on the surface portion of the base region; and The field-stop region is selectively formed on the surface of the base region outside the outer well region, has a higher impurity concentration than the base region, is deeper than the trench gate structure, and has the same depth as the cap region.

17. The semiconductor device according to claim 16, characterized in that, The field cutoff region has a first concentration gradient and a second concentration gradient in the depth direction of the SiC chip. The first concentration gradient includes a first peak value and is equal to the concentration gradient of the cap region. The second concentration gradient includes a second peak value that is higher than the first peak value on the main surface side closer to the first peak value.

18. The semiconductor device according to claim 17, characterized in that, The second concentration gradient in the field cutoff region is equal to the concentration gradient in the source region along the depth direction of the SiC chip.

19. The semiconductor device according to any one of claims 16 to 18, characterized in that, It also includes a second conductivity type gate well region formed at the bottom of the gate trench. The field cutoff region is formed deeper than the gate well region.

20. The semiconductor device according to any one of claims 16 to 19, characterized in that, Also includes: An insulating layer is formed on the main surface of the SiC chip; as well as The source electrode is selectively opposed to the device structure, the outer well region, and the field-stop region via the insulating layer, and is selectively connected to the source region and the outer well region via the insulating layer. The field cutoff region is covered by the insulating layer and is formed in an electrically floating state.

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