Semiconductor device and method for manufacturing semiconductor device
Patent Information
- Application Number
- CN202580016699.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-19
- Filing Date
- 2025-02-10
- Publication Date
- 2026-09-25
AI Technical Summary
[0010]根据本发明,能够提供即使在电极的配置间距小而成为5μm以下的配置间距的情况下也能够得到可靠性高的金属连接的半导体装置及其制造方法。
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Figure CN122827031A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology
[0002] In conventional microbump bonding technology, the following method is used: through a via opening is formed in the resin by photolithography using a heat-resistant photosensitive resin as the resin surrounding the embedded metal electrode, and a metal electrode is formed in the via.
[0003] Existing technical documents
[0004] Patent documents
[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-204818 Summary of the Invention
[0006] In existing heat-resistant photosensitive resins, it is impossible to increase the aspect ratio of vias to more than 1. Therefore, as the via diameter decreases, the height of the via, i.e., the height of the metal electrode, also decreases. When the via diameter decreases and the height of the metal electrode is reduced to the same level as the via diameter, there is a problem that the amount of solder material used for connecting the metal electrodes to each other decreases, making it difficult to obtain a highly reliable metal connection.
[0007] Therefore, the object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can achieve a highly reliable metal connection even when the electrode spacing is small, less than 5 μm.
[0008] The semiconductor device of the present invention is a flip-chip interconnect semiconductor device, comprising a semiconductor device, a wiring device, and a connection portion connecting the semiconductor device and the wiring device. The semiconductor device has a first main surface on which a first electrode is disposed at a spacing of 5 μm or less. The wiring device has a second main surface on which a second electrode is disposed at a spacing of 5 μm or less corresponding to the spacing. The connection portion has a columnar metal electrode disposed at a spacing of 5 μm or less corresponding to the spacing, connecting the first electrode of the semiconductor device and the second electrode of the wiring device, and a resin portion disposed around the columnar metal electrode. The area equivalent diameter of the cross-section of the columnar metal electrode orthogonal to the axial direction is smaller than the spacing, and the axial length of the columnar metal electrode from the portion connected to the first main surface to the portion connected to the second main surface is more than twice the spacing.
[0009] The method for manufacturing a semiconductor device according to the present invention includes: a step of preparing a semiconductor device having electrodes arranged on a main surface with a spacing of 5 μm or less; a step of forming an organic insulating film on a main surface of the semiconductor device; a step of hardening the organic insulating film; a step of forming holes in the organic insulating film on the electrodes by dry etching to a spacing corresponding to the spacing of the electrodes; a step of filling the holes with metal to form columnar metal electrodes; and a step of aligning the semiconductor device with other wiring devices and connecting them by flip-chip interconnection.
[0010] According to the present invention, a semiconductor device and a method thereof can be provided that can achieve highly reliable metal interconnection even when the electrode spacing is small, such as 5 μm or less. Attached Figure Description
[0011] Figure 1 This is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
[0012] Figure 2 These are cross-sectional views of semiconductor devices with other structures.
[0013] Figure 3A This is a diagram showing a cross-section of a semiconductor device.
[0014] Figure 3B This is a diagram showing the state in which a resin film has been formed on a semiconductor device.
[0015] Figure 3C This is a diagram showing the state in which a resist film is formed on a resin film.
[0016] Figure 3D This is a diagram showing the state of the resist film after photolithography.
[0017] Figure 3E This is a diagram showing the state of the resist film and the resin film after dry etching.
[0018] Figure 3F This is a diagram showing the state after the resist film has been removed.
[0019] Figure 3G This diagram shows the state in which a seed layer is formed on the surface of the resin film, the first main surface, and the inner surface of the third recess.
[0020] Figure 3H This diagram shows the state in which an electrode layer is formed in the third recess, etc.
[0021] Figure 3I This is a diagram showing the state in which the surface of the resin film is planarized.
[0022] Figure 3JThis is a diagram showing the connection between semiconductor devices and wiring devices. Detailed Implementation
[0023] (Semiconductor devices)
[0024] The specific implementation method is described with reference to the accompanying drawings. Figure 1 This is a cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 1 includes a semiconductor device 10, a connection portion 50, and a wiring device 30. The semiconductor device 10 is electrically connected to the wiring device 30 via the connection portion 50.
[0025] (Semiconductor devices and wiring devices)
[0026] Semiconductor device 10 refers to a semiconductor component, such as a silicon wafer, on which semiconductor elements are formed. An example of semiconductor device 10 is a semiconductor chip. Semiconductor device 10 includes a first substrate 12 and a first electrode 16. The first substrate 12 refers to a portion of the semiconductor device 10, such as a silicon wafer, that serves as a substrate on which semiconductor elements are formed. An electrode formed on one surface of the semiconductor device 10 is called the first electrode 16. The surface on which the first electrode 16 is formed in the semiconductor device 10 is called the first main surface 14.
[0027] (Wiring devices)
[0028] Wiring device 30 refers to a component, such as a silicon wafer, on which a wiring layer is formed. An example of wiring device 30 includes an interposer. Semiconductor elements can also be formed in wiring device 30. Examples of wiring device 30 include semiconductor devices including active elements such as semiconductor elements, substrates such as silicon interposers that do not include active elements and only have wiring, and RDL interposers that have a wiring layer formed on a carrier made of glass or the like and then peeled off from the carrier, leaving only the wiring layer. Wiring device 30 includes a second substrate 32 and a second electrode 36. The second substrate 32 refers to a portion of the wiring device 30, such as a silicon wafer, on which a wiring layer is formed. An electrode formed on one surface of wiring device 30 is called the second electrode 36. The surface on which the second electrode 36 is formed in wiring device 30 is called the second main surface 34.
[0029] (Connecting part)
[0030] The connection portion 50 refers to the portion that connects the semiconductor device 10 and the wiring device 30. The connection portion 50 includes a columnar metal electrode 54 and a resin portion 52. The columnar metal electrode 54 refers to the portion that electrically connects the first electrode 16 and the second electrode 36. The resin portion 52 refers to the portion of the connection portion 50 that is made of resin and is disposed around the columnar metal electrode 54. The resin portion 52 is formed of an insulating resin. The material of the resin film 80 may be, for example, polyimide, polyamide-imide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc.
[0031] The columnar metal electrode 54 can be formed using copper, solder, etc. Figure 1 In the example shown, the columnar metal electrode 54 has a first electrode portion 61, a second electrode portion 62, and a third electrode portion 63. They are arranged sequentially from the first main surface 14 in the order of first electrode portion 61, third electrode portion 63, and second electrode portion 62. The first electrode portion 61 is connected to the first main surface 14. The second electrode portion 62 is connected to the second main surface 34. The first electrode portion 61, the second electrode portion 62, and the third electrode portion 63 can be formed from different materials. For example, the first electrode portion 61 and the second electrode portion 62 can be formed from copper, and the third electrode portion 63 can be formed from solder. As explained later, when the semiconductor device 10 and the wiring device 30 are bonded by hybrid bonding, the first electrode 16 and the second electrode 36 can be easily connected by having the third electrode portion 63 formed from solder. When the solder melts, the copper and solder components may diffuse into each other. Therefore, a barrier layer such as nickel, which can suppress this phenomenon, can be formed between the first electrode portion 61 and the third electrode portion 63, and between the second electrode portion 62 and the third electrode portion 63.
[0032] (Axial direction and principal plane direction)
[0033] In Figure 1 The direction indicated by the middle arrow 101 is called the axial direction 101 of the columnar metal electrode 54. Axial direction 101 is also the connection direction between the semiconductor device 10 and the wiring device 30. Figure 1 The direction indicated by the middle arrow 102 is orthogonal to the axis direction 101. The direction of arrow 102 is called the principal plane direction 102. The principal plane direction 102 is parallel to the first principal plane 14 and the second principal plane 34.
[0034] (Electrode spacing)
[0035] Figure 1 The length 201 shown is the spacing in the main surface direction 102 of the first electrode 16. Figure 1The length 202 shown is the spacing in the principal surface direction 102 of the second electrode 36. Both lengths 201 and 202 are 5 μm or less. That is, the spacing in the principal surface direction 102 of the first electrode 16 and the second electrode 36 is 5 μm or less.
[0036] Figure 1 The length 203 shown is the spacing along the principal surface direction 102 of the columnar metal electrodes 54. The length 203 is 5 μm or less. That is, the spacing along the principal surface direction 102 of the columnar metal electrodes 54 is 5 μm or less.
[0037] The spacing of the first electrode 16, the second electrode 36, and the columnar metal electrode 54 in the main surface direction 102 corresponds to each other. Correspondence means that they are substantially the same.
[0038] (Configuration spacing)
[0039] Will Figure 1 The length 201 shown is called the configuration spacing 201.
[0040] (Area equivalent diameter of columnar metal electrode)
[0041] The area equivalent diameter in the cross-section of the cylindrical metal electrode 54 perpendicular to the axial direction 101 is defined as the area equivalent diameter. The area equivalent diameter (area circle equivalent diameter) refers to the diameter of a perfect circle having an area equal to the cross-sectional area of the cylindrical metal electrode 54. The area equivalent diameter is less than the arrangement spacing 201.
[0042] The area equivalent diameter of the columnar metal electrode 54 is preferably less than 5 μm. More preferably, it is 3 μm or less. It can also be 2.5 μm or less.
[0043] The area equivalent diameter is preferably less than 2 / 3 of the configuration spacing 201. The area equivalent diameter can also be less than half of the configuration spacing 201.
[0044] Furthermore, the cross-sectional area of the columnar metal electrode 54 in the section perpendicular to the axial direction 101 is preferably 30 square μm or less. More preferably, the cross-sectional area of the columnar metal electrode 54 in the section perpendicular to the axial direction 101 is 20 square μm or less. The cross-sectional area of the columnar metal electrode 54 in the section perpendicular to the axial direction 101 may also be 5 square μm or less.
[0045] As described above, in the semiconductor device 1 of this embodiment, the area equivalent diameter of the columnar metal electrodes 54 is small. Therefore, even when the arrangement spacing 201 is small, short circuits or the like will not occur between adjacent columnar metal electrodes 54, and the first electrode 16 and the second electrode 36 can be connected.
[0046] The cross-sectional shape of the columnar metal electrode 54 in the section perpendicular to the axial direction 101 is not particularly limited. The cross-sectional shape can be, for example, circular, rectangular, etc.
[0047] (Axial length of the columnar metal electrode)
[0048] Figure 1 The length 211 represents the length of the columnar metal electrode 54 in the axial direction 101. This length 211 is referred to as the axial length 211. The axial length 211 is approximately equal to the distance in the axial direction 101 between the first main surface 14 and the second main surface 34. The axial length 211 is more than twice the length of the spacing 201.
[0049] The axial length 211 of the columnar metal electrode 54 is preferably 10 μm or more. More preferably, the axial length 211 is 15 μm or more. The axial length 211 of the columnar metal electrode 54 may also be 8 μm or more.
[0050] The axial length 211 is preferably more than three times the configuration spacing 201.
[0051] Furthermore, the axial length 211 is preferably at least twice the area equivalent diameter of the columnar metal electrode 54. More preferably, the axial length 211 is at least three times the area equivalent diameter.
[0052] As described above, in the semiconductor device 1 of this embodiment, when viewed in a cross-section parallel to the axial direction 101 and the main surface direction 102, the length of the columnar metal electrode 54 in the axial direction 101 is considerably longer than the length of the columnar metal electrode 54 in the main surface direction 102. That is, when viewed in a cross-section parallel to the axial direction 101 and the main surface direction 102, the columnar metal electrode 54 has a shape that is elongated in the axial direction 101. Therefore, even with a small spacing, short circuits or the like between adjacent columnar metal electrodes 54 are prevented, ensuring the volume of the columnar metal electrodes 54. Therefore, even with a small spacing, a highly reliable metal connection can be obtained.
[0053] (Shortest length of resin section)
[0054] Figure 1 The length 205 represents the length of the resin portion 52 in the main surface direction 102 disposed between adjacent columnar metal electrodes 54. Here, when the length 205 of the resin portion 52 in the main surface direction 102 varies depending on the position in the axial direction 101, the shortest length 205 is referred to as the shortest resin portion length 205. The area equivalent diameter of the columnar metal electrode 54 is preferably smaller than the shortest resin portion length 205. As a result, a high-density connection can be achieved while ensuring the insulation of adjacent columnar metal electrodes 54.
[0055] (Linearity of columnar metal electrodes)
[0056] The straightness of the columnar metal electrode 54 will be explained. The straightness of the columnar metal electrode 54 refers to the degree to which the line representing the side surface 56 of the columnar metal electrode 54 approximates a straight line in a cross-section parallel to the axial direction 101 and the principal surface direction 102. The straightness of the columnar metal electrode 54 can also be referred to as the flatness of the side surface 56. Hereinafter, the straightness of the columnar metal electrode 54 will be explained from the viewpoint of its outer diameter 207.
[0057] (Outer diameter)
[0058] Figure 1 The length 207 shown is the length of the columnar metal electrode 54 in the main surface direction 102 of a cross-section parallel to the axial direction 101 and the main surface direction 102. When the cross-section of the columnar metal electrode 54 is rectangular, the length 207 corresponds to the side dimension. When the cross-section of the columnar metal electrode 54 is circular, the length 207 corresponds to the outer diameter dimension. Hereinafter, the length 207 will be referred to as the outer diameter dimension 207.
[0059] In the semiconductor device 1 of this embodiment, the outer diameter 207 of the portion of the columnar metal electrode 54 that is in contact with the first main surface 14 and the outer diameter 207 of the portion of the columnar metal electrode 54 that is in contact with the second main surface 34 are substantially the same. The outer diameter 207 of the portion of the columnar metal electrode 54 that is in contact with the first main surface 14 is referred to as the first outer diameter 2071. The outer diameter 207 of the portion of the columnar metal electrode 54 that is in contact with the second main surface 34 is referred to as the second outer diameter 2072. The first outer diameter 2071 and the second outer diameter 2072 are substantially the same. "Substantially the same" means that the second outer diameter 2072 is 95% or more and 105% or less of the outer diameter 207 of the first outer diameter 2071, and the first outer diameter 2071 is 95% or more and 105% or less of the outer diameter 207 of the second outer diameter 2072.
[0060] The outer diameter dimension 207 is preferably substantially the same from the portion where the columnar metal electrode 54 connects to the first main surface 14 to the portion where the columnar metal electrode 54 connects to the second main surface 34. Here, the outer diameter dimension 207 at the central position between the first main surface 14 and the second main surface 34 is defined as the reference outer diameter dimension 2073. "Substantially the same outer diameter dimension 207 from the portion where the columnar metal electrode 54 connects to the first main surface 14 to the portion where the columnar metal electrode 54 connects to the second main surface 34" means that the outer diameter dimension 207 at any position between the portion where the columnar metal electrode 54 connects to the first main surface 14 and the portion where the columnar metal electrode 54 connects to the second main surface 34 is 95% or more and 105% or less of the reference outer diameter dimension 2073.
[0061] As described above, in the semiconductor device 1 of this embodiment, the outer diameter 207 of the columnar metal electrode 54 does not change significantly from the portion connected to the first main surface 14 to the portion connected to the second main surface 34. This indicates that the columnar metal electrode 54 has high linearity. Because the columnar metal electrode 54 has high linearity in the semiconductor device 1 of this embodiment, the spacing between adjacent columnar metal electrodes 54 in the main surface direction 102 can be narrowed. As a result, high-density wiring can be achieved. Furthermore, even with a small spacing, short circuits or the like between adjacent columnar metal electrodes 54 are prevented, ensuring the volume of the columnar metal electrodes 54. Therefore, even with a small spacing, highly reliable metal connections can be obtained.
[0062] (Arithmetic mean roughness of the side surface of a columnar metal electrode)
[0063] The arithmetic mean roughness of the side surface 56 of the columnar metal electrode 54 is described. The side surface 56 of the columnar metal electrode 54 can also be referred to as the boundary surface between the columnar metal electrode 54 and the resin portion 52. In a cross-section along the axial direction 101 of the columnar metal electrode 54, the arithmetic mean roughness Ra of the side surface 56 of the columnar metal electrode 54 is 0.03 μm or less. When the arithmetic mean roughness Ra of the side surface 56 is 0.03 μm or less, voids are less likely to form between the resin portion 52 and the side surface 56 of the columnar metal electrode 54, thus improving the durability of the semiconductor device 1.
[0064] (Rectangularity of the longitudinal section of the columnar metal electrode)
[0065] illustrate Figure 1The rectangularity of the columnar metal electrode 54 in a cross-section (longitudinal section) along the axial direction 101 is shown. Here, rectangularity refers to (area inside the outline / area of the circumscribed rectangle of the outline). To explain the rectangularity of the columnar metal electrode 54 in more detail, the rectangularity is obtained by dividing "the area formed by the outline of the columnar metal electrode 54 in the longitudinal section of the columnar metal electrode 54" by "the area of the smallest rectangle formed in a way that minimizes the area of the rectangle circumscribed by the outline of the columnar metal electrode 54". For example, the rectangularity is calculated based on the longitudinal section (centroid) of the columnar metal electrode 54 along the axial direction 101, passing through the center (centroid) of the cross-section (cross-section) perpendicular to the axial direction 101 of the columnar metal electrode 54. The rectangularity of the columnar metal electrode 54 in the longitudinal section of the columnar metal electrode 54 of this embodiment is 0.95 or higher. By ensuring that the rectangularity of the longitudinal section of the columnar metal electrode 54 is 0.95 or higher and the outer diameter is small (207), the volume of the columnar metal electrode 54 can be ensured, preventing short circuits between adjacent columnar metal electrodes 54 even with a small spacing. Therefore, a highly reliable metal connection can be obtained even with a small spacing. Furthermore, it is difficult to set the rectangularity of the longitudinal section of the columnar metal electrode disposed within a recess processed by photolithography to be high, and it is less than 0.9.
[0066] (Other structures of semiconductor devices)
[0067] Reference Figure 2 This describes the other structures of semiconductor device 1. Figure 1 The semiconductor device 1 shown has a three-layer structure consisting of a semiconductor device 10, a connection portion 50, and a wiring device 30. In contrast, Figure 2 The semiconductor device 11 shown has a five-layer structure, in which the wiring device 30 and the connection portion 50 are each comprised of two layers. Hereinafter, the semiconductor device 11 will be mainly described in conjunction with... Figure 1 Different parts of the semiconductor device 1 shown.
[0068] Figure 2 The semiconductor device 11 shown has a structure in which a semiconductor device 10, a first connection portion 501, a first wiring device 301, a second connection portion 502, and a second wiring device 302 are sequentially stacked in the axial direction 101, starting from a semiconductor device 10. The first connection portion 501 and the second connection portion 502 have... Figure 1 The connection portion 50 shown has the same structure. In contrast, the first wiring device 301 and the second wiring device 302 have the same... Figure 1The wiring device 30 shown has different structures. Unlike wiring device 30, the first wiring device 301 and the second wiring device 302 have through electrodes formed. The through electrode formed in the first wiring device 301 is referred to as the first through electrode 71. The through electrode formed in the second wiring device 302 is referred to as the second through electrode 72. By forming through electrodes, the first wiring device 301 and the second wiring device 302 of the semiconductor device 11 can function as a three-dimensional stacked device or an interposer.
[0069] The structure of the layers will be described sequentially starting with semiconductor device 10. The first main surface 14 of semiconductor device 10 is in contact with the third main surface 511 of the first connection portion 501. At the interface between the first main surface 14 and the third main surface 511, the first electrode 16 of semiconductor device 10 is electrically connected to the columnar metal electrode 54 of the first connection portion 501.
[0070] The fourth main surface 512 of the first connection portion 501 is connected to the fifth main surface 311 of the first wiring device 301. At the interface between the fourth main surface 512 and the fifth main surface 311, the columnar metal electrode 54 of the first connection portion 501 is electrically connected to the first through electrode 71 of the first wiring device 301.
[0071] The sixth main surface 312 of the first wiring device 301 is connected to the seventh main surface 521 of the second connection portion 502. At the interface between the sixth main surface 312 and the seventh main surface 521, the first through electrode 71 of the first wiring device 301 is electrically connected to the columnar metal electrode 54 of the second connection portion 502.
[0072] The eighth main surface 522 of the second connection portion 502 is connected to the ninth main surface 321 of the second wiring device 302. At the interface between the eighth main surface 522 and the ninth main surface 321, the columnar metal electrode 54 of the second connection portion 502 is electrically connected to the second through electrode 72 of the second wiring device 302.
[0073] On the 10th main surface 322 of the second wiring device 302, a connection terminal 60, such as a solder ball, is provided at a position electrically connected to the second through electrode 72. The semiconductor device 1 is connected to, for example, an interposer or a printed wiring substrate via the connection terminal 60.
[0074] like Figure 2 As shown, by forming through electrodes in the wiring device, multiple layers of wiring devices can be included in the semiconductor device 11. This enables the handling of more complex wiring.
[0075] (Manufacturing method)
[0076] Reference Figures 3A to 3J This describes the manufacturing method of semiconductor device 1. Figures 3A to 3JThis is a diagram illustrating the manufacturing method of semiconductor device 1, showing a cross-section of the first substrate 12, etc. The manufacturing process begins... Figures 3A to 3J Progressing in sequence. Figures 3A to 3J It's merely a diagram used to illustrate a general outline of the manufacturing process. Therefore, in Figures 3A to 3J The diagrams of electrodes, wiring, and other components that do not significantly impact the manufacturing process have been omitted. Furthermore, related explanations have also been omitted.
[0077] (Semiconductor device preparation process)
[0078] Figure 3A This is a cross-sectional view showing the semiconductor device 10. In the semiconductor device preparation process, semiconductor elements, wiring, electrodes, etc., are formed on the first substrate 12 of the semiconductor device 10. The semiconductor elements, wiring, electrodes, etc., are... Figure 3A Not shown in the figure. The first substrate 12 may be, for example, a silicon substrate.
[0079] (Resin film formation process)
[0080] Figure 3B This diagram illustrates the state in which a resin film 80 has been formed on the semiconductor device 10. In the resin film formation process, the resin film 80 is formed on the first main surface 14 of the first substrate 12. The resin film 80 is formed by coating an insulating resin onto the first main surface 14, etc. The material of the resin film 80 can be, for example, polyimide, polyamide-imide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc.
[0081] Specific examples of methods for forming the resin film 80 will be given. When a liquid resin is used as the material for the resin film 80, the liquid resin is applied to a first substrate 12, such as a semiconductor wafer, semiconductor chip, or silicon substrate, by methods such as spin coating, slot coating, or spraying, and then dried and cured by heating or light irradiation. When a film-like resin is used, the film-like resin is adhered to the first substrate 12 and cured by heating or light irradiation. When a solid resin is used, the solid resin is heated to melt and a film is formed on the first substrate 12.
[0082] (Resist film formation process)
[0083] Figure 3C This diagram shows the state in which a resist film 84 has been formed on the resin film 80. The surface of the resin film 80 is referred to as the resin film surface 82. In the resist film forming process, the resist film 84 is formed on the resin film surface 82. The resist film 84 can be formed by coating or printing methods, etc. The material of the resist film 84 is not particularly limited as long as it is a photosensitive resist material.
[0084] (Photolithography process)
[0085] Figure 3D This diagram shows the state of the resist film 84 after photolithography. In the photolithography process, the resist film 84 is processed into predetermined intervals, sizes, and shapes. The resist film 84 is then removed according to a predetermined pattern, forming recesses, or vias, in the resist film 84. These recesses are also called through-holes. Figure 3D The recess formed in the resist film 84 shown is called the first recess 90. Inside the first recess 90, the resin film surface 82 of the resin film 80 is exposed.
[0086] (Dry etching process)
[0087] Figure 3E This diagram shows the state of the resist film 84 and the resin film 80 after dry etching. In the dry etching process, the resin film 80 is dry etched through a first recess 90 formed by a photolithography process. This dry etching forms a recess that penetrates both the resist film 84 and the resin film 80. Figure 3E The recess shown that penetrates the resist film 84 and the resin film 80 is called the second recess 92. Inside the second recess 92, the first main surface 14 of the semiconductor device 10 is exposed. Dry etching is performed by introducing a gas mixed with oxygen into a vacuum chamber to generate plasma. The plasma generator can be a parallel planar type, an ICP type, a microwave type, or a combination thereof.
[0088] In the dry etching process, in addition to the resin film 80, a portion of the resist film 84 is also etched. Figure 3D The length of the resist film 84 before dry etching, axially 101, is set to length 111. Figure 3E The length of the axial direction 101 of the dry-etched resist film 84 is set to length 112. For example... Figure 3D as well as Figure 3E As shown, length 112 is shorter than length 111. Figure 3D as well as Figure 3E In the example shown, length 112 is half the length 111.
[0089] (Cross-sectional shape of the third concave part)
[0090] Furthermore, the second recess 92 is formed by dry etching. Therefore, the cross-sectional shape of the second recess 92 in the plane parallel to the axial direction 101 and the main surface direction 102 is... Figure 3DThe first recess 90 shown is closer to a rectangle. Furthermore, in the cross-section of the recess along the axial direction, recesses processed by photolithography are sometimes schematically depicted as rectangles in the figures, but the actual rectangularity is low, less than 0.9 or lower. Specifically, regarding recesses processed by photolithography, for example in… Figure 3D As also shown, the edges of the via top and bottom are rounded, thus reducing the rectangularity of the recess in the axial cross-section. On the other hand, according to dry etching, a very high rectangularity recess can be formed in the axial cross-section. Specifically, regarding recesses processed by dry etching, such as... Figure 3F As shown, both the top and bottom of the via become very sharp, and the rectangularity of the recess in the cross-section along the axial direction becomes very high. As a result, the rectangularity of the columnar metal electrode 54 formed by the process described later can be 0.95 or higher in the cross-section along the axial direction 101 of the columnar metal electrode 54.
[0091] (Resist removal process)
[0092] Figure 3F This diagram shows the state after the resist film 84 has been removed. In the resist removal process, the resist film 84 remaining after dry etching is removed. By removing the resist film 84, only the patterned resin film 80 remains on the semiconductor device 10. The recess formed in the resin film 80 is referred to as the third recess 94. The third recess 94 is... Figure 3E A portion of the first main surface 14 side of the second recess 92 shown. In removing the resist, methods such as using a chemical solution or removing it with oxygen plasma can be employed.
[0093] The formation process of the third recess 94, as summarized above, is described below. A resin film 80 is provided as the film for forming the third recess 94, i.e., the via. A via formation process is performed through the resin film 80 by dry etching. Specifically, a photosensitive resist film 84 is formed on the resin film 80, and the photosensitive resist film 84 is removed only from the areas of the resin film 80 where the via formation process is desired by photolithography. The via formation process is then performed using a plasma etching apparatus. Etching gases such as O2, Ar, N2, SF6, NF3, and CF4 can be used.
[0094] Furthermore, the method for forming the third recess is not limited to the methods described above. As another method, a metal film such as copper is formed on a resin film using sputtering or similar methods, and a photosensitive resist film is formed on it. Then, the photosensitive resist is removed only from the areas of the resin film where via formation is desired using photolithography. Next, the metal film in the areas where the photosensitive resist has been removed is removed by wet etching with a liquid such as an acid or alkali, followed by the aforementioned dry etching. Afterward, dry etching of the resin film is performed, and then the photosensitive resist and metal film on the surface of the resin film are removed. This allows the formation of vias similar to the third recess. Furthermore, these removals can be performed by chemical dissolution, physical grinding, polishing, etc.
[0095] (Cross-sectional shape of the third concave part)
[0096] The third recess 94 is a part of the second recess 92 formed by dry etching. Therefore, the cross-sectional shape of the third recess 94 in the plane parallel to the axial direction 101 and the main surface direction 102 is similar to... Figure 3D The first recess 90 shown is closer to a rectangle.
[0097] (Aspect ratio of the third concave portion)
[0098] exist Figure 3F In this diagram, length 121 represents the length of the axial direction 101 of the third recess 94. Length 122 represents the length of the main surface direction 102 of the third recess 94. The aspect ratio of the third recess 94, i.e., length 121 / length 122, can be greater than 1. Length 121 / length 122 is more preferably 4 or greater. The third recess 94 is formed by dry etching. Therefore, the aspect ratio of length 121 / length 122, i.e., the cross-section of the third recess 94 parallel to the axial direction 101 and the main surface direction 102, can be increased. Furthermore, the rectangularity of the cross-section of the third recess 94 parallel to the axial direction 101 and the main surface direction 102 can be improved.
[0099] Figure 3F The length 251 represents the spacing 251 of the third recess 94 in the main surface direction 102. In the semiconductor device 1 of this embodiment, as described above, the third recess 94 has a large aspect ratio and high rectangularity, so the spacing 251 can be reduced. In addition, even when the spacing is small, the volume of the plated electrode layer 132, which is to be a columnar metal electrode 54, can be ensured.
[0100] (Seed sputtering process)
[0101] Figure 3G This diagram shows the state in which a seed layer 130 is formed on the surface 82 of the resin film and the inner surface of the third recess 94. The seed layer 130 is formed by seed sputtering.
[0102] In the seed sputtering process, a seed layer 130 is formed by sputtering on the resin film surface 82, the inner surface of the third recess 94, and the first main surface 14 exposed through the third recess 94. The formed seed layer 130 becomes the electrode in the subsequent process, namely the electroplating process. There are no particular limitations on the conductive material used in the seed layer 130.
[0103] (Electroplating process)
[0104] Figure 3H This diagram shows the state in which an electrode layer 132 is formed in the third recess 94, etc. In the electroplating process, the seed layer 130 formed in the seed sputtering process is used as an electrode for electroplating. Through this electroplating, the plated electrode layer 132 is formed inside the third recess 94 and on the surface 82 of the resin film. The material of the plated electrode layer 132 is not particularly limited. The material of the plated electrode layer 132 can be, for example, copper or solder. The material of the plated electrode layer 132 preferably includes at least solder. Furthermore, the method of filling the third recess 94 with conductive material is not limited to plating. For example, conductive material can also be filled into the third recess 94 by printing conductive paste, etc.
[0105] As mentioned above, Figure 1 The columnar metal electrode 54 shown is formed by filling the third recess 94, i.e., the via, formed in the resin film 80. The method for forming this columnar metal electrode 54 is not particularly limited as long as it involves filling the via. Methods include forming it using metal paste, forming it using electroless plating, and forming it using electrolytic plating. In this embodiment, electrolytic plating is described as an example. In the case of electrolytic plating, a seed layer made of metal is formed on the surface of the resin film 80 where the via is formed and inside the via. Then, based on this seed layer, electrolytic plating is performed by applying an electric current until the via is filled. The method and material for forming the seed layer are not particularly limited; methods include sequentially forming a Ti layer and a copper layer by sputtering.
[0106] (CMP planarization process)
[0107] Figure 3IThis diagram shows the state in which the surface 82 of the resin film 80, which serves as the surface of the resin film 80, is planarized. In the CMP (Chemical Mechanical Polishing) planarization process, the surface of the resin film 80, etc., is planarized. In the planarization process, not only CMP but also a cutting tool can be used. A metal layer, namely the plated electrode layer 132, formed by electrolytic plating, is also formed on the surface of the resin film 80, and is therefore removed by CMP treatment (CMP planarization process). During polishing, the thickness of the polishing layer is adjusted in a way that achieves the shape of the columnar metal electrode 54 described earlier. Through this polishing, it is possible to achieve… Figure 3I The components shown are joined by mixed bonding with other components having the same planarized resin film surface 82. Furthermore, when two components are mixed bonded, it is preferable that the materials of their respective resin films 80 are the same. In this planarization process, grinding is performed such that the length 261 is greater than or equal to the arrangement spacing 201. This length 261 is the axial length from the portion connecting to the first main surface 14, which is a main surface of the semiconductor device, to the resin film surface 82, which is the grinding finish surface, and the deposited electrode layer 132, which is to become the columnar metal electrode 54. Alternatively, grinding is performed such that the length 261 is greater than or equal to the area equivalent diameter of the cross-section of the deposited electrode layer 132, which is to become the columnar metal electrode 54.
[0108] (Jointing process)
[0109] Figure 3J This diagram illustrates the state in which the semiconductor device 10 and the wiring device 30 are joined. During the joining process, the components having the same... Figure 3I After aligning the same resin film 80 and other components, including the electrode layer 132, with the semiconductor device 10 shown, flip-chip bonding is performed. Figure 3J The image shows the state in which the semiconductor device 10 and the wiring device 30 are joined together.
[0110] The resin film 80 of the semiconductor device 10 and the resin film 80 of the wiring device 30 are bonded to each other on their respective resin film surfaces 82. Additionally, the plated electrode layer 132 of the semiconductor device 10 and the plated electrode layer 132 of the wiring device 30 are bonded together.
[0111] A connection portion 50 is formed by bonding the resin film 80 of the semiconductor device 10 and the resin film 80 of the wiring device 30, and by bonding the plated electrode layer 132 of the semiconductor device 10 and the plated electrode layer 132 of the wiring device 30. More specifically, the resin film 80 of the semiconductor device 10 and the resin film 80 of the wiring device 30 are bonded to form a resin portion 52 of the connection portion 50. Preferably, the resin film 80 of the semiconductor device 10 and the resin film 80 of the wiring device 30 are bonded by hybrid bonding. The plated electrode layer 132 of the semiconductor device 10 and the plated electrode layer 132 of the wiring device 30 are bonded to form a columnar metal electrode 54.
[0112] The above bonding process will be explained in detail. To achieve gap-free bonding between semiconductor wafers, semiconductor chips, and semiconductor chips and wafers, the surface of the resin film 80 requires high smoothness. When the arithmetic mean roughness Ra of the resin film surface, as measured by atomic force microscopy, is less than 1 nm, the occurrence of voids during bonding is easily suppressed. Furthermore, when Ra is less than 0.5 nm, even bonding under low pressure easily suppresses the occurrence of voids.
[0113] When bonding semiconductor wafers together, the alignment of opposing columnar metal electrodes can be performed with high precision using a wafer bonding apparatus. When bonding semiconductor chips together or between semiconductor chips and semiconductor wafers, high-precision alignment can be achieved using a flip-chip bonder.
[0114] The manufacturing method described above can be modified in various ways. For example, in the above description, a single plated electrode layer 132 is formed in the third recess 94. Multiple electrode layers 132 can also be formed in the third recess 94. For example, two types of electrode layers can be formed sequentially in the axial direction 101 starting from the first main surface 14. In this case, the layer in contact with the main surface corresponds to the previously referenced layer. Figure 1 The first electrode portion 61 or the second electrode portion 62 is described. Furthermore, another layer is positioned corresponding to the third electrode portion 63. Thus, it is possible to form... Figure 1 The illustrated columnar metal electrode 54 has a first electrode portion 61, a second electrode portion 62, and a third electrode portion 63. In this case, the third electrode portion 63 is formed by aligning the electrode layers of one of the electrodes being joined with the electrode layers of the other electrode being joined.
[0115] When multiple electrode layers 132 are formed in the third recess 94, one layer in contact with the main surface can be formed with copper, and the remaining layer can be formed with solder. Thus, the columnar metal electrode 54 can be formed, i.e., the electrodes can be connected to each other, using soldering processes such as reflow.
[0116] Specifically, in order to form a solder layer at the tip of the columnar metal within the third recess 94, a copper layer located below the solder layer is formed first during electroplating. The thickness of the copper layer within the via (third recess 94) is left below the depth of the via layer before electroplating of the solder layer is performed. By setting (copper layer thickness) = (via depth) - (desired solder layer thickness), the necessary copper layer thickness can be obtained. A solder layer thickness of 3 μm or more allows for sufficiently strong soldering, and is therefore preferred.
[0117] Furthermore, during the aforementioned bonding process, after aligning the components to be bonded, pressure is applied at a temperature below the melting temperature of the solder, followed by heating to a temperature above the melting temperature of the solder. The bonded pair of columnar metal electrode layers can be formed either at the front end of only one side or at the front ends of both sides. When heating below the melting point of the solder, if the heating is performed at a temperature above the glass transition temperature of the resin film, voids are less likely to occur, and the resin surrounding the columnar metal electrode layers is more easily deformed in the film thickness direction, i.e., in the direction of the height of the column, making bonding between the columnar metal electrode layers easier, which is therefore preferred.
[0118] One aspect of the semiconductor device 1 described above is as follows. Specifically, one important method for increasing the performance of semiconductor systems is to use a semiconductor packaging structure that increases the bandwidth of signal transmission between semiconductor chips, such as logic semiconductor chips and memory semiconductor chips. To increase the bandwidth of signal transmission, methods include increasing the transmission rate of each signal line and increasing the number of signal lines. Shortening the length of signal lines to reduce signal transmission losses is effective in increasing the transmission rate of each signal line. Furthermore, a three-dimensional stacked semiconductor chip structure is effective for this purpose. As a way to increase the number of signal lines, making the signal lines thinner and reducing the spacing between signal lines is effective. Microbump technology is effective as a method for three-dimensionally stacked semiconductor chips, thinning signal wiring, and reducing the spacing between signal lines. This technology uses columnar electrodes made of metal with small cross-sectional areas and short lengths to electrically connect three-dimensionally stacked semiconductor chips. Copper, solder, and structures with solder formed at the front end of the copper can be used as columnar metal electrodes. Copper-to-copper bonding requires temperatures above 350°C, making the use of solder materials in columnar metal electrodes effective. However, when using temperatures above 350°C, problems may arise such as damage to semiconductor performance, exceeding the heat resistance limits of the materials used, or increased warpage of the semiconductor package.
[0119] In the bonding process using solder material on electrodes, a step is taken to temporarily melt the solder material. Therefore, when the spacing between bump electrodes is narrow, there is a risk of short circuits between adjacent columnar metal electrodes caused by the solder material. To prevent this, a work method that pre-fills the spaces between the columnar metal electrodes with an insulating resin material before bonding the semiconductor chips is effective. In this work method, it is important to cure the insulating resin material before bonding to prevent it from flowing during bonding. Furthermore, since not only the columnar metal electrodes but also the insulating resin need to be bonded during the bonding process, the surface of the insulating resin needs to be smoothed before the bonding process.
[0120] By reducing the cross-sectional area of the columnar metal electrodes and configuring them at high density, the number of signal lines connecting semiconductor chips can be increased, thereby increasing the bandwidth.
[0121] The edge interface area of UCIe-1.0, the interface standard for chips, is 388.8 μm. With the 55 μm columnar metal electrode spacing of already practical technologies, 57 columns of electrodes are required from the edge of the chip to its interior. In contrast, by reducing the spacing to 5 μm or less, only 5 columns are needed, reducing the wiring length for inter-chip connections by more than 4 mm. This results in significantly lower power consumption and a substantial increase in the transmission rate per electrode. By reducing the electrode cross-sectional area to 30 square μm or less, connection failures due to positional misalignment during semiconductor chip bonding are less likely. Furthermore, reducing the electrode cross-sectional area to 20 square μm or less ensures sufficient spacing between the columnar metal electrodes and guarantees reliable insulation between them.
[0122] When the length of the columnar metal electrode of the semiconductor chip being bonded is 10 μm or more, the thickness of the insulating resin layer can be increased, thus increasing the absorption capacity of the bitten particles during the bonding of the semiconductor chip or semiconductor wafer. When the length of the columnar metal electrode of the semiconductor chip is 8 μm or more, it is easier to suppress the brittle deterioration of the columnar metal electrode caused by the mutual diffusion of solder material and copper.
[0123] When the resin contains at least one of polyimide, polybenzoxazole, and benzocyclobutene, it is less prone to degassing, deterioration, and peeling caused by heat applied during metal electrode bonding. Furthermore, semiconductor wafers or chips can be bonded under low pressure, so the glass transition temperature of the resin material is preferably below the melting point of the solder material.
[0124] As solder materials, metals such as Sn, Sn-Ag, Sn-Bi, Sn-Cu, and Sn-Ag-Cu alloys are preferred.
[0125] The method for manufacturing a semiconductor device disclosed herein (e.g., a method for manufacturing a semiconductor device in which two or more semiconductor chips are stacked, the semiconductor chips are electrically connected to each other via columnar metal electrodes containing solder material, the gaps between the semiconductor chips other than the columnar metal electrodes are filled with resin, the length / diameter of the columnar metal electrode is 4 or more, the closest spacing of the columnar metal electrodes is 5 μm or less, the cross-sectional area is 30 square μm or less, and the length is 10 μm or more) is not particularly limited, and can be achieved by: after forming a resin film on the surface of a semiconductor wafer or semiconductor chip, forming vias reaching the surface of the semiconductor wafer by dry etching, then fabricating metal electrodes by filling the vias with metal material, and then performing a planarization process on the surface of the resin film, and bonding the metal electrodes and the resin film to each other in such a way that the metal electrodes of both semiconductor wafers or semiconductor chips face each other.
[0126] (1) A semiconductor device is a flip-chip interconnect semiconductor device, wherein, It includes a semiconductor device, a wiring device, and a connection portion connecting the semiconductor device and the wiring device. The semiconductor device has a first main surface with a first electrode arranged at a spacing of less than 5 μm. The wiring device has a second main surface on which the second electrode is arranged at a spacing of less than 5 μm corresponding to the configuration spacing. The connection portion includes a columnar metal electrode connecting the first electrode of the semiconductor device and the second electrode of the wiring device, and a resin portion disposed around the columnar metal electrode. The columnar metal electrode is disposed at a spacing of 5 μm or less corresponding to the arrangement spacing. The area equivalent diameter of the cross-section orthogonal to the axial direction of the columnar metal electrode is smaller than the arrangement spacing. The axial length of the columnar metal electrode from the portion that contacts the first main surface to the portion that contacts the second main surface is more than twice the arrangement spacing.
[0127] (2) The manufacturing method of a semiconductor device includes: A process for preparing a semiconductor device having electrodes arranged on a main surface with a spacing of less than 5 μm; The process of forming an organic insulating film on a main surface of the semiconductor device; The process of hardening the organic insulating film; The process of forming holes at a spacing corresponding to the arrangement spacing of the electrodes by dry etching the organic insulating film on the electrodes; The process of filling the hole with metal to form a columnar metal electrode; and The process of aligning the semiconductor device with other wiring devices and connecting them via flip-chip interconnect.
[0128] (3) In the above-mentioned method for manufacturing semiconductor devices, In the process of forming the hole, the area equivalent diameter of the cross-section of the hole orthogonal to the axial direction is smaller than the arrangement spacing. In the process of forming the columnar metal electrode, the area equivalent diameter of the cross-section of the columnar metal electrode orthogonal to the axial direction is smaller than the arrangement spacing.
[0129] (4) In the above-mentioned method for manufacturing semiconductor devices, Between the metal filling process and the flip-chip interconnect process, there is a process of planarizing the organic insulating film formed on the main surface and the columnar metal electrode.
[0130] (5) In the above-mentioned method for manufacturing semiconductor devices, In the planarization process, the length is ground to be the length above the remaining arrangement spacing, which is the length in the axial direction of the columnar metal electrode from the portion that is in contact with one of the main surfaces of the semiconductor device to the grinding end surface.
[0131] (6) In the above-mentioned method for manufacturing a semiconductor device, In the planarization process, the length is ground to the equivalent diameter of the remaining cross-sectional area of the columnar metal electrode, which is the length in the axial direction from the portion that contacts one of the main surfaces of the semiconductor device to the grinding end surface.
[0132] (Explanation of reference numerals in the attached image)
[0133] 1: Semiconductor device; 10: Semiconductor apparatus; 11: Semiconductor apparatus; 12: First substrate; 14: First main surface; 16: First electrode; 30: Wiring device; 32: Second substrate; 34: Second main surface; 36: Second electrode; 50: Connecting portion; 52: Resin portion; 54: Columnar metal electrode; 56: Side surface; 60: Connecting terminal; 61: First electrode portion; 62: Second electrode portion; 63: Third electrode portion; 71: First through electrode; 72: Second through electrode; 80: Resin film; 82: Resin film surface; 84: Resist film; 90: First recess; 92: Second recess; 94: Third recess; 101: Axial direction; 102: Main surface direction; 130: Seed layer; 132: Electrode layer; 201: Configuration spacing; 205: Shortest length of resin part; 207: Outer diameter; 211: Axial length; 251: Spacing; 301: First wiring device; 302: Second wiring device; 311: Fifth main surface; 312: Sixth main surface; 321: Ninth main surface; 322: Tenth main surface; 501: First connecting part; 502: Second connecting part; 511: Third main surface; 512: Fourth main surface; 521: Seventh main surface; 522: Eighth main surface; 2071: First outer diameter; 2072: Second outer diameter; 2073: Reference outer diameter.
Claims
1. A semiconductor device with flip-chip interconnects, wherein, The semiconductor device includes a semiconductor device, a wiring device, and a connection portion connecting the semiconductor device and the wiring device. The semiconductor device has a first main surface with a first electrode arranged at a spacing of less than 5 μm. The wiring device has a second main surface on which the second electrode is arranged at a spacing of less than 5 μm corresponding to the configuration spacing. The connecting portion has a columnar metal electrode connecting the first electrode of the semiconductor device and the second electrode of the wiring device, and a resin portion disposed around the columnar metal electrode. The columnar metal electrode is disposed at a spacing of 5 μm or less corresponding to the arrangement spacing. The area equivalent diameter of the cross-section orthogonal to the axial direction of the columnar metal electrode is smaller than the arrangement spacing. The axial length of the columnar metal electrode from the portion that contacts the first main surface to the portion that contacts the second main surface is more than twice the arrangement spacing.
2. The semiconductor device according to claim 1, wherein, The cross-sectional area of the columnar metal electrode, orthogonal to the axial direction, is less than 30 square μm.
3. A method for manufacturing a semiconductor device, comprising: A process for preparing a semiconductor device having electrodes arranged on a main surface with a spacing of less than 5 μm; The process of forming an organic insulating film on a main surface of the semiconductor device; The process of hardening the organic insulating film; The process of forming holes at a spacing corresponding to the arrangement spacing of the electrodes by dry etching the organic insulating film on the electrodes; The process of filling the hole with metal to form a columnar metal electrode; and The process of aligning the semiconductor device with other wiring devices and connecting them via flip-chip interconnect.
4. The method for manufacturing a semiconductor device according to claim 3, wherein, In the process of forming the hole, the area equivalent diameter of the cross-section of the hole orthogonal to the axial direction is smaller than the arrangement spacing. In the process of forming the columnar metal electrode, the area equivalent diameter of the cross-section of the columnar metal electrode orthogonal to the axial direction is smaller than the arrangement spacing.
5. The method for manufacturing a semiconductor device according to claim 3 or 4, wherein, Between the process of filling the metal and the process of performing the flip chip connection, there is a planarization process that planarizes the organic insulating film formed on the one main surface and the columnar metal electrode.
6. The method for manufacturing a semiconductor device according to claim 5, wherein, In the planarization process, the length is ground to be the length above the remaining arrangement spacing, which is the length in the axial direction of the columnar metal electrode from the portion that is in contact with one of the main surfaces of the semiconductor device to the grinding end surface.
7. The method for manufacturing a semiconductor device according to claim 5, wherein, In the planarization process, the length is the length of the columnar metal electrode in the axial direction from the portion that contacts one of the main surfaces of the semiconductor device to the grinding end surface, plus the length of the area equivalent diameter of the remaining cross-section of the columnar metal electrode.
Citation Information
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Electronic apparatus
JP2019204818A