Method for controlling surface roughness of silicon wafer

Abstract

The method for controlling the surface roughness of a silicon wafer comprises the following steps: pretreating the surface of the silicon wafer; forming a photoetching pattern on the surface of the silicon wafer; etching the surface of the silicon wafer by using plasma etching or wet etching; chemically and mechanically polishing the surface of the etched silicon wafer; and cleaning the silicon wafer. The method realizes the accurate control of the surface roughness of the silicon wafer by combining the photoetching, etching and chemical mechanical polishing technologies.

Description

Technical Field

[0001] This invention relates to the field of semiconductor and photovoltaic cell manufacturing, and in particular to a method for controlling the surface roughness of silicon wafers. Background Technology

[0002] Silicon wafers are a critical material in the manufacture of semiconductor devices and photovoltaic cells. The surface roughness of silicon wafers is crucial to the electrical and optical performance of devices. Traditional methods for controlling silicon wafer surface roughness mainly rely on mechanical polishing or chemical etching, but these methods are difficult to achieve precise control and uniformity, leading to unstable device performance.

[0003] Therefore, there is an urgent need to provide an improved method for controlling the surface roughness of silicon wafers to overcome the above problems. Summary of the Invention

[0004] The purpose of this invention is to provide an improved method for controlling the surface roughness of silicon wafers. This method achieves precise control of the surface roughness of silicon wafers by combining photolithography, etching, and chemical mechanical polishing techniques.

[0005] To achieve the above objectives, the present invention provides a method for controlling the surface roughness of a silicon wafer, comprising the following steps:

[0006] Pre-treat the surface of the silicon wafer;

[0007] A photolithographic pattern is formed on the surface of the silicon wafer;

[0008] The surface of the silicon wafer is etched using plasma etching or wet etching.

[0009] The surface of the etched silicon wafer is subjected to chemical mechanical polishing; and

[0010] Clean the silicon wafer.

[0011] Compared to existing technologies, this invention first pre-treats the silicon wafer surface, combining photolithography, etching, and chemical mechanical polishing techniques to create a uniform roughness on the silicon wafer surface, thereby precisely controlling roughness, size, and distribution. This method can improve the conversion efficiency of photovoltaic cells, reduce leakage current in semiconductor devices, and improve the overall performance and reliability of the devices.

[0012] Preferably, the pretreatment includes chemical cleaning of the silicon wafer.

[0013] Preferably, the chemical cleaning includes immersion in an acidic solution.

[0014] Preferably, the formation of the photolithographic pattern includes: forming a positive or negative photoresist on the surface of the silicon wafer, and performing exposure and development processes.

[0015] Preferably, the plasma etching includes: controlling the operating power to be 100-500W, the chamber pressure to be 5-20Pa, and the etching time to be 5-20 minutes.

[0016] Preferably, the wet etching process includes controlling the temperature of the etching solution to be 25-45°C and the etching time to be 5-20 minutes.

[0017] Preferably, the concentration of the etching solution is controlled to be 5-15%.

[0018] Preferably, the chemical mechanical polishing includes: using a polishing slurry and a polishing pad, controlling the polishing pressure at 5-20 psi, and controlling the polishing time at 30-60 minutes.

[0019] Preferably, the polishing solution is potassium hydroxide or hydrogen peroxide.

[0020] Preferably, the polishing pad is polyurethane or cerium oxide. Detailed Implementation

[0021] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific implementation methods of this application are described in detail below with reference to some embodiments. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0022] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0023] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0024] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0025] The method for controlling the surface roughness of silicon wafers according to the present invention will be further described below with reference to embodiments, but this does not limit the present invention. The method of the present invention aims to provide an improved method for controlling the surface roughness of silicon wafers, which achieves precise control of the surface roughness of silicon wafers by combining photolithography, etching and chemical mechanical polishing techniques.

[0026] In one embodiment of the method for controlling the surface roughness of a silicon wafer according to the present invention, the method includes the following steps:

[0027] Pre-treat the surface of the silicon wafer;

[0028] A photolithographic pattern is formed on the surface of the silicon wafer;

[0029] The surface of the silicon wafer is etched using plasma etching or wet etching.

[0030] The surface of the etched silicon wafer is subjected to chemical mechanical polishing; and

[0031] Clean the silicon wafer.

[0032] This invention first pre-treats the silicon wafer surface, combining photolithography, etching, and chemical mechanical polishing techniques to create a uniform roughness on the silicon wafer surface, thereby precisely controlling the roughness, size, and distribution. This method can improve the conversion efficiency of photovoltaic cells, reduce leakage current in semiconductor devices, and improve the overall performance and reliability of the devices.

[0033] In one specific embodiment, the silicon wafer is first pretreated, such as by chemical cleaning, to remove the oxide layer and impurities. For example, it is immersed in an acidic solution. Specifically, the acidic solution, such as hydrochloric acid or hydrofluoric acid, has a concentration of 5-10%, a temperature of 25-40°C, and an immersion time of 5-15 minutes.

[0034] In a preferred embodiment, an ultrasonic cleaning step is added after chemical cleaning to remove stubborn organic impurities.

[0035] In a more preferred embodiment, the silicon wafer can be further passivated, such as by using phosphoric acid or boric acid, to meet the needs of different silicon wafer materials.

[0036] Next, photolithography is performed. Specifically, photolithography is used to form a photolithographic pattern on the surface of the silicon wafer. The pattern type and size are designed according to the required roughness. The formation of the photolithographic pattern includes: forming positive or negative photoresist on the surface of the silicon wafer, and performing an exposure process. Specifically, the thickness of the photoresist is 100-500 nm, and the exposure dose used in the exposure process is 100-500 mJ / cm. 2 During the development process, select the appropriate developer and time according to the type of photoresist.

[0037] In a preferred embodiment, extreme ultraviolet lithography (EUVL) or electron beam lithography is combined to further improve patterning accuracy, making it suitable for roughness control in smaller dimensions.

[0038] In a more preferred embodiment, multilayer photoresist technology can be used to achieve more complex roughness structures by exposing and developing each layer sequentially.

[0039] Next, an etching process is performed, such as plasma etching or wet etching, to transfer the photoresist pattern to the silicon wafer surface. In one embodiment, plasma etching includes controlling the operating power to be 100-500W, the chamber pressure to be 5-20Pa, and the etching time to be 5-20 minutes. Preferably, argon or helium is used as the plasma gas to optimize the etching rate and selectivity. In one embodiment, wet etching includes controlling the temperature of the etching solution to be 25-45°C and the etching time to be 5-20 minutes. In one embodiment, the concentration of the etching solution is 5-15%. For example, the etching solution is a hydrofluoric acid solution.

[0040] Next, polishing is performed. Specifically, the surface of the etched silicon wafer is chemically and mechanically polished. As an example, a polishing slurry and polishing pad are used, with the polishing pressure controlled at 5-20 psi and the polishing time controlled at 30-60 minutes. Optionally, the polishing slurry is potassium hydroxide or hydrogen peroxide. The polishing pad is polyurethane or cerium oxide. Of course, other types of polishing slurries and polishing plates can also be used to improve polishing efficiency and surface quality. Preferably, the polishing parameters can be automatically adjusted by monitoring the surface roughness in real time during the polishing process.

[0041] Finally, the silicon wafer is cleaned. As an example, the surface of the silicon wafer is thoroughly cleaned with deionized water to remove residual polishing fluid and impurities. For example, a water temperature of 25-40°C is used, and the cleaning time is 5-10 minutes.

[0042] After the above process, the roughness of the bottom of the silicon wafer is controlled with nanometer-level precision, the surface is uniform and consistent, and there is no obvious damage, which meets the requirements of high-performance semiconductor devices and photovoltaic cells.

[0043] In summary, this invention first pre-treats the silicon wafer surface, combining photolithography, etching, and chemical mechanical polishing techniques to form a uniform roughness on the silicon wafer surface, thereby precisely controlling the roughness, size, and distribution. This method can improve the conversion efficiency of photovoltaic cells, reduce leakage current in semiconductor devices, and improve the overall performance and reliability of the devices.

[0044] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for controlling the surface roughness of a silicon wafer, characterized in that, Includes the following steps: Pre-treat the surface of the silicon wafer; A photolithographic pattern is formed on the surface of the silicon wafer; The surface of the silicon wafer is etched using plasma etching or wet etching. The surface of the etched silicon wafer is then subjected to chemical mechanical polishing. as well as Clean the silicon wafer.

2. The method for controlling the surface roughness of a silicon wafer as described in claim 1, characterized in that, The pretreatment includes chemically cleaning the silicon wafer.

3. The method for controlling the surface roughness of a silicon wafer as described in claim 2, characterized in that, The chemical cleaning includes soaking in an acidic solution.

4. The method for controlling the surface roughness of a silicon wafer as described in claim 1, characterized in that, The formation of the photolithography pattern includes: forming positive or negative photoresist on the surface of the silicon wafer, and performing exposure and development processes.

5. The method for controlling the surface roughness of a silicon wafer as described in claim 1, characterized in that, The plasma etching process includes controlling the operating power to be 100-500W, the chamber pressure to be 5-20Pa, and the etching time to be 5-20 minutes.

6. The method for controlling the surface roughness of a silicon wafer as described in claim 1, characterized in that, The wet etching process includes controlling the temperature of the etching solution to 25-45℃ and the etching time to 5-20 minutes.

7. The method for controlling the surface roughness of a silicon wafer as described in claim 6, characterized in that: The concentration of the etching solution is controlled to be 5-15%.

8. The method for controlling the surface roughness of a silicon wafer as described in claim 1, characterized in that: The chemical mechanical polishing includes: using polishing fluid and polishing pads, controlling the polishing pressure at 5-20 psi, and controlling the polishing time at 30-60 minutes.

9. The method for controlling the surface roughness of a silicon wafer as described in claim 8, characterized in that: The polishing solution is potassium hydroxide or hydrogen peroxide.

10. The method for controlling the surface roughness of a silicon wafer as described in claim 8, characterized in that: The polishing pad is made of polyurethane or cerium oxide.