Wafer edge profile correction and polishing integrated processing technology and device

Abstract

The present application relates to the technical field of semiconductor material manufacturing, and particularly relates to wafer edge profile correction and polishing integrated processing technology, characterized by comprising the following steps: step 1: conveying a wafer to be processed to a processing platform; step 2: performing 360-degree scanning on the wafer edge to obtain multiple sets of diameter data, calculating the ellipticity, eccentricity and edge profile three-dimensional model of the wafer; step 3: processing the wafer edge after chamfer station correction, performing elliptical correction; adjusting the wafer position to eliminate the eccentricity; step 4: conveying the corrected wafer to an edge etching module, adjusting the chamber temperature through a temperature control assembly according to a preset etching width to control the etching gap; injecting etching liquid to selectively etch the wafer edge; step 5: sequentially performing rough polishing and fine polishing on the etched wafer; step 6: cleaning and drying; step 7: detecting the processed wafer edge and feeding the measurement result back to a central control system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor material manufacturing technology, and in particular to an integrated process and apparatus for wafer edge contour correction and polishing. Background Technology

[0002] In semiconductor manufacturing, wafer edge treatment is a crucial yet easily overlooked step. As technology nodes continue to shrink, the uniformity, flatness, and non-damaging nature of wafer edges have an increasingly significant impact on the yield of subsequent processes. Currently, wafer edge treatment mainly faces the following technical bottlenecks: Elliptical deformation problem: Wafers are prone to elliptical deformation during the rolling process, which can lead to alignment deviations in subsequent photolithography and etching processes, affecting the consistency of chip performance.

[0003] Uneven edge etching: In traditional wet etching processes, it is difficult to control the uniformity of the etching width at the wafer edge. The difference between the maximum and minimum etching width often exceeds 0.1 mm, which cannot meet the requirements of high-end processes.

[0004] Inconsistent surface roughness in edge polishing: Existing edge polishing equipment is difficult to meet the edge polishing requirements of different types of semiconductor silicon wafers at the same time. The surface roughness is inconsistent after polishing, which affects the quality of the front and back surfaces of the wafer.

[0005] Low process integration: Existing edge processing is mostly an independent process, which is not well integrated with mainstream planarization processes such as CMP, increasing the number of process steps and the risk of wafer contamination. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide an integrated process and apparatus for wafer edge contour correction and polishing.

[0007] The technical solution of the present invention is as follows: The integrated wafer edge contour correction and polishing process includes the following steps: Step 1: Wafer Loading and Pre-alignment The wafer to be processed is transferred to the processing platform to complete the initial position correction and positioning of the wafer; Step 2: Online measurement of edge contour The multi-angle laser scanning system is activated to perform a 360-degree scan on the edge of the wafer, acquiring radial contour data sets in multiple angular directions along the circumference. Each radial contour data set consists of three-dimensional coordinate data of multiple sampling points along the radial direction from one side of the wafer to the other. Based on the obtained radial profile data set, the ellipticity, eccentricity, and edge profile three-dimensional model of the wafer are calculated. Step 3: Ellipse Correction and Contouring Before processing, the chamfering table records the X, Y, and Z axis coordinates. After the chamfering table rotates one revolution, the X, Y, and Z axis coordinates are recorded at this time. The machine automatically calculates the difference and corrects it if there is any, so as to correct the ellipse of the product and eliminate the eccentricity. Step 4: Precise Edge Etching The corrected wafer is transferred to the edge etching module and clamped in the middle of the closed chamber formed by the upper and lower cavities. The closed chamber only leaves a ring-shaped slit at the outer edge of the wafer as an etching gap. Based on the preset etching width, the temperature of the etching solution is precisely controlled by the temperature control component to stabilize the etching rate. Combined with precise time control, the selective etching width of the wafer edge is precisely controlled within the etching gap. Step 5: Polishing the Sequence Edges After etching, the wafer enters the edge polishing station, where it undergoes rough polishing and fine polishing in sequence. The edge polishing process parameters are adjusted by feedforward based on the edge contour data obtained in steps 2 and 3, so as to maintain contour accuracy while removing the damaged layer. Step 6: Washing and Drying Step 7: Online Detection and Feedback The edges of the processed wafers are inspected, and the measurement results are fed back to the central control system for process parameter optimization.

[0008] In a further proposed solution, in step 1, the wafer positioning accuracy is ±0.5mm.

[0009] In a further scheme, in step 2, at least 12 sets of radial profile data are acquired. To suppress measurement noise and interference from local defects, each radial profile data set is oversampled, with 10-12 sampling points configured.

[0010] In a further embodiment, in step 5, during the rough polishing process, diamond polishing fluid is used to rough polish the edges, V-grooves, and flat edges to remove the corrosion damage layer.

[0011] In a further embodiment, in step 5, during the fine polishing process, colloidal silica polishing slurry is used to finely polish the edges, V-grooves, and flat edges to obtain a mirror-like edge surface.

[0012] In a further embodiment, in step 6, megasonic cleaning is used to remove polishing residue particles, followed by isopropanol vapor drying to obtain a clean and dry surface.

[0013] The present invention also provides an apparatus for implementing the aforementioned processing technology, comprising a rack, multiple functional modules, and an integrated cleanroom transport system, wherein, The multiple functional modules are fixed on the frame and include a pre-alignment module, a multi-angle laser scanning measurement module, a chamfering stage module, an edge etching module, a sequential edge polishing module, a cleaning and drying module, and an online detection module for sequentially performing steps 1 to 7; each functional module is an independent unit that can be disassembled and replaced. The integrated clean transport system is installed between the functional modules and is used for automatic short-distance transfer of wafers between the modules to achieve continuous wafer transfer across processes.

[0014] In a further proposed solution, each functional module is equipped with standardized mechanical interfaces, standardized electrical interfaces, standardized fluid interfaces, and standardized communication interfaces of the same specifications. Functional modules of the same specifications can be replaced as a whole, and after disassembly and assembly, mechanical locking, power supply, fluid pipelines, and control signal docking can be completed synchronously through various standardized interfaces.

[0015] In a further embodiment, the integrated clean transport system includes a clean gripping robot.

[0016] In a further embodiment, the edge etching module has an openable upper cavity and a lower cavity, at least one of which is provided with an annular shielding protrusion; the upper and lower cavities are closed to form an independent sealed reaction chamber, the annular shielding protrusion shields the main area of ​​the wafer, and only an annular slit is formed at the outer edge of the wafer as an etching gap; the edge etching module is equipped with a temperature control component to regulate the temperature of the etching solution and the etching time. The beneficial effects of this invention are: The integrated design significantly reduces the number of times the wafer is transferred between different devices, thus reducing the risk of particulate contamination.

[0017] The intelligent compensation algorithm enables accurate prediction and compensation of wafer edge morphology, improving process consistency and yield. Specifically, step 2 involves a 360-degree scan of the wafer edge and calculation of ellipticity, eccentricity, and edge contour data, providing a precise measurement basis for processing. Step 3 uses a chamfering stage to record the coordinates before and after processing and automatically calculates and corrects for differences, achieving accurate compensation for wafer ellipticity deviations and improving process consistency and yield.

[0018] The modular design allows the device to be flexibly adapted to different wafer sizes (200mm / 300mm / 450mm) and process requirements.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below.

[0021] This embodiment provides an integrated wafer edge contour correction and polishing process, including the following steps: Step 1: Wafer Loading and Pre-alignment The wafers to be processed are transported to the processing platform by AGV carts or robotic arms, and coarse positioning is performed by a pre-alignment mechanism with a positioning accuracy of ±0.5mm.

[0022] Step 2: Online measurement of edge contour The multi-angle laser scanning system is activated to perform a 360-degree scan on the edge of the wafer, acquiring radial contour data sets in multiple angular directions along the circumference. Each radial contour data set consists of three-dimensional coordinate data of multiple sampling points along the radial direction from one side of the wafer to the other. Based on the obtained radial profile data set, the ellipticity, eccentricity and edge profile three-dimensional model of the wafer are calculated (the Y-axis and Z-axis data of the edge profile are added to the X-axis data of the diameter direction to synthesize the three-dimensional model). Step 3: Ellipse Correction and Contouring Before processing, the chamfering table records the X, Y, and Z axis coordinates. After the chamfering table rotates one revolution, the X, Y, and Z axis coordinates are recorded at this time. The machine automatically calculates the difference and corrects it if there is a difference, so as to correct the ellipse of the product and eliminate the eccentricity. This records the three-axis coordinates of the chamfering stage itself. The correction is that the grinding wafer remains stationary. Based on the ellipticity, eccentricity, and edge contour three-dimensional model obtained in step 2, the position of the chamfering stage is adjusted to the target position to perform chamfering on the wafer, so as to eliminate eccentricity and correct ellipticity, so as to achieve the purpose of processing the target contour on the chamfering stage.

[0023] Step 4: Precise Edge Etching The corrected wafer is transferred to the edge etching module, and the upper and lower chambers are closed to form a sealed processing space.

[0024] The temperature of the chamber is adjusted according to the preset corrosion width to control the corrosion gap.

[0025] Inject an etchant (such as a HF / HNO3 mixed solution) to selectively etch the wafer edges. The etching time is adjustable from 1 to 5 minutes.

[0026] Step 5: Polishing the Sequence Edges After etching, the wafer enters the edge polishing area, where the following processes are performed sequentially: Rough polishing: Use diamond polishing slurry (diamond grit size 5-10μm) to rough polish the edges, V-grooves and flat edges to remove the corrosion damage layer.

[0027] Fine polishing: Fine polishing is performed using colloidal silica polishing slurry (silica particle size 0.1-0.5μm) to obtain a mirror-like edge surface.

[0028] Step 6: Washing and Drying Megasonic cleaning technology was used to remove polishing residue particles, followed by isopropanol vapor drying to obtain a clean and dry surface.

[0029] Step 7: Online Detection and Feedback The edges of the processed wafer are detected using a white light interferometer, and the measurement results are fed back to the central control system for process parameter optimization.

[0030] The following table compares the effects of this invention with existing technologies: The integrated processing device for implementing the process described in this embodiment adopts a modular architecture. Its frame is a fully enclosed chamber with isolation valves (e.g., time-sharing isolation gate valves) at its inlet and outlet. Internally, it integrates a pre-alignment module, a multi-angle laser scanning measurement module, a chamfering stage module, an edge etching module, a sequential edge polishing module, and an online inspection module for sequentially executing steps 1-7. Each module is a functionally independent unit with standardized mechanical, electrical, fluid, and communication interfaces. Short-distance automatic wafer transfer is achieved between modules through an integrated clean transport system within the platform. The aforementioned modules and the transport system can directly utilize mature functional modules from existing wafer fabrication production lines. The internal mechanical, electrical control, and fluid structures of each module are conventional technologies in the field and will not be elaborated upon here.

[0031] In some embodiments, modules that require protection or maintenance of the process environment, such as edge etching modules and sequential edge polishing modules, adopt a closed structure with isolation valves (e.g., time-sharing isolation gate valves) at the inlet and outlet. Other modules may be equipped with isolation valves depending on process requirements.

[0032] This modular design allows for rapid switching between 200mm, 300mm, and 450mm wafers on the same platform by replacing or adjusting specific modules (such as platforms, fixtures, and corresponding piping adapted to different wafer sizes). In traditional processes, wafers need to be repeatedly loaded, unloaded, and transported over long distances between multiple independent devices. In contrast, this invention requires only one loading and one unloading. The wafer completes all processing and inspection steps within the controlled microenvironment inside the platform, significantly reducing the risk of particulate contamination from wafer exposure to the external environment and robotic gripping.

[0033] The entire process is completed with the support of a fully automated, unmanned transport system. It takes about 15-20 minutes to process a 300mm wafer, which is much shorter than the 45-60 minutes required for traditional multi-machine processing.

[0034] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.

Claims

1. An integrated process for wafer edge contour correction and polishing, characterized in that, Includes the following steps: Step 1: Wafer Loading and Pre-alignment The wafer to be processed is transferred to the processing platform to complete the initial position correction and positioning of the wafer; Step 2: Online measurement of edge contour The multi-angle laser scanning system is activated to perform a 360-degree scan of the wafer edge and acquire radial contour data sets in multiple angular directions along the circumference. Each radial contour data set consists of three-dimensional coordinate data of multiple sampling points along the radial direction from one side of the wafer to the other. Based on the obtained radial profile data set, the ellipticity, eccentricity, and edge profile three-dimensional model of the wafer are calculated. Step 3: Ellipse Correction and Contouring Before processing, the chamfering table records the X, Y, and Z axis coordinates. After the chamfering table rotates one revolution, the X, Y, and Z axis coordinates are recorded at this time. The machine automatically calculates the difference and corrects it if there is any, so as to correct the ellipse of the product and eliminate the eccentricity. Step 4: Precise Edge Etching The corrected wafer is transferred to the edge etching module and clamped in the middle of the closed chamber formed by the upper and lower cavities. The closed chamber only leaves a ring-shaped slit at the outer edge of the wafer as an etching gap. Based on the preset etching width, the temperature of the etching solution is precisely controlled by the temperature control component to stabilize the etching rate. Combined with precise time control, the selective etching width of the wafer edge is precisely controlled within the etching gap. Step 5: Polishing the Sequence Edges After etching, the wafer enters the edge polishing station, where it undergoes rough polishing and fine polishing in sequence. The process parameters for edge polishing are adjusted by feedforward based on the edge contour data obtained in steps 2 and 3, so as to maintain contour accuracy while removing the damaged layer. Step 6: Washing and Drying Step 7: Online Detection and Feedback The edges of the processed wafers are inspected, and the measurement results are fed back to the central control system for process parameter optimization.

2. The integrated wafer edge contour correction and polishing process according to claim 1, characterized in that, In step 1, the positioning accuracy of the wafer is ±0.5mm.

3. The integrated wafer edge contour correction and polishing process according to claim 1, characterized in that, In step 2, at least 12 radial profile data sets are acquired. To suppress measurement noise and interference from local defects, each radial profile data set is oversampled, with 10-12 sampling points configured.

4. The integrated wafer edge contour correction and polishing process according to claim 1, characterized in that, In step 5, during the rough polishing process, diamond polishing fluid is used to rough polish the edges, V-grooves, and flat edges to remove the corrosion damage layer.

5. The integrated wafer edge contour correction and polishing process according to claim 1, characterized in that, In step 5, during the fine polishing process, colloidal silica polishing slurry is used to fine polish the edges, V-grooves, and flat edges to obtain a mirror-like edge surface.

6. The integrated wafer edge contour correction and polishing process according to claim 1, characterized in that, In step 6, megasonic cleaning is used to remove polishing residue particles, followed by isopropanol vapor drying to obtain a clean and dry surface.

7. An apparatus for implementing the processing technology of any one of claims 1-6, characterized in that: It includes a rack, multiple functional modules, and an integrated cleanroom transport system, among which, The multiple functional modules are fixed on the frame and include a pre-alignment module, a multi-angle laser scanning measurement module, a chamfering stage module, an edge etching module, a sequential edge polishing module, a cleaning and drying module, and an online detection module for sequentially performing steps 1 to 7; each functional module is an independent unit that can be disassembled and replaced. The integrated clean transport system is installed between the functional modules and is used for automatic short-distance transfer of wafers between the modules to achieve continuous wafer transfer across processes.

8. The apparatus according to claim 7, characterized in that: Each functional module is equipped with standardized mechanical interfaces, standardized electrical interfaces, standardized fluid interfaces, and standardized communication interfaces of the same specifications. Functional modules of the same specifications can be replaced as a whole. After disassembly and assembly, mechanical locking, power supply, fluid pipelines, and control signal docking can be completed synchronously through various standardized interfaces.

9. The apparatus according to claim 7, characterized in that: The integrated clean transport system includes a clean gripping robot.

10. The apparatus according to claim 7, characterized in that: The edge etching module has an openable upper cavity and a lower cavity, and at least one of the upper cavity and the lower cavity is provided with an annular shielding protrusion; the upper and lower cavities are closed to form an independent sealed reaction chamber, and the annular shielding protrusion shields the main area of ​​the wafer, forming an annular slit only at the outer edge of the wafer as an etching gap; the edge etching module is equipped with a temperature control component to regulate the temperature of the etching solution and the etching time.

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