Tantalum-based superconducting quantum chip, preparation method thereof and surface treatment method

Abstract

The application discloses a tantalum-based superconducting quantum chip and a preparation method and a surface treatment method thereof. The surface treatment method comprises the following steps: removing an oxide layer on a tantalum film surface with a circuit pattern; and depositing in-situ tantalum nitride on the tantalum film surface by a magnetron sputtering method, wherein the thickness of the tantalum nitride is 2.5-3.5 nm. Through multiple mechanisms such as eliminating dielectric loss of an insulating layer, reducing interface TLS density, avoiding near-neighbor effect inhibition and improving interface order degree, the decoherence time of a quantum bit can be improved.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum chip technology, specifically to a tantalum-based superconducting quantum chip and its preparation and surface treatment methods. Background Technology

[0002] Tantalum-based superconducting quantum chips represent a breakthrough in the field of quantum computing in recent years. By replacing traditional aluminum or niobium with tantalum metal in the core circuitry of the chip, they significantly improve the performance and stability of qubits.

[0003] Superconducting quantum computing is one of the most promising technological pathways to practical quantum computing. The performance of its core information unit—the superconducting qubit—especially its decoherence time, directly determines the complexity and fidelity of quantum algorithms. However, the decoherence time of superconducting qubits has long been limited by the two-level system (TLS) defects present at the interface between the superconducting material and its surrounding environment (such as substrates, interface oxides, photoresist residues, etc.). These TLSs become energy dissipation channels, leading to quantum state decoherence.

[0004] To suppress TLS, the industry commonly employs passivation methods on the surface of superconducting materials. For high-performance α-phase tantalum (α-Ta) superconducting quantum circuits, the most common existing technique is to use a piranha solution (typically a mixture of concentrated sulfuric acid and hydrogen peroxide) to strongly oxidize the fabricated tantalum circuit, generating a tantalum pentoxide (Ta₂O₅) layer on its surface. This technique can passivate the surface to a certain extent, suppress TLS, and improve the decoherence time of qubits to the order of 500 microseconds, making it a standard process in this field.

[0005] However, in tantalum-based superconducting quantum chips, the oxide layer is a double-edged sword. It serves as a natural barrier to protect the circuitry, but it is also one of the main sources of noise that leads to information loss. As a wet chemical process, chemical oxidation still suffers from problems such as uncontrollable processes and low safety, limiting its application in large-scale mass production. Summary of the Invention

[0006] To address the aforementioned deficiencies in this field, this application aims to provide a tantalum-based superconducting quantum chip, its fabrication method, and its surface treatment method.

[0007] According to one aspect of this application, a surface treatment method for a tantalum-based superconducting quantum chip is provided, comprising: removing the oxide layer on the surface of a tantalum film having circuits, and depositing tantalum nitride in situ on the surface of the tantalum film by magnetron sputtering. The thickness of tantalum nitride is 2.5-3.5 nm.

[0008] According to some embodiments of this application, the gas used for in-situ deposition is a mixture of nitrogen (N2) and argon (Ar); optionally, the N2 partial pressure is 0.05 Pa ~ 0.2 Pa; optionally, it is 0.1 Pa. The Ar partial pressure is 0.5 Pa ~ 1.5 Pa; optionally, it is 0.8 Pa. The N2 to Ar gas ratio is 1:5 ~ 1:10; optionally, N2:Ar = 1:8. The sputtering power is 100 W ~ 200 W; optionally, it is 150 W. The deposition time is adjustable according to the required thickness, 5-30 seconds; optionally, it is 10 seconds.

[0009] According to another aspect of this application, a method for fabricating a tantalum-based superconducting quantum chip is also provided, comprising: A tantalum film is deposited on the first surface of the substrate, and a circuit pattern is prepared by exposure, development and etching processes. The oxide layer on the surface of the tantalum film was removed using an argon-ion back sputtering process; After removing the oxide layer, tantalum nitride is deposited in situ on the tantalum film surface by magnetron sputtering. Selective etching of tantalum nitride was used to fabricate a tantalum-based superconducting quantum chip. The thickness of tantalum nitride is 2.5-3.5 nm.

[0010] Optionally, the tantalum film is an α-phase tantalum film.

[0011] Optionally, the tantalum film thickness is 150-200 nm.

[0012] Optionally, the tantalum film thickness is 180 nm.

[0013] Optionally, the tantalum nitride thickness is 3 nm.

[0014] According to some embodiments of this application, the process parameters for removing the oxide layer on the surface of a tantalum film by argon ion backsputtering are as follows: the working gas is argon, the gas flow rate is 10-20 sccm; the process gas pressure is 0.5-1.0 Pa; the sputtering power is 120-180W; and the processing time is 3-10 s.

[0015] According to some embodiments of this application, in the process of in-situ deposition of tantalum nitride on the surface of a tantalum film using magnetron sputtering, the gas used is a mixture of nitrogen (N2) and argon (Ar). Optionally, N2 partial pressure: 0.05 Pa ~ 0.2 Pa; optionally 0.1 Pa. Ar partial pressure: 0.5 Pa ~ 1.5 Pa; optionally 0.8 Pa. N2 to Ar gas ratio: 1:5 ~ 1:10; optionally N2:Ar=1:8. Sputtering power: 100 W ~ 200 W; optionally 150 W. Deposition time: adjustable according to thickness requirements, 5-30 seconds; optionally 10 seconds.

[0016] According to another aspect of this application, a tantalum-based superconducting quantum chip prepared by the above-described preparation method is also provided. Attached Figure Description

[0017] Figure 1 This is a schematic flowchart illustrating the fabrication method of a tantalum-based superconducting quantum chip, which is an example embodiment of this application. Detailed Implementation

[0018] The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] Unless otherwise specified, this application is conducted under standard conditions or conditions recommended by the manufacturer. The raw materials or excipients used, as well as the reagents or instruments used, whose manufacturers are not specified, are all conventional products that can be obtained commercially.

[0021] The following is a detailed description of this application.

[0022] Currently, tantalum circuits are subjected to strong oxidation treatment using piranha solution (typically a mixture of concentrated sulfuric acid and hydrogen peroxide) to form a tantalum pentoxide (Ta₂O₅) layer on their surface. This technique can passivate the surface and suppress TLS to some extent, improving the decoherence time of qubits to the order of 500 microseconds, and has become a standard process in this field. However, the above technique has the following drawbacks and limitations: Poor process controllability leads to large performance fluctuations: The wet chemical oxidation process is severely affected by various factors such as ambient temperature, solution concentration, reaction time, and operating methods, making it difficult to precisely control the thickness and density of the generated Ta2O5 oxide layer. This directly results in significant fluctuations in the performance (decoherence time) of different batches and even different qubits on the same chip, leading to low yield, poor repeatability, and severely hindering the manufacturing of large-scale, consistent quantum chips.

[0023] The process has poor safety and poses high risks: the piranha solution reacts violently, releasing large amounts of heat and oxygen, while simultaneously generating highly explosive and toxic peroxysulfuric acid (H2SO5). This process poses a threat to the personal safety of operators (chemical burns, poisoning risks) and also presents laboratory safety hazards (explosion risks), failing to meet modern semiconductor manufacturing safety standards.

[0024] The oxide layer is non-superconducting and may introduce additional losses: Ta2O5 is an insulator, and in the extremely low temperature environment of mK where superconducting qubits operate, its interface with superconducting tantalum may introduce unexpected losses due to the proximity effect or other mechanisms, which in principle limits the potential for further improvement in decoherence time.

[0025] In particular, poor process controllability leads to large performance fluctuations, which is a core obstacle to improving the yield and consistency of quantum chip manufacturing.

[0026] To address the aforementioned technical issues, this application innovatively employs an in-situ nitriding process that replaces the unstable oxide layer with tantalum nitride. On the surface of the patterned tantalum superconducting circuit, a superconducting tantalum nitride (TaN) film with precisely controllable thickness is grown in situ as an encapsulation layer. By forming a superconducting-superconducting interface to replace the original superconducting-insulator interface, the issues of process controllability and safety are fundamentally resolved, and it is expected to more effectively suppress two-level system (TLS) losses.

[0027] Furthermore, this application controls the thickness of the tantalum nitride layer to be within the range of 3-5 nm, enabling tantalum nitride (TaN) to form a continuous and dense film on the surface of the tantalum film. Specifically, if the tantalum nitride thickness is too thin (<2.5 nm), a continuous and dense film cannot be formed, and it cannot replace the oxide layer; if it is too thick (>3.55 nm), the proximity effect will significantly suppress the superconducting bandgap of the underlying tantalum, thus compromising the performance of the qubit.

[0028] The preparation method in this application employs in-situ integration without breaking the vacuum, meaning that argon ion backsputtering and tantalum nitride deposition are carried out continuously in the same vacuum chamber. This combination ensures the immediate deposition of tantalum nitride on an atomically clean tantalum surface, avoiding oxidation and contamination from any intermediate steps.

[0029] This application achieves a beneficial effect of improving decoherence time by more than 20% by controlling the thickness of tantalum nitride and depositing it on the tantalum surface by in-situ magnetron sputtering. It combines the physical and chemical states at the interface, the suppression effect on the two-level system (TLS), and the final effect on the coherence of qubits at extremely low temperatures (<20 mK). This successfully solves the dual technical problems of "uncontrollable process" and "performance bottleneck".

[0030] The technical solution of this application, such as Figure 1 As shown, a method for fabricating a tantalum-based superconducting quantum chip is provided, comprising: Figure 1 AB: A tantalum film (2) is deposited on the first surface of the substrate (1), and a circuit pattern (3) is prepared by exposure, development and etching processes; Figure 1 C: The oxide layer on the surface of the tantalum film is removed by argon ion back sputtering process (4). Figure 1 D: After removing the oxide layer, tantalum nitride is deposited in situ on the surface of the tantalum film (5). Figure 1 E: Selective etching of tantalum nitride (5) to obtain tantalum-based superconducting quantum chip (6); The thickness of tantalum nitride is 2.5-3.5 nm.

[0031] Optionally, the tantalum nitride thickness is 3 nm.

[0032] Optionally, the tantalum film is an α-phase tantalum film.

[0033] Optionally, the tantalum film thickness is 150-200 nm.

[0034] Optionally, the tantalum film thickness is 180 nm.

[0035] Optionally, in depositing a tantalum film on the first surface of the substrate, the process parameters are as follows: working gas: high-purity argon (Ar), flow rate 15-25 sccm; process pressure: 0.8-1.2 Pa; sputtering power: 120-180 W; deposition time: adjustable according to the target thickness; thickness: 150-200 nm. Further optional, gas: Ar 20 sccm; pressure: 1.0 Pa; power: 150 W; time: 2 min; thickness: 180 nm.

[0036] Optionally, the deposited tantalum film is in the α phase, exhibiting excellent superconducting properties. Sputtering power and gas pressure are controlled to ensure crystallization quality.

[0037] Optionally, the circuit pattern is prepared through exposure, development, and etching processes, including: spin-coating photoresist (such as S1813) at 2500-3500 rpm; pre-baking at 110-120℃ for 1-3 minutes; exposing the circuit pattern using laser direct writing or a photolithography machine; development using a developer (such as MF319) for 45-90 seconds to obtain a patterned photoresist mask; and etching the tantalum film areas not protected by the photoresist using reactive ion etching (RIE) technology with CF4 as the etching gas.

[0038] Further optional, photoresist: S1813 (3000 rpm); pre-baking: 115℃ / 2 min; development: MF319 / 1 min; RIE etching: CF4 flow rate 30 sccm, gas pressure 2 Pa, power 100 W, time 4 min.

[0039] Optionally, in removing the oxide layer on the surface of the tantalum film using argon-ion backsputtering, the process parameters are as follows: the working gas is argon, the gas flow rate is 10-20 sccm; the process gas pressure is 0.5-1.0 Pa; the sputtering power is 120-180 W; and the processing time is 3-10 s.

[0040] Further optionally, the gas is Ar 15 sccm; the pressure is 0.8 Pa; the power is 150 W; and the time is 5 s.

[0041] Alternatively, by physically bombarding and removing polymer residues and natural oxide layers remaining on the tantalum circuit surface after etching, an atomically clean and fresh tantalum surface is exposed, providing an ideal substrate for subsequent in-situ tantalum nitride deposition.

[0042] Optionally, during the in-situ deposition of tantalum nitride on the tantalum film surface, a mixture of nitrogen (N2) and argon (Ar) is used. Optionally, N2 partial pressure: 0.05 Pa ~ 0.2 Pa; optionally 0.1 Pa. Ar partial pressure: 0.5 Pa ~ 1.5 Pa; optionally 0.8 Pa. Gas ratio: 1:5 ~ 1:10; optionally N2:Ar=1:8. Sputtering power: 100 W ~ 200 W; optionally 150 W. Deposition time: adjustable according to thickness requirements, 5-30 seconds; optionally 10 seconds.

[0043] This step is performed in the same vacuum chamber as the previous steps, achieving "in-situ" preparation and avoiding re-oxidation of the surface upon contact with the atmosphere. By precisely controlling the N2 / Ar ratio, gas pressure, and power, atomically precise ultrathin TaN film growth can be achieved.

[0044] Alternatively, in specific applications, other chemically stable and electrically conductive noble metals (such as gold (Au), platinum (Pt), and palladium (Pd) may be used as alternatives to tantalum nitride. The advantage of noble metals lies in their extremely high chemical stability, but they are essentially normal metals, forming a superconducting-normal metal interface with superconducting tantalum at extremely low temperatures. The proximity effect induces a normal-state region on the tantalum surface, which, even when the metal film is controlled within an extremely thin range of 2.5–3.5 nm, still somewhat suppresses the superconducting bandgap of tantalum. In contrast, this application uses tantalum nitride, which is also in a superconducting state, to form a superconducting-superconducting interface, thus eliminating the adverse effects of the proximity effect in principle. Furthermore, the lattice matching between tantalum nitride and tantalum is superior to that between noble metals and tantalum, which is beneficial for obtaining an interface with lower defect density and theoretically allows for a longer decoherence time. Therefore, this application possesses unique theoretical advantages under extreme performance requirements.

[0045] In some instances, selective etching of tantalum nitride is used to remove redundant TaN layers deposited in non-circuit areas on the chip (such as pad areas and areas between circuits and ground), ensuring good electrical contact performance and insulation.

[0046] Optionally, the etching gas is CF4, with a flow rate of 30 sccm. Process gas pressure: 2 Pa. Etching power: 100 W. Time: 15 seconds.

[0047] Optionally, the etching selectivity ratio TaN:Ta > 3:1 is used to ensure that the tantalum nitride layer in the target area is completely removed without over-etching the underlying tantalum circuit body, and to preserve the TaN on the circuit sidewalls.

[0048] According to another aspect of this application, a surface treatment method for a tantalum-based superconducting quantum chip is also provided, comprising: removing the oxide layer on the surface of a tantalum film having circuits, and then depositing tantalum nitride in situ by magnetron sputtering. The thickness of tantalum nitride is 2.5-3.5 nm.

[0049] Optionally, during the in-situ deposition of tantalum nitride on the tantalum film surface, a mixture of nitrogen (N2) and argon (Ar) is used. Optionally, N2 partial pressure: 0.05 Pa ~ 0.2 Pa; optionally 0.1 Pa. Ar partial pressure: 0.5 Pa ~ 1.5 Pa; optionally 0.8 Pa. Gas ratio: 1:5 ~ 1:10; optionally N2:Ar=1:8. Sputtering power: 100 W ~ 200 W; optionally 150 W. Deposition time: adjustable according to thickness requirements, 5-30 seconds; optionally 10 seconds.

[0050] Compared with the existing technology that uses piranha solution to chemically oxidize tantalum pentoxide (Ta2O5) to form an insulating layer, this application selects tantalum nitride (TaN) as the passivation layer on the tantalum surface. This is fundamentally different in terms of material physical properties, interface electronic structure and device performance, and has one or more of the following beneficial effects.

[0051] I. Elimination of Loss Channels in Non-Superconducting Layers at Superconducting-Superconducting Interfaces In existing technologies, Ta₂O₅ is an insulator. At the extremely low temperatures (<20 mK) required for quantum chip operation, the superconducting-insulator interface formed by Ta₂O₅ and superconducting tantalum introduces various loss mechanisms: charge defects in the insulator can act as a source of two-level systems (TLS); electric field penetration at the interface induces quasi-particle states on the tantalum surface; furthermore, the dielectric loss of the insulator layer directly contributes to the energy relaxation channels of the qubit. These factors collectively limit further improvements in decoherence time (currently around 500 μs).

[0052] This application uses TaN as a passivation layer, whose superconducting transition temperature (Tc) is approximately 4.5 K, placing it in a superconducting state within the mK temperature range. Therefore, this application constructs a superconducting (α-Ta)–superconducting (TaN) interface. At this interface, there is no dielectric loss due to the insulating layer, no quasi-particle states induced by electric field penetration, and since both are superconductors, the TLS density at the interface is theoretically much lower than that at the superconducting–insulator interface. Physically, this application eliminates the main loss mechanism caused by the insulating layer in existing technologies, providing a theoretical basis for breakthroughs in decoherence time.

[0053] II. Lattice matching optimization of interface defect density Alpha-phase tantalum has a body-centered cubic (bcc) structure with a lattice constant of approximately 3.30 Å. TaN has a face-centered cubic (fcc) or hexagonal structure, and its lattice constant is similar to that of α-Ta within a certain composition range, with a lower lattice mismatch. In contrast, Ta₂O₅ has an amorphous or polycrystalline structure, and its interface with α-Ta contains numerous dangling bonds, oxygen vacancies, and structural defects, which are themselves the main source of TLS (lattice lattice mismatch).

[0054] In this application, TaN, like tantalum, belongs to the tantalum-based material system, and the chemical bonding between the interatomic atoms is more ordered, which is conducive to the formation of an atomically flat interface with low defect density. Theoretical analysis shows that the interfacial TLS density is positively correlated with the interfacial disorder, therefore this application can significantly reduce the energy relaxation rate caused by TLS.

[0055] III. Zero suppression of the nearest neighbor effect vs. the nearest neighbor effect loss of the insulating layer While existing Ta₂O₅ insulating layers do not directly suppress the superconducting bandgap of tantalum through the proximity effect, quasi-particle scattering and charge defects at the interface indirectly affect the superconducting state of the tantalum surface through Coulomb interactions. In this application, TaN is a superconductor with a similar superconducting bandgap to α-Ta (Δ ≈ 0.7-0.9 meV). When the two form a superconducting-superconducting interface, the proximity effect not only does not suppress superconductivity but may even enhance the superconducting coherence of the interface through bandgap coupling. This is a key physical characteristic that distinguishes this application from metal film schemes (superconducting-normal metal interfaces) and existing Ta₂O₅ schemes (superconducting-insulator interfaces).

[0056] IV. Breakthrough in Process Controllability: A Paradigm Shift from Wet to Dry Processes The core drawback of existing chemical oxidation methods lies in the uncontrollable process: factors such as the concentration, temperature, reaction time, and operation method of the piranha solution are difficult to control precisely, resulting in significant batch-to-batch differences in the thickness (usually fluctuating between a few nanometers and tens of nanometers), density, and stoichiometry of the Ta2O5 layer, which directly manifests as large fluctuations in the decoherence time of quantum bits (statistical deviations can reach more than ±20%).

[0057] This application employs reactive magnetron sputtering, where parameters such as the N2 / Ar ratio, partial pressure, sputtering power, and deposition time can be digitally set and monitored in real time. The TaN layer thickness can be controlled with an accuracy of ±0.5 nm, ensuring high consistency in composition and crystallinity. Performance fluctuations between devices can be controlled within ±5%, significantly improving yield.

[0058] V. Intrinsic Safety and Environmental Compatibility The existing technology uses a piranha solution that reacts violently, releasing large amounts of heat and oxygen, and generating highly explosive and toxic peroxysulfuric acid (H2SO5), posing risks of chemical burns, poisoning, and explosion to operators. This application completes the entire process within a vacuum chamber, without using any hazardous chemicals, eliminating safety hazards from the design stage and complying with modern semiconductor manufacturing safety regulations and environmental standards.

[0059] VI. Decoherence Time Based on the above analysis, this application utilizes multiple mechanisms, including eliminating dielectric loss in the insulating layer, reducing interface TLS density, avoiding nearest-neighbor effect suppression, and improving interface order, to increase the decoherence time of qubits from approximately 500 μs in existing technologies to over 600 μs, and can reach 700 μs under optimal process conditions. Compared to existing technologies, this represents an improvement of 20%–40%.

[0060] In some examples, this application also provides a tantalum-based superconducting quantum chip prepared by the above-described preparation method.

[0061] According to some example embodiments of this application, the above-described technical solutions of this application directly overcome the technical defects of existing chemical oxidation methods and produce one or more of the following technical effects: The problem of process controllability has been solved: by adopting vacuum reactive sputtering, process parameters (gas pressure, power, gas ratio, time) can be digitally and precisely controlled, realizing precise control of TaN layer thickness (±0.5 nm) and quality, which greatly improves the consistency and yield of chip performance and solves the problem of large performance fluctuations in existing technologies.

[0062] Safety risks have been eliminated: The entire process, especially the critical surface cleaning and nitriding steps, is completed in a vacuum environment, completely eliminating hazardous chemicals such as highly dangerous piranha solutions, making it inherently safe and compliant with semiconductor manufacturing safety standards.

[0063] The potential performance limit has been improved: a superconducting TaN layer (Tc≈4.5K) is used to form a superconducting-superconducting interface with the tantalum circuit at the mK temperature range where the qubit operates. This avoids the nearest neighbor effect loss that may be caused by non-superconducting insulators, and in principle, it makes it possible to significantly improve the decoherence time (expected >600 μs).

[0064] It has good compatibility and scalability: the process is fully compatible with standard semiconductor planar processes (such as photolithography, etching, sputtering), easy to integrate into existing superconducting quantum chip manufacturing processes, and suitable for wafer-level mass production.

[0065] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A surface treatment method for a tantalum-based superconducting quantum chip, characterized in that, include: Remove the oxide layer from the surface of the tantalum film containing the circuitry; as well as Tantalum nitride was deposited in situ on the surface of the tantalum film using magnetron sputtering. The thickness of the tantalum nitride is 2.5-3.5 nm.

2. The surface treatment method for a tantalum-based superconducting quantum chip according to claim 1, characterized in that, The gas used for the in-situ deposition of tantalum nitride is a mixture of nitrogen and argon. The partial pressure of N2 is 0.05 Pa to 0.2 Pa. Ar partial pressure: 0.5 Pa ~ 1.5 Pa; The gas ratio of N2 to Ar is 1:5 to 1:

10. Sputtering power: 100 W ~ 200 W; Deposition time: 5-30 seconds.

3. A method for fabricating a tantalum-based superconducting quantum chip, characterized in that, include: A tantalum film is deposited on the first surface of the substrate, and exposure, development and etching processes are performed sequentially to prepare the circuit pattern. The oxide layer on the surface of the tantalum film is removed by argon ion back sputtering. After removing the oxide layer, tantalum nitride is deposited in situ on the surface of the tantalum film; The tantalum nitride is selectively etched to obtain the tantalum-based superconducting quantum chip; The thickness of the tantalum nitride is 2.5-3.5 nm.

4. The method for fabricating a tantalum-based superconducting quantum chip according to claim 3, characterized in that, The tantalum film is an α-phase tantalum film.

5. The method for fabricating a tantalum-based superconducting quantum chip according to claim 3 or 4, characterized in that, The thickness of the tantalum film is 150-200 nm.

6. The method for fabricating a tantalum-based superconducting quantum chip according to claim 3 or 4, characterized in that, The tantalum film has a thickness of 180 nm.

7. The method for fabricating a tantalum-based superconducting quantum chip according to claim 3, characterized in that, The tantalum nitride has a thickness of 3 nm.

8. The method for fabricating a tantalum-based superconducting quantum chip according to claim 3, characterized in that, The process parameters for removing the oxide layer on the surface of the tantalum film using argon-ion backsputtering are as follows: the working gas is argon, the gas flow rate is 10-20 sccm, the process gas pressure is 0.5-1.0 Pa, the sputtering power is 120-180 W, and the processing time is 3-10 s.

9. The method for fabricating a tantalum-based superconducting quantum chip according to claim 3, characterized in that, During the in-situ deposition of tantalum nitride on the surface of the tantalum film, a mixture of nitrogen and argon is used. The partial pressure of N2 is 0.05 Pa to 0.2 Pa. Ar partial pressure: 0.5 Pa ~ 1.5 Pa; The gas ratio of N2 to Ar is 1:5 to 1:

10. Sputtering power: 100 W ~ 200 W; Deposition time: 5-30 seconds.

10. A tantalum-based superconducting quantum chip prepared by any one of the preparation methods described in claims 3-9.

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