Vibration-immune MEMS accelerometer ultra-low noise fast test system and method, noise screening system and method

Abstract

This invention provides a vibration-immune MEMS accelerometer ultra-low noise rapid testing system and method, as well as a noise screening system and method, relating to the field of noise detection circuit technology. It includes: an ultra-low noise power management module for providing multiple DC power supplies; a first, second, and third chip-under-test (DUT) interface for connecting three identical DUT chips respectively; a switching module for selecting two of the three DUT chips to connect to the system; a first-stage differential amplifier module for first differential amplification; an inter-stage high-pass filter module with a differential structure; and a second-stage differential amplifier module for second differential amplification, with the output connected to a spectrum analyzer. The advantages of this invention are that it can eliminate the effects of DC blocking capacitance and piezoelectric interference, suppress power frequency noise, and achieve common-mode vibration immunity.

Description

Technical Field

[0001] This invention relates to the field of noise detection circuit technology, and more specifically, to a vibration-immune MEMS accelerometer ultra-low noise rapid testing system and method, and a noise screening system and method. Background Technology

[0002] In the field of nanovolt (nV) and microvolt (μV) noise measurement, we conduct precise noise index testing for devices such as MEMS accelerometers, MEMS gyroscopes, low dropout linear regulators (LDOs), and voltage reference sources.

[0003] Noise testing typically requires measuring flicker noise in the 0.1Hz to 10Hz frequency range. Current technologies often involve connecting a large-capacity DC blocking capacitor in series with a high-gain amplifier at the output of the chip under test (DUT) for signal extraction. However, this approach has several drawbacks: the polarized molecules in the large-capacity capacitor experience slow internal polarization relaxation during charging and discharging, requiring 12–24 hours for the output voltage and leakage current to stabilize after power-on. This has a fatal impact on high-throughput testing in automated production testing (ATE) environments; the dielectric undergoes strain under weak mechanical vibration, injecting additional charge and contaminating the nV-level chip noise spectrum. In ordinary laboratory environments, spurious piezoelectric signals often exceed the actual chip noise by tens of times, leading to complete test failure; the leakage current (typically in the nanoamp range) of wet tantalum capacitors generates shot noise with a power density reaching several nV / √Hz, directly drowning out the weak noise signal of the DUT itself; and the DC blocking capacitor costs over ¥3000 and is bulky, occupying more than 50cm² of PCB space. Furthermore, to handle leakage current from large capacitors, traditional designs connect a bias resistor in parallel with ground to discharge the leakage current. If a large resistor (e.g., 100kΩ) is used to meet low-frequency cutoff requirements, the thermal noise generated by this resistor is much higher than the noise density of the chip under test itself. If a small resistor (e.g., 1.2kΩ) is used, the cutoff frequency of the RC high-pass filter needs to be reduced to 0.1Hz, requiring a 1300uF DC blocking capacitor. Moreover, the output impedance of different chips is unknown; for chips with higher impedance, a high-pass filter module formed by a large DC blocking capacitor and a small resistor cannot accurately test the chip's output voltage, resulting in significant testing errors. In addition, there are issues with power frequency interference and power supply coupling, the inability to separate individual noise in dual-chip differential testing, and extremely low production line efficiency for ultra-low noise chips.

[0004] Therefore, a new noise testing architecture is urgently needed to solve the above problems, and to eliminate the effects of DC blocking capacitance and piezoelectric interference, suppress power frequency noise, and achieve common mode vibration immunity without sacrificing any performance indicators. Summary of the Invention

[0005] The purpose of this invention is to provide a vibration-immune MEMS accelerometer ultra-low noise rapid testing system and method, and a noise screening system and method, which can eliminate the influence of DC blocking capacitance and piezoelectric interference, suppress power frequency noise, and achieve common-mode vibration immunity.

[0006] This invention is achieved through the following technical solution: A vibration-immune MEMS accelerometer ultra-low noise rapid testing system includes: Ultra-low noise power management module for providing multiple DC power supplies; The first, second, and third chip-under-test interfaces are used to connect three chips of the same model to the test. The switching module is used to select two out of the three chips under test to be connected to the system; The first-stage differential amplifier module is used to perform the first differential amplification. Its positive input terminal and negative input terminal are DC coupled to two chips under test selected by the switching module, and its output terminal is connected to the input terminal of the inter-stage high-pass filter module. The interstage high-pass filter module has a differential structure. The first end of the first branch is connected to the output of the first-stage differential amplifier module, and the second end of the first branch is connected to the negative input of the second-stage differential amplifier module. The first end of the second branch is grounded, and the second end of the second branch is connected to the positive input of the second-stage differential amplifier module. The second-stage differential amplifier module is used for the second differential amplification, and its output is connected to the spectrum analyzer.

[0007] Preferably, the ultra-low noise power management module includes a DC source and a chip power supply branch and an amplifier power supply branch connected to the DC source. The chip power supply branch is used to power the three chips under test, and the amplifier power supply branch is used to power the first-stage differential amplifier module and the second-stage differential amplifier module. The chip power supply branch includes at least two first linear regulators connected in series; The positive voltage power supply branch of the amplifier power supply branch includes at least two stages of second linear regulators connected in series; The negative voltage power supply branch of the amplifier power supply branch includes at least two stages of third linear regulators connected in series.

[0008] Preferably, the first branch and the second branch of the inter-stage high-pass filter module have the same structure, both including a piezoelectric capacitor and a resistor. The first and second ends of the piezoelectric capacitor are the input and output ends, respectively, and the second end of the piezoelectric capacitor is connected to the first end of the resistor, and the second end of the resistor is grounded.

[0009] Preferably, the resistance value of the resistor is... Voltage gain of the first-stage differential amplifier module The equivalent noise of the input of the second-stage differential amplifier module Satisfy the following expression: ; in, Boltzmann's constant, Absolute temperature The nominal noise of the chip under test. This means that the value to the left of the symbol is less than the value to the right and the difference is greater than a preset first threshold. The resistance value of the resistor The capacitance value of the piezoelectric-free capacitor and the cutoff frequency of the inter-stage high-pass filter module Satisfy the following expression: ; in, The value to the left of the symbol is greater than the value to the right, and the difference is greater than the preset second threshold.

[0010] Preferably, the lengths of the three input traces, the return path, and the layout of the key components of the first-stage differential amplifier module on the printed circuit board are mirror-symmetrical about the axis of symmetry.

[0011] This invention also provides a rapid testing method for ultra-low noise MEMS accelerometers with vibration immunity, based on the aforementioned rapid testing system for ultra-low noise MEMS accelerometers with vibration immunity, comprising the following steps: The switching module selects two chips under test to connect to the system and performs the following operations: The ultra-low noise power management module is used to perform multi-stage ripple suppression on the power supply paths of the chip under test, the first-stage differential amplifier module, and the second-stage differential amplifier module to achieve power supply. The input terminal of the first-stage differential amplifier module is shorted and connected to the interface of any chip under test to obtain the system noise floor. The positive and negative input terminals of the first-stage differential amplifier module are respectively connected to the two chips under test, and the noise is amplified in the first differential manner. The DC component is filtered out by the inter-stage high-pass filter module; The second-stage differential amplifier module amplifies the noise a second time and outputs it to the spectrum analyzer; The noise power spectral density collected by the spectrum analyzer is integrated in the frequency domain to obtain the total noise. After subtracting the system background noise in the power domain, the result is divided by the total system gain to obtain the superimposed noise result of the two chips under test. After obtaining the superimposed noise results of all pairwise combinations of the chips under test, the noise of each chip under test is separated by algebraic solution.

[0012] Preferably, the method for separating the noise of each chip under test by algebraic solution is as follows: Number the chip under test, and establish and solve the following equation: ; ; ; in, The result of the superimposed noise of the first and second chips under test connected to the system. The superimposed noise result for the second and third chips under test connected to the system. The superimposed noise result of the third chip under test and the first chip under test connected to the system. , and The noise levels are for the first, second, and third chips under test, respectively.

[0013] This invention also provides a vibration-immune MEMS accelerometer noise screening method, based on the noise separation results of the chip under test in the above-mentioned vibration-immune MEMS accelerometer ultra-low noise rapid testing method, and calibrating a reference noise according to the separated noise of each chip under test. The reference noise and a single chip to be screened are connected to the system, as follows: The reference noise is connected to one input terminal of the first-stage differential amplifier module, and the single chip to be screened is connected to the other input terminal of the first-stage differential amplifier module. The noise of a single chip to be screened is calculated based on the reference noise and the output of the second-stage differential amplifier module: The total noise is obtained by integrating the noise power spectral density acquired by the spectrum analyzer in the frequency domain. After subtracting the system background noise in the power domain, the result is divided by the total system gain to obtain the superimposed noise of the single chip to be screened and the reference noise. ; Calculate the noise of the single chip to be screened. : .

[0014] Preferably, the chip under test and the single chip to be screened are tested under the same environment.

[0015] This invention also provides a vibration-immune MEMS accelerometer noise screening system. Based on the above-mentioned vibration-immune MEMS accelerometer noise screening method, multiple circuits used in the vibration-immune MEMS accelerometer noise screening method are established to form a multi-channel screening circuit. Data is acquired from the multi-channel screening circuit through a multi-channel ADC. The acquired data is stored through an FPGA and transmitted to a host computer for judgment.

[0016] The technical solution of the present invention has at least the following advantages and beneficial effects: This invention utilizes two identical chips under test, directly connected to the positive and negative input terminals of the first-stage differential amplifier. The DC potential difference output by the two chips is used as a common-mode bias, eliminating the need for a large-capacity DC blocking capacitor at the input terminal. This significantly shortens the charging waiting time and eliminates the piezoelectric interference of the capacitor and the shot noise caused by its leakage current. This invention utilizes the high gain of the first-stage differential amplifier to significantly suppress the thermal noise of the resistor in the inter-stage high-pass filter module and the input noise of the second-stage differential amplifier after being referred to the input terminal. This solves the problems of high noise with large resistors and high cutoff frequency with small resistors, allowing the second-stage differential amplifier to be a low-cost amplifier, which can greatly reduce the system hardware cost. This invention is based on three chips under test. By switching modules, three pairwise combined measurements are performed. Then, through algebraic solution, the noise of each chip is accurately separated. The noise parameters of each chip can be separated without increasing the number of tests. This invention is based on a chip calibration component that isolates noise, which can quickly screen and detect noise in subsequent chips under test. It can also be expanded into a multi-channel testing device, greatly improving the testing efficiency on the production line. This invention is reasonably designed, has a simple structure, is cost-effective, and is easy to promote and implement. Attached Figure Description

[0017] Figure 1 This is a circuit connection diagram of the vibration-immune MEMS accelerometer ultra-low noise rapid testing system provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the circuit connection for calculating the noise of a single chip to be screened, provided in Embodiment 2 of the present invention. Figure 3 This is a connection diagram of the noise screening system provided in Embodiment 2 of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Example 1 This embodiment provides a vibration-immune MEMS accelerometer ultra-low noise rapid testing system. (See reference...) Figure 1 The red lines in the diagram (Noise1-Noise5) represent the noise at the corresponding nodes, including the following components: (1) An ultra-low noise power management module, used to provide multiple DC power supplies. The ultra-low noise power management module includes a DC source and a chip power supply branch connected to the DC source (corresponding to...). Figure 1 The circuit includes a DUT power supply branch and an amplifier power supply branch. The chip power supply branch is used to power the three chips under test, and the amplifier power supply branch is used to power the first-stage differential amplifier module and the second-stage differential amplifier module.

[0020] The chip power supply branch includes at least two series-connected first linear regulators VR1 with high power supply rejection ratio (PSRR) and low dropout voltage, preferably TPS7A89, to reduce the power frequency noise of the dual-channel chips under test from the source and reduce the difference in power frequency noise amplitude caused by the mismatch of the dual-channel PSRR.

[0021] The positive voltage power supply branch of the amplifier power supply includes at least two stages of a second linear regulator VR2 connected in series, the model used in this embodiment being LT1963; the negative voltage power supply branch of the amplifier power supply includes at least two stages of a third linear regulator VR3 connected in series, such as LT1964. The amplifier power supply branch is configured between the DC source and the power supply pins of the first-stage differential amplifier module / second-stage differential amplifier module, used to isolate the power frequency ripple in the external DC input power supply, preventing the power frequency ripple from coupling to the signal output terminal due to the amplifier's limited power supply rejection ratio (PSRR), thus compensating for the amplifier's own PSRR shortness in the power frequency band, ensuring that the output terminal remains "clean" at high gain, i.e., maintaining a low noise level, without relying on battery power. At the same time, by utilizing the dual-path symmetrical design and common-source power supply, the environmental power frequency interference is converted into a common-mode signal, which is actively canceled by the instrumentation amplifier's rejection ratio CMRR (>120dB), achieving a power frequency rejection of >120dB in an unshielded environment.

[0022] It should be noted that the ultra-low noise power management module can be replaced with a chemical battery to power the system.

[0023] (2) The first, second, and third test chip interfaces are used to connect three test chips of the same model, and are numbered as the first, second, and third test chips respectively according to their corresponding test chip interfaces (corresponding to...). Figure 1 (DUT1, DUT2, and DUT3 in the DUT).

[0024] (3) Switching module, used to select two of the three chips under test to be connected to the system.

[0025] The switching module in this embodiment is implemented using several switches: the first switch connects its first terminal to the interface of the first chip under test (DUT) and its second terminal to the positive input terminal of the first-stage differential amplifier module; the second switch connects its first terminal to the interface of the second DUT and its second terminal to the positive input terminal of the first-stage differential amplifier module; the third switch connects its first terminal to the interface of the second DUT and its second terminal to the negative input terminal of the first-stage differential amplifier module; and the fourth switch connects its first terminal to the interface of the third DUT and its second terminal to the negative input terminal of the first-stage differential amplifier module. By combining the closing and opening of these switches, the combination of connected DUTs can be selected. Each switch can be controlled by an FPGA or a microcontroller.

[0026] (4) The first-stage differential amplifier module is used to perform the first differential amplification. Its positive input terminal and negative input terminal are DC coupled to the two chips under test selected by the switching module, and its output terminal is connected to the input terminal of the inter-stage high-pass filter module.

[0027] It should be noted that the voltage gain of the first-stage differential amplifier module must simultaneously satisfy the following: (i) the first-stage differential amplifier module does not saturate due to the multiplication of the DC difference between the outputs of the two chips under test within the linear output range; (ii) the noise contribution of the resistive thermal noise of the inter-stage high-pass filter module and the equivalent noise of the second-stage differential amplifier module after being referred to the input terminal of the first stage is less than the nominal noise of the chip under test.

[0028] (5) Interstage high-pass filter module, which is a differential structure. The first end of the first branch is connected to the output end of the first stage differential amplifier module, the second end of the first branch is connected to the negative input end of the second stage differential amplifier module, the first end of the second branch is grounded, and the second end of the second branch is connected to the positive input end of the second stage differential amplifier module.

[0029] In this embodiment, the first branch and the second branch of the inter-stage high-pass filter module have the same structure, both including a piezoelectric capacitor and a resistor. The first and second ends of the piezoelectric capacitor are the input and output ends, respectively, and the second end of the piezoelectric capacitor is connected to the first end of the resistor, and the second end of the resistor is grounded.

[0030] (6) Second-stage differential amplifier module, used for second differential amplification, with the output terminal connected to the spectrum analyzer.

[0031] Based on the above solution, on the one hand, the resistance value of the resistor... Voltage gain of the first-stage differential amplifier module The equivalent noise of the input of the second-stage differential amplifier module Satisfy the following expression: ; in, Boltzmann's constant, Absolute temperature The nominal noise of the chip under test. This indicates that the value to the left of the symbol is less than the value to the right, and the difference is greater than a preset first threshold. This is due to the voltage gain of the first-stage differential amplifier module. The noise reduction suppression effect allows the second-stage differential amplifier module to use a low-cost amplifier with lower noise performance.

[0032] On the other hand, the resistance value of the resistor The capacitance value of the piezoelectric-free capacitor and the cutoff frequency of the inter-stage high-pass filter module Satisfy the following expression: ; in, The value to the left of the symbol is greater than the value to the right and the difference is greater than the preset second threshold. In other words, the resistance value must be much greater than the impedance of the DC blocking capacitor at the cutoff frequency.

[0033] The voltage gain of the first-stage differential amplifier module selected in this embodiment is... The frequency response is selected as 250x (optional model AD8429), which significantly suppresses the thermal noise of the resistors in the interstage high-pass filter module and the input noise of the second-stage differential amplifier after being referred to the input terminal; the resistor value is 35 kΩ, and the capacitance of the non-piezoelectric capacitor is 47 kΩ. For specific component selection, a standard 35kΩ resistor (thermal noise 24nV / √Hz) is used in conjunction with a small-capacity 47Ω resistor. Film capacitors (piezoelectric-free capacitors), preferably film capacitors such as polypropylene (PP) or polyester (PET) film capacitors, have a dielectric absorption coefficient <1% and leakage current <1nA, and do not generate additional charge injection under mechanical vibration. Compared to electrolytic capacitors (dielectric absorption >5%) and wet tantalum capacitors (which exhibit piezoelectric effects), film capacitors fundamentally eliminate interference with MEMS accelerometer test results. This setup can achieve extremely low cutoff frequencies (e.g., 0.0968Hz), while the resistive thermal noise referred to the input is only 24 / 100 = 0.096nV / √Hz, far lower than the noise of the chip itself. At this point, the cutoff frequency is... That is, about Depending on the cutoff frequency required for different tests, the resistor and capacitor values ​​can be modified; further increasing the resistor value can further reduce the cutoff frequency. The second-stage differential amplifier module can be the AD8421, whose gain... The total system gain is 20. .

[0034] The following is a verification of the gain reduction suppression principle. Total system noise. The calculation method is as follows: ; in, , and These are the noise levels of the first-stage differential amplifier module, the inter-stage high-pass filter module, and the second-stage differential amplifier module, respectively.

[0035] Substitute typical values ​​(assuming the noise density remains constant in the 10Hz-10kHz frequency band): (AD8429); (35kΩ@300K); (AD8421); ; calculate: ; As can be seen, the contribution of the subsequent stage (resistive thermal noise and noise of the second-stage differential amplifier module) is only 0.46%, which verifies the design principle of this embodiment.

[0036] In the above scheme, the first-stage differential amplifier module establishes the operating point using the common-mode DC level output by the first and second chips under test, and no series DC blocking capacitor is set between the input terminal of the first-stage differential amplifier module and the output terminal of the chip under test.

[0037] Finally, the lengths of the three input traces, the return path, and the layout of key components of the first-stage differential amplifier module on the printed circuit board are mirror-symmetrical about the axis of symmetry to improve common-mode rejection performance.

[0038] Example 2 This embodiment provides a rapid testing method for ultra-low noise MEMS accelerometers with vibration immunity. The method is based on a rapid testing system for ultra-low noise MEMS accelerometers with vibration immunity as described in the above embodiment, and includes the following steps: The switching module selects two chips under test to connect to the system and performs the following operations: Step S1: The ultra-low noise power management module is used to perform multi-stage ripple suppression on the power supply paths of the chip under test, the first-stage differential amplifier module, and the second-stage differential amplifier module to achieve power supply.

[0039] Step S2: Short-circuit the input terminal of the first-stage differential amplifier module and connect it to the interface of any chip under test to obtain the system noise floor.

[0040] Step S3: Connect the positive and negative input terminals of the first-stage differential amplifier module to the two chips under test respectively and perform first differential amplification on the noise.

[0041] Step S4: Filter out the DC component using the inter-stage high-pass filter module.

[0042] Step S5: The second-stage differential amplifier module amplifies the noise a second time and outputs it to the spectrum analyzer.

[0043] Step S6: Integrate the noise power spectral density collected by the spectrum analyzer in the frequency domain to obtain the total noise, and subtract the system background noise in the power domain and divide by the total system gain to obtain the superimposed noise result of the two chips under test.

[0044] The following are the data processing methods for spectrum analyzers: The noise power spectral density output by the spectrum analyzer is represented by discrete data points: The unit is dBm / Hz.

[0045] First, convert dBm to linear power: ; Then, perform trapezoidal numerical integration (in the power domain). For the spectrum range Perform a trapezoidal integral, and let the number of frequency points be . If the scanning range is 10kHz, then the interval between adjacent frequency points is... The total noise is obtained. : ; Next, the power domain subtracts the background noise. The noise after deducting the background noise is obtained.

[0046] ; Will Converted to spectrum analyzer input voltage , Given the input impedance of the spectrum analyzer, we obtain... : ; based on and total system gain The corresponding noise is calculated at the input of a single chip. : .

[0047] The following is a calculation example: Input parameter assumptions: System noise floor density: .

[0048] Total noise density under load (chip + system noise floor): .

[0049] Total system gain: .

[0050] Spectrum analyzer input impedance: .

[0051] System noise floor density dBm converted to linear power density (W / Hz) , The corresponding power density is obtained after converting the total noise density under load to linear power density. .

[0052] Bandwidth integration (to obtain total power W), assuming the noise density is flat, simplifies to density multiplied by bandwidth. Total noise level: System background noise density The total noise density under load is .

[0053] Power domain subtraction of background noise (the purpose is to obtain net power): .

[0054] Converted to RMS voltage at the input terminal of the spectrum analyzer. , .

[0055] When converted to the input of a single chip, due to the use of a dual-path differential architecture (signal source is...) (times), and the system gain is 5000. , .

[0056] Calculation results: Under these conditions of -90dBm noise floor and -70dBm load reading, the integrated noise of a single chip within a 10Hz-10kHz bandwidth is approximately 995nVrms. This result demonstrates that even with a significant 20dBm power spectral density variation in the spectrum analyzer, integrated noise signals below 1µV can still be accurately measured using the power subtraction method.

[0057] Step S7: After obtaining the superimposed noise results of all pairwise combinations of the chips under test, the noise of each chip under test is separated by algebraic solution as follows: Each chip under test is numbered, and the following equation is established and solved: ; ; ; in, The result of the superimposed noise of the first and second chips under test connected to the system. The superimposed noise result for the second and third chips under test connected to the system. The superimposed noise result of the third chip under test and the first chip under test connected to the system. , and These are the noise levels for the first, second, and third chips under test, respectively. The solution results are: .

[0058] It should be noted that the input noise of the first-stage differential amplifier module AD8429 is approximately After being magnified 5000 times, it is .exist The integral voltage within the bandwidth is approximately: Its corresponding power ( The system's noise floor level is around this order of magnitude.

[0059] The principle behind this step is that the intrinsic thermal noise and flicker noise (1 / f noise) within the three MEMS accelerometers under test (i.e., the three chips under test) are caused by the lattice thermal motion and carrier capture / release within their respective chips. Since these are three physically independent chips, their internal noise is completely uncorrelated in the time domain and statistically. According to random signal analysis theory, when two uncorrelated noise signals... and When the signals are input to the positive and negative input terminals of a differential amplifier, respectively, the variance of the differential output signal (i.e., noise power) is equal to the sum of the variances of the two signals. The common-mode noise caused by environmental mechanical vibration is canceled out by the high CMRR of the differential amplifier. To ensure separation accuracy, interference from the test system itself must first be eliminated. The system noise floor is denoted as... When the first and second chips under test are connected to the system for testing, since the chip noise is also uncorrelated with the system's background noise, the integral result of the total noise power spectral density (or variance) obtained by the acquisition system is... Satisfy the following equation: ; During the signal processing stage, this system rigorously subtracts the system's inherent noise in the power domain (rather than the voltage domain) to obtain the net noise power that is purely the sum of the noise from the two chips under test. : .

[0060] Based on the above physical model, the system changes the access combination by switching the matrix, and sequentially completes three pairwise differential measurements in a very short time (avoiding ambient temperature drift). After subtracting the system's background noise, a system of three linear equations in this embodiment can be established, namely: Net noise power of test group A (DUT1 & DUT2): (Equation 1); Net noise power of test group B (DUT2 & DUT3): (Equation 2); Net noise power of test group C (DUT3 & DUT1): (Equation 3); Solution method 1: Adding both sides of the equation, we can obtain twice the total noise power of the three chips.

[0061] The total noise power of the three chips is: (Equation 4); Solve separately Simply subtract (Equation 2) which does not include DUT1 from (Equation 4) (i.e. ): .

[0062] Taking the square root of both sides of the equation, we get... : .

[0063] Similarly, the exact solution can be obtained by utilizing cyclic symmetry. and : .

[0064] The noise calibration reference noise for each of the separated chips under test Then, noise screening can be performed according to the noise screening method for vibration-immunized MEMS accelerometers, specifically as follows: The noise calibration reference noise is determined based on the noise of each isolated chip under test. By connecting the reference noise and a single chip to be screened into the system, it can be referenced. Figure 2 The connection method involves connecting the calibration component corresponding to the reference noise to one input terminal of the first-stage differential amplifier module, and connecting a single chip to be screened (DUT_test2 to DUT_testN in the figure) to the other input terminal of the first-stage differential amplifier module. The noise of the single chip to be screened is calculated based on the reference noise and the output of the second-stage differential amplifier module.

[0065] The method for calculating the noise of a single chip to be screened is as follows: The total noise is obtained by integrating the noise power spectral density acquired by the spectrum analyzer in the frequency domain. After subtracting the system background noise in the power domain, the result is divided by the total system gain to obtain the superimposed noise of the single chip to be screened and the reference noise. ; Calculate the noise of the single chip to be screened. : .

[0066] The above scheme utilizes multi-stage power supply pre-stabilization and clean positive and negative power supplies to suppress ripple at the source. Combined with the dual-path differential architecture to suppress common-mode signals such as vibration and power frequency interference, and the high gain of the first stage to suppress noise in the subsequent stage, it achieves high signal-to-noise ratio measurement in an environment without shielding or vibration isolation table.

[0067] It should be noted that noise levels vary at different temperatures, and noise stability needs to be calibrated periodically to ensure accuracy. Therefore, the chip under test (DUT) and the single chip to be screened are tested under the same conditions. The noise testing method for a single chip to be screened can be used to test the noise value of any chip, but it must be ensured that the difference between the output voltage of the single chip to be screened and the output voltage of the calibration chip (i.e., the DUT corresponding to the reference noise) does not cause the first-stage differential amplifier module to saturate.

[0068] Furthermore, the circuitry connected during the vibration-immunized MEMS accelerometer noise screening method can be replicated to form a multi-channel vibration-immunized MEMS accelerometer noise screening system, for example, replicated to form 8-channel, 16-channel, or more channels. See [reference needed]. Figure 3Data is acquired through a multi-channel high-precision ADC, and the acquired data is stored in the FPGA and transmitted to the host computer for judgment.

[0069] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A vibration-immune MEMS accelerometer ultra-low noise rapid testing system, characterized in that, include: Ultra-low noise power management module for providing multiple DC power supplies; The first, second, and third chip-under-test interfaces are used to connect three chips of the same model to the test. The switching module is used to select two out of the three chips under test to be connected to the system; The first-stage differential amplifier module is used to perform the first differential amplification. Its positive input terminal and negative input terminal are DC coupled to two chips under test selected by the switching module, and its output terminal is connected to the input terminal of the inter-stage high-pass filter module. The interstage high-pass filter module has a differential structure. The first end of the first branch is connected to the output of the first-stage differential amplifier module, and the second end of the first branch is connected to the negative input of the second-stage differential amplifier module. The first end of the second branch is grounded, and the second end of the second branch is connected to the positive input of the second-stage differential amplifier module. The second-stage differential amplifier module is used for the second differential amplification, and its output is connected to the spectrum analyzer.

2. The vibration-immune MEMS accelerometer ultra-low noise rapid testing system according to claim 1, characterized in that, The ultra-low noise power management module includes a DC source and a chip power supply branch and an amplifier power supply branch connected to the DC source. The chip power supply branch is used to power the three chips under test, and the amplifier power supply branch is used to power the first-stage differential amplifier module and the second-stage differential amplifier module. The chip power supply branch includes at least two first linear regulators connected in series; The positive voltage power supply branch of the amplifier power supply branch includes at least two stages of second linear regulators connected in series; The negative voltage power supply branch of the amplifier power supply branch includes at least two stages of third linear regulators connected in series.

3. The vibration-immune MEMS accelerometer ultra-low noise rapid testing system according to claim 1, characterized in that, The first and second branches of the inter-stage high-pass filter module have the same structure, both including a piezoelectric capacitor and a resistor. The first and second ends of the piezoelectric capacitor are the input and output ends, respectively, and the second end of the piezoelectric capacitor is connected to the first end of the resistor, while the second end of the resistor is grounded.

4. The vibration-immune MEMS accelerometer ultra-low noise rapid testing system according to claim 3, characterized in that, The resistance value of the resistor Voltage gain of the first-stage differential amplifier module The equivalent noise of the input of the second-stage differential amplifier module Satisfy the following expression: ； in, Boltzmann's constant, Absolute temperature The nominal noise of the chip under test. This means that the value to the left of the symbol is less than the value to the right and the difference is greater than a preset first threshold. The resistance value of the resistor The capacitance value of the piezoelectric-free capacitor and the cutoff frequency of the inter-stage high-pass filter module Satisfy the following expression: ； in, The value to the left of the symbol is greater than the value to the right, and the difference is greater than the preset second threshold.

5. The vibration-immune MEMS accelerometer ultra-low noise rapid testing system according to claim 1, characterized in that, The lengths of the three input traces, return paths, and key component layouts of the first-stage differential amplifier module on the printed circuit board are mirror-symmetrical about the axis of symmetry.

6. A vibration-immune MEMS accelerometer ultra-low noise rapid testing method, based on the vibration-immune MEMS accelerometer ultra-low noise rapid testing system according to any one of claims 1-5, characterized in that, Includes the following steps: The switching module selects two chips under test to connect to the system and performs the following operations: The ultra-low noise power management module is used to perform multi-stage ripple suppression on the power supply paths of the chip under test, the first-stage differential amplifier module, and the second-stage differential amplifier module to achieve power supply. The input terminal of the first-stage differential amplifier module is shorted and connected to the interface of any chip under test to obtain the system noise floor. The positive and negative input terminals of the first-stage differential amplifier module are respectively connected to the two chips under test, and the noise is amplified in the first differential manner. The DC component is filtered out by the inter-stage high-pass filter module; The second-stage differential amplifier module amplifies the noise a second time and outputs it to the spectrum analyzer; The noise power spectral density collected by the spectrum analyzer is integrated in the frequency domain to obtain the total noise. After subtracting the system background noise in the power domain, the result is divided by the total system gain to obtain the superimposed noise result of the two chips under test. After obtaining the superimposed noise results of all pairwise combinations of the chips under test, the noise of each chip under test is separated by algebraic solution.

7. The vibration-immunized MEMS accelerometer ultra-low noise rapid testing method according to claim 6, characterized in that, The method for separating the noise of each chip under test by algebraic solution is as follows: Number the chip under test, and establish and solve the following equation: ； ； ； in, The result of the superimposed noise of the first and second chips under test connected to the system. The superimposed noise result for the second and third chips under test connected to the system. The superimposed noise result of the third chip under test and the first chip under test connected to the system. , and The noise levels are for the first, second, and third chips under test, respectively.

8. A vibration-immune MEMS accelerometer noise screening method, based on the noise separation result of the chip under test according to the vibration-immune MEMS accelerometer ultra-low noise rapid testing method according to any one of claims 6-7, characterized in that, The noise calibration reference noise is determined based on the noise of each isolated chip under test. The reference noise and a single chip to be screened are connected to the system, as follows: The reference noise is connected to one input terminal of the first-stage differential amplifier module, and the single chip to be screened is connected to the other input terminal of the first-stage differential amplifier module. The noise of a single chip to be screened is calculated based on the reference noise and the output of the second-stage differential amplifier module: The total noise is obtained by integrating the noise power spectral density acquired by the spectrum analyzer in the frequency domain. After subtracting the system background noise in the power domain, the result is divided by the total system gain to obtain the superimposed noise of the single chip to be screened and the reference noise. ; Calculate the noise of the single chip to be screened. : 。 9. The vibration-immunized MEMS accelerometer noise screening method according to claim 8, characterized in that, The chip under test and the single chip to be screened are tested under the same environment.

10. A vibration-immune MEMS accelerometer noise screening system, based on the vibration-immune MEMS accelerometer noise screening method as described in any one of claims 8-9, characterized in that, Multiple circuits for the vibration-immune MEMS accelerometer noise screening method are established to form a multi-channel screening circuit. Data is acquired from the multi-channel screening circuit through a multi-channel ADC. The acquired data is stored through an FPGA and transmitted to a host computer for judgment.

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