A full-symmetry differential photoelectric signal detection circuit and an adaptive control method thereof

Abstract

The application discloses a full-symmetry differential photoelectric signal detection circuit and an adaptive control method thereof, and relates to the technical field of photoelectric signal detection.The circuit comprises the following modules and corresponding connection relations: a photoelectric detector output end is connected to two opposite input ends of a symmetrical differential transimpedance amplification circuit, a digital gain adjustment circuit is in parallel connection between high-impedance input ends and output ends of the symmetrical differential transimpedance amplification circuit in a symmetrical structure, an output end of the symmetrical differential transimpedance amplification circuit is connected to a digital bias adjustment circuit, an output end of the digital bias adjustment circuit is connected to a two-stage differential amplification circuit, and an FPGA control module is in communication connection with the digital gain adjustment circuit and the digital bias adjustment circuit.The application realizes photoelectric signal measurement with a wide dynamic range, high linearity and strong anti-interference capability through a single circuit, and can be applied to precise photoelectric measurement scenes such as spectrum analysis, optical communication detection and weak light signal detection.

Description

Technical Field

[0001] This invention relates to the field of photoelectric signal detection technology, and in particular to a fully symmetrical differential photoelectric signal detection circuit and its adaptive control method. Background Technology

[0002] In photoelectric detection systems such as spectral analysis, optical communication detection, and weak light signal detection, the photoelectric signal detection circuit, as the interface circuit between the photoelectric detector and the subsequent signal processing module, directly determines the measurement accuracy and dynamic response performance of the entire system through its range adaptability, detection linearity, and operational stability.

[0003] Currently, photoelectric signal detection circuits mainly face the following technical challenges: First, the measured optical signals typically cover a wide dynamic range from nanowatts to milliwatts, while traditional fixed-gain designs cannot simultaneously meet the high-sensitivity amplification requirements for weak light signals and the anti-saturation requirements for strong light signals; Second, factors such as dark current in photodetectors, operational amplifier input offset, temperature drift, and ambient stray light can introduce a fixed DC bias, which may overwhelm weak nanowatt-level signals or cause the circuit to deviate from its linear operating region; Third, common-mode noise and device noise further degrade signal quality.

[0004] To address the aforementioned issues, several solutions have been proposed in existing technologies. Regarding fully differential transimpedance amplifier architectures, relevant literature discloses schemes that convert the output current signal of a photodetector into a differential voltage signal. These schemes effectively suppress common-mode noise, but are mostly fixed-gain designs, unable to adapt to wide dynamic range optical signals. In terms of adjustable and adaptive gain, existing technologies have proposed gain-variable transimpedance amplifiers based on R-2R resistor attenuation networks, gain-adaptive photodetector circuits based on microcontrollers, and photodetector devices with selectable channel gain ranges. However, these schemes typically employ asymmetrical structures or single-ended control methods for gain adjustment, and their ability to achieve synchronous gain switching under a symmetrical differential architecture is still imperfect. Regarding DC bias processing, existing technologies include balanced detectors to suppress DC components, software calibration to eliminate initial offset, and hardware closed-loop zeroing to compensate for dark current. However, these are mostly static calibrations or open-loop compensations, making it difficult to dynamically track and adjust in real-time as gain levels change and system operating states drift.

[0005] In summary, existing photoelectric signal detection circuits still have the following shortcomings: the fixed gain of the fully differential architecture cannot cover a wide dynamic range; the synchronous switching control of the gain-adjustable scheme under the symmetrical differential architecture is not yet perfect; the DC bias processing lacks dynamic closed-loop tracking capability; gain adjustment and bias cancellation are usually designed as independent functional modules, lacking a unified collaborative control mechanism. These shortcomings limit the measurement accuracy and dynamic response performance of photoelectric detection circuits in precision metrology scenarios. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a fully symmetrical differential photoelectric signal detection circuit and its adaptive control method, which achieves high-fidelity measurement of photoelectric signals with high linearity and high anti-interference capability over a wide dynamic range, while effectively suppressing common-mode noise and dynamically canceling DC bias to ensure that the signal always operates in the linear region.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows: A fully symmetrical differential photoelectric signal detection circuit includes a photodetector, a symmetrical differential transimpedance amplifier circuit, a digital gain adjustment circuit, a digital bias adjustment circuit, an FPGA control module, and a two-stage differential amplifier circuit. The output terminal of the photodetector is connected to the two inverting input terminals of the symmetrical differential transimpedance amplifier circuit, and the non-inverting input terminals of the symmetrical differential transimpedance amplifier circuit are grounded. The digital gain adjustment circuit is symmetrically connected in parallel between the high-impedance input terminal and the output terminal of the symmetrical differential transimpedance amplifier circuit. The output of the symmetrical differential transimpedance amplifier circuit is connected to the digital bias adjustment circuit. The output of the digital bias adjustment circuit is connected to the input of the two-stage differential amplifier circuit. The FPGA control module is communicatively connected to the digital gain adjustment circuit and the digital bias adjustment circuit, respectively. The FPGA control module has built-in gain adaptive switching control logic and DC bias dynamic cancellation control logic, which are used to adaptively switch the gain level of the digital gain adjustment circuit according to the amplitude of the acquired signal, and synchronously control the digital bias adjustment circuit to dynamically cancel the DC component, so that the output signal always works in the linear region.

[0008] In the above scheme, the symmetrical differential transimpedance amplifier circuit includes a symmetrically arranged dual transimpedance amplifier and feedback capacitors respectively connected between the two high-impedance input terminals and the output terminals of the dual transimpedance amplifier; the feedback capacitors are used to improve the circuit response speed and prevent self-oscillation.

[0009] In the above scheme, the digital gain adjustment circuit includes: An analog-to-digital converter is used to acquire the differential voltages at the two output terminals of the symmetrical differential transimpedance amplifier circuit in real time and convert them into digital signals to be transmitted back to the FPGA control module. An analog switch is used to receive instructions from the FPGA control module to select a specific channel. The gain stepping network consists of feedback resistors symmetrically distributed on both sides of the dual-channel transimpedance amplifier. The feedback resistors are divided into multiple levels according to their resistance values. The gain stepping network is connected to the analog switch and is used to match optical signals of different intensities to achieve specific gain amplification.

[0010] In the above scheme, the gain stepping network includes six gain levels in 10x increments, corresponding to feedback resistor values ​​of 200Ω, 2KΩ, 20KΩ, 200KΩ, 2MΩ, and 20MΩ, respectively, with a corresponding transimpedance gain of 2×(10^2 / 2000). 2 ~10 7 V / A; The analog switch is an 8-to-1 analog switch. The FPGA control module drives the analog switch to synchronously select the corresponding gain level by outputting high and low levels to the A, B, and C control terminals of the 8-to-1 analog switch.

[0011] In the above scheme, the digital bias adjustment circuit includes: A dual-channel digital-to-analog converter is used to convert the digital signals output by the FPGA control module into analog signals for output. Dual-channel operational amplifier-based voltage followers are used to buffer and isolate the analog signals output by the dual-channel digital-to-analog converter. A dual-channel operational amplifier-based subtractor circuit is used to perform differential operations between the output signal of the dual-channel operational amplifier-based voltage follower and the output signal of the symmetrical differential transimpedance amplifier circuit. A dual-channel analog-to-digital converter is used to convert the acquired dual-channel operational amplifier-based subtractor circuit output signals into digital signals and send them back to the FPGA control module.

[0012] An adaptive control method for a fully symmetrical differential photoelectric signal detection circuit based on the circuit described above includes the following steps: S100: System initialization, setting the initial gain level, and performing initial bias calibration under no light source input conditions, recording the inherent DC bias; S200: Input the optical signal to be measured, and synchronously acquire the differential output voltage after bias adjustment at the current gain level through the analog-to-digital converter; S300: The FPGA control module performs adaptive gain determination based on the acquired differential output voltage amplitude: if the current output voltage exceeds the preset linear range threshold, it switches to the matching gain level according to the pre-built voltage range-photocurrent-feedback resistor mapping relationship; if the current output voltage is within the preset linear range threshold, it maintains the current gain level. S400: After completing the gain level switching or maintaining the current level, the FPGA control module retrieves the feedback resistor-compensation voltage mapping relationship corresponding to the level and dynamically calculates the required DC compensation voltage parameters. S500: The calculated DC compensation voltage is superimposed with the initial bias calibration value to generate the final calibration signal, which is fed back to the bias adjustment circuit through the digital-to-analog converter to cancel the DC component introduced by dark current, op-amp offset and gain change. S600: Repeat steps S200 to S500 to form a closed-loop control until the output voltage stabilizes at the center of the linear operating region.

[0013] In the above scheme, the preset linear range threshold in step S300 is set according to the reserved rail voltage margin of the power supply threshold of the dual-channel transimpedance amplifier; the FPGA control module continuously collects multiple sets of data and takes the average value to suppress signal fluctuations in the initial stage of startup, and sets a hysteresis threshold at the boundary of adjacent voltage intervals, and only triggers gear switching when the output voltage crosses the interval amplitude exceeds the hysteresis threshold.

[0014] In the above scheme, the feedback resistor-compensation voltage mapping relationship in step S400 and the voltage range-photocurrent-feedback resistor mapping relationship in step S300 are synchronously established and updated in real time by the FPGA control module; when the gain level switching is triggered, the compensation voltage parameter is retrieved according to the new level synchronous index after switching, so as to realize the synchronous linkage of gain adjustment and bias cancellation.

[0015] An adaptive switching method for photoelectric signal gain based on the circuit described above includes the following steps: S1: Connect the initial step resistor in the gain stepping network to the feedback loop of the symmetrical differential transimpedance amplifier circuit. S2: The differential voltage at the output of the symmetrical differential transimpedance amplifier circuit is acquired in real time by an analog-to-digital converter, and the converted digital signal is transmitted to the FPGA control module. S3: The FPGA control module compares the acquired differential voltage with a preset gain switching threshold. If the differential voltage is greater than the determination threshold, a first control signal is generated to drive the analog switch to synchronously select the lower resistance level in the gain step network to reduce the transimpedance gain. If the differential voltage is less than or equal to the judgment threshold, the current photocurrent amplitude is inferred from the differential voltage, the gain and signal-to-noise ratio under each gain level are analyzed, the optimal level is selected, and a second control signal is generated to drive the analog switch to synchronously select the corresponding gain level. S4: Establish and update the voltage range-photocurrent-feedback resistor mapping relationship within the FPGA control module, which is used to directly look up the table and locate and complete the gear switching during subsequent sampling and judgment.

[0016] A method for dynamic cancellation of DC bias in photoelectric signals based on the circuit described above includes the following steps: T1: Start the system and ensure that there is no light source input to the photodetector. Synchronously acquire the output signal after bias adjustment through the analog-to-digital converter to obtain the raw data containing only the inherent DC bias. T2: The collected data is transmitted to the FPGA control module for analysis, the amplitude and polarity of the inherent DC bias are calculated, and a digital calibration signal is generated based on the calculation results; T3: The digital calibration signal is converted into an analog calibration signal by a digital-to-analog converter, and fed back to the inverting input of the subtractor circuit via a voltage follower. It is then differentially processed with the output signal of the symmetrical differential transimpedance amplifier circuit to complete the initial cancellation calibration of the inherent DC bias. T4: After the light source is connected, the output signal after bias adjustment at each gain level is synchronously acquired through the analog-to-digital converter; T5: The collected data is transmitted to the FPGA control module for filtering and quantization. The compensation voltage parameters are calculated based on the trend of the separated DC signal, and the mapping relationship between the feedback resistor and the compensation voltage is recorded. T6: The compensation voltage is superimposed with the initial calibration voltage, and output to the voltage follower through the digital-to-analog converter. Then, it is fed back to the inverting input of the subtractor circuit for differential operation to maintain the signal in the linear operating region. T7: The FPGA control module periodically collects the output signal after bias adjustment in the current working mode through the analog-to-digital converter. If the collected data exceeds the linear range threshold, the compensation voltage parameters are recalculated, and the output voltage of the digital-to-analog converter is checked and corrected to maintain the compensation accuracy.

[0017] Through the above technical solution, the fully symmetrical differential photoelectric signal detection circuit and its adaptive control method provided by the present invention have the following beneficial effects: (i) The present invention adopts a fully symmetrical differential transimpedance amplifier circuit topology, which makes the common-mode noise cancel each other out during differential transmission. The setting of the feedback capacitor effectively improves the circuit response speed and prevents self-excited oscillation, significantly improving the anti-interference ability and working stability of the circuit.

[0018] (II) This invention achieves adaptive switching of transimpedance gain through a digital gain adjustment circuit. The gain stepping network contains six gain levels in 10-fold increments, corresponding to a transimpedance gain of 2×(10). 2 ~10 7 With a gain of 100V / A, it can cover a wide dynamic range of optical signals from nanowatts to milliwatts. In low light conditions, it automatically switches to a high-gain setting for sensitive amplification, and in strong light conditions, it automatically switches to a low-gain setting to avoid saturation, maintaining high linearity across the entire measurement range. Furthermore, wide dynamic range optical signal detection can be achieved with a single circuit, eliminating the need to change detection circuits with different gains for different signal magnitudes, effectively reducing system costs.

[0019] (III) This invention achieves dynamic closed-loop cancellation of DC bias through digital bias adjustment circuit. When the system starts up, the initial calibration is completed under the condition of no light source. After the light source is connected, the output signal after bias adjustment is collected in real time and the compensation voltage is dynamically updated. This effectively cancels the DC component introduced by factors such as dark current of photodetector, operational amplifier input offset, temperature drift and environmental stray light, and prevents the amplifier output signal from saturating or distorting.

[0020] (iv) This invention achieves unified and coordinated control of gain adjustment and bias cancellation through the FPGA control module, and synchronously establishes the mapping relationship of "voltage range-photocurrent-feedback resistor" and "feedback resistor-compensation voltage". When the gain level is switched, the compensation voltage parameter is retrieved according to the synchronous index of the new level. At the same time, by continuously collecting multiple sets of data and taking the average value, the startup fluctuation is suppressed, the hysteresis threshold is set to avoid frequent switching, and the preset periodic compensation calibration logic is used to combat temperature drift and aging, so as to ensure the stability and reliability of the system in the full dynamic range.

[0021] (v) The two-stage differential amplifier circuit uses an instrumentation operational amplifier as its core and sets the gain to 1. While ensuring the complete transmission of the signal, it avoids introducing additional noise or excessive amplification that leads to saturation distortion. Finally, it outputs a high-precision, low-noise single-ended AC signal for subsequent acquisition and analysis.

[0022] In summary, this invention achieves high-fidelity measurement of photoelectric signals with wide dynamic range, high linearity, and strong anti-interference capability in a single circuit by organically combining a fully symmetrical differential structure, adaptive digital gain switching, dynamic digital bias cancellation, and a collaborative control mechanism. It can be widely applied in precision photoelectric metrology scenarios such as spectral analysis, optical communication detection, and weak light signal detection. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0024] Figure 1 This is a schematic diagram of a fully symmetrical differential photoelectric signal detection circuit disclosed in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0026] like Figure 1 As shown, the present invention provides a fully symmetrical differential photoelectric signal detection circuit, including a photodetector, a symmetrical differential transimpedance amplifier circuit, a digital gain adjustment circuit, a digital bias adjustment circuit, an FPGA control module, and a two-stage differential amplifier circuit.

[0027] I. Photodetector An alternating light signal, modulated electrically or optically, is input to a photodetector to obtain a weak photocurrent signal. The photodetector's Cathode and Anode interfaces output differential weak photocurrent signals, which are then connected to the two inverting inputs of a symmetrical differential transimpedance amplifier circuit. Using a differential output method to connect to the subsequent differential amplifier circuit effectively utilizes the common-mode rejection capability of the later stage circuit, reducing the impact of common-mode interference on measurement accuracy from the signal link source.

[0028] II. Symmetrical Differential Transimpedance Amplifier Circuit The non-inverting input of the symmetrical differential transimpedance amplifier circuit shares a common ground. The symmetrical differential transimpedance amplifier circuit utilizes a high common-mode rejection ratio, low noise, rail-to-rail dual transimpedance amplifier to construct a symmetrical differential structure. This is achieved by symmetrically connecting feedback capacitors in parallel at the high-impedance input and output of the dual transimpedance amplifier. The feedback capacitors are used to improve the circuit response speed and suppress self-oscillation.

[0029] The calculation relationship between single-channel output voltage and single-channel input photocurrent is as follows: ; in, For single-channel output voltage, For single-channel input photocurrent, This is the resistance value of the feedback resistor.

[0030] The output of the symmetrical differential transimpedance amplifier circuit is connected to a digital bias adjustment circuit.

[0031] In this embodiment, by adopting a fully symmetrical differential structure, common-mode noise (such as power supply fluctuations, environmental electromagnetic interference, substrate coupling noise, etc.) cancels each other out during differential transmission, which significantly improves the circuit's anti-interference capability and operational stability, enabling the detection circuit to maintain high measurement accuracy even in complex electromagnetic environments.

[0032] To ensure consistent gain for weak photocurrent signals in a symmetrical differential structure, the selection steps for the feedback resistor value are as follows: 1) Metal foil resistors with an accuracy better than ±0.05% and a temperature coefficient ≤ ±2ppm / ℃ are used to resist solder the circuit board; 2) Using a dual-channel ultra-high resolution current source input to the inverting input terminal of the transimpedance amplifier, the output voltage difference of the symmetrical differential transimpedance amplifier circuit is measured differentially using a high-precision digital multimeter. The relative deviation is calculated based on cross-measurement or multiple repeated measurements: ; in, This is a relative deviation. This is the measured value of the output pressure difference. This is the theoretical voltage; 3) Based on the instrument uncertainty judgment, when the relative deviation... The voltage is very close to the theoretical voltage. According to relative deviation Complete the selection of feedback resistor values.

[0033] Through the above screening steps, the feedback resistor values ​​of the dual-channel transimpedance amplifier are ensured to be highly matched, guaranteeing the gain consistency of the symmetrical differential structure from a hardware perspective, thus laying the foundation for subsequent high-precision measurements.

[0034] III. Digital Gain Adjustment Circuit The digital gain adjustment circuit includes an analog-to-digital converter, analog switches, and a gain stepping network. The digital gain adjustment circuit has a symmetrical structure and is connected in parallel between the high-impedance input and output terminals of the symmetrical differential transimpedance amplifier circuit.

[0035] The analog-to-digital converter (ADC) is used to acquire the differential voltage at the two output terminals of the symmetrical differential transimpedance amplifier circuit in real time and convert it into a digital signal to be sent back to the FPGA control module.

[0036] Analog switches are used to receive instructions from the FPGA control module to select specific channels.

[0037] The gain stepping network consists of feedback resistors symmetrically distributed on both sides of the dual-channel transimpedance amplifier. The feedback resistors are divided into multiple levels according to their resistance values ​​and are connected to an analog switch to match optical signals of different intensities to achieve specific gain amplification.

[0038] In this embodiment, the gain stepping network includes six gain levels in 10-fold increments, corresponding to feedback resistor values ​​of 200Ω, 2kΩ, 20kΩ, 200kΩ, 2MΩ, and 20MΩ, respectively, with corresponding transimpedance gains of [missing value]. V / A to V / A. Through the aforementioned gain level settings, a single circuit can cover a wide dynamic range of optical signals from nanowatts to milliwatts: automatically switching to a high gain level for sensitive amplification in weak light and automatically switching to a low gain level to avoid saturation in strong light, maintaining high linearity measurement across the entire range. There is no need to replace the detection circuit with different gain levels for different signal magnitudes, effectively reducing system costs. The analog switch is an 8-to-1 analog switch. The FPGA control module drives the analog switch to synchronously select the corresponding gain level by outputting high and low levels to the A, B, and C control terminals of the 8-to-1 analog switch. Using an 8-to-1 analog switch in conjunction with FPGA digital control achieves rapid synchronous switching of gain levels, ensuring the consistency and real-time performance of dual-channel gain switching.

[0039] IV. Digital Bias Adjustment Circuit The digital bias adjustment circuit includes a dual-channel digital-to-analog converter, a dual-channel operational amplifier-based voltage follower, a dual-channel operational amplifier-based subtractor circuit, and a dual-channel analog-to-digital converter.

[0040] A dual-channel digital-to-analog converter (DAC) is used to convert digital signals output from the FPGA control module into analog signals.

[0041] Dual-channel op-amp-based voltage followers are used to implement buffer isolation for the analog signals output by the dual-channel digital-to-analog converter.

[0042] The dual-channel op-amp-based subtractor circuit is used to perform differential operations between the output signals of the dual-channel op-amp-based voltage follower and the output signals of the symmetrical differential transimpedance amplifier circuit.

[0043] The dual-channel analog-to-digital converter (ADC) is used to convert the acquired dual-channel op-amp-based subtractor circuit output signals into digital signals and send them back to the FPGA control module.

[0044] This implementation achieves dynamic closed-loop cancellation of DC bias through a digital bias adjustment circuit. Compared with static calibration or open-loop compensation schemes, it can track and cancel the DC component introduced by factors such as dark current of photodetector, op-amp input offset, temperature drift and ambient stray light in real time, and prevent the amplifier output signal from saturating or distorting.

[0045] V. Two-stage differential amplifier circuit The two-stage differential amplifier circuit, with an instrumentation operational amplifier (op-amp) as its core, amplifies the opposite-polarity, symmetrically amplituded voltage signals output from a dual-channel op-amp-based subtractor circuit into a single-ended voltage signal. Utilizing the op-amp's internal precision-matched resistor network, gain error is reduced, common-mode rejection is enhanced, noise and offset drift are lowered, ensuring low distortion and high stability during signal amplification. The output voltage signal of the two-stage differential amplifier circuit is: ; in, The gain of the two-stage differential amplifier circuit is determined by the gain resistor of the instrumentation operational amplifier. Decide: ; Considering that the front-stage symmetrical differential transimpedance amplifier circuit amplifies signals of different intensities through a digital gain adjustment circuit, ensuring the amplitude and quality of the signal during transmission and processing within the system, and to avoid introducing additional noise and prevent excessive signal amplification beyond the processing range of subsequent systems, leading to saturation or distortion, the gain of the second-stage differential amplifier circuit in this embodiment is... Set to 1. With the above settings, the two-stage differential amplifier circuit ensures complete signal transmission without introducing additional noise or excessive amplification, ultimately outputting a high-precision, low-noise single-ended AC signal for subsequent acquisition and analysis.

[0046] VI. Adaptive Control Method The adaptive control method for a fully symmetrical differential photoelectric signal detection circuit provided by this invention includes the following steps: S100: System initialization, setting the initial gain level, and performing initial bias calibration under no light source input conditions, recording the inherent DC bias; S200: Receives the optical signal under test and synchronously acquires the differential output voltage after bias adjustment at the current gain level via an analog-to-digital converter. ; S300: The FPGA control module outputs the differential voltage amplitude based on the acquired data. Perform adaptive gain determination: If the current output voltage exceeds the preset linear range threshold... If the current output voltage is within the preset linear range threshold, the system will switch to the matching gain level based on the pre-established voltage range-photocurrent-feedback resistor mapping relationship. If it is inside, the current gain level will be maintained; S400: After completing the gain level switching or maintaining the current level, the FPGA control module retrieves the feedback resistor-compensation voltage mapping relationship corresponding to the level and dynamically calculates the required DC compensation voltage parameters. S500: The calculated DC compensation voltage is superimposed with the initial bias calibration value to generate the final calibration signal, which is fed back to the bias adjustment circuit through the digital-to-analog converter to cancel the DC component introduced by dark current, op-amp offset and gain change. S600: Repeat steps S200 to S500 to form a closed-loop control until the output voltage stabilizes at the center of the linear operating region.

[0047] Through the above adaptive control method, the FPGA control module realizes unified and coordinated control of gain adjustment and bias cancellation: after the gain level is switched, the compensation voltage parameter is retrieved according to the synchronous index of the new level, avoiding the problem of bias state mismatch caused by gain change, and ensuring the stability and reliability of the system in the full dynamic range.

[0048] In step S300, a preset linear range threshold is set. The power supply threshold of the dual-channel transimpedance amplifier is set with a reserved rail voltage margin. The FPGA control module continuously collects multiple sets of data and averages them to suppress signal fluctuations during startup. A hysteresis threshold is set at the boundary between adjacent voltage ranges, and gear switching is triggered only when the output voltage amplitude across the range exceeds the hysteresis threshold. Through the above anti-jitter and hysteresis mechanisms, frequent erroneous gear switching caused by signal fluctuations during startup and small-amplitude signal fluctuations in steady state is effectively avoided, ensuring the stability and reliability of gain adjustment.

[0049] In step S400, the feedback resistor-compensation voltage mapping relationship and the voltage range-photocurrent-feedback resistor mapping relationship in step S300 are synchronously established and updated in real time by the FPGA control module; when the gain level switching is triggered, the compensation voltage parameter is retrieved according to the new level synchronous index after switching, so as to realize the synchronous linkage of gain adjustment and bias cancellation.

[0050] VII. Gain Adaptive Switching Method The photoelectric signal gain adaptive switching method provided by this invention includes the following steps: S1: Connect the initial step resistor in the gain stepping network to the feedback loop of the symmetrical differential transimpedance amplifier circuit. S2: Real-time acquisition of the differential voltage at the output of the symmetrical differential transimpedance amplifier circuit via an analog-to-digital converter. The converted digital signal is then transmitted to the FPGA control module. S3: The FPGA control module will collect the differential voltage. Compared with the preset gain switching threshold Comparison: If differential voltage Then the first control signal is generated, which drives the analog switch to synchronously select the lower resistance range in the gain step network to reduce the transimpedance gain. If differential voltage Then, based on the differential voltage, the current photocurrent amplitude is inferred, the gain and signal-to-noise ratio under each gain level are analyzed, the optimal level is selected, and a second control signal is generated to drive the analog switch to synchronously select the corresponding gain level. S4: Establish and update the voltage range-photocurrent-feedback resistor mapping relationship within the FPGA control module, which is used to directly look up the table and complete the gear switching during subsequent sampling and judgment.

[0051] The above-mentioned adaptive gain switching method realizes the automatic matching of transimpedance gain according to the intensity of input optical signal. When the light signal is weak, it automatically switches to high gain to achieve sensitive detection, and when the light signal is strong, it automatically switches to low gain to avoid saturation, maintaining high linearity measurement across the entire range.

[0052] VIII. Dynamic DC Bias Cancellation Method The photoelectric signal DC bias dynamic cancellation method provided by the present invention includes the following steps: T1: Start the system and ensure there is no light source input to the photodetector. Simultaneously acquire the output signals of the dual-channel operational amplifier-based subtractor circuit via the analog-to-digital converter. and To obtain raw data containing only the inherent DC bias; T2: The collected data is transmitted to the FPGA control module for analysis, the amplitude and polarity of the inherent DC bias are calculated, and a digital calibration signal is generated based on the calculation results; T3: Converts digital calibration signals to analog calibration signals via a digital-to-analog converter. and The voltage follower feeds back to the inverting input of the dual-channel operational amplifier-based subtractor circuit, where it performs differential operation with the output signal of the symmetrical differential transimpedance amplifier circuit to complete the initial cancellation calibration of the inherent DC bias. T4: After connecting the light source, the output signals of the dual-channel op-amp-based subtractor circuit at each gain level are synchronously acquired through the analog-to-digital converter. and ; T5: The acquired data is transmitted to the FPGA control module for filtering and quantization processing, and the compensation voltage parameters are calculated based on the trend of the separated DC signal. and And record the mapping relationship between the feedback resistor and the compensation voltage; T6: Superimpose the compensation voltage with the initial calibration voltage, i.e. , The signal is output to a voltage follower via a digital-to-analog converter and then fed back to the inverting input of a dual-channel op-amp-based subtractor circuit for differential operation, maintaining the signal in the linear operating region. T7: The FPGA control module periodically acquires the output signals of the dual-channel op-amp-based subtractor circuit in the current operating mode via an analog-to-digital converter. and If the collected data exceeds the linear range threshold, the compensation voltage parameters are recalculated, and the output voltage of the digital-to-analog converter is calibrated and corrected. and To maintain compensation accuracy.

[0053] The aforementioned dynamic DC bias cancellation method achieves triple protection of DC bias through initial calibration, adaptive adjustment, and periodic calibration correction. Initial bias cancellation is completed upon system startup. After the light source is connected, dynamic tracking compensation is performed based on signal changes. Pre-set periodic calibration logic counteracts drift caused by thermal effects and device aging, ensuring that the DC bias is effectively cancelled throughout long-term system operation and that the signal always operates in the linear region.

[0054] In summary, this invention achieves high-fidelity measurement of photoelectric signals with wide dynamic range, high linearity, and strong anti-interference capability in a single circuit by organically combining a fully symmetrical differential structure, adaptive digital gain switching, dynamic digital bias cancellation, and a collaborative control mechanism. It can be widely applied in precision photoelectric metrology scenarios such as spectral analysis, optical communication detection, and weak light signal detection.

[0055] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A fully symmetrical differential photoelectric signal detection circuit, characterized in that, It includes a photodetector, a symmetrical differential transimpedance amplifier circuit, a digital gain adjustment circuit, a digital bias adjustment circuit, an FPGA control module, and a two-stage differential amplifier circuit; The output terminal of the photodetector is connected to the two inverting input terminals of the symmetrical differential transimpedance amplifier circuit, and the non-inverting input terminals of the symmetrical differential transimpedance amplifier circuit are grounded. The digital gain adjustment circuit is symmetrically connected in parallel between the high-impedance input terminal and the output terminal of the symmetrical differential transimpedance amplifier circuit. The output of the symmetrical differential transimpedance amplifier circuit is connected to the digital bias adjustment circuit. The output of the digital bias adjustment circuit is connected to the input of the two-stage differential amplifier circuit. The FPGA control module is communicatively connected to the digital gain adjustment circuit and the digital bias adjustment circuit, respectively. The FPGA control module has built-in gain adaptive switching control logic and DC bias dynamic cancellation control logic, which are used to adaptively switch the gain level of the digital gain adjustment circuit according to the amplitude of the acquired signal, and synchronously control the digital bias adjustment circuit to dynamically cancel the DC component, so that the output signal always works in the linear region.

2. The fully symmetrical differential photoelectric signal detection circuit according to claim 1, characterized in that, The symmetrical differential transimpedance amplifier circuit includes a symmetrically arranged dual transimpedance amplifier and feedback capacitors connected between the two high-impedance input terminals and the output terminals of the dual transimpedance amplifier; the feedback capacitors are used to improve the circuit response speed and prevent self-oscillation.

3. The fully symmetrical differential photoelectric signal detection circuit according to claim 2, characterized in that, The digital gain adjustment circuit includes: An analog-to-digital converter is used to acquire the differential voltages at the two output terminals of the symmetrical differential transimpedance amplifier circuit in real time and convert them into digital signals to be transmitted back to the FPGA control module. An analog switch is used to receive instructions from the FPGA control module to select a specific channel. The gain stepping network consists of feedback resistors symmetrically distributed on both sides of the dual-channel transimpedance amplifier. The feedback resistors are divided into multiple levels according to their resistance values. The gain stepping network is connected to the analog switch and is used to match optical signals of different intensities to achieve specific gain amplification.

4. The fully symmetrical differential photoelectric signal detection circuit according to claim 3, characterized in that, The gain stepping network includes six gain levels in 10x increments, corresponding to feedback resistor values ​​of 200Ω, 2KΩ, 20KΩ, 200KΩ, 2MΩ, and 20MΩ, with corresponding transimpedance gains of 2×(10^2 / 2000). 2 ~10 7 V / A; The analog switch is an 8-to-1 analog switch. The FPGA control module drives the analog switch to synchronously select the corresponding gain level by outputting high and low levels to the A, B, and C control terminals of the 8-to-1 analog switch.

5. The fully symmetrical differential photoelectric signal detection circuit according to claim 1, characterized in that, The digital bias adjustment circuit includes: A dual-channel digital-to-analog converter is used to convert the digital signals output by the FPGA control module into analog signals for output. Dual-channel operational amplifier-based voltage followers are used to buffer and isolate the analog signals output by the dual-channel digital-to-analog converter. A dual-channel operational amplifier-based subtractor circuit is used to perform differential operations between the output signal of the dual-channel operational amplifier-based voltage follower and the output signal of the symmetrical differential transimpedance amplifier circuit. A dual-channel analog-to-digital converter is used to convert the acquired dual-channel operational amplifier-based subtractor circuit output signals into digital signals and send them back to the FPGA control module.

6. An adaptive control method for a fully symmetrical differential photoelectric signal detection circuit based on the circuit described in any one of claims 1 to 5, characterized in that, Includes the following steps: S100: System initialization, setting the initial gain level, and performing initial bias calibration under no light source input conditions, recording the inherent DC bias; S200: Input the optical signal to be measured, and synchronously acquire the differential output voltage after bias adjustment at the current gain level through the analog-to-digital converter; S300: The FPGA control module performs gain adaptive determination based on the acquired differential output voltage amplitude: if the current output voltage exceeds the preset linear range threshold, it switches to the matching gain level according to the pre-established voltage range-photocurrent-feedback resistor mapping relationship. If the current output voltage is within the preset linear range threshold, then maintain the current gain level; S400: After completing the gain level switching or maintaining the current level, the FPGA control module retrieves the feedback resistor-compensation voltage mapping relationship corresponding to the level and dynamically calculates the required DC compensation voltage parameters. S5 00: The calculated DC compensation voltage is superimposed with the initial bias calibration value to generate the final calibration signal, which is fed back to the bias adjustment circuit through the digital-to-analog converter to cancel the DC component introduced by dark current, op-amp offset and gain change. S600: Repeat steps S200 to S500 to form a closed-loop control until the output voltage stabilizes at the center of the linear operating region.

7. The adaptive control method according to claim 6, characterized in that, The preset linear range threshold in step S300 is set according to the reserved rail voltage margin of the power supply threshold of the dual-channel transimpedance amplifier; the FPGA control module continuously collects multiple sets of data and takes the average value to suppress signal fluctuations in the initial stage of startup, and sets a hysteresis threshold at the boundary of adjacent voltage ranges. The gear switching is triggered only when the output voltage crosses the range and exceeds the hysteresis threshold.

8. The adaptive control method according to claim 6, characterized in that, The feedback resistor-compensation voltage mapping relationship described in step S400 and the voltage range-photocurrent-feedback resistor mapping relationship described in step S300 are synchronously established and updated in real time by the FPGA control module; when the gain level switching is triggered, the compensation voltage parameter is retrieved according to the synchronous index of the new level after switching, so as to realize the synchronous linkage of gain adjustment and bias cancellation.

9. A method for adaptive switching of photoelectric signal gain based on the circuit described in any one of claims 1 to 5, characterized in that, Includes the following steps: S1: Connect the initial step resistor in the gain stepping network to the feedback loop of the symmetrical differential transimpedance amplifier circuit. S2: The differential voltage at the output of the symmetrical differential transimpedance amplifier circuit is acquired in real time by an analog-to-digital converter, and the converted digital signal is transmitted to the FPGA control module. S3: The FPGA control module compares the acquired differential voltage with a preset gain switching threshold. If the differential voltage is greater than the determination threshold, a first control signal is generated to drive the analog switch to synchronously select the lower resistance level in the gain step network to reduce the transimpedance gain. If the differential voltage is less than or equal to the judgment threshold, the current photocurrent amplitude is inferred from the differential voltage, the gain and signal-to-noise ratio under each gain level are analyzed, the optimal level is selected, and a second control signal is generated to drive the analog switch to synchronously select the corresponding gain level. S4: Establish and update the voltage range-photocurrent-feedback resistor mapping relationship within the FPGA control module, which is used to directly look up the table and locate and complete the gear switching during subsequent sampling and judgment.

10. A method for dynamic cancellation of DC bias in photoelectric signals based on the circuit described in any one of claims 1 to 5, characterized in that, Includes the following steps: T1: Start the system and ensure that there is no light source input to the photodetector. Synchronously acquire the output signal after bias adjustment through the analog-to-digital converter to obtain the raw data containing only the inherent DC bias. T2: The collected data is transmitted to the FPGA control module for analysis, the amplitude and polarity of the inherent DC bias are calculated, and a digital calibration signal is generated based on the calculation results; T3: The digital calibration signal is converted into an analog calibration signal by a digital-to-analog converter, and fed back to the inverting input of the subtractor circuit via a voltage follower. It is then differentially processed with the output signal of the symmetrical differential transimpedance amplifier circuit to complete the initial cancellation calibration of the inherent DC bias. T4: After the light source is connected, the output signal after bias adjustment at each gain level is synchronously acquired through the analog-to-digital converter; T5: The collected data is transmitted to the FPGA control module for filtering and quantization. The compensation voltage parameters are calculated based on the trend of the separated DC signal, and the mapping relationship between the feedback resistor and the compensation voltage is recorded. T6: The compensation voltage is superimposed with the initial calibration voltage, and output to the voltage follower through the digital-to-analog converter. Then, it is fed back to the inverting input of the subtractor circuit for differential operation to maintain the signal in the linear operating region. T7: The FPGA control module periodically collects the output signal after bias adjustment in the current working mode through the analog-to-digital converter. If the collected data exceeds the linear range threshold, the compensation voltage parameters are recalculated, and the output voltage of the digital-to-analog converter is checked and corrected to maintain the compensation accuracy.

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