A signal line data analysis method and system for a test platform

Abstract

The application discloses a kind of signal line data analysis method and system for test platform, it is related to signal line test technical field, including obtaining and analyzing line design drawing, generating associated graph containing topological node, passage connecting line and signal flow direction;Real-time monitoring line, capture change event by comparing cable port pairing, mark target line and starting node;According to graph generation detection instruction and issue;Execute end two-way injection signal to target line, measure positive and negative direction delay, obtain each section symmetry parameter and node jump value, obtain measured data;Measured data is associated with graph, and fitting delay curve extracts deviated associated line;According to jump value sorting, check connectivity to associated line, highlight display abnormal line and target line in interface.The application can automatically perceive line change, improve operation and maintenance reliability.

Description

Technical Field

[0001] This invention relates to the field of signal line testing technology, specifically a signal line data analysis method and system for a test platform. Background Technology

[0002] Currently, test platforms generally employ manual management for signal line maintenance. This involves staff checking line connections one by one according to design drawings or equipment manuals. When line modifications occur on the test platform, existing management methods require manual tracing of all potentially affected signal links. However, there are numerous cross-correspondences between line connections and equipment configurations on test platforms, making manual checks difficult to fully cover. This easily leads to omissions or errors, resulting in abnormal test data or equipment malfunctions. Summary of the Invention

[0003] The purpose of this invention is to provide a signal line data analysis method and system for test platforms to solve the problems raised in the prior art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a signal line data analysis method for a test platform, the data analysis method comprising: Obtain the circuit design diagram of the test platform, parse the circuit design diagram, and generate the circuit association diagram of the test platform; The system monitors the signal lines of the test platform in real time, captures line modification events, generates line detection commands based on the line correlation map, and sends the line detection commands to the line detection execution terminal. After receiving the line detection command, the line detection execution terminal performs line status detection on the target line where the line has been modified, and collects the actual measured data of the target line. The measured data of the line are correlated with the line correlation map to extract the data of the associated lines that have signal correlation with the target line; Based on the extracted associated line data, the connectivity of the associated lines is verified, and the connectivity verification results of the target line and associated lines are synchronously loaded onto the monitoring interface of the test platform.

[0005] Furthermore, the circuit design diagram of the test platform is obtained, and the circuit design diagram is parsed to generate a circuit association diagram of the test platform, including: Read the numbering identifiers recorded in the circuit design diagram. The numbering identifiers include Class I numbering identifiers, Class II numbering identifiers, and Class III numbering identifiers. Among them, Class I numbering identifiers are hardware port numbers, Class II numbering identifiers are signal transmission cable numbers, and Class III numbering identifiers are board device numbers. Set the first-class number identifier as the topology node in the line association map, and bind the second-class and third-class number identifiers to the corresponding topology nodes; Traverse the connection records of signal transmission lines in the line design diagram, and use the topology nodes corresponding to the two hardware ports connected at both ends of a single signal transmission line as the connection start point and connection end point, respectively, to build the path connection between the topology nodes; according to the signal transmission flow direction marked in the line design diagram, add a signal flow direction mark to each path connection; wherein, the signal flow direction mark is used to distinguish between the uplink signal path and the downlink signal path. The number of path connections, uplink signal paths, and downlink signal paths of each topology node are counted as node attributes for each topology node. These node attributes are then recorded in the corresponding topology node to generate a line association map of the test platform. This invention transforms complex physical connections into a calculable and traversable digital model by hierarchically numbering hardware ports, cables, and circuit boards in the circuit design diagram and establishing a topology node, path connection, and flow direction marker. This diagram not only preserves the device hierarchy but also clarifies the signal transmission direction, providing structured basic data for subsequent modification capture, path traversal, and correlation analysis. It significantly improves the informatization level and processing efficiency of circuit management and avoids omissions and misjudgments caused by manual diagram reading.

[0006] Furthermore, the real-time monitoring of the test platform's signal lines, including capturing events related to line modifications, includes: Read the Class I and Class III number identifiers of each topology node in the line association map, define the horizontal axis X based on the horizontal arrangement order of the test platform cabinets, and define the vertical axis Y based on the vertical layer arrangement order of the cabinets, and establish a coordinate reference system; use the horizontal sequence number of the cabinet corresponding to the Class I number identifier of each topology node as the X-axis coordinate value and the vertical layer sequence number of the cabinet as the Y-axis coordinate value, and mark them in the coordinate reference system to obtain the position coordinates of each topology node; The system continuously collects the pairing information of the two ends of the Class I ID corresponding to all Class II IDs on the test platform, and generates the real-time port pairing relationship for each signal transmission cable. The real-time port pairing relationship is matched one by one with the port pairing relationship in the line association map. The path connection corresponding to the Class II ID with inconsistent pairing relationship is filtered out and marked as the target line. The topology nodes corresponding to both ends of the target line are marked as the modification start node, and the time of modification is recorded to generate the line modification event. This invention introduces a cabinet coordinate reference system to spatially locate each port node, facilitating physical location identification. Simultaneously, by continuously comparing the real-time collected pairing relationships between the ports at both ends of the cable with the inherent pairing relationships in the map, it can automatically and in real time detect any cable plugging, unplugging, or reconnection behavior, and accurately mark the starting node and time of the change. This process requires no manual intervention, eliminating the lag and uncertainty of manual inspection, and significantly improving the detection speed and accuracy of line changes. Furthermore, based on the line association map, line detection commands are generated and sent to the line detection execution terminal, including: Using each modification starting node as a base point, and based on the signal flow direction markings of the path connections, all signal transmission paths passing through the target lines are traversed. Each signal transmission path is divided into several path units according to the number of path connections it passes through. The closer the path unit is to the modification starting node, the higher its detection priority. Among the path units of the same priority, those belonging to the same three-category number identifier as the modification starting node are given priority in sorting, and the path units corresponding to the uplink signal path are given priority in sorting, thus generating an ordered line detection sequence. The modified starting node identifier, target route information, and ordered route detection sequence are integrated and encapsulated into a route detection instruction. The corresponding route detection execution terminal is matched according to the three types of number identifiers of the topology nodes corresponding to each path unit, and the route detection execution terminal issues the route detection instruction. In the embodiments of the present invention, taking the starting node of the modification as the center, all transmission paths passing through the target line are traversed according to the signal flow direction, and each path is divided into path units according to its distance from the modification point. At the same time, the detection priority is set according to the device affiliation and signal direction to form an ordered detection sequence. This sorting strategy ensures that the line segments most likely to be affected and with the largest impact range are detected first, which can quickly locate key fault points. Meanwhile, the corresponding detection execution end is matched according to the board to which the path unit belongs, realizing distributed and parallel instruction issuance, which effectively shortens the overall detection response time. Furthermore, after receiving the line detection command, the line detection execution terminal performs line status detection on the target line where the line modification has occurred, and collects the actual measured data of the target line, including: The line detection execution end parses the line detection command, extracts all topology nodes contained in the path unit corresponding to the target line, sorts all topology nodes according to the signal flow direction marking of the path connection, and generates a reference node sequence. Detection signals are injected into the first topological node of the baseline node sequence, and the arrival time of the signal at each topological node is recorded sequentially along the signal flow direction. The signals are then arranged in the order of arrival to generate a forward propagation time sequence. Detection signals are injected into the topology nodes at the end of the baseline node sequence. The signal arrival time of each topology node is recorded in reverse signal flow, and the signals are arranged in the order of arrival to generate a reverse propagation time sequence. Obtain each pair of adjacent topological nodes in the baseline node sequence, calculate the corresponding adjacent time difference in the forward propagation time series, denoted as the forward delay, and calculate the corresponding adjacent time difference in the reverse propagation time series, denoted as the reverse delay. The absolute value of the difference between the forward and reverse time delays of each path connection is calculated to obtain the time delay symmetry parameter corresponding to each path connection. The absolute value of the difference between the time delay symmetry parameters corresponding to the forward adjacent path connection and the backward adjacent path connection of each intermediate node in the reference node sequence is calculated to obtain the time delay jump value at the intermediate node. By integrating the time delay symmetry parameters and time delay jump values ​​corresponding to each topology node, the measured data of the target line are obtained. This invention measures the transmission delay of the same path connection in both directions by injecting detection signals bidirectionally, and obtains a delay symmetry parameter by taking the absolute value of the difference. This parameter can effectively compensate for the inherent delay and clock deviation of the equipment, and truly reflect the physical transmission characteristics of the line itself. Furthermore, by using the difference in delay symmetry parameters between the two connection segments before and after the intermediate node, a delay jump value is obtained. This value can sensitively indicate whether there are abnormalities such as signal reflection, poor contact, or impedance abrupt change at the node. This measurement method does not rely on an external reference clock, has strong anti-interference ability, and can accurately locate the fine-grained state of each node and each connection, providing a reliable basis for subsequent correlation analysis.

[0007] Furthermore, correlation analysis is performed between the measured data of the line and the line correlation map to extract the associated line data that has signal correlation with the target line, including: Extract the measured data of the target route, and establish an associated coordinate system with the sequence number of each path connection in the target route as the x-axis and the time delay symmetry parameter corresponding to each path connection as the y-axis. Mark the time delay symmetry parameter corresponding to each path connection in the associated coordinate system according to the sequence number to obtain the corresponding parameter coordinate points. The parameter coordinate points in the associated coordinate system are fitted with a smooth curve to generate a smooth baseline corresponding to the target route. The parameter coordinate points outside the smooth baseline are extracted, and the path connecting the extracted parameter coordinate points is marked as the associated route. Extract the time delay symmetry parameters corresponding to the associated lines and the time delay jump values ​​corresponding to the topology nodes at both ends; This invention plots the time delay symmetry parameters of each segment of the target line into curves in sequence, and obtains a baseline through smooth fitting. It can objectively determine which connections have time delay characteristics that significantly deviate from the overall trend. These deviations are often caused by abnormalities such as signal crosstalk, impedance changes, or loose connections due to alteration events. This effectively identifies related lines that have signal coupling or mutual influence with the target line. This method does not rely on preset thresholds but is based on dynamic judgment of the data distribution itself. It is highly adaptable and can discover hidden correlations that are difficult to detect with human experience, significantly improving the comprehensiveness and accuracy of problem investigation.

[0008] Furthermore, based on the extracted associated line data, the connectivity of the associated lines is verified, and the connectivity verification results of the target line and associated lines are synchronously loaded onto the monitoring interface of the test platform, including: The system iterates through the associated line data in descending order of delay jump values, identifying the Class II identifiers of each associated line. Based on the line association map, it obtains the Class I identifiers at both ends of the corresponding path connection. It then sends connectivity detection pulse signals to the topology nodes corresponding to the Class I identifiers at both ends and records the return status of the pulse signals. If the pulse signal is fully transmitted back, the connection status of the corresponding associated line is determined to be normal; if no pulse transmission signal is received or the pulse transmission signal is incomplete, the connection status of the corresponding associated line is determined to be abnormal; simultaneously, a connectivity check is performed on the target line to obtain the connection status of the target line. The associated lines and the target line whose connectivity status is abnormal will be highlighted on the test platform monitoring interface. This invention sorts associated lines according to their delay jump values ​​from largest to smallest and then verifies them sequentially, ensuring that the line with the most severe anomaly is detected first, thereby quickly locating the root cause of the fault with limited resources. It uses a pulse signal feedback method to verify connectivity, which is simple and reliable and can accurately distinguish between various states such as normal, disconnected, and signal attenuation. Finally, the abnormal line and the target line are simultaneously highlighted on the monitoring interface, intuitively presenting the fault location and the scope of impact, which greatly reduces the troubleshooting time for maintenance personnel and improves the operation and maintenance efficiency and reliability of the testing platform.

[0009] Furthermore, to better implement the above method, a signal line data analysis system for a test platform is also provided. This data analysis system includes: a line diagram construction module, a line monitoring module, an instruction generation module, a data acquisition module, a correlation analysis module, and a verification display module. The route map construction module is used to obtain the route design diagram of the test platform, parse the route design diagram, and generate the route association map of the test platform. The line monitoring module is used to monitor the signal lines of the test platform in real time and capture line modification events; The instruction generation module is used to generate line detection instructions based on the line association map and send the line detection instructions to the line detection execution terminal. The data acquisition module is set at the line detection execution terminal. After receiving the line detection command, it performs line status detection on the target line where the line has been modified according to the line detection command and collects the measured line data of the target line. The correlation analysis module is used to perform correlation analysis between the measured data of the line and the correlation map of the line, and extract the correlation line data that has a signal correlation with the target line; The verification display module is used to verify the connectivity of the associated lines based on the extracted associated line data, and to synchronously load the target line and the connectivity verification results of the associated lines to the monitoring interface of the test platform.

[0010] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention constructs an association graph containing nodes, connections, and flow direction markers by analyzing the route design diagram, transforming the physical connection relationship into a computable digital model. This provides a structured foundation for automated monitoring and path traversal, avoids omissions and misjudgments caused by manual map reading, and significantly improves the informatization level of route management.

[0011] 2. This invention introduces a cabinet coordinate reference system and continuously compares the cable port pairing relationship, which can automatically and in real time detect any line plugging or unplugging or reconnection behavior, accurately mark the starting node and time of the change, eliminate the lag in inspection, and greatly improve the speed and accuracy of change detection without manual intervention.

[0012] 3. This invention takes the change of the starting node as the center, sets the detection priority according to the signal flow direction, distance, device affiliation and uplink priority, generates an ordered detection sequence, ensures that the line segment most likely to be affected is detected first, and at the same time matches the corresponding execution end to realize distributed parallel distribution, which effectively shortens the overall detection response time.

[0013] 4. This invention uses bidirectional injection of detection signals and calculates time delay symmetry parameters and time delay jump values, which can effectively offset the inherent delay and clock deviation of the equipment, truly reflect the physical transmission characteristics of the line, keenly indicate abnormalities such as poor contact or impedance change at the node, have strong anti-interference ability, and accurate fine-grained positioning.

[0014] 5. This invention dynamically determines associated lines that deviate from the overall trend by fitting the delay parameter curve. It does not rely on preset thresholds, has strong adaptability, and can detect the influence of hidden signal coupling. After sorting by delay jump value, pulse connectivity verification is performed sequentially, prioritizing the investigation of serious anomalies. The faulty lines and target lines are highlighted synchronously, intuitively presenting the fault location and the scope of impact, greatly reducing investigation time and improving the operation and maintenance efficiency and reliability of the test platform. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the method flow of a signal line data analysis method and system for a test platform according to the present invention; Figure 2 This is a schematic diagram illustrating an application scenario of the signal line data analysis method and system for a test platform according to the present invention. Detailed Implementation

[0016] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Example 1: As Figure 1 As shown, the present invention provides a technical solution, a signal line data analysis method for a test platform, the data analysis method comprising: Obtain the circuit design diagram of the test platform, parse the circuit design diagram, and generate the circuit association diagram of the test platform; The system monitors the signal lines of the test platform in real time, captures line modification events, generates line detection commands based on the line correlation map, and sends the line detection commands to the line detection execution terminal. After receiving the line detection command, the line detection execution terminal performs line status detection on the target line where the line has been modified, and collects the actual measured data of the target line. The measured data of the line are correlated with the line correlation map to extract the data of the associated lines that have signal correlation with the target line; Based on the extracted associated line data, the connectivity of the associated lines is verified, and the connectivity verification results of the target line and associated lines are synchronously loaded into the monitoring interface of the test platform. The process of obtaining the circuit design diagram of the test platform, parsing the circuit design diagram, and generating the circuit association map of the test platform includes: Read the numbering identifiers recorded in the circuit design diagram. The numbering identifiers include Class I numbering identifiers, Class II numbering identifiers, and Class III numbering identifiers. Among them, Class I numbering identifiers are hardware port numbers, Class II numbering identifiers are signal transmission cable numbers, and Class III numbering identifiers are board device numbers. Set the first-class number identifier as the topology node in the line association map, and bind the second-class and third-class number identifiers to the corresponding topology nodes; Traverse the connection records of signal transmission lines in the line design diagram, and use the topology nodes corresponding to the two hardware ports connected at both ends of a single signal transmission line as the connection start point and connection end point, respectively, to build the path connection between the topology nodes; according to the signal transmission flow direction marked in the line design diagram, add a signal flow direction mark to each path connection; wherein, the signal flow direction mark is used to distinguish between the uplink signal path and the downlink signal path. The number of path connections, uplink signal paths, and downlink signal paths of each topology node are counted as node attributes for each topology node. These node attributes are then recorded in the corresponding topology node to generate a line association map of the test platform. In an embodiment of the present invention, a test platform includes three cabinets. The circuit design diagram records port numbers P001 to P120, cable numbers C001 to C300, and board numbers B01 to B16. During parsing, each port is used as a topology node, and cables and boards are bound to the corresponding port nodes. Based on the connection records in the design diagram, the path connection between nodes is built, the signal flow direction is marked, the number of connections and the number of uplink and downlink paths of each node are counted, and finally a circuit association map containing all topology relationships and attribute information is generated. Among them, the real-time monitoring of the signal lines of the test platform, and the capture of line modification events, include: Read the Class I and Class III number identifiers of each topology node in the line association map, define the horizontal axis X based on the horizontal arrangement order of the test platform cabinets, and define the vertical axis Y based on the vertical layer arrangement order of the cabinets, and establish a coordinate reference system; use the horizontal sequence number of the cabinet corresponding to the Class I number identifier of each topology node as the X-axis coordinate value and the vertical layer sequence number of the cabinet as the Y-axis coordinate value, and mark them in the coordinate reference system to obtain the position coordinates of each topology node; The system continuously collects the pairing information of the two ends of the Class I ID corresponding to all Class II IDs on the test platform, and generates the real-time port pairing relationship for each signal transmission cable. The real-time port pairing relationship is matched one by one with the port pairing relationship in the line association map. The path connection corresponding to the Class II ID with inconsistent pairing relationship is filtered out and marked as the target line. The topology nodes corresponding to both ends of the target line are marked as the modification start node, and the time of modification is recorded to generate the line modification event. In an embodiment of the present invention, each port node is mapped to a coordinate system using the horizontal serial number and vertical layer of the cabinet as coordinate axes; the system continuously collects real-time port pairings at both ends of all cables, and if it finds that the original paired ports P023-P089 of cable C087 have changed to P023-P091, then the path is marked as the target line, and P023 and P091 are marked as the modification start nodes, the modification time is recorded, and a line modification event is generated; The process of generating line detection commands based on the line association map and sending these commands to the line detection execution terminal includes: Using each modification starting node as a base point, and based on the signal flow direction markings of the path connections, all signal transmission paths passing through the target lines are traversed. Each signal transmission path is divided into several path units according to the number of path connections it passes through. The closer the path unit is to the modification starting node, the higher its detection priority. Among the path units of the same priority, those belonging to the same three-category number identifier as the modification starting node are given priority in sorting, and the path units corresponding to the uplink signal path are given priority in sorting, thus generating an ordered line detection sequence. The modified starting node identifier, target route information, and ordered route detection sequence are integrated and encapsulated into a route detection instruction. The corresponding route detection execution terminal is matched according to the three types of number identifiers of the topology nodes corresponding to each path unit, and the route detection execution terminal issues the route detection instruction. In an embodiment of the present invention, taking the modified starting node P023 as the base point, all signal paths passing through the target line are traversed along the signal flow direction. Priority is divided according to the number of hops between the path unit and P023. Within the same number of hops, path units belonging to the same board as P023 are detected first, and uplink paths are given priority, forming an ordered detection sequence. The starting node identifier, target line information and ordered detection sequence are encapsulated into detection instructions, and instructions are issued to the corresponding detection execution terminal according to the board to which each unit belongs. The line detection execution terminal receives the line detection command and performs line status detection on the target line where the line has been modified, collecting the actual measured data of the target line, including: The line detection execution end parses the line detection command, extracts all topology nodes contained in the path unit corresponding to the target line, sorts all topology nodes according to the signal flow direction marking of the path connection, and generates a reference node sequence. Detection signals are injected into the first topological node of the baseline node sequence, and the arrival time of the signal at each topological node is recorded sequentially along the signal flow direction. The signals are then arranged in the order of arrival to generate a forward propagation time sequence. Detection signals are injected into the topology nodes at the end of the baseline node sequence. The signal arrival time of each topology node is recorded in reverse signal flow, and the signals are arranged in the order of arrival to generate a reverse propagation time sequence. Obtain each pair of adjacent topological nodes in the baseline node sequence, calculate the corresponding adjacent time difference in the forward propagation time series, denoted as the forward delay, and calculate the corresponding adjacent time difference in the reverse propagation time series, denoted as the reverse delay. The absolute value of the difference between the forward and reverse time delays of each path connection is calculated to obtain the time delay symmetry parameter corresponding to each path connection. The absolute value of the difference between the time delay symmetry parameters corresponding to the forward adjacent path connection and the backward adjacent path connection of each intermediate node in the reference node sequence is calculated to obtain the time delay jump value at the intermediate node. By integrating the time delay symmetry parameters and time delay jump values ​​corresponding to each topology node, the measured data of the target line are obtained. In an embodiment of the present invention, after executing the parsing instruction, the topology node sequence of the target line is extracted, a detection signal is injected from the first end to record the forward arrival time of each node, and a signal is injected from the last end to record the reverse arrival time; the forward and reverse time delays between each adjacent node are calculated, and the absolute value of the difference is taken to obtain the time delay symmetry parameter; then the absolute value of the difference between the time delay symmetry parameters of the two segments before and after the intermediate node is calculated to obtain the time delay jump value, and the data are integrated as the actual measured data of the line; This involves performing correlation analysis between measured line data and line correlation maps to extract associated line data that have signal correlation with the target line, including: Extract the measured data of the target route, and establish an associated coordinate system with the sequence number of each path connection in the target route as the x-axis and the time delay symmetry parameter corresponding to each path connection as the y-axis. Mark the time delay symmetry parameter corresponding to each path connection in the associated coordinate system according to the sequence number to obtain the corresponding parameter coordinate points. The parameter coordinate points in the associated coordinate system are fitted with a smooth curve to generate a smooth baseline corresponding to the target route. The parameter coordinate points outside the smooth baseline are extracted, and the path connecting the extracted parameter coordinate points is marked as the associated route. Extract the time delay symmetry parameters corresponding to the associated lines and the time delay jump values ​​corresponding to the topology nodes at both ends; In an embodiment of the present invention, a coordinate system is established with the sequence number of each path connection in the target line as the horizontal axis and the time delay symmetry parameter as the vertical axis. After marking each parameter point, a smooth curve fitting is performed. The path connection corresponding to the parameter point that deviates significantly from the smooth baseline is marked as an associated line, and the time delay symmetry parameter of these associated lines and the time delay jump value of the nodes at both ends of the line are extracted. The process includes verifying the connectivity of the associated lines based on the extracted associated line data, and synchronously loading the connectivity verification results of the target line and associated lines onto the monitoring interface of the test platform. The system iterates through the associated line data in descending order of delay jump values, identifying the Class II identifiers of each associated line. Based on the line association map, it obtains the Class I identifiers at both ends of the corresponding path connection. It then sends connectivity detection pulse signals to the topology nodes corresponding to the Class I identifiers at both ends and records the return status of the pulse signals. If the pulse signal is fully transmitted back, the connection status of the corresponding associated line is determined to be normal; if no pulse transmission signal is received or the pulse transmission signal is incomplete, the connection status of the corresponding associated line is determined to be abnormal; simultaneously, a connectivity check is performed on the target line to obtain the connection status of the target line. The associated lines and the target line whose connectivity status is abnormal will be highlighted on the test platform monitoring interface. In an embodiment of the present invention, each associated line is processed sequentially from large to small according to the delay jump value, and a connectivity detection pulse is sent to both ends of the line. If the pulse is returned completely, the connection is determined to be normal; otherwise, it is determined to be abnormal. Simultaneously, the connectivity of the target line is verified. Finally, the abnormal associated lines and the target line are highlighted in red in the monitoring interface, while the other normal lines remain in the normal color. Example 2: Figure 2 As shown, in order to better implement the above method, a signal line data analysis system for a test platform is also provided. The data analysis system includes: a line map construction module, a line monitoring module, an instruction generation module, a data acquisition module, a correlation analysis module, and a verification display module. The route map construction module is used to obtain the route design diagram of the test platform, parse the route design diagram, and generate the route association map of the test platform. The line monitoring module is used to monitor the signal lines of the test platform in real time and capture line modification events; The instruction generation module is used to generate line detection instructions based on the line association map and send the line detection instructions to the line detection execution terminal. The data acquisition module is set at the line detection execution terminal. After receiving the line detection command, it performs line status detection on the target line where the line has been modified according to the line detection command and collects the measured line data of the target line. The correlation analysis module is used to perform correlation analysis between the measured data of the line and the correlation map of the line, and extract the correlation line data that has a signal correlation with the target line; The verification display module is used to verify the connectivity of the associated lines based on the extracted associated line data, and to synchronously load the target line and the connectivity verification results of the associated lines to the monitoring interface of the test platform.

[0018] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A signal line data analysis method for a test platform, characterized in that, The data analysis methods include: Obtain the circuit design diagram of the test platform, parse the circuit design diagram, and generate the circuit association diagram of the test platform; The system monitors the signal lines of the test platform in real time, captures line modification events, generates line detection commands based on the line correlation map, and sends the line detection commands to the line detection execution terminal. After receiving the line detection command, the line detection execution terminal performs line status detection on the target line where the line has been modified, and collects the actual measured data of the target line. The measured data of the line are correlated with the line correlation map to extract the data of the associated lines that have signal correlation with the target line; Based on the extracted associated line data, the connectivity of the associated lines is verified, and the connectivity verification results of the target line and associated lines are synchronously loaded onto the monitoring interface of the test platform.

2. The signal line data analysis method for a test platform according to claim 1, characterized in that, Obtain the circuit design diagram of the test platform, parse the circuit design diagram, and generate the circuit association map of the test platform, including: Read the numbering identifiers recorded in the circuit design diagram. The numbering identifiers include Class I numbering identifiers, Class II numbering identifiers, and Class III numbering identifiers. Among them, Class I numbering identifiers are hardware port numbers, Class II numbering identifiers are signal transmission cable numbers, and Class III numbering identifiers are board device numbers. Set the first-class number identifier as the topology node in the line association map, and bind the second-class and third-class number identifiers to the corresponding topology nodes; Traverse the connection records of signal transmission lines in the line design diagram, and use the topology nodes corresponding to the two hardware ports connected at both ends of a single signal transmission line as the connection start point and connection end point, respectively, to build the path connection between the topology nodes; according to the signal transmission flow direction marked in the line design diagram, add a signal flow direction mark to each path connection; wherein, the signal flow direction mark is used to distinguish between the uplink signal path and the downlink signal path. The number of path connections, uplink signal paths, and downlink signal paths of each topology node are counted as node attributes for each topology node. These node attributes are then recorded in the corresponding topology node to generate a line association map of the test platform.

3. The signal line data analysis method for a test platform according to claim 1, characterized in that, Real-time monitoring of the signal lines of the test platform, capturing events related to line modifications, including: Read the Class I and Class III number identifiers of each topology node in the line association map, define the horizontal axis X based on the horizontal arrangement order of the test platform cabinets, and define the vertical axis Y based on the vertical layer arrangement order of the cabinets, and establish a coordinate reference system; use the horizontal sequence number of the cabinet corresponding to the Class I number identifier of each topology node as the X-axis coordinate value and the vertical layer sequence number of the cabinet as the Y-axis coordinate value, and mark them in the coordinate reference system to obtain the position coordinates of each topology node; The system continuously collects the pairing information of the two ends of the Class I ID corresponding to all Class II IDs on the test platform, and generates the real-time port pairing relationship for each signal transmission cable. The real-time port pairing relationship is matched one by one with the port pairing relationship in the line association map. The path connection corresponding to the Class II ID with inconsistent pairing relationship is filtered out and marked as the target line. The topology nodes corresponding to both ends of the target line are marked as the modification start node, and the time of modification is recorded to generate a line modification event.

4. The signal line data analysis method for a test platform according to claim 3, characterized in that, Based on the line association map, a line detection command is generated and sent to the line detection execution terminal, including: Using each modification starting node as a base point, and based on the signal flow direction markings of the path connections, all signal transmission paths passing through the target lines are traversed. Each signal transmission path is divided into several path units according to the number of path connections it passes through. The closer the path unit is to the modification starting node, the higher its detection priority. Among the path units of the same priority, those belonging to the same three-category number identifier as the modification starting node are given priority in sorting, and the path units corresponding to the uplink signal path are given priority in sorting, thus generating an ordered line detection sequence. The modified starting node identifier, target route information, and ordered route detection sequence are integrated and encapsulated into a route detection instruction. The corresponding route detection execution terminal is matched according to the three types of number identifiers of the topology nodes corresponding to each path unit, and the route detection execution terminal issues the route detection instruction.

5. The signal line data analysis method for a test platform according to claim 1, characterized in that, After receiving the line detection command, the line detection execution terminal performs line status detection on the target line where the line has been modified, and collects the actual measured data of the target line, including: The line detection execution end parses the line detection command, extracts all topology nodes contained in the path unit corresponding to the target line, sorts all topology nodes according to the signal flow direction marking of the path connection, and generates a reference node sequence. Detection signals are injected into the first topological node of the baseline node sequence, and the arrival time of the signal at each topological node is recorded sequentially along the signal flow direction. The signals are then arranged in the order of arrival to generate a forward propagation time sequence. Detection signals are injected into the topology nodes at the end of the baseline node sequence. The signal arrival time of each topology node is recorded in reverse signal flow, and the signals are arranged in the order of arrival to generate a reverse propagation time sequence. Obtain each pair of adjacent topological nodes in the baseline node sequence, calculate the corresponding adjacent time difference in the forward propagation time series, denoted as the forward delay, and calculate the corresponding adjacent time difference in the reverse propagation time series, denoted as the reverse delay. The absolute value of the difference between the forward and reverse time delays of each path connection is calculated to obtain the time delay symmetry parameter corresponding to each path connection. The absolute value of the difference between the time delay symmetry parameters corresponding to the forward adjacent path connection and the backward adjacent path connection of each intermediate node in the reference node sequence is calculated to obtain the time delay jump value at the intermediate node. By integrating the time delay symmetry parameters and time delay jump values ​​corresponding to each topology node, the measured data of the target line are obtained.

6. The signal line data analysis method for a test platform according to claim 1, characterized in that, The measured data of the line are correlated with the line correlation map to extract the associated line data that have signal correlation with the target line, including: Extract the measured data of the target route, and establish an associated coordinate system with the sequence number of each path connection in the target route as the x-axis and the time delay symmetry parameter corresponding to each path connection as the y-axis. Mark the time delay symmetry parameter corresponding to each path connection in the associated coordinate system according to the sequence number to obtain the corresponding parameter coordinate points. The parameter coordinate points in the associated coordinate system are fitted with a smooth curve to generate a smooth baseline corresponding to the target route. The parameter coordinate points outside the smooth baseline are extracted, and the path connecting the extracted parameter coordinate points is marked as the associated route. Extract the time delay symmetry parameters corresponding to the associated lines and the time delay jump values ​​corresponding to the topology nodes at both ends.

7. The signal line data analysis method for a test platform according to claim 1, characterized in that, Based on the extracted associated line data, the connectivity of the associated lines is verified, and the connectivity verification results of the target line and associated lines are synchronously loaded into the monitoring interface of the test platform, including: The system iterates through the associated line data in descending order of delay jump values, identifying the Class II identifiers of each associated line. Based on the line association map, it obtains the Class I identifiers at both ends of the corresponding path connection. It then sends connectivity detection pulse signals to the topology nodes corresponding to the Class I identifiers at both ends and records the return status of the pulse signals. If the pulse signal is fully transmitted back, the connection status of the corresponding associated line is determined to be normal; if no pulse transmission signal is received or the pulse transmission signal is incomplete, the connection status of the corresponding associated line is determined to be abnormal; simultaneously, a connectivity check is performed on the target line to obtain the connection status of the target line. The associated lines and target lines with abnormal connectivity status will be highlighted on the test platform monitoring interface.

8. A signal line data analysis system for a test platform, used to execute the signal line data analysis method for a test platform according to any one of claims 1-7, characterized in that, The data analysis system includes: a route map construction module, a route monitoring module, an instruction generation module, a data acquisition module, a correlation analysis module, and a verification and display module; The route map construction module is used to obtain the route design diagram of the test platform, parse the route design diagram, and generate the route association map of the test platform. The line monitoring module is used to monitor the signal lines of the test platform in real time and capture line modification events; The instruction generation module is used to generate a line detection instruction based on the line association map and send the line detection instruction to the line detection execution terminal. The data acquisition module is located at the line detection execution terminal. After receiving the line detection command, it performs line status detection on the target line where the line has been modified according to the line detection command and collects the actual measured data of the target line. The correlation analysis module is used to perform correlation analysis between the measured data of the line and the correlation map of the line, and extract the correlation line data that has a signal correlation with the target line; The verification display module is used to verify the connectivity of the associated lines based on the extracted associated line data, and to synchronously load the target line and the connectivity verification results of the associated lines to the monitoring interface of the test platform.

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